From f6906b2289dbc9090eeccf1c35fc05f26468d3ac Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Sun, 23 Oct 2016 10:52:46 +0000 Subject: [PATCH] Refs #123. - Added CAN communication interface support to XCM4 port and the XMC4700 Relax Kit demo. - Added UART and CAN channel configuration check to XMC4 port. - Updated SVD file in the demos for the XMC4700 Relax Kit. - Updated OpenBLT version number in preparation for the next release. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@165 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- .../Boot/bin/openblt_xmc4700.elf | Bin 893128 -> 933944 bytes .../Boot/bin/openblt_xmc4700.map | 1765 +- .../Boot/bin/openblt_xmc4700.srec | 833 +- .../Boot/blt_conf.h | 27 + .../Boot/cfg/{xmc4500.svd => xmc4700.svd} | 218898 ++++++++------- .../Boot/ide/xmc4700.depend | 12 +- .../Boot/ide/xmc4700.ebp | 6 +- .../Boot/ide/xmc4700.elay | 13 +- .../Boot/main.c | 42 +- .../Prog/bin/demoprog_xmc4700.elf | Bin 772252 -> 808572 bytes .../Prog/bin/demoprog_xmc4700.map | 889 +- .../Prog/bin/demoprog_xmc4700.srec | 490 +- .../Prog/boot.c | 150 +- .../Prog/cfg/{xmc4500.svd => xmc4700.svd} | 218898 ++++++++------- .../Prog/ide/xmc4700.depend | 243 +- .../Prog/ide/xmc4700.ebp | 2 +- .../Prog/ide/xmc4700.elay | 6 +- Target/Source/ARMCM4_XMC4/can.c | 240 + Target/Source/ARMCM4_XMC4/uart.c | 5 + Target/Source/boot.h | 2 +- 20 files changed, 249140 insertions(+), 193381 deletions(-) rename Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/{xmc4500.svd => xmc4700.svd} (68%) rename Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/{xmc4500.svd => xmc4700.svd} (68%) create mode 100644 Target/Source/ARMCM4_XMC4/can.c diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.elf b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.elf index ebdea43f72a8b8f58e6123f2b1baed7110eb9ef4..befadf1bbb27b5170285208ecafea9d4b0794292 100644 GIT binary patch delta 207920 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zU9q?|oRrjamOP5HgtdthRMNV|eXOK4!JwRztY&va8EXJ3(PgdK_*u5CtTj&n2imx= zTh{thd=$1G>W8N<{-olM_y(VG%H6V7yMEyarAs+$Lcm`9SBY=pl(BsO(Hgz3W)Wor z-}k(u*M$Ws*ZAJ~Os^YZR;=Z5ANx+PE4oD~&iB zI5Jfh;odN7l0`XM-dZ3vuDL~*T+sU>MIRJ~%f^nz#pTm-^;0|DqQjxI|D%@s{{Tm_ BxhDVs diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.map b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.map index e8158041..1f97d57e 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.map +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/bin/openblt_xmc4700.map @@ -125,11 +125,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\led.o .debug_macro 0x00000000 0x1c ..\obj\led.o .debug_macro 0x00000000 0x22 ..\obj\led.o - .debug_macro 0x00000000 0x65 ..\obj\led.o - .debug_macro 0x00000000 0x50 ..\obj\led.o + .debug_macro 0x00000000 0x93 ..\obj\led.o + .debug_macro 0x00000000 0x3e ..\obj\led.o .debug_macro 0x00000000 0x1c ..\obj\led.o .debug_macro 0x00000000 0x9f ..\obj\led.o - .debug_macro 0x00000000 0x28 ..\obj\led.o + .debug_macro 0x00000000 0x40 ..\obj\led.o .debug_macro 0x00000000 0x174 ..\obj\led.o .debug_macro 0x00000000 0x22 ..\obj\led.o .debug_macro 0x00000000 0x87 ..\obj\led.o @@ -297,17 +297,17 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc4_eru.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc4_eru.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc4_eru.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc4_eru.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_eru.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_eru.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0x2a1 ..\obj\lib\xmclib\src\xmc4_eru.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc4_eru.o .debug_line 0x00000000 0x45b ..\obj\lib\xmclib\src\xmc4_eru.o - .debug_str 0x00000000 0x7730b ..\obj\lib\xmclib\src\xmc4_eru.o + .debug_str 0x00000000 0x773e7 ..\obj\lib\xmclib\src\xmc4_eru.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc4_eru.o .debug_frame 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc4_eru.o .ARM.attributes @@ -422,11 +422,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_flash.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_flash.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc4_flash.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc4_flash.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc4_flash.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc4_flash.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc4_flash.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_flash.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_flash.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_flash.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc4_flash.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_flash.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc4_gpio.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc4_gpio.o @@ -506,11 +506,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc4_gpio.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc4_gpio.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_gpio.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_macro 0x00000000 0xdc4 ..\obj\lib\xmclib\src\xmc4_gpio.o @@ -621,11 +621,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc4_rtc.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc4_rtc.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc4_rtc.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc4_rtc.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_rtc.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_rtc.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x16 ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc4_rtc.o @@ -640,7 +640,7 @@ Discarded input sections .debug_macro 0x00000000 0x35 ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_line 0x00000000 0x5d1 ..\obj\lib\xmclib\src\xmc4_rtc.o - .debug_str 0x00000000 0x76743 ..\obj\lib\xmclib\src\xmc4_rtc.o + .debug_str 0x00000000 0x7681f ..\obj\lib\xmclib\src\xmc4_rtc.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc4_rtc.o .debug_frame 0x00000000 0x9c ..\obj\lib\xmclib\src\xmc4_rtc.o .ARM.attributes @@ -945,11 +945,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_scu.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_scu.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc4_scu.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc4_scu.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc4_scu.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc4_scu.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_scu.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc4_scu.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc4_scu.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc4_scu.o COMMON 0x00000000 0x80 ..\obj\lib\xmclib\src\xmc4_scu.o @@ -1031,14 +1031,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_acmp.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_acmp.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_acmp.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_acmp.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_acmp.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_acmp.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_acmp.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_acmp.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_acmp.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_acmp.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_acmp.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_acmp.o .debug_line 0x00000000 0x40a ..\obj\lib\xmclib\src\xmc_acmp.o - .debug_str 0x00000000 0x753d1 ..\obj\lib\xmclib\src\xmc_acmp.o + .debug_str 0x00000000 0x754ad ..\obj\lib\xmclib\src\xmc_acmp.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_acmp.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_acmp.o @@ -1120,14 +1120,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_bccu.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_bccu.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_bccu.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_bccu.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_bccu.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_bccu.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_bccu.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_bccu.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_bccu.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_bccu.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_bccu.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_bccu.o .debug_line 0x00000000 0x40a ..\obj\lib\xmclib\src\xmc_bccu.o - .debug_str 0x00000000 0x753d1 ..\obj\lib\xmclib\src\xmc_bccu.o + .debug_str 0x00000000 0x754ad ..\obj\lib\xmclib\src\xmc_bccu.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_bccu.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_bccu.o @@ -1175,22 +1175,8 @@ Discarded input sections .text 0x00000000 0x0 ..\obj\lib\xmclib\src\xmc_can.o .data 0x00000000 0x0 ..\obj\lib\xmclib\src\xmc_can.o .bss 0x00000000 0x0 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_NODE_NominalBitTimeConfigure - 0x00000000 0x150 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_AllocateMOtoNodeList - 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_Disable 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_Enable - 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_SetBaudrateClockSource - 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_GetBaudrateClockSource - 0x00000000 0xc ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_GetBaudrateClockFrequency - 0x00000000 0x20 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_Init - 0x00000000 0x94 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_SetIdentifier 0x00000000 0x3c ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_GetIdentifier @@ -1199,14 +1185,6 @@ Discarded input sections 0x00000000 0x24 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_SetAcceptanceMask 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_UpdateData - 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_Config - 0x00000000 0x94 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_Transmit - 0x00000000 0x24 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_ReceiveData - 0x00000000 0x3c ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_Receive 0x00000000 0xc8 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_NODE_EnableEvent @@ -1223,15 +1201,6 @@ Discarded input sections 0x00000000 0x34 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_GATEWAY_InitSourceObject 0x00000000 0x5c ..\obj\lib\xmclib\src\xmc_can.o - .rodata.str1.4 - 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o - .debug_info 0x00000000 0x1448 ..\obj\lib\xmclib\src\xmc_can.o - .debug_abbrev 0x00000000 0x3a4 ..\obj\lib\xmclib\src\xmc_can.o - .debug_loc 0x00000000 0xd21 ..\obj\lib\xmclib\src\xmc_can.o - .debug_aranges - 0x00000000 0xd8 ..\obj\lib\xmclib\src\xmc_can.o - .debug_ranges 0x00000000 0xe0 ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x246 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x892 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x174 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_can.o @@ -1264,21 +1233,13 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_can.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_can.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_can.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x70a ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x20 ..\obj\lib\xmclib\src\xmc_can.o - .debug_line 0x00000000 0x788 ..\obj\lib\xmclib\src\xmc_can.o - .debug_str 0x00000000 0x79cd0 ..\obj\lib\xmclib\src\xmc_can.o - .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_can.o - .debug_frame 0x00000000 0x20c ..\obj\lib\xmclib\src\xmc_can.o - .ARM.attributes - 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_can.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc_ccu4.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc_ccu4.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc_ccu4.o @@ -1423,16 +1384,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_ccu4.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_ccu4.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_ccu4.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_ccu4.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ccu4.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ccu4.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0x740 ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_line 0x00000000 0xc42 ..\obj\lib\xmclib\src\xmc_ccu4.o - .debug_str 0x00000000 0x795e0 ..\obj\lib\xmclib\src\xmc_ccu4.o + .debug_str 0x00000000 0x796bc ..\obj\lib\xmclib\src\xmc_ccu4.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_ccu4.o .debug_frame 0x00000000 0x358 ..\obj\lib\xmclib\src\xmc_ccu4.o .ARM.attributes @@ -1602,17 +1563,17 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_ccu8.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_ccu8.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_ccu8.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_ccu8.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ccu8.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ccu8.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x3e3 ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0x12 ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_line 0x00000000 0xd96 ..\obj\lib\xmclib\src\xmc_ccu8.o - .debug_str 0x00000000 0x797c0 ..\obj\lib\xmclib\src\xmc_ccu8.o + .debug_str 0x00000000 0x7989c ..\obj\lib\xmclib\src\xmc_ccu8.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_ccu8.o .debug_frame 0x00000000 0x474 ..\obj\lib\xmclib\src\xmc_ccu8.o .ARM.attributes @@ -1719,14 +1680,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_common.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_common.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_common.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_common.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_common.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_common.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_common.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_common.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_common.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_common.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_common.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_common.o .debug_line 0x00000000 0x51a ..\obj\lib\xmclib\src\xmc_common.o - .debug_str 0x00000000 0x75594 ..\obj\lib\xmclib\src\xmc_common.o + .debug_str 0x00000000 0x75670 ..\obj\lib\xmclib\src\xmc_common.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_common.o .debug_frame 0x00000000 0xe0 ..\obj\lib\xmclib\src\xmc_common.o .ARM.attributes @@ -1839,16 +1800,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_dac.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_dac.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_dac.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_dac.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_dac.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_dac.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x51 ..\obj\lib\xmclib\src\xmc_dac.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_dac.o .debug_line 0x00000000 0x69b ..\obj\lib\xmclib\src\xmc_dac.o - .debug_str 0x00000000 0x76e53 ..\obj\lib\xmclib\src\xmc_dac.o + .debug_str 0x00000000 0x76f2f ..\obj\lib\xmclib\src\xmc_dac.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_dac.o .debug_frame 0x00000000 0x168 ..\obj\lib\xmclib\src\xmc_dac.o .ARM.attributes @@ -2004,17 +1965,17 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_dma.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_dma.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_dma.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_dma.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_dma.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_dma.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x3c2 ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dma.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_dma.o .debug_line 0x00000000 0x81d ..\obj\lib\xmclib\src\xmc_dma.o - .debug_str 0x00000000 0x796fd ..\obj\lib\xmclib\src\xmc_dma.o + .debug_str 0x00000000 0x797d9 ..\obj\lib\xmclib\src\xmc_dma.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_dma.o .debug_frame 0x00000000 0x2d4 ..\obj\lib\xmclib\src\xmc_dma.o .ARM.attributes @@ -2134,16 +2095,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_dsd.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_dsd.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_dsd.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_dsd.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_dsd.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_dsd.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_dsd.o .debug_macro 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc_dsd.o .debug_line 0x00000000 0x696 ..\obj\lib\xmclib\src\xmc_dsd.o - .debug_str 0x00000000 0x76a25 ..\obj\lib\xmclib\src\xmc_dsd.o + .debug_str 0x00000000 0x76b01 ..\obj\lib\xmclib\src\xmc_dsd.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_dsd.o .debug_frame 0x00000000 0x190 ..\obj\lib\xmclib\src\xmc_dsd.o .ARM.attributes @@ -2238,16 +2199,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_ebu.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_ebu.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_ebu.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_ebu.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ebu.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ebu.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ebu.o .debug_macro 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc_ebu.o .debug_line 0x00000000 0x49a ..\obj\lib\xmclib\src\xmc_ebu.o - .debug_str 0x00000000 0x7672e ..\obj\lib\xmclib\src\xmc_ebu.o + .debug_str 0x00000000 0x7680a ..\obj\lib\xmclib\src\xmc_ebu.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_ebu.o .debug_frame 0x00000000 0x64 ..\obj\lib\xmclib\src\xmc_ebu.o .ARM.attributes @@ -2330,14 +2291,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ecat.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ecat.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_ecat.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_ecat.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_ecat.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_ecat.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_ecat.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ecat.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ecat.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ecat.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_ecat.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ecat.o .debug_line 0x00000000 0x40a ..\obj\lib\xmclib\src\xmc_ecat.o - .debug_str 0x00000000 0x753d1 ..\obj\lib\xmclib\src\xmc_ecat.o + .debug_str 0x00000000 0x754ad ..\obj\lib\xmclib\src\xmc_ecat.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_ecat.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_ecat.o @@ -2453,16 +2414,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_eru.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_eru.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_eru.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_eru.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_eru.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_eru.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc_eru.o .debug_macro 0x00000000 0x2a1 ..\obj\lib\xmclib\src\xmc_eru.o .debug_line 0x00000000 0x66a ..\obj\lib\xmclib\src\xmc_eru.o - .debug_str 0x00000000 0x779b4 ..\obj\lib\xmclib\src\xmc_eru.o + .debug_str 0x00000000 0x77a90 ..\obj\lib\xmclib\src\xmc_eru.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_eru.o .debug_frame 0x00000000 0x19c ..\obj\lib\xmclib\src\xmc_eru.o .ARM.attributes @@ -2616,11 +2577,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_eth_mac.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_eth_mac.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_eth_mac.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_eth_mac.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_eth_mac.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_eth_mac.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x131 ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0x16 ..\obj\lib\xmclib\src\xmc_eth_mac.o @@ -2628,7 +2589,7 @@ Discarded input sections .debug_macro 0x00000000 0x29 ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_line 0x00000000 0x8aa ..\obj\lib\xmclib\src\xmc_eth_mac.o - .debug_str 0x00000000 0x785b0 ..\obj\lib\xmclib\src\xmc_eth_mac.o + .debug_str 0x00000000 0x7868c ..\obj\lib\xmclib\src\xmc_eth_mac.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_eth_mac.o .debug_frame 0x00000000 0x334 ..\obj\lib\xmclib\src\xmc_eth_mac.o .ARM.attributes @@ -2735,16 +2696,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_fce.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_fce.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_fce.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_fce.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_fce.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_fce.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_fce.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_fce.o .debug_line 0x00000000 0x586 ..\obj\lib\xmclib\src\xmc_fce.o - .debug_str 0x00000000 0x763d3 ..\obj\lib\xmclib\src\xmc_fce.o + .debug_str 0x00000000 0x764af ..\obj\lib\xmclib\src\xmc_fce.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_fce.o .debug_frame 0x00000000 0x130 ..\obj\lib\xmclib\src\xmc_fce.o .ARM.attributes @@ -2827,11 +2788,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_gpio.o .debug_macro 0x00000000 0xdc4 ..\obj\lib\xmclib\src\xmc_gpio.o @@ -2914,14 +2875,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_hrpwm.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_hrpwm.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_hrpwm.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_hrpwm.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_hrpwm.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_hrpwm.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_hrpwm.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_hrpwm.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_hrpwm.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_hrpwm.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_hrpwm.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_hrpwm.o .debug_line 0x00000000 0x40c ..\obj\lib\xmclib\src\xmc_hrpwm.o - .debug_str 0x00000000 0x753cf ..\obj\lib\xmclib\src\xmc_hrpwm.o + .debug_str 0x00000000 0x754ab ..\obj\lib\xmclib\src\xmc_hrpwm.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_hrpwm.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_hrpwm.o @@ -3038,17 +2999,17 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_i2c.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_i2c.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_i2c.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_i2c.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_i2c.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_i2c.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x8b ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x2ef ..\obj\lib\xmclib\src\xmc_i2c.o .debug_macro 0x00000000 0x2e ..\obj\lib\xmclib\src\xmc_i2c.o .debug_line 0x00000000 0x654 ..\obj\lib\xmclib\src\xmc_i2c.o - .debug_str 0x00000000 0x76c28 ..\obj\lib\xmclib\src\xmc_i2c.o + .debug_str 0x00000000 0x76d04 ..\obj\lib\xmclib\src\xmc_i2c.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_i2c.o .debug_frame 0x00000000 0x12c ..\obj\lib\xmclib\src\xmc_i2c.o .ARM.attributes @@ -3155,18 +3116,18 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_i2s.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_i2s.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_i2s.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_i2s.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_i2s.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_i2s.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x91 ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x2ef ..\obj\lib\xmclib\src\xmc_i2s.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_i2s.o .debug_line 0x00000000 0x571 ..\obj\lib\xmclib\src\xmc_i2s.o - .debug_str 0x00000000 0x76fa8 ..\obj\lib\xmclib\src\xmc_i2s.o + .debug_str 0x00000000 0x77084 ..\obj\lib\xmclib\src\xmc_i2s.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_i2s.o .debug_frame 0x00000000 0xb8 ..\obj\lib\xmclib\src\xmc_i2s.o .ARM.attributes @@ -3287,16 +3248,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_ledts.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_ledts.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_ledts.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_ledts.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ledts.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ledts.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_ledts.o .debug_macro 0x00000000 0x2c ..\obj\lib\xmclib\src\xmc_ledts.o .debug_line 0x00000000 0x618 ..\obj\lib\xmclib\src\xmc_ledts.o - .debug_str 0x00000000 0x7687e ..\obj\lib\xmclib\src\xmc_ledts.o + .debug_str 0x00000000 0x7695a ..\obj\lib\xmclib\src\xmc_ledts.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_ledts.o .debug_frame 0x00000000 0x1cc ..\obj\lib\xmclib\src\xmc_ledts.o .ARM.attributes @@ -3379,14 +3340,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_math.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_math.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_math.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_math.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_math.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_math.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_math.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_math.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_math.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_math.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_math.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_math.o .debug_line 0x00000000 0x40a ..\obj\lib\xmclib\src\xmc_math.o - .debug_str 0x00000000 0x753d1 ..\obj\lib\xmclib\src\xmc_math.o + .debug_str 0x00000000 0x754ad ..\obj\lib\xmclib\src\xmc_math.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_math.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_math.o @@ -3468,14 +3429,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_pau.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_pau.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_pau.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_pau.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_pau.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_pau.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_pau.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_pau.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_pau.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_pau.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_pau.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_pau.o .debug_line 0x00000000 0x408 ..\obj\lib\xmclib\src\xmc_pau.o - .debug_str 0x00000000 0x753cf ..\obj\lib\xmclib\src\xmc_pau.o + .debug_str 0x00000000 0x754ab ..\obj\lib\xmclib\src\xmc_pau.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_pau.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_pau.o @@ -3579,16 +3540,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_posif.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_posif.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_posif.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_posif.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_posif.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_posif.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_posif.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_posif.o .debug_line 0x00000000 0x591 ..\obj\lib\xmclib\src\xmc_posif.o - .debug_str 0x00000000 0x76864 ..\obj\lib\xmclib\src\xmc_posif.o + .debug_str 0x00000000 0x76940 ..\obj\lib\xmclib\src\xmc_posif.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_posif.o .debug_frame 0x00000000 0xec ..\obj\lib\xmclib\src\xmc_posif.o .ARM.attributes @@ -3671,14 +3632,14 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_prng.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_prng.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_prng.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_prng.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_prng.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_prng.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_prng.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_prng.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_prng.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_prng.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_prng.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_prng.o .debug_line 0x00000000 0x40a ..\obj\lib\xmclib\src\xmc_prng.o - .debug_str 0x00000000 0x753d1 ..\obj\lib\xmclib\src\xmc_prng.o + .debug_str 0x00000000 0x754ad ..\obj\lib\xmclib\src\xmc_prng.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_prng.o .ARM.attributes 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_prng.o @@ -3800,11 +3761,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_rtc.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_rtc.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_rtc.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_rtc.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_rtc.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_rtc.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x16 ..\obj\lib\xmclib\src\xmc_rtc.o @@ -3819,7 +3780,7 @@ Discarded input sections .debug_macro 0x00000000 0xd7 ..\obj\lib\xmclib\src\xmc_rtc.o .debug_macro 0x00000000 0x35 ..\obj\lib\xmclib\src\xmc_rtc.o .debug_line 0x00000000 0x6a5 ..\obj\lib\xmclib\src\xmc_rtc.o - .debug_str 0x00000000 0x7682e ..\obj\lib\xmclib\src\xmc_rtc.o + .debug_str 0x00000000 0x7690a ..\obj\lib\xmclib\src\xmc_rtc.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_rtc.o .debug_frame 0x00000000 0x110 ..\obj\lib\xmclib\src\xmc_rtc.o .ARM.attributes @@ -3934,16 +3895,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_sdmmc.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_sdmmc.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_sdmmc.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_sdmmc.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_sdmmc.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_sdmmc.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0x47 ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_line 0x00000000 0x63a ..\obj\lib\xmclib\src\xmc_sdmmc.o - .debug_str 0x00000000 0x77566 ..\obj\lib\xmclib\src\xmc_sdmmc.o + .debug_str 0x00000000 0x77642 ..\obj\lib\xmclib\src\xmc_sdmmc.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_sdmmc.o .debug_frame 0x00000000 0x170 ..\obj\lib\xmclib\src\xmc_sdmmc.o .ARM.attributes @@ -4052,18 +4013,18 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_spi.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_spi.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_spi.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_spi.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_spi.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_spi.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x91 ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x2ef ..\obj\lib\xmclib\src\xmc_spi.o .debug_macro 0x00000000 0x2a ..\obj\lib\xmclib\src\xmc_spi.o .debug_line 0x00000000 0x580 ..\obj\lib\xmclib\src\xmc_spi.o - .debug_str 0x00000000 0x77183 ..\obj\lib\xmclib\src\xmc_spi.o + .debug_str 0x00000000 0x7725f ..\obj\lib\xmclib\src\xmc_spi.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_spi.o .debug_frame 0x00000000 0xe4 ..\obj\lib\xmclib\src\xmc_spi.o .ARM.attributes @@ -4153,11 +4114,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_uart.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_uart.o .debug_macro 0x00000000 0x91 ..\obj\lib\xmclib\src\xmc_uart.o @@ -4337,11 +4298,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_usbd.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_usbd.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_usbd.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_usbd.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_usbd.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usbd.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x16 ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0x16 ..\obj\lib\xmclib\src\xmc_usbd.o @@ -4350,7 +4311,7 @@ Discarded input sections .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_usbd.o .debug_macro 0x00000000 0xc5 ..\obj\lib\xmclib\src\xmc_usbd.o .debug_line 0x00000000 0xa51 ..\obj\lib\xmclib\src\xmc_usbd.o - .debug_str 0x00000000 0x790ae ..\obj\lib\xmclib\src\xmc_usbd.o + .debug_str 0x00000000 0x7918a ..\obj\lib\xmclib\src\xmc_usbd.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_usbd.o .debug_frame 0x00000000 0x3d4 ..\obj\lib\xmclib\src\xmc_usbd.o .ARM.attributes @@ -4501,11 +4462,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_usbh.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_usbh.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_usbh.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_usbh.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_usbh.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usbh.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usbh.o @@ -4513,7 +4474,7 @@ Discarded input sections .debug_macro 0x00000000 0xba ..\obj\lib\xmclib\src\xmc_usbh.o .debug_macro 0x00000000 0x1f8 ..\obj\lib\xmclib\src\xmc_usbh.o .debug_line 0x00000000 0x96c ..\obj\lib\xmclib\src\xmc_usbh.o - .debug_str 0x00000000 0x7e390 ..\obj\lib\xmclib\src\xmc_usbh.o + .debug_str 0x00000000 0x7e46c ..\obj\lib\xmclib\src\xmc_usbh.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_usbh.o .debug_frame 0x00000000 0x248 ..\obj\lib\xmclib\src\xmc_usbh.o .ARM.attributes @@ -4611,11 +4572,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_usic.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x8b ..\obj\lib\xmclib\src\xmc_usic.o .debug_macro 0x00000000 0x2ef ..\obj\lib\xmclib\src\xmc_usic.o @@ -4846,16 +4807,16 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_vadc.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_vadc.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_vadc.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_vadc.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_vadc.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_vadc.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_vadc.o .debug_macro 0x00000000 0x74 ..\obj\lib\xmclib\src\xmc_vadc.o .debug_line 0x00000000 0x1262 ..\obj\lib\xmclib\src\xmc_vadc.o - .debug_str 0x00000000 0x78759 ..\obj\lib\xmclib\src\xmc_vadc.o + .debug_str 0x00000000 0x78835 ..\obj\lib\xmclib\src\xmc_vadc.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_vadc.o .debug_frame 0x00000000 0x7ac ..\obj\lib\xmclib\src\xmc_vadc.o .ARM.attributes @@ -4947,15 +4908,15 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_wdt.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_wdt.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_wdt.o - .debug_macro 0x00000000 0x65 ..\obj\lib\xmclib\src\xmc_wdt.o - .debug_macro 0x00000000 0x50 ..\obj\lib\xmclib\src\xmc_wdt.o + .debug_macro 0x00000000 0x93 ..\obj\lib\xmclib\src\xmc_wdt.o + .debug_macro 0x00000000 0x3e ..\obj\lib\xmclib\src\xmc_wdt.o .debug_macro 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_wdt.o .debug_macro 0x00000000 0x9f ..\obj\lib\xmclib\src\xmc_wdt.o - .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_wdt.o + .debug_macro 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_wdt.o .debug_macro 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_wdt.o .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_wdt.o .debug_line 0x00000000 0x45c ..\obj\lib\xmclib\src\xmc_wdt.o - .debug_str 0x00000000 0x761b3 ..\obj\lib\xmclib\src\xmc_wdt.o + .debug_str 0x00000000 0x7628f ..\obj\lib\xmclib\src\xmc_wdt.o .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_wdt.o .debug_frame 0x00000000 0x58 ..\obj\lib\xmclib\src\xmc_wdt.o .ARM.attributes @@ -5003,6 +4964,9 @@ Discarded input sections .group 0x00000000 0x8 ..\obj\main.o .group 0x00000000 0x8 ..\obj\main.o .group 0x00000000 0x8 ..\obj\main.o + .group 0x00000000 0x8 ..\obj\main.o + .group 0x00000000 0x8 ..\obj\main.o + .group 0x00000000 0x8 ..\obj\main.o .text 0x00000000 0x0 ..\obj\main.o .data 0x00000000 0x0 ..\obj\main.o .bss 0x00000000 0x0 ..\obj\main.o @@ -5010,11 +4974,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\main.o .debug_macro 0x00000000 0x1c ..\obj\main.o .debug_macro 0x00000000 0x22 ..\obj\main.o - .debug_macro 0x00000000 0x65 ..\obj\main.o - .debug_macro 0x00000000 0x50 ..\obj\main.o + .debug_macro 0x00000000 0x93 ..\obj\main.o + .debug_macro 0x00000000 0x3e ..\obj\main.o .debug_macro 0x00000000 0x1c ..\obj\main.o .debug_macro 0x00000000 0x9f ..\obj\main.o - .debug_macro 0x00000000 0x28 ..\obj\main.o + .debug_macro 0x00000000 0x40 ..\obj\main.o .debug_macro 0x00000000 0x174 ..\obj\main.o .debug_macro 0x00000000 0x22 ..\obj\main.o .debug_macro 0x00000000 0x87 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0x00000000 0x43 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x20 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x187 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x30d ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x10 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x35 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x16e ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x2d ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x3b ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0xe66 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x16 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x165d5 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x19 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x4c ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0xa5 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x70a ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x20 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0xdc4 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_macro 0x00000000 0xba ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o @@ -5067,11 +5123,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o @@ -5117,11 +5173,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x174 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .debug_macro 0x00000000 0x87 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o @@ -5167,11 +5223,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o .data 0x00000000 0x0 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o .bss 0x00000000 0x0 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o @@ -5190,11 +5246,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o @@ -5211,11 +5267,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o @@ -5263,11 +5319,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x174 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .debug_macro 0x00000000 0x87 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o @@ -5315,11 +5371,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\assert.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\assert.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\assert.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\assert.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\assert.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\assert.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\assert.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\assert.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\assert.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\assert.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\assert.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\backdoor.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\backdoor.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\backdoor.o @@ -5336,11 +5392,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\backdoor.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\backdoor.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\backdoor.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\backdoor.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\backdoor.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\backdoor.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\backdoor.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\backdoor.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\backdoor.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\backdoor.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\backdoor.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\boot.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\boot.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\boot.o @@ -5357,11 +5413,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\boot.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\boot.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\boot.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\boot.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\boot.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\boot.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\boot.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\boot.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\boot.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\boot.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\boot.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\com.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\com.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\com.o @@ -5378,11 +5434,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\com.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\com.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\com.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\com.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\com.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\com.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\com.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\com.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\com.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\com.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\com.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\cop.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\cop.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\cop.o @@ -5399,11 +5455,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\cop.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\cop.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\cop.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\cop.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\cop.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\cop.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\cop.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\cop.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\cop.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\cop.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\cop.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\file.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\file.o .group 0x00000000 0x8 ..\obj\~#\~#\~#\source\file.o @@ -5441,11 +5497,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\file.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\file.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\file.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\file.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\file.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\file.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x4c ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0x8d ..\obj\~#\~#\~#\source\file.o @@ -5463,7 +5519,7 @@ Discarded input sections .debug_macro 0x00000000 0x35 ..\obj\~#\~#\~#\source\file.o .debug_macro 0x00000000 0xac ..\obj\~#\~#\~#\source\file.o .debug_line 0x00000000 0x2fa ..\obj\~#\~#\~#\source\file.o - .debug_str 0x00000000 0x5f72 ..\obj\~#\~#\~#\source\file.o + .debug_str 0x00000000 0x604e ..\obj\~#\~#\~#\source\file.o .comment 0x00000000 0x6f ..\obj\~#\~#\~#\source\file.o .ARM.attributes 0x00000000 0x39 ..\obj\~#\~#\~#\source\file.o @@ -5488,13 +5544,13 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\net.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\net.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\net.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\net.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\net.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\net.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\net.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\net.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\net.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\net.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\net.o .debug_line 0x00000000 0xee ..\obj\~#\~#\~#\source\net.o - .debug_str 0x00000000 0x2dd8 ..\obj\~#\~#\~#\source\net.o + .debug_str 0x00000000 0x2eb4 ..\obj\~#\~#\~#\source\net.o .comment 0x00000000 0x6f ..\obj\~#\~#\~#\source\net.o .ARM.attributes 0x00000000 0x39 ..\obj\~#\~#\~#\source\net.o @@ -5514,11 +5570,11 @@ Discarded input sections .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\xcp.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\xcp.o .debug_macro 0x00000000 0x22 ..\obj\~#\~#\~#\source\xcp.o - .debug_macro 0x00000000 0x65 ..\obj\~#\~#\~#\source\xcp.o - .debug_macro 0x00000000 0x50 ..\obj\~#\~#\~#\source\xcp.o + .debug_macro 0x00000000 0x93 ..\obj\~#\~#\~#\source\xcp.o + .debug_macro 0x00000000 0x3e ..\obj\~#\~#\~#\source\xcp.o .debug_macro 0x00000000 0x1c ..\obj\~#\~#\~#\source\xcp.o .debug_macro 0x00000000 0x9f ..\obj\~#\~#\~#\source\xcp.o - .debug_macro 0x00000000 0x28 ..\obj\~#\~#\~#\source\xcp.o + .debug_macro 0x00000000 0x40 ..\obj\~#\~#\~#\source\xcp.o .text 0x00000000 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) .data 0x00000000 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) .bss 0x00000000 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) @@ -5566,7 +5622,7 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- 0x00000000 __HEAP_SIZE = 0x0 0x00000800 __STACK_SIZE = 0x800 -.text 0x08000000 0x1c9c +.text 0x08000000 0x22c4 *(.isr_vector) .isr_vector 0x08000000 0x200 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o 0x08000000 __isr_vector @@ -5645,348 +5701,389 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- .text.XMC_SCU_CLOCK_UngatePeripheralClock 0x080008d0 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o 0x080008d0 XMC_SCU_CLOCK_UngatePeripheralClock + .text.XMC_CAN_NODE_NominalBitTimeConfigure + 0x080008e8 0x150 ..\obj\lib\xmclib\src\xmc_can.o + 0x080008e8 XMC_CAN_NODE_NominalBitTimeConfigure + .text.XMC_CAN_AllocateMOtoNodeList + 0x08000a38 0x1c ..\obj\lib\xmclib\src\xmc_can.o + 0x08000a38 XMC_CAN_AllocateMOtoNodeList + .text.XMC_CAN_Enable + 0x08000a54 0x28 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000a54 XMC_CAN_Enable + .text.XMC_CAN_SetBaudrateClockSource + 0x08000a7c 0x10 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000a7c XMC_CAN_SetBaudrateClockSource + .text.XMC_CAN_GetBaudrateClockSource + 0x08000a8c 0xc ..\obj\lib\xmclib\src\xmc_can.o + 0x08000a8c XMC_CAN_GetBaudrateClockSource + .text.XMC_CAN_GetBaudrateClockFrequency + 0x08000a98 0x20 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000a98 XMC_CAN_GetBaudrateClockFrequency + .text.XMC_CAN_Init + 0x08000ab8 0x94 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000ab8 XMC_CAN_Init + .text.XMC_CAN_MO_UpdateData + 0x08000b4c 0x40 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000b4c XMC_CAN_MO_UpdateData + .text.XMC_CAN_MO_Config + 0x08000b8c 0x94 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000b8c XMC_CAN_MO_Config + .text.XMC_CAN_MO_Transmit + 0x08000c20 0x24 ..\obj\lib\xmclib\src\xmc_can.o + 0x08000c20 XMC_CAN_MO_Transmit + .text.XMC_CAN_MO_ReceiveData + 0x08000c44 0x3c ..\obj\lib\xmclib\src\xmc_can.o + 0x08000c44 XMC_CAN_MO_ReceiveData .text.XMC_GPIO_SetMode - 0x080008e8 0x138 ..\obj\lib\xmclib\src\xmc_gpio.o - 0x080008e8 XMC_GPIO_SetMode + 0x08000c80 0x138 ..\obj\lib\xmclib\src\xmc_gpio.o + 0x08000c80 XMC_GPIO_SetMode .text.XMC_UART_CH_Init - 0x08000a20 0x6c ..\obj\lib\xmclib\src\xmc_uart.o - 0x08000a20 XMC_UART_CH_Init + 0x08000db8 0x6c ..\obj\lib\xmclib\src\xmc_uart.o + 0x08000db8 XMC_UART_CH_Init .text.XMC_UART_CH_Transmit - 0x08000a8c 0x24 ..\obj\lib\xmclib\src\xmc_uart.o - 0x08000a8c XMC_UART_CH_Transmit + 0x08000e24 0x24 ..\obj\lib\xmclib\src\xmc_uart.o + 0x08000e24 XMC_UART_CH_Transmit .text.XMC_UART_CH_GetReceivedData - 0x08000ab0 0x18 ..\obj\lib\xmclib\src\xmc_uart.o - 0x08000ab0 XMC_UART_CH_GetReceivedData + 0x08000e48 0x18 ..\obj\lib\xmclib\src\xmc_uart.o + 0x08000e48 XMC_UART_CH_GetReceivedData .text.XMC_USIC_CH_SetBaudrate - 0x08000ac8 0x8c ..\obj\lib\xmclib\src\xmc_usic.o - 0x08000ac8 XMC_USIC_CH_SetBaudrate + 0x08000e60 0x8c ..\obj\lib\xmclib\src\xmc_usic.o + 0x08000e60 XMC_USIC_CH_SetBaudrate .text.XMC_USIC_CH_TXFIFO_Configure - 0x08000b54 0x30 ..\obj\lib\xmclib\src\xmc_usic.o - 0x08000b54 XMC_USIC_CH_TXFIFO_Configure + 0x08000eec 0x30 ..\obj\lib\xmclib\src\xmc_usic.o + 0x08000eec XMC_USIC_CH_TXFIFO_Configure .text.XMC_USIC_CH_RXFIFO_Configure - 0x08000b84 0x34 ..\obj\lib\xmclib\src\xmc_usic.o - 0x08000b84 XMC_USIC_CH_RXFIFO_Configure + 0x08000f1c 0x34 ..\obj\lib\xmclib\src\xmc_usic.o + 0x08000f1c XMC_USIC_CH_RXFIFO_Configure .text.XMC_USIC_Enable - 0x08000bb8 0x6c ..\obj\lib\xmclib\src\xmc_usic.o - 0x08000bb8 XMC_USIC_Enable + 0x08000f50 0x6c ..\obj\lib\xmclib\src\xmc_usic.o + 0x08000f50 XMC_USIC_Enable .text.XMC_USIC_CH_Enable - 0x08000c24 0xe0 ..\obj\lib\xmclib\src\xmc_usic.o - 0x08000c24 XMC_USIC_CH_Enable - .text.Init 0x08000d04 0x2c ..\obj\main.o + 0x08000fbc 0xe0 ..\obj\lib\xmclib\src\xmc_usic.o + 0x08000fbc XMC_USIC_CH_Enable + .text.Init 0x0800109c 0x2c ..\obj\main.o .text.PostInit - 0x08000d30 0x50 ..\obj\main.o - .text.main 0x08000d80 0x14 ..\obj\main.o - 0x08000d80 main - .text.CpuInit 0x08000d94 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - 0x08000d94 CpuInit + 0x080010c8 0x98 ..\obj\main.o + .text.main 0x08001160 0x14 ..\obj\main.o + 0x08001160 main + .text.CanInit 0x08001174 0x150 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + 0x08001174 CanInit + .text.CanTransmitPacket + 0x080012c4 0x48 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + 0x080012c4 CanTransmitPacket + .text.CanReceivePacket + 0x0800130c 0x4c ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + 0x0800130c CanReceivePacket + .text.CpuInit 0x08001358 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + 0x08001358 CpuInit .text.CpuStartUserProgram - 0x08000d9c 0x38 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - 0x08000d9c CpuStartUserProgram + 0x08001360 0x38 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + 0x08001360 CpuStartUserProgram .text.CpuMemCopy - 0x08000dd4 0x20 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - 0x08000dd4 CpuMemCopy + 0x08001398 0x20 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + 0x08001398 CpuMemCopy .text.FlashTranslateToNonCachedAddress - 0x08000df4 0xc ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080013b8 0xc ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashGetSector - 0x08000e00 0x48 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080013c4 0x48 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashGetSectorBaseAddr - 0x08000e48 0x38 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x0800140c 0x38 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashInitBlock - 0x08000e80 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x08001444 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashWriteBlock - 0x08000ea8 0x90 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x0800146c 0x90 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashSwitchBlock - 0x08000f38 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080014fc 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashAddToBlock - 0x08000f78 0x7c ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x0800153c 0x7c ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashEraseSectors - 0x08000ff4 0x80 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080015b8 0x80 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .text.FlashInit - 0x08001074 0x18 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x08001074 FlashInit + 0x08001638 0x18 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x08001638 FlashInit .text.FlashWrite - 0x0800108c 0x60 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x0800108c FlashWrite + 0x08001650 0x60 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x08001650 FlashWrite .text.FlashErase - 0x080010ec 0x34 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x080010ec FlashErase + 0x080016b0 0x34 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080016b0 FlashErase .text.FlashWriteChecksum - 0x08001120 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x08001120 FlashWriteChecksum + 0x080016e4 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080016e4 FlashWriteChecksum .text.FlashVerifyChecksum - 0x08001170 0x58 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x08001170 FlashVerifyChecksum + 0x08001734 0x58 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x08001734 FlashVerifyChecksum .text.FlashDone - 0x080011c8 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x080011c8 FlashDone + 0x0800178c 0x40 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x0800178c FlashDone .text.FlashGetUserProgBaseAddress - 0x08001208 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - 0x08001208 FlashGetUserProgBaseAddress + 0x080017cc 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080017cc FlashGetUserProgBaseAddress .text.CpuIrqDisable - 0x08001210 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - 0x08001210 CpuIrqDisable + 0x080017d4 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + 0x080017d4 CpuIrqDisable .text.CpuIrqEnable - 0x08001214 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - 0x08001214 CpuIrqEnable - .text 0x08001218 0x12c ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o - 0x08001218 Reset_Handler - 0x0800125e NMI_Handler - 0x08001260 HardFault_Handler - 0x08001262 MemManage_Handler - 0x08001264 BusFault_Handler - 0x08001266 UsageFault_Handler - 0x08001268 SVC_Handler - 0x0800126a DebugMon_Handler - 0x0800126c PendSV_Handler - 0x0800126e SysTick_Handler - 0x08001270 Default_Handler - 0x08001272 SCU_0_IRQHandler - 0x08001274 ERU0_0_IRQHandler - 0x08001276 ERU0_1_IRQHandler - 0x08001278 ERU0_2_IRQHandler - 0x0800127a ERU0_3_IRQHandler - 0x0800127c ERU1_0_IRQHandler - 0x0800127e ERU1_1_IRQHandler - 0x08001280 ERU1_2_IRQHandler - 0x08001282 ERU1_3_IRQHandler - 0x08001284 PMU0_0_IRQHandler - 0x08001286 VADC0_C0_0_IRQHandler - 0x08001288 VADC0_C0_1_IRQHandler - 0x0800128a VADC0_C0_2_IRQHandler - 0x0800128c VADC0_C0_3_IRQHandler - 0x0800128e VADC0_G0_0_IRQHandler - 0x08001290 VADC0_G0_1_IRQHandler - 0x08001292 VADC0_G0_2_IRQHandler - 0x08001294 VADC0_G0_3_IRQHandler - 0x08001296 VADC0_G1_0_IRQHandler - 0x08001298 VADC0_G1_1_IRQHandler - 0x0800129a VADC0_G1_2_IRQHandler - 0x0800129c VADC0_G1_3_IRQHandler - 0x0800129e VADC0_G2_0_IRQHandler - 0x080012a0 VADC0_G2_1_IRQHandler - 0x080012a2 VADC0_G2_2_IRQHandler - 0x080012a4 VADC0_G2_3_IRQHandler - 0x080012a6 VADC0_G3_0_IRQHandler - 0x080012a8 VADC0_G3_1_IRQHandler - 0x080012aa VADC0_G3_2_IRQHandler - 0x080012ac VADC0_G3_3_IRQHandler - 0x080012ae DSD0_0_IRQHandler - 0x080012b0 DSD0_1_IRQHandler - 0x080012b2 DSD0_2_IRQHandler - 0x080012b4 DSD0_3_IRQHandler - 0x080012b6 DSD0_4_IRQHandler - 0x080012b8 DSD0_5_IRQHandler - 0x080012ba DSD0_6_IRQHandler - 0x080012bc DSD0_7_IRQHandler - 0x080012be DAC0_0_IRQHandler - 0x080012c0 DAC0_1_IRQHandler - 0x080012c2 CCU40_0_IRQHandler - 0x080012c4 CCU40_1_IRQHandler - 0x080012c6 CCU40_2_IRQHandler - 0x080012c8 CCU40_3_IRQHandler - 0x080012ca CCU41_0_IRQHandler - 0x080012cc CCU41_1_IRQHandler - 0x080012ce CCU41_2_IRQHandler - 0x080012d0 CCU41_3_IRQHandler - 0x080012d2 CCU42_0_IRQHandler - 0x080012d4 CCU42_1_IRQHandler - 0x080012d6 CCU42_2_IRQHandler - 0x080012d8 CCU42_3_IRQHandler - 0x080012da CCU43_0_IRQHandler - 0x080012dc CCU43_1_IRQHandler - 0x080012de CCU43_2_IRQHandler - 0x080012e0 CCU43_3_IRQHandler - 0x080012e2 CCU80_0_IRQHandler - 0x080012e4 CCU80_1_IRQHandler - 0x080012e6 CCU80_2_IRQHandler - 0x080012e8 CCU80_3_IRQHandler - 0x080012ea CCU81_0_IRQHandler - 0x080012ec CCU81_1_IRQHandler - 0x080012ee CCU81_2_IRQHandler - 0x080012f0 CCU81_3_IRQHandler - 0x080012f2 POSIF0_0_IRQHandler - 0x080012f4 POSIF0_1_IRQHandler - 0x080012f6 POSIF1_0_IRQHandler - 0x080012f8 POSIF1_1_IRQHandler - 0x080012fa CAN0_0_IRQHandler - 0x080012fc CAN0_1_IRQHandler - 0x080012fe CAN0_2_IRQHandler - 0x08001300 CAN0_3_IRQHandler - 0x08001302 CAN0_4_IRQHandler - 0x08001304 CAN0_5_IRQHandler - 0x08001306 CAN0_6_IRQHandler - 0x08001308 CAN0_7_IRQHandler - 0x0800130a USIC0_0_IRQHandler - 0x0800130c USIC0_1_IRQHandler - 0x0800130e USIC0_2_IRQHandler - 0x08001310 USIC0_3_IRQHandler - 0x08001312 USIC0_4_IRQHandler - 0x08001314 USIC0_5_IRQHandler - 0x08001316 USIC1_0_IRQHandler - 0x08001318 USIC1_1_IRQHandler - 0x0800131a USIC1_2_IRQHandler - 0x0800131c USIC1_3_IRQHandler - 0x0800131e USIC1_4_IRQHandler - 0x08001320 USIC1_5_IRQHandler - 0x08001322 USIC2_0_IRQHandler - 0x08001324 USIC2_1_IRQHandler - 0x08001326 USIC2_2_IRQHandler - 0x08001328 USIC2_3_IRQHandler - 0x0800132a USIC2_4_IRQHandler - 0x0800132c USIC2_5_IRQHandler - 0x0800132e LEDTS0_0_IRQHandler - 0x08001330 FCE0_0_IRQHandler - 0x08001332 GPDMA0_0_IRQHandler - 0x08001334 SDMMC0_0_IRQHandler - 0x08001336 USB0_0_IRQHandler - 0x08001338 ETH0_0_IRQHandler - 0x0800133a GPDMA1_0_IRQHandler - .text.NvmInit 0x08001344 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - 0x08001344 NvmInit + 0x080017d8 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + 0x080017d8 CpuIrqEnable + .text 0x080017dc 0x12c ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o + 0x080017dc Reset_Handler + 0x08001822 NMI_Handler + 0x08001824 HardFault_Handler + 0x08001826 MemManage_Handler + 0x08001828 BusFault_Handler + 0x0800182a UsageFault_Handler + 0x0800182c SVC_Handler + 0x0800182e DebugMon_Handler + 0x08001830 PendSV_Handler + 0x08001832 SysTick_Handler + 0x08001834 Default_Handler + 0x08001836 SCU_0_IRQHandler + 0x08001838 ERU0_0_IRQHandler + 0x0800183a ERU0_1_IRQHandler + 0x0800183c ERU0_2_IRQHandler + 0x0800183e ERU0_3_IRQHandler + 0x08001840 ERU1_0_IRQHandler + 0x08001842 ERU1_1_IRQHandler + 0x08001844 ERU1_2_IRQHandler + 0x08001846 ERU1_3_IRQHandler + 0x08001848 PMU0_0_IRQHandler + 0x0800184a VADC0_C0_0_IRQHandler + 0x0800184c VADC0_C0_1_IRQHandler + 0x0800184e VADC0_C0_2_IRQHandler + 0x08001850 VADC0_C0_3_IRQHandler + 0x08001852 VADC0_G0_0_IRQHandler + 0x08001854 VADC0_G0_1_IRQHandler + 0x08001856 VADC0_G0_2_IRQHandler + 0x08001858 VADC0_G0_3_IRQHandler + 0x0800185a VADC0_G1_0_IRQHandler + 0x0800185c VADC0_G1_1_IRQHandler + 0x0800185e VADC0_G1_2_IRQHandler + 0x08001860 VADC0_G1_3_IRQHandler + 0x08001862 VADC0_G2_0_IRQHandler + 0x08001864 VADC0_G2_1_IRQHandler + 0x08001866 VADC0_G2_2_IRQHandler + 0x08001868 VADC0_G2_3_IRQHandler + 0x0800186a VADC0_G3_0_IRQHandler + 0x0800186c VADC0_G3_1_IRQHandler + 0x0800186e VADC0_G3_2_IRQHandler + 0x08001870 VADC0_G3_3_IRQHandler + 0x08001872 DSD0_0_IRQHandler + 0x08001874 DSD0_1_IRQHandler + 0x08001876 DSD0_2_IRQHandler + 0x08001878 DSD0_3_IRQHandler + 0x0800187a DSD0_4_IRQHandler + 0x0800187c DSD0_5_IRQHandler + 0x0800187e DSD0_6_IRQHandler + 0x08001880 DSD0_7_IRQHandler + 0x08001882 DAC0_0_IRQHandler + 0x08001884 DAC0_1_IRQHandler + 0x08001886 CCU40_0_IRQHandler + 0x08001888 CCU40_1_IRQHandler + 0x0800188a CCU40_2_IRQHandler + 0x0800188c CCU40_3_IRQHandler + 0x0800188e CCU41_0_IRQHandler + 0x08001890 CCU41_1_IRQHandler + 0x08001892 CCU41_2_IRQHandler + 0x08001894 CCU41_3_IRQHandler + 0x08001896 CCU42_0_IRQHandler + 0x08001898 CCU42_1_IRQHandler + 0x0800189a CCU42_2_IRQHandler + 0x0800189c CCU42_3_IRQHandler + 0x0800189e CCU43_0_IRQHandler + 0x080018a0 CCU43_1_IRQHandler + 0x080018a2 CCU43_2_IRQHandler + 0x080018a4 CCU43_3_IRQHandler + 0x080018a6 CCU80_0_IRQHandler + 0x080018a8 CCU80_1_IRQHandler + 0x080018aa CCU80_2_IRQHandler + 0x080018ac CCU80_3_IRQHandler + 0x080018ae CCU81_0_IRQHandler + 0x080018b0 CCU81_1_IRQHandler + 0x080018b2 CCU81_2_IRQHandler + 0x080018b4 CCU81_3_IRQHandler + 0x080018b6 POSIF0_0_IRQHandler + 0x080018b8 POSIF0_1_IRQHandler + 0x080018ba POSIF1_0_IRQHandler + 0x080018bc POSIF1_1_IRQHandler + 0x080018be CAN0_0_IRQHandler + 0x080018c0 CAN0_1_IRQHandler + 0x080018c2 CAN0_2_IRQHandler + 0x080018c4 CAN0_3_IRQHandler + 0x080018c6 CAN0_4_IRQHandler + 0x080018c8 CAN0_5_IRQHandler + 0x080018ca CAN0_6_IRQHandler + 0x080018cc CAN0_7_IRQHandler + 0x080018ce USIC0_0_IRQHandler + 0x080018d0 USIC0_1_IRQHandler + 0x080018d2 USIC0_2_IRQHandler + 0x080018d4 USIC0_3_IRQHandler + 0x080018d6 USIC0_4_IRQHandler + 0x080018d8 USIC0_5_IRQHandler + 0x080018da USIC1_0_IRQHandler + 0x080018dc USIC1_1_IRQHandler + 0x080018de USIC1_2_IRQHandler + 0x080018e0 USIC1_3_IRQHandler + 0x080018e2 USIC1_4_IRQHandler + 0x080018e4 USIC1_5_IRQHandler + 0x080018e6 USIC2_0_IRQHandler + 0x080018e8 USIC2_1_IRQHandler + 0x080018ea USIC2_2_IRQHandler + 0x080018ec USIC2_3_IRQHandler + 0x080018ee USIC2_4_IRQHandler + 0x080018f0 USIC2_5_IRQHandler + 0x080018f2 LEDTS0_0_IRQHandler + 0x080018f4 FCE0_0_IRQHandler + 0x080018f6 GPDMA0_0_IRQHandler + 0x080018f8 SDMMC0_0_IRQHandler + 0x080018fa USB0_0_IRQHandler + 0x080018fc ETH0_0_IRQHandler + 0x080018fe GPDMA1_0_IRQHandler + .text.NvmInit 0x08001908 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x08001908 NvmInit .text.NvmWrite - 0x0800134c 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - 0x0800134c NvmWrite + 0x08001910 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x08001910 NvmWrite .text.NvmErase - 0x08001354 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - 0x08001354 NvmErase + 0x08001918 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x08001918 NvmErase .text.NvmVerifyChecksum - 0x0800135c 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - 0x0800135c NvmVerifyChecksum + 0x08001920 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x08001920 NvmVerifyChecksum .text.NvmGetUserProgBaseAddress - 0x08001364 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - 0x08001364 NvmGetUserProgBaseAddress - .text.NvmDone 0x0800136c 0x14 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - 0x0800136c NvmDone + 0x08001928 0x8 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x08001928 NvmGetUserProgBaseAddress + .text.NvmDone 0x08001930 0x14 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x08001930 NvmDone .text.TimerReset - 0x08001380 0xc ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - 0x08001380 TimerReset + 0x08001944 0xc ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + 0x08001944 TimerReset .text.TimerInit - 0x0800138c 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - 0x0800138c TimerInit + 0x08001950 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + 0x08001950 TimerInit .text.TimerUpdate - 0x080013b4 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - 0x080013b4 TimerUpdate + 0x08001978 0x1c ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + 0x08001978 TimerUpdate .text.TimerGet - 0x080013d0 0x10 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - 0x080013d0 TimerGet + 0x08001994 0x10 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + 0x08001994 TimerGet .text.UartTransmitByte - 0x080013e0 0x38 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x080019a4 0x38 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .text.UartReceiveByte - 0x08001418 0x24 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x080019dc 0x24 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .text.UartInit - 0x0800143c 0x5c ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - 0x0800143c UartInit + 0x08001a00 0x5c ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x08001a00 UartInit .text.UartTransmitPacket - 0x08001498 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - 0x08001498 UartTransmitPacket + 0x08001a5c 0x50 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x08001a5c UartTransmitPacket .text.UartReceivePacket - 0x080014e8 0xa0 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - 0x080014e8 UartReceivePacket + 0x08001aac 0xa0 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x08001aac UartReceivePacket .text.AssertFailure - 0x08001588 0x10 ..\obj\~#\~#\~#\source\assert.o - 0x08001588 AssertFailure + 0x08001b4c 0x10 ..\obj\~#\~#\~#\source\assert.o + 0x08001b4c AssertFailure .text.BackDoorCheck - 0x08001598 0x38 ..\obj\~#\~#\~#\source\backdoor.o - 0x08001598 BackDoorCheck + 0x08001b5c 0x38 ..\obj\~#\~#\~#\source\backdoor.o + 0x08001b5c BackDoorCheck .text.BackDoorInit - 0x080015d0 0x20 ..\obj\~#\~#\~#\source\backdoor.o - 0x080015d0 BackDoorInit + 0x08001b94 0x20 ..\obj\~#\~#\~#\source\backdoor.o + 0x08001b94 BackDoorInit .text.BootInit - 0x080015f0 0x1c ..\obj\~#\~#\~#\source\boot.o - 0x080015f0 BootInit + 0x08001bb4 0x1c ..\obj\~#\~#\~#\source\boot.o + 0x08001bb4 BootInit .text.BootTask - 0x0800160c 0x14 ..\obj\~#\~#\~#\source\boot.o - 0x0800160c BootTask - .text.ComInit 0x08001620 0x18 ..\obj\~#\~#\~#\source\com.o - 0x08001620 ComInit - .text.ComTask 0x08001638 0x24 ..\obj\~#\~#\~#\source\com.o - 0x08001638 ComTask - .text.ComFree 0x0800165c 0x4 ..\obj\~#\~#\~#\source\com.o - 0x0800165c ComFree + 0x08001bd0 0x14 ..\obj\~#\~#\~#\source\boot.o + 0x08001bd0 BootTask + .text.ComInit 0x08001be4 0x20 ..\obj\~#\~#\~#\source\com.o + 0x08001be4 ComInit + .text.ComTask 0x08001c04 0x38 ..\obj\~#\~#\~#\source\com.o + 0x08001c04 ComTask + .text.ComFree 0x08001c3c 0x4 ..\obj\~#\~#\~#\source\com.o + 0x08001c3c ComFree .text.ComTransmitPacket - 0x08001660 0x18 ..\obj\~#\~#\~#\source\com.o - 0x08001660 ComTransmitPacket + 0x08001c40 0x2c ..\obj\~#\~#\~#\source\com.o + 0x08001c40 ComTransmitPacket .text.ComGetActiveInterfaceMaxRxLen - 0x08001678 0x18 ..\obj\~#\~#\~#\source\com.o - 0x08001678 ComGetActiveInterfaceMaxRxLen + 0x08001c6c 0x24 ..\obj\~#\~#\~#\source\com.o + 0x08001c6c ComGetActiveInterfaceMaxRxLen .text.ComGetActiveInterfaceMaxTxLen - 0x08001690 0x18 ..\obj\~#\~#\~#\source\com.o - 0x08001690 ComGetActiveInterfaceMaxTxLen + 0x08001c90 0x24 ..\obj\~#\~#\~#\source\com.o + 0x08001c90 ComGetActiveInterfaceMaxTxLen .text.ComIsConnected - 0x080016a8 0x8 ..\obj\~#\~#\~#\source\com.o - 0x080016a8 ComIsConnected - .text.CopInit 0x080016b0 0x8 ..\obj\~#\~#\~#\source\cop.o - 0x080016b0 CopInit + 0x08001cb4 0x8 ..\obj\~#\~#\~#\source\com.o + 0x08001cb4 ComIsConnected + .text.CopInit 0x08001cbc 0x8 ..\obj\~#\~#\~#\source\cop.o + 0x08001cbc CopInit .text.CopService - 0x080016b8 0x8 ..\obj\~#\~#\~#\source\cop.o - 0x080016b8 CopService + 0x08001cc4 0x8 ..\obj\~#\~#\~#\source\cop.o + 0x08001cc4 CopService .text.XcpComputeChecksum - 0x080016c0 0x20 ..\obj\~#\~#\~#\source\xcp.o + 0x08001ccc 0x20 ..\obj\~#\~#\~#\source\xcp.o .text.XcpProtectResources - 0x080016e0 0xc ..\obj\~#\~#\~#\source\xcp.o + 0x08001cec 0xc ..\obj\~#\~#\~#\source\xcp.o .text.XcpSetCtoError - 0x080016ec 0x14 ..\obj\~#\~#\~#\source\xcp.o + 0x08001cf8 0x14 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdDisconnect - 0x08001700 0x1c ..\obj\~#\~#\~#\source\xcp.o + 0x08001d0c 0x1c ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdGetStatus - 0x0800171c 0x20 ..\obj\~#\~#\~#\source\xcp.o + 0x08001d28 0x20 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdSynch - 0x0800173c 0xc ..\obj\~#\~#\~#\source\xcp.o + 0x08001d48 0xc ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdGetId - 0x08001748 0x2c ..\obj\~#\~#\~#\source\xcp.o + 0x08001d54 0x2c ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdSetMta - 0x08001774 0x18 ..\obj\~#\~#\~#\source\xcp.o + 0x08001d80 0x18 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdBuildCheckSum - 0x0800178c 0x28 ..\obj\~#\~#\~#\source\xcp.o + 0x08001d98 0x28 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdProgramPrepare - 0x080017b4 0xc ..\obj\~#\~#\~#\source\xcp.o + 0x08001dc0 0xc ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdProgramStart - 0x080017c0 0x28 ..\obj\~#\~#\~#\source\xcp.o + 0x08001dcc 0x28 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdConnect - 0x080017e8 0x40 ..\obj\~#\~#\~#\source\xcp.o + 0x08001df4 0x40 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdUpload - 0x08001828 0x40 ..\obj\~#\~#\~#\source\xcp.o + 0x08001e34 0x40 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdShortUpload - 0x08001868 0x40 ..\obj\~#\~#\~#\source\xcp.o + 0x08001e74 0x40 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdProgramMax - 0x080018a8 0x40 ..\obj\~#\~#\~#\source\xcp.o + 0x08001eb4 0x40 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdProgram - 0x080018e8 0x5c ..\obj\~#\~#\~#\source\xcp.o + 0x08001ef4 0x5c ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdProgramClear - 0x08001944 0x28 ..\obj\~#\~#\~#\source\xcp.o + 0x08001f50 0x28 ..\obj\~#\~#\~#\source\xcp.o .text.XcpCmdProgramReset - 0x0800196c 0x18 ..\obj\~#\~#\~#\source\xcp.o + 0x08001f78 0x18 ..\obj\~#\~#\~#\source\xcp.o .text.XcpTransmitPacket - 0x08001984 0xc ..\obj\~#\~#\~#\source\xcp.o - .text.XcpInit 0x08001990 0x1c ..\obj\~#\~#\~#\source\xcp.o - 0x08001990 XcpInit + 0x08001f90 0xc ..\obj\~#\~#\~#\source\xcp.o + .text.XcpInit 0x08001f9c 0x1c ..\obj\~#\~#\~#\source\xcp.o + 0x08001f9c XcpInit .text.XcpIsConnected - 0x080019ac 0x10 ..\obj\~#\~#\~#\source\xcp.o - 0x080019ac XcpIsConnected + 0x08001fb8 0x10 ..\obj\~#\~#\~#\source\xcp.o + 0x08001fb8 XcpIsConnected .text.XcpPacketTransmitted - 0x080019bc 0x10 ..\obj\~#\~#\~#\source\xcp.o - 0x080019bc XcpPacketTransmitted + 0x08001fc8 0x10 ..\obj\~#\~#\~#\source\xcp.o + 0x08001fc8 XcpPacketTransmitted .text.XcpPacketReceived - 0x080019cc 0xe0 ..\obj\~#\~#\~#\source\xcp.o - 0x080019cc XcpPacketReceived - .text.exit 0x08001aac 0x28 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) - 0x08001aac exit + 0x08001fd8 0xe0 ..\obj\~#\~#\~#\source\xcp.o + 0x08001fd8 XcpPacketReceived + .text.exit 0x080020b8 0x28 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) + 0x080020b8 exit .text.__libc_init_array - 0x08001ad4 0x4c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) - 0x08001ad4 __libc_init_array - .text.memset 0x08001b20 0x10 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) - 0x08001b20 memset - .text._exit 0x08001b30 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) - 0x08001b30 _exit + 0x080020e0 0x4c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) + 0x080020e0 __libc_init_array + .text.memset 0x0800212c 0x10 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) + 0x0800212c memset + .text._exit 0x0800213c 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) + 0x0800213c _exit *(.init) - *fill* 0x08001b32 0x2 - .init 0x08001b34 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o - 0x08001b34 _init - .init 0x08001b38 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o + *fill* 0x0800213e 0x2 + .init 0x08002140 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o + 0x08002140 _init + .init 0x08002144 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o *(.fini) - .fini 0x08001b40 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o - 0x08001b40 _fini - .fini 0x08001b44 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o + .fini 0x0800214c 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o + 0x0800214c _fini + .fini 0x08002150 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors) @@ -5999,60 +6096,62 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- *(.dtors) *(.rodata*) .rodata.str1.4 - 0x08001b4c 0x1e ..\obj\lib\xmclib\src\xmc4_gpio.o - *fill* 0x08001b6a 0x2 + 0x08002158 0x1e ..\obj\lib\xmclib\src\xmc4_gpio.o + *fill* 0x08002176 0x2 .rodata.str1.4 - 0x08001b6c 0x1d ..\obj\lib\xmclib\src\xmc_gpio.o - *fill* 0x08001b89 0x3 + 0x08002178 0x1c ..\obj\lib\xmclib\src\xmc_can.o .rodata.str1.4 - 0x08001b8c 0x1d ..\obj\lib\xmclib\src\xmc_usic.o - *fill* 0x08001ba9 0x3 + 0x08002194 0x1d ..\obj\lib\xmclib\src\xmc_gpio.o + *fill* 0x080021b1 0x3 + .rodata.str1.4 + 0x080021b4 0x1d ..\obj\lib\xmclib\src\xmc_usic.o + *fill* 0x080021d1 0x3 .rodata.flashLayout - 0x08001bac 0xb4 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x080021d4 0xb4 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .rodata.str1.4 - 0x08001c60 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x08002288 0x28 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o 0x26 (size before relaxing) .rodata.xcpStationId - 0x08001c88 0x8 ..\obj\~#\~#\~#\source\xcp.o + 0x080022b0 0x8 ..\obj\~#\~#\~#\source\xcp.o .rodata.str1.1 - 0x08001c90 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) - *fill* 0x08001c92 0x2 + 0x080022b8 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) + *fill* 0x080022ba 0x2 .rodata._global_impure_ptr - 0x08001c94 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) - 0x08001c94 _global_impure_ptr + 0x080022bc 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) + 0x080022bc _global_impure_ptr *(.eh_frame*) - .eh_frame 0x08001c98 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o - .eh_frame 0x08001c98 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o + .eh_frame 0x080022c0 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o + .eh_frame 0x080022c0 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o -.glue_7 0x08001c9c 0x0 - .glue_7 0x08001c9c 0x0 linker stubs +.glue_7 0x080022c4 0x0 + .glue_7 0x080022c4 0x0 linker stubs -.glue_7t 0x08001c9c 0x0 - .glue_7t 0x08001c9c 0x0 linker stubs +.glue_7t 0x080022c4 0x0 + .glue_7t 0x080022c4 0x0 linker stubs -.vfp11_veneer 0x08001c9c 0x0 - .vfp11_veneer 0x08001c9c 0x0 linker stubs +.vfp11_veneer 0x080022c4 0x0 + .vfp11_veneer 0x080022c4 0x0 linker stubs -.v4_bx 0x08001c9c 0x0 - .v4_bx 0x08001c9c 0x0 linker stubs +.v4_bx 0x080022c4 0x0 + .v4_bx 0x080022c4 0x0 linker stubs -.iplt 0x08001c9c 0x0 - .iplt 0x08001c9c 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o +.iplt 0x080022c4 0x0 + .iplt 0x080022c4 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o .ARM.extab *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x08001c9c __exidx_start = . + 0x080022c4 __exidx_start = . -.ARM.exidx 0x08001c9c 0x8 +.ARM.exidx 0x080022c4 0x8 *(.ARM.exidx* .gnu.linkonce.armexidx.*) - .ARM.exidx 0x08001c9c 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o - 0x08001ca4 __exidx_end = . - 0x08001ca4 __etext = . + .ARM.exidx 0x080022c4 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o + 0x080022cc __exidx_end = . + 0x080022cc __etext = . -.rel.dyn 0x08001ca4 0x0 - .rel.iplt 0x08001ca4 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o +.rel.dyn 0x080022cc 0x0 + .rel.iplt 0x080022cc 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o -.data 0x20000000 0x6c load address 0x08001ca4 +.data 0x20000000 0x6c load address 0x080022cc 0x20000000 __data_start__ = . *(vtable) *(.data*) @@ -6080,18 +6179,18 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- 0x2000006c . = ALIGN (0x4) 0x2000006c __data_end__ = . -.jcr 0x2000006c 0x0 load address 0x08001d10 +.jcr 0x2000006c 0x0 load address 0x08002338 .jcr 0x2000006c 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o -.igot.plt 0x2000006c 0x0 load address 0x08001d10 +.igot.plt 0x2000006c 0x0 load address 0x08002338 .igot.plt 0x2000006c 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o -.no_init 0x2000006c 0x14 load address 0x08001d10 +.no_init 0x2000006c 0x14 load address 0x08002338 .no_init 0x2000006c 0x14 ..\obj\lib\system_xmc4700.o 0x2000006c SystemCoreClock 0x20000070 g_chipid -.bss 0x20000080 0x914 load address 0x08001d24 +.bss 0x20000080 0x954 load address 0x08002350 0x20000080 __bss_start__ = . *(.bss*) .bss 0x20000080 0x1c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o @@ -6101,46 +6200,49 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- 0x200000a0 0x2 ..\obj\led.o .bss.ledOn.7153 0x200000a2 0x1 ..\obj\led.o - *fill* 0x200000a3 0x1 + *fill* 0x200000a3 0x5 + .bss.transmitMsgObj + 0x200000a8 0x20 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .bss.receiveMsgObj + 0x200000c8 0x20 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o .bss.bootBlockInfo - 0x200000a4 0x404 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x200000e8 0x404 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .bss.blockInfo - 0x200004a8 0x404 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x200004ec 0x404 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .bss.millisecond_counter - 0x200008ac 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - .bss.xcpCtoRxLength.7660 - 0x200008b0 0x1 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - *fill* 0x200008b1 0x3 - .bss.xcpCtoReqPacket.7659 - 0x200008b4 0x41 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .bss.xcpCtoRxInProgress.7661 - 0x200008f5 0x1 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - *fill* 0x200008f6 0x2 - .bss.xcpCtoRxStartTime.7662 - 0x200008f8 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x200008f0 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + .bss.xcpCtoReqPacket.7661 + 0x200008f4 0x41 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .bss.xcpCtoRxLength.7662 + 0x20000935 0x1 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .bss.xcpCtoRxInProgress.7663 + 0x20000936 0x1 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + *fill* 0x20000937 0x1 + .bss.xcpCtoRxStartTime.7664 + 0x20000938 0x4 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .bss.assert_failure_line - 0x200008fc 0x4 ..\obj\~#\~#\~#\source\assert.o + 0x2000093c 0x4 ..\obj\~#\~#\~#\source\assert.o .bss.backdoorOpen - 0x20000900 0x1 ..\obj\~#\~#\~#\source\backdoor.o - *fill* 0x20000901 0x3 + 0x20000940 0x1 ..\obj\~#\~#\~#\source\backdoor.o + *fill* 0x20000941 0x3 .bss.backdoorOpenTime - 0x20000904 0x4 ..\obj\~#\~#\~#\source\backdoor.o - .bss.xcpCtoReqPacket.4270 - 0x20000908 0x40 ..\obj\~#\~#\~#\source\com.o - .bss.xcpInfo 0x20000948 0x4c ..\obj\~#\~#\~#\source\xcp.o + 0x20000944 0x4 ..\obj\~#\~#\~#\source\backdoor.o + .bss.xcpCtoReqPacket.4277 + 0x20000948 0x40 ..\obj\~#\~#\~#\source\com.o + .bss.xcpInfo 0x20000988 0x4c ..\obj\~#\~#\~#\source\xcp.o *(COMMON) - 0x20000994 __bss_end__ = . + 0x200009d4 __bss_end__ = . -.heap 0x20000998 0x0 - 0x20000998 __end__ = . - 0x20000998 end = __end__ +.heap 0x200009d8 0x0 + 0x200009d8 __end__ = . + 0x200009d8 end = __end__ *(.heap*) - .heap 0x20000998 0x0 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o - 0x20000998 __HeapLimit = . + .heap 0x200009d8 0x0 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o + 0x200009d8 __HeapLimit = . -.stack_dummy 0x20000998 0x800 +.stack_dummy 0x200009d8 0x800 *(.stack) - .stack 0x20000998 0x800 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o + .stack 0x200009d8 0x800 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o 0x20006000 __StackTop = (ORIGIN (RAM) + LENGTH (RAM)) 0x20005800 __StackLimit = (__StackTop - SIZEOF (.stack_dummy)) 0x20006000 PROVIDE (__stack, __StackTop) @@ -6186,6 +6288,7 @@ LOAD ..\obj\lib\xmclib\src\xmc_usic.o LOAD ..\obj\lib\xmclib\src\xmc_vadc.o LOAD ..\obj\lib\xmclib\src\xmc_wdt.o LOAD ..\obj\main.o +LOAD ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o LOAD ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o LOAD ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o LOAD ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o @@ -6236,53 +6339,57 @@ OUTPUT(..\bin\openblt_xmc4700.elf elf32-littlearm) .ARM.attributes 0x00000193 0x39 ..\obj\lib\xmclib\src\xmc4_scu.o .ARM.attributes - 0x000001cc 0x39 ..\obj\lib\xmclib\src\xmc_gpio.o + 0x000001cc 0x39 ..\obj\lib\xmclib\src\xmc_can.o .ARM.attributes - 0x00000205 0x39 ..\obj\lib\xmclib\src\xmc_uart.o + 0x00000205 0x39 ..\obj\lib\xmclib\src\xmc_gpio.o .ARM.attributes - 0x0000023e 0x39 ..\obj\lib\xmclib\src\xmc_usic.o + 0x0000023e 0x39 ..\obj\lib\xmclib\src\xmc_uart.o .ARM.attributes - 0x00000277 0x39 ..\obj\main.o + 0x00000277 0x39 ..\obj\lib\xmclib\src\xmc_usic.o .ARM.attributes - 0x000002b0 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + 0x000002b0 0x39 ..\obj\main.o .ARM.attributes - 0x000002e9 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + 0x000002e9 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o .ARM.attributes - 0x00000322 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + 0x00000322 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .ARM.attributes - 0x0000035b 0x1f ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o + 0x0000035b 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .ARM.attributes - 0x0000037a 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + 0x00000394 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o .ARM.attributes - 0x000003b3 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + 0x000003cd 0x1f ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o .ARM.attributes - 0x000003ec 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + 0x000003ec 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o .ARM.attributes - 0x00000425 0x39 ..\obj\~#\~#\~#\source\assert.o + 0x00000425 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o .ARM.attributes - 0x0000045e 0x39 ..\obj\~#\~#\~#\source\backdoor.o + 0x0000045e 0x39 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o .ARM.attributes - 0x00000497 0x39 ..\obj\~#\~#\~#\source\boot.o + 0x00000497 0x39 ..\obj\~#\~#\~#\source\assert.o .ARM.attributes - 0x000004d0 0x39 ..\obj\~#\~#\~#\source\com.o + 0x000004d0 0x39 ..\obj\~#\~#\~#\source\backdoor.o .ARM.attributes - 0x00000509 0x39 ..\obj\~#\~#\~#\source\cop.o + 0x00000509 0x39 ..\obj\~#\~#\~#\source\boot.o .ARM.attributes - 0x00000542 0x39 ..\obj\~#\~#\~#\source\xcp.o + 0x00000542 0x39 ..\obj\~#\~#\~#\source\com.o .ARM.attributes - 0x0000057b 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) + 0x0000057b 0x39 ..\obj\~#\~#\~#\source\cop.o .ARM.attributes - 0x000005af 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) + 0x000005b4 0x39 ..\obj\~#\~#\~#\source\xcp.o .ARM.attributes - 0x000005e3 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) + 0x000005ed 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) .ARM.attributes - 0x00000617 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) + 0x00000621 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) .ARM.attributes - 0x0000064b 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) + 0x00000655 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) .ARM.attributes - 0x0000067f 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o + 0x00000689 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) .ARM.attributes - 0x000006b3 0x22 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o + 0x000006bd 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) + .ARM.attributes + 0x000006f1 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o + .ARM.attributes + 0x00000725 0x22 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o .comment 0x00000000 0x6e .comment 0x00000000 0x6e ..\obj\hooks.o @@ -6292,10 +6399,12 @@ OUTPUT(..\bin\openblt_xmc4700.elf elf32-littlearm) .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc4_flash.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc4_gpio.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc4_scu.o + .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_can.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_gpio.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_uart.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_usic.o .comment 0x0000006e 0x6f ..\obj\main.o + .comment 0x0000006e 0x6f ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o .comment 0x0000006e 0x6f ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o .comment 0x0000006e 0x6f ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o .comment 0x0000006e 0x6f ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o @@ -6309,76 +6418,82 @@ OUTPUT(..\bin\openblt_xmc4700.elf elf32-littlearm) .comment 0x0000006e 0x6f ..\obj\~#\~#\~#\source\cop.o .comment 0x0000006e 0x6f ..\obj\~#\~#\~#\source\xcp.o -.debug_info 0x00000000 0x90ad +.debug_info 0x00000000 0xb2d8 .debug_info 0x00000000 0x318 ..\obj\hooks.o .debug_info 0x00000318 0x3db ..\obj\led.o .debug_info 0x000006f3 0x943 ..\obj\lib\system_xmc4700.o .debug_info 0x00001036 0xa38 ..\obj\lib\xmclib\src\xmc4_flash.o .debug_info 0x00001a6e 0x4cf ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_info 0x00001f3d 0x2588 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_info 0x000044c5 0x44b ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_info 0x00004910 0x8fd ..\obj\lib\xmclib\src\xmc_uart.o - .debug_info 0x0000520d 0xe63 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_info 0x00006070 0x872 ..\obj\main.o - .debug_info 0x000068e2 0x211 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - .debug_info 0x00006af3 0x999 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - .debug_info 0x0000748c 0x84 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - .debug_info 0x00007510 0xa4 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o - .debug_info 0x000075b4 0x228 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - .debug_info 0x000077dc 0x11f ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - .debug_info 0x000078fb 0x988 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .debug_info 0x00008283 0xf2 ..\obj\~#\~#\~#\source\assert.o - .debug_info 0x00008375 0x114 ..\obj\~#\~#\~#\source\backdoor.o - .debug_info 0x00008489 0x156 ..\obj\~#\~#\~#\source\boot.o - .debug_info 0x000085df 0x289 ..\obj\~#\~#\~#\source\com.o - .debug_info 0x00008868 0xb6 ..\obj\~#\~#\~#\source\cop.o - .debug_info 0x0000891e 0x78f ..\obj\~#\~#\~#\source\xcp.o + .debug_info 0x000044c5 0x1448 ..\obj\lib\xmclib\src\xmc_can.o + .debug_info 0x0000590d 0x44b ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_info 0x00005d58 0x8fd ..\obj\lib\xmclib\src\xmc_uart.o + .debug_info 0x00006655 0xe63 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_info 0x000074b8 0xa74 ..\obj\main.o + .debug_info 0x00007f2c 0xb6c ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_info 0x00008a98 0x211 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + .debug_info 0x00008ca9 0x999 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + .debug_info 0x00009642 0x84 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + .debug_info 0x000096c6 0xa4 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o + .debug_info 0x0000976a 0x228 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + .debug_info 0x00009992 0x11f ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + .debug_info 0x00009ab1 0x988 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .debug_info 0x0000a439 0xf2 ..\obj\~#\~#\~#\source\assert.o + .debug_info 0x0000a52b 0x114 ..\obj\~#\~#\~#\source\backdoor.o + .debug_info 0x0000a63f 0x156 ..\obj\~#\~#\~#\source\boot.o + .debug_info 0x0000a795 0x2fe ..\obj\~#\~#\~#\source\com.o + .debug_info 0x0000aa93 0xb6 ..\obj\~#\~#\~#\source\cop.o + .debug_info 0x0000ab49 0x78f ..\obj\~#\~#\~#\source\xcp.o -.debug_abbrev 0x00000000 0x205c +.debug_abbrev 0x00000000 0x26d7 .debug_abbrev 0x00000000 0x16d ..\obj\hooks.o .debug_abbrev 0x0000016d 0x188 ..\obj\led.o .debug_abbrev 0x000002f5 0x1c1 ..\obj\lib\system_xmc4700.o .debug_abbrev 0x000004b6 0x221 ..\obj\lib\xmclib\src\xmc4_flash.o .debug_abbrev 0x000006d7 0x196 ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_abbrev 0x0000086d 0x301 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_abbrev 0x00000b6e 0x17e ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_abbrev 0x00000cec 0x265 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_abbrev 0x00000f51 0x2bc ..\obj\lib\xmclib\src\xmc_usic.o - .debug_abbrev 0x0000120d 0x217 ..\obj\main.o - .debug_abbrev 0x00001424 0xc8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - .debug_abbrev 0x000014ec 0x1ff ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - .debug_abbrev 0x000016eb 0x45 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o - .debug_abbrev 0x00001730 0x14 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o - .debug_abbrev 0x00001744 0xca ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - .debug_abbrev 0x0000180e 0xd4 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o - .debug_abbrev 0x000018e2 0x285 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .debug_abbrev 0x00001b67 0xae ..\obj\~#\~#\~#\source\assert.o - .debug_abbrev 0x00001c15 0x7f ..\obj\~#\~#\~#\source\backdoor.o - .debug_abbrev 0x00001c94 0x63 ..\obj\~#\~#\~#\source\boot.o - .debug_abbrev 0x00001cf7 0x144 ..\obj\~#\~#\~#\source\com.o - .debug_abbrev 0x00001e3b 0x63 ..\obj\~#\~#\~#\source\cop.o - .debug_abbrev 0x00001e9e 0x1be ..\obj\~#\~#\~#\source\xcp.o + .debug_abbrev 0x00000b6e 0x3a4 ..\obj\lib\xmclib\src\xmc_can.o + .debug_abbrev 0x00000f12 0x17e ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_abbrev 0x00001090 0x265 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_abbrev 0x000012f5 0x2bc ..\obj\lib\xmclib\src\xmc_usic.o + .debug_abbrev 0x000015b1 0x246 ..\obj\main.o + .debug_abbrev 0x000017f7 0x299 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_abbrev 0x00001a90 0xc8 ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + .debug_abbrev 0x00001b58 0x1ff ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + .debug_abbrev 0x00001d57 0x45 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cpu_comp.o + .debug_abbrev 0x00001d9c 0x14 ..\obj\~#\~#\~#\source\armcm4_xmc4\gcc\cstart.o + .debug_abbrev 0x00001db0 0xca ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + .debug_abbrev 0x00001e7a 0xd4 ..\obj\~#\~#\~#\source\armcm4_xmc4\timer.o + .debug_abbrev 0x00001f4e 0x285 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .debug_abbrev 0x000021d3 0xae ..\obj\~#\~#\~#\source\assert.o + .debug_abbrev 0x00002281 0x7f ..\obj\~#\~#\~#\source\backdoor.o + .debug_abbrev 0x00002300 0x63 ..\obj\~#\~#\~#\source\boot.o + .debug_abbrev 0x00002363 0x153 ..\obj\~#\~#\~#\source\com.o + .debug_abbrev 0x000024b6 0x63 ..\obj\~#\~#\~#\source\cop.o + .debug_abbrev 0x00002519 0x1be ..\obj\~#\~#\~#\source\xcp.o -.debug_loc 0x00000000 0x324e +.debug_loc 0x00000000 0x4298 .debug_loc 0x00000000 0x2c ..\obj\hooks.o .debug_loc 0x0000002c 0xc4 ..\obj\led.o .debug_loc 0x000000f0 0xa8 ..\obj\lib\system_xmc4700.o .debug_loc 0x00000198 0x6df ..\obj\lib\xmclib\src\xmc4_flash.o .debug_loc 0x00000877 0x298 ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_loc 0x00000b0f 0xeb4 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_loc 0x000019c3 0xef ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_loc 0x00001ab2 0x277 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_loc 0x00001d29 0x580 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_loc 0x000022a9 0x6c ..\obj\main.o - .debug_loc 0x00002315 0xdb ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o - .debug_loc 0x000023f0 0x727 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o - .debug_loc 0x00002b17 0xa5 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o - .debug_loc 0x00002bbc 0x1e6 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o - .debug_loc 0x00002da2 0x42 ..\obj\~#\~#\~#\source\assert.o - .debug_loc 0x00002de4 0x42 ..\obj\~#\~#\~#\source\com.o - .debug_loc 0x00002e26 0x428 ..\obj\~#\~#\~#\source\xcp.o + .debug_loc 0x000019c3 0xd21 ..\obj\lib\xmclib\src\xmc_can.o + .debug_loc 0x000026e4 0xef ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_loc 0x000027d3 0x277 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_loc 0x00002a4a 0x580 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_loc 0x00002fca 0xc8 ..\obj\main.o + .debug_loc 0x00003092 0x284 ..\obj\~#\~#\~#\source\armcm4_xmc4\can.o + .debug_loc 0x00003316 0xdb ..\obj\~#\~#\~#\source\armcm4_xmc4\cpu.o + .debug_loc 0x000033f1 0x727 ..\obj\~#\~#\~#\source\armcm4_xmc4\flash.o + .debug_loc 0x00003b18 0xa5 ..\obj\~#\~#\~#\source\armcm4_xmc4\nvm.o + .debug_loc 0x00003bbd 0x1e6 ..\obj\~#\~#\~#\source\armcm4_xmc4\uart.o + .debug_loc 0x00003da3 0x42 ..\obj\~#\~#\~#\source\assert.o + .debug_loc 0x00003de5 0x8b ..\obj\~#\~#\~#\source\com.o + .debug_loc 0x00003e70 0x428 ..\obj\~#\~#\~#\source\xcp.o -.debug_aranges 0x00000000 0xa10 +.debug_aranges 0x00000000 0xb18 .debug_aranges 0x00000000 0x30 ..\obj\hooks.o .debug_aranges @@ -6392,229 +6507,247 @@ OUTPUT(..\bin\openblt_xmc4700.elf elf32-littlearm) .debug_aranges 0x000001b0 0x3b0 ..\obj\lib\xmclib\src\xmc4_scu.o .debug_aranges - 0x00000560 0x28 ..\obj\lib\xmclib\src\xmc_gpio.o + 0x00000560 0xd8 ..\obj\lib\xmclib\src\xmc_can.o .debug_aranges - 0x00000588 0x50 ..\obj\lib\xmclib\src\xmc_uart.o + 0x00000638 0x28 ..\obj\lib\xmclib\src\xmc_gpio.o .debug_aranges - 0x000005d8 0x80 ..\obj\lib\xmclib\src\xmc_usic.o + 0x00000660 0x50 ..\obj\lib\xmclib\src\xmc_uart.o .debug_aranges - 0x00000658 0x30 ..\obj\main.o + 0x000006b0 0x80 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+S315080022DC00000000000000000000000000000000E4 +S315080022EC00000000B82200080000000000000000F2 +S315080022FC00000000000000000000000000000000C4 +S3150800230C00000000000000000000000000000000B3 +S3150800231C00000000000000000000000000000000A3 +S3110800232C0000000025020008010200085D +S315080023380000000000000000000000000000000087 +S309080023480000000083 S70508000000F2 diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/blt_conf.h b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/blt_conf.h index 407b7adc..9554cecc 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/blt_conf.h +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/blt_conf.h @@ -56,6 +56,33 @@ /**************************************************************************************** * C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N ****************************************************************************************/ +/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE + * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed + * in bits/second. Two CAN messages are reserved for communication with the host. The + * message identifier for sending data from the target to the host is configured with + * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with + * BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data + * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and + * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more + * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the + * CAN controller channel. + * + */ +/** \brief Enable/disable CAN transport layer. */ +#define BOOT_COM_CAN_ENABLE (1) +/** \brief Configure the desired CAN baudrate. */ +#define BOOT_COM_CAN_BAUDRATE (500000) +/** \brief Configure CAN message ID target->host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (1) + /* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed * in bits/second. The maximum amount of data bytes in a message for data transmission diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/xmc4500.svd b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/xmc4700.svd similarity index 68% rename from Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/xmc4500.svd rename to Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/xmc4700.svd index 6a7370da..5411b7ad 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/xmc4500.svd +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/cfg/xmc4700.svd @@ -1,95720 +1,123178 @@ - - - - - - - - - - - Infineon - XMC4500 - 1.2.0 (Reference Manual v1.2) - SVD file - - CM4 - r2p0 - little - true - true - 6 - false - - 8 - 32 - - - PPB - Cortex-M4 Private Peripheral Block - 0xE000E000 - - 0x0 - 0x1000 - registers - - - - ACTLR - Auxiliary Control Register - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - DISMCYCINT - Disable load/store multiple - 0 - 0 - read-write - - - DISDEFWBUF - Disable write buffer - 1 - 1 - read-write - - - DISFOLD - Disable IT folding - 2 - 2 - read-write - - - DISFPCA - Disable FPCA update - 8 - 8 - read-write - - - DISOOFP - Disable out of order FP execution - 9 - 9 - read-write - - - - - SYST_CSR - SysTick Control and Status Register - 0x010 - 32 - 0x00000004 - 0xFFFFFFFF - - - ENABLE - Enable - 0 - 0 - read-write - - - value1 - counter disabled - 0b0 - - - value2 - counter enabled. - 0b1 - - - - - TICKINT - Tick Interrupt Enable - 1 - 1 - read-write - - - value1 - counting down to zero does not assert the SysTick exception request - 0b0 - - - value2 - counting down to zero to asserts the SysTick exception request. - 0b1 - - - - - CLKSOURCE - Indicates the clock source: - 2 - 2 - read-write - - - value1 - external clock - 0b0 - - - value2 - processor clock. - 0b1 - - - - - COUNTFLAG - Counter Flag - 16 - 16 - read-write - - - - - SYST_RVR - SysTick Reload Value Register - 0x014 - 32 - 0x00000000 - 0x00000000 - - - RELOAD - Reload Value - 0 - 23 - read-write - - - - - SYST_CVR - SysTick Current Value Register - 0x018 - 32 - 0x00000000 - 0x00000000 - - - CURRENT - Current Value - 0 - 23 - read-write - - - - - SYST_CALIB - SysTick Calibration Value Register r - 0x01C - 32 - 0xC0000000 - 0xFFFFFFFF - - - TENMS - Ten Milliseconds Reload Value - 0 - 23 - read-write - - - SKEW - Ten Milliseconds Skewed - 30 - 30 - read-write - - - value1 - TENMS value is exact - 0b0 - - - value2 - TENMS value is inexact, or not given. - 0b1 - - - - - NOREF - No Reference Clock - 31 - 31 - read-write - - - value1 - reference clock provided - 0b0 - - - value2 - no reference clock provided. - 0b1 - - - - - - - NVIC_ISER0 - Interrupt Set-enable Register 0 - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISER1 - Interrupt Set-enable Register 1 - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISER2 - Interrupt Set-enable Register 2 - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISER3 - Interrupt Set-enable Register 3 - 0x10C - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER0 - Interrupt Clear-enable Register 0 - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER1 - Interrupt Clear-enable Register 1 - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER2 - Interrupt Clear-enable Register 2 - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER3 - Interrupt Clear-enable Register 3 - 0x18C - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISPR0 - Interrupt Set-pending Register 0 - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ISPR1 - Interrupt Set-pending Register 1 - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ISPR2 - Interrupt Set-pending Register 2 - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ISPR3 - Interrupt Set-pending Register 3 - 0x20C - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR0 - Interrupt Clear-pending Register 0 - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR1 - Interrupt Clear-pending Register 1 - 0x284 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR2 - Interrupt Clear-pending Register 2 - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR3 - Interrupt Clear-pending Register 3 - 0x28C - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_IABR0 - Interrupt Active Bit Register 0 - 0x300 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IABR1 - Interrupt Active Bit Register 1 - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IABR2 - Interrupt Active Bit Register 2 - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IABR3 - Interrupt Active Bit Register 3 - 0x30C - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IPR0 - Interrupt Priority Register 0 - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR1 - Interrupt Priority Register 1 - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR2 - Interrupt Priority Register 2 - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR3 - Interrupt Priority Register 3 - 0x40C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR4 - Interrupt Priority Register 4 - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR5 - Interrupt Priority Register 5 - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR6 - Interrupt Priority Register 6 - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR7 - Interrupt Priority Register 7 - 0x41C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR8 - Interrupt Priority Register 8 - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR9 - Interrupt Priority Register 9 - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR10 - Interrupt Priority Register 10 - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR11 - Interrupt Priority Register 11 - 0x42C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR12 - Interrupt Priority Register 12 - 0x430 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR13 - Interrupt Priority Register 13 - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR14 - Interrupt Priority Register 14 - 0x438 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR15 - Interrupt Priority Register 15 - 0x43C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR16 - Interrupt Priority Register 16 - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR17 - Interrupt Priority Register 17 - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR18 - Interrupt Priority Register 18 - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR19 - Interrupt Priority Register 19 - 0x44C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR20 - Interrupt Priority Register 20 - 0x450 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR21 - Interrupt Priority Register 21 - 0x454 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR22 - Interrupt Priority Register 22 - 0x458 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR23 - Interrupt Priority Register 23 - 0x45C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR24 - Interrupt Priority Register 24 - 0x460 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR25 - Interrupt Priority Register 25 - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR26 - Interrupt Priority Register 26 - 0x468 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR27 - Interrupt Priority Register 27 - 0x46C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - CPUID - CPUID Base Register - 0xD00 - 32 - 0x410FC241 - 0xFFFFFFFF - - - Revision - Revision number - 0 - 3 - read-only - - - value1 - Patch 1 - 0x1 - - - - - PartNo - Part number of the processor - 4 - 15 - read-only - - - value1 - Cortex-M4 - 0xC24 - - - - - Constant - Reads as 0xF - 16 - 19 - read-only - - - Variant - Variant number - 20 - 23 - read-only - - - value1 - Revision 0 - 0x0 - - - - - Implementer - Implementer code - 24 - 31 - read-only - - - value1 - ARM - 0x41 - - - - - - - ICSR - Interrupt Control and State Register - 0xD04 - 32 - 0x00000000 - 0xFFFFFFFF - - - VECTACTIVE - Active exception number - 0 - 8 - read-only - - - value1 - Thread mode - 0x00 - - - - - RETTOBASE - Return to Base - 11 - 11 - read-only - - - value1 - there are preempted active exceptions to execute - 0b0 - - - value2 - there are no active exceptions, or the currently-executing exception is the only active exception. - 0b1 - - - - - VECTPENDING - Vector Pending - 12 - 17 - read-only - - - value1 - no pending exceptions - 0x0 - - - - - ISRPENDING - Interrupt pending flag - 22 - 22 - read-only - - - value1 - interrupt not pending - 0b0 - - - value2 - interrupt pending. - 0b1 - - - - - Res - Reserved - 23 - 23 - read-only - - - PENDSTCLR - SysTick exception clear-pending bit - 25 - 25 - write-only - - - value1 - no effect - 0b0 - - - value2 - removes the pending state from the SysTick exception. - 0b1 - - - - - PENDSTSET - SysTick exception set-pending bit - 26 - 26 - read-write - - - value1 - no effect - 0b0 - - - value2 - changes SysTick exception state to pending. - 0b1 - - - - - PENDSVCLR - PendSV clear-pending bit - 27 - 27 - write-only - - - value1 - no effect - 0b0 - - - value2 - removes the pending state from the PendSV exception. - 0b1 - - - - - PENDSVSET - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending., - 28 - 28 - read-write - - - NMIPENDSET - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending., - 31 - 31 - read-write - - - - - VTOR - Vector Table Offset Register - 0xD08 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBLOFF - Vector table base offset field - 10 - 31 - read-write - - - - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - 32 - 0xFA050000 - 0xFFFFFFFF - - - VECTRESET - Reserved for Debug use. - 0 - 0 - write-only - - - VECTCLRACTIVE - Reserved for Debug use. - 1 - 1 - write-only - - - SYSRESETREQ - System reset request - 2 - 2 - write-only - - - value1 - no system reset request - 0b0 - - - value2 - asserts a signal to the outer system that requests a reset. - 0b1 - - - - - PRIGROUP - Interrupt priority grouping field - 8 - 10 - read-write - - - ENDIANNESS - Data endianness bit - 15 - 15 - read-only - - - value1 - Little-endian - 0b0 - - - value2 - Big-endian. - 0b1 - - - - - VECTKEY - Register key - 16 - 31 - read-write - - - - - SCR - System Control Register - 0xD10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLEEPONEXIT - Sleep on Exit - 1 - 1 - read-write - - - value1 - do not sleep when returning to Thread mode. - 0b0 - - - value2 - enter sleep, or deep sleep, on return from an ISR. - 0b1 - - - - - SLEEPDEEP - Sleep or Deep Sleep - 2 - 2 - read-write - - - value1 - sleep - 0b0 - - - value2 - deep sleep - 0b1 - - - - - SEVONPEND - Send Event on Pending bit: - 4 - 4 - read-write - - - value1 - only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded - 0b0 - - - value2 - enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - 0b1 - - - - - - - CCR - Configuration and Control Register - 0xD14 - 32 - 0x00000200 - 0xFFFFFFFF - - - NONBASETHRDENA - Non Base Thread Mode Enable - 0 - 0 - read-write - - - value1 - processor can enter Thread mode only when no exception is active. - 0b0 - - - value2 - processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. . - 0b1 - - - - - USERSETMPEND - User Set Pending Enable - 1 - 1 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - UNALIGN_TRP - Unaligned Access Trap Enable - 3 - 3 - read-write - - - value1 - do not trap unaligned halfword and word accesses - 0b0 - - - value2 - trap unaligned halfword and word accesses. - 0b1 - - - - - DIV_0_TRP - Divide by Zero Trap Enable - 4 - 4 - read-write - - - value1 - do not trap divide by 0 - 0b0 - - - value2 - trap divide by 0. - 0b1 - - - - - BFHFNMIGN - Bus Fault Hard Fault and NMI Ignore - 8 - 8 - read-write - - - value1 - data bus faults caused by load and store instructions cause a lock-up - 0b0 - - - value2 - handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. - 0b1 - - - - - STKALIGN - Stack Alignment - 9 - 9 - read-write - - - value1 - 4-byte aligned - 0b0 - - - value2 - 8-byte aligned. - 0b1 - - - - - - - SHPR1 - System Handler Priority Register 1 - 0xD18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_4 - Priority of system handler 4, MemManage - 0 - 7 - read-write - - - PRI_5 - Priority of system handler 5, BusFault - 8 - 15 - read-write - - - PRI_6 - Priority of system handler 6, UsageFault - 16 - 23 - read-write - - - - - SHPR2 - System Handler Priority Register 2 - 0xD1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_11 - Priority of system handler 11, SVCall - 24 - 31 - read-write - - - - - SHPR3 - System Handler Priority Register 3 - 0xD20 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_14 - Priority of system handler 14 - 16 - 23 - read-write - - - PRI_15 - Priority of system handler 15 - 24 - 31 - read-write - - - - - SHCSR - System Handler Control and State Register - 0xD24 - 32 - 0x00000000 - 0xFFFFFFFF - - - MEMFAULTACT - MemManage exception active bit - 0 - 0 - read-write - - - BUSFAULTACT - BusFault exception active bit - 1 - 1 - read-write - - - USGFAULTACT - UsageFault exception active bit - 3 - 3 - read-write - - - SVCALLACT - SVCall active bit - 7 - 7 - read-write - - - MONITORACT - Debug monitor active bit - 8 - 8 - read-write - - - PENDSVACT - PendSV exception active bit - 10 - 10 - read-write - - - SYSTICKACT - SysTick exception active bit - 11 - 11 - read-write - - - USGFAULTPENDED - UsageFault exception pending bit - 12 - 12 - read-write - - - MEMFAULTPENDED - MemManage exception pending bit - 13 - 13 - read-write - - - BUSFAULTPENDED - BusFault exception pending bit - 14 - 14 - read-write - - - SVCALLPENDED - SVCall pending bit - 15 - 15 - read-write - - - MEMFAULTENA - MemManage enable bit - 16 - 16 - read-write - - - BUSFAULTENA - BusFault enable bit - 17 - 17 - read-write - - - USGFAULTENA - UsageFault enable bit - 18 - 18 - read-write - - - - - CFSR - Configurable Fault Status Register - 0xD28 - 32 - 0x00000000 - 0xFFFFFFFF - - - IACCVIOL - Instruction access violation flag - 0 - 0 - read-write - - - value1 - no instruction access violation fault - 0b0 - - - value2 - the processor attempted an instruction fetch from a location that does not permit execution. - 0b1 - - - - - DACCVIOL - Data access violation flag - 1 - 1 - read-write - - - value1 - no data access violation fault - 0b0 - - - value2 - the processor attempted a load or store at a location that does not permit the operation. - 0b1 - - - - - MUNSTKERR - MemManage fault on unstacking for a return from exception - 3 - 3 - read-write - - - value1 - no unstacking fault - 0b0 - - - value2 - unstack for an exception return has caused one or more access violations. - 0b1 - - - - - MSTKERR - MemManage fault on stacking for exception entry - 4 - 4 - read-write - - - value1 - no stacking fault - 0b0 - - - value2 - stacking for an exception entry has caused one or more access violations. - 0b1 - - - - - MLSPERR - MemManage fault during floating point lazy state preservation - 5 - 5 - read-write - - - value1 - No MemManage fault occurred during floating-point lazy state preservation - 0b0 - - - value2 - A MemManage fault occurred during floating-point lazy state preservation - 0b1 - - - - - MMARVALID - MemManage Fault Address Register (MMFAR) valid flag - 7 - 7 - read-write - - - value1 - value in MMAR is not a valid fault address - 0b0 - - - value2 - MMAR holds a valid fault address. - 0b1 - - - - - IBUSERR - Instruction bus error - 8 - 8 - read-write - - - value1 - no instruction bus error - 0b0 - - - value2 - instruction bus error. - 0b1 - - - - - PRECISERR - Precise data bus error - 9 - 9 - read-write - - - value1 - no precise data bus error - 0b0 - - - value2 - a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. - 0b1 - - - - - IMPRECISERR - Imprecise data bus error - 10 - 10 - read-write - - - value1 - no imprecise data bus error - 0b0 - - - value2 - a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. - 0b1 - - - - - UNSTKERR - BusFault on unstacking for a return from exception - 11 - 11 - read-write - - - value1 - no unstacking fault - 0b0 - - - value2 - stacking for an exception entry has caused one or more BusFaults. - 0b1 - - - - - STKERR - BusFault on stacking for exception entry - 12 - 12 - read-write - - - value1 - no stacking fault - 0b0 - - - value2 - stacking for an exception entry has caused one or more BusFaults. - 0b1 - - - - - LSPERR - BusFault during floating point lazy state preservation - 13 - 13 - read-write - - - value1 - No bus fault occurred during floating-point lazy state preservation. - 0b0 - - - value2 - A bus fault occurred during floating-point lazy state preservation - 0b1 - - - - - BFARVALID - BusFault Address Register (BFAR) valid flag - 15 - 15 - read-write - - - value1 - value in BFAR is not a valid fault address - 0b0 - - - value2 - BFAR holds a valid fault address. - 0b1 - - - - - UNDEFINSTR - Undefined instruction UsageFault - 16 - 16 - read-write - - - value1 - no undefined instruction UsageFault - 0b0 - - - value2 - the processor has attempted to execute an undefined instruction. - 0b1 - - - - - INVSTATE - Invalid state UsageFault - 17 - 17 - read-write - - - value1 - no invalid state UsageFault - 0b0 - - - value2 - the processor has attempted to execute an instruction that makes illegal use of the EPSR. - 0b1 - - - - - INVPC - Invalid PC load UsageFault - 18 - 18 - read-write - - - value1 - no invalid PC load UsageFault - 0b0 - - - value2 - the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. - 0b1 - - - - - NOCP - No coprocessor UsageFault - 19 - 19 - read-write - - - value1 - no UsageFault caused by attempting to access a coprocessor - 0b0 - - - value2 - the processor has attempted to access a coprocessor. - 0b1 - - - - - UNALIGNED - Unaligned access UsageFault - 24 - 24 - read-write - - - value1 - no unaligned access fault, or unaligned access trapping not enabled - 0b0 - - - value2 - the processor has made an unaligned memory access. - 0b1 - - - - - DIVBYZERO - Divide by zero UsageFault - 25 - 25 - read-write - - - value1 - no divide by zero fault, or divide by zero trapping not enabled - 0b0 - - - value2 - the processor has executed an SDIV or UDIV instruction with a divisor of 0 - 0b1 - - - - - - - HFSR - HardFault Status Register - 0xD2C - 32 - 0x00000000 - 0xFFFFFFFF - - - VECTTBL - BusFault on vector table read - 1 - 1 - read-write - - - value1 - no BusFault on vector table read - 0b0 - - - value2 - BusFault on vector table read - 0b1 - - - - - FORCED - Forced HardFault - 30 - 30 - read-write - - - value1 - no forced HardFault - 0b0 - - - value2 - forced HardFault. - 0b1 - - - - - DEBUGEVT - Reserved for Debug use - 31 - 31 - read-write - - - - - MMFAR - MemManage Fault Address Register - 0xD34 - 32 - 0x00000000 - 0x00000000 - - - ADDRESS - Address causing the fault - 0 - 31 - read-write - - - - - BFAR - BusFault Address Register - 0xD38 - 32 - 0x00000000 - 0x00000000 - - - ADDRESS - Address causing the fault - 0 - 31 - read-write - - - - - AFSR - Auxiliary Fault Status Register - 0xD3C - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Reserved - 0 - 31 - read-write - - - - - CPACR - Coprocessor Access Control Register - 0xD88 - 32 - 0x00000000 - 0xFFFFFFFF - - - CP10 - Access privileges for coprocessor 10 - 20 - 21 - read-write - - - value1 - Access denied. Any attempted access generates a NOCP UsageFault. - 0b00 - - - value2 - Privileged access only. An unprivileged access generates a NOCP fault. - 0b01 - - - value3 - Reserved. The result of any access is Unpredictable. - 0b10 - - - value4 - Full access. - 0b11 - - - - - CP11 - Access privileges for coprocessor 11 - 22 - 23 - read-write - - - value1 - Access denied. Any attempted access generates a NOCP UsageFault. - 0b00 - - - value2 - Privileged access only. An unprivileged access generates a NOCP fault. - 0b01 - - - value3 - Reserved. The result of any access is Unpredictable. - 0b10 - - - value4 - Full access. - 0b11 - - - - - - - MPU_TYPE - MPU Type Register - 0xD90 - 32 - 0x00000800 - 0xFFFFFFFF - - - SEPARATE - Support for unified or separate instruction and date memory maps - 0 - 0 - read-only - - - DREGION - Number of supported MPU data regions - 8 - 15 - read-only - - - IREGION - Number of supported MPU instruction regions - 16 - 23 - read-only - - - - - MPU_CTRL - MPU Control Register - 0xD94 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Enable MPU - 0 - 0 - read-write - - - value1 - MPU disabled - 0b0 - - - value2 - MPU enabled. - 0b1 - - - - - HFNMIENA - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers - 1 - 1 - read-write - - - value1 - MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit - 0b0 - - - value2 - the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. - 0b1 - - - - - PRIVDEFENA - Enables privileged software access to the default memory map - 2 - 2 - read-write - - - value1 - If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. - 0b0 - - - value2 - If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - 0b1 - - - - - - - MPU_RNR - MPU Region Number Register - 0xD98 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - Region - 0 - 7 - read-write - - - - - MPU_RBAR - MPU Region Base Address Register - 0xD9C - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR - MPU Region Attribute and Size Register - 0xDA0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - MPU_RBAR_A1 - MPU Region Base Address Register A1 - 0xDA4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR_A1 - MPU Region Attribute and Size Register A1 - 0xDA8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - MPU_RBAR_A2 - MPU Region Base Address Register A2 - 0xDAC - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR_A2 - MPU Region Attribute and Size Register A2 - 0xDB0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - MPU_RBAR_A3 - MPU Region Base Address Register A3 - 0xDB4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR_A3 - MPU Region Attribute and Size Register A3 - 0xDB8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - STIR - Software Trigger Interrupt Register - 0xF00 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTID - Interrupt ID of the interrupt to trigger - 0 - 8 - write-only - - - - - FPCCR - Floating-point Context Control Register - 0xF34 - 32 - 0x00000000 - 0xFFFFFFFF - - - LSPACT - Lazy State Preservation Active - 0 - 0 - read-write - - - value1 - Lazy state preservation is not active. - 0b0 - - - value2 - Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. - 0b1 - - - - - USER - User allocated Stack Frame - 1 - 1 - read-write - - - value1 - Privilege level was not user when the floating-point stack frame was allocated. - 0b0 - - - value2 - Privilege level was user when the floating-point stack frame was allocated. - 0b1 - - - - - THREAD - Thread Mode allocated Stack Frame - 3 - 3 - read-write - - - value1 - Mode was not Thread Mode when the floating-point stack frame was allocated. - 0b0 - - - value2 - Mode was Thread Mode when the floating-point stack frame was allocated. - 0b1 - - - - - HFRDY - HardFault Ready - 4 - 4 - read-write - - - value1 - Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. - 0b0 - - - value2 - Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. - 0b1 - - - - - MMRDY - MemManage Ready - 5 - 5 - read-write - - - value1 - MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. - 0b0 - - - value2 - MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. - 0b1 - - - - - BFRDY - BusFault Ready - 6 - 6 - read-write - - - value1 - BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. - 0b0 - - - value2 - BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. - 0b1 - - - - - MONRDY - Monitor Ready - 8 - 8 - read-write - - - value1 - Debug Monitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. - 0b0 - - - value2 - Debug Monitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. - 0b1 - - - - - LSPEN - Lazy State Preservation Enabled - 30 - 30 - read-write - - - value1 - Disable automatic lazy state preservation for floating-point context. - 0b0 - - - value2 - Enable automatic lazy state preservation for floating-point context. - 0b1 - - - - - ASPEN - Automatic State Preservation - 31 - 31 - read-write - - - value1 - Disable CONTROL setting on execution of a floating-point instruction. - 0b0 - - - value2 - Enable CONTROL setting on execution of a floating-point instruction. - 0b1 - - - - - - - FPCAR - Floating-point Context Address Register - 0xF38 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRESS - Address - 3 - 31 - read-write - - - - - FPDSCR - Floating-point Default Status Control Register - 0xF3C - 32 - 0x00000000 - 0xFFFFFFFF - - - RMode - Default value for FPSCR.RMode - 22 - 23 - read-write - - - FZ - Default value for FPSCR.FZ - 24 - 24 - read-write - - - DN - Default value for FPSCR.DN - 25 - 25 - read-write - - - AHP - Default value for FPSCR.AHP - 26 - 26 - read-write - - - - - - - DLR - DMA Line Router - 0x50004900 - - 0x0 - 0x0100 - registers - - - - OVRSTAT - Overrun Status - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - LN0 - Line 0 Overrun Status - 0 - 0 - read-only - - - LN1 - Line 1 Overrun Status - 1 - 1 - read-only - - - LN2 - Line 2 Overrun Status - 2 - 2 - read-only - - - LN3 - Line 3 Overrun Status - 3 - 3 - read-only - - - LN4 - Line 4 Overrun Status - 4 - 4 - read-only - - - LN5 - Line 5 Overrun Status - 5 - 5 - read-only - - - LN6 - Line 6 Overrun Status - 6 - 6 - read-only - - - LN7 - Line 7 Overrun Status - 7 - 7 - read-only - - - LN8 - Line 8 Overrun Status - 8 - 8 - read-only - - - LN9 - Line 9 Overrun Status - 9 - 9 - read-only - - - LN10 - Line 10 Overrun Status - 10 - 10 - read-only - - - LN11 - Line 11 Overrun Status - 11 - 11 - read-only - - - - - OVRCLR - Overrun Clear - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - LN0 - Line 0 Overrun Status Clear - 0 - 0 - write-only - - - LN1 - Line 1 Overrun Status Clear - 1 - 1 - write-only - - - LN2 - Line 2 Overrun Status Clear - 2 - 2 - write-only - - - LN3 - Line 3 Overrun Status Clear - 3 - 3 - write-only - - - LN4 - Line 4 Overrun Status Clear - 4 - 4 - write-only - - - LN5 - Line 5 Overrun Status Clear - 5 - 5 - write-only - - - LN6 - Line 6 Overrun Status Clear - 6 - 6 - write-only - - - LN7 - Line 7 Overrun Status Clear - 7 - 7 - write-only - - - LN8 - Line 8 Overrun Status Clear - 8 - 8 - write-only - - - LN9 - Line 9 Overrun Status Clear - 9 - 9 - write-only - - - LN10 - Line 10 Overrun Status Clear - 10 - 10 - write-only - - - LN11 - Line 11 Overrun Status Clear - 11 - 11 - write-only - - - - - SRSEL0 - Service Request Selection 0 - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RS0 - Request Source for Line 0 - 0 - 3 - read-write - - - RS1 - Request Source for Line 1 - 4 - 7 - read-write - - - RS2 - Request Source for Line 2 - 8 - 11 - read-write - - - RS3 - Request Source for Line 3 - 12 - 15 - read-write - - - RS4 - Request Source for Line 4 - 16 - 19 - read-write - - - RS5 - Request Source for Line 5 - 20 - 23 - read-write - - - RS6 - Request Source for Line 6 - 24 - 27 - read-write - - - RS7 - Request Source for Line 7 - 28 - 31 - read-write - - - - - SRSEL1 - Service Request Selection 1 - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - RS8 - Request Source for Line 8 - 0 - 3 - read-write - - - RS9 - Request Source for Line 9 - 4 - 7 - read-write - - - RS10 - Request Source for Line 10 - 8 - 11 - read-write - - - RS11 - Request Source for Line 11 - 12 - 15 - read-write - - - - - LNEN - Line Enable - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - LN0 - Line 0 Enable - 0 - 0 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN1 - Line 1 Enable - 1 - 1 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN2 - Line 2 Enable - 2 - 2 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN3 - Line 3 Enable - 3 - 3 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN4 - Line 4 Enable - 4 - 4 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN5 - Line 5 Enable - 5 - 5 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN6 - Line 6 Enable - 6 - 6 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN7 - Line 7 Enable - 7 - 7 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN8 - Line 8 Enable - 8 - 8 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN9 - Line 9 Enable - 9 - 9 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN10 - Line 10 Enable - 10 - 10 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN11 - Line 11 Enable - 11 - 11 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - - - - - ERU0 - Event Request Unit 0 - ERU - ERU - 0x50004800 - - 0x0 - 0x0100 - registers - - - - EXISEL - Event Input Select - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - EXS0A - Event Source Select for A0 (ERS0) - 0 - 1 - read-write - - - value1 - Input ERU_0A0 is selected - 0b00 - - - value2 - Input ERU_0A1 is selected - 0b01 - - - value3 - Input ERU_0A2 is selected - 0b10 - - - value4 - Input ERU_0A3 is selected - 0b11 - - - - - EXS0B - Event Source Select for B0 (ERS0) - 2 - 3 - read-write - - - value1 - Input ERU_0B0 is selected - 0b00 - - - value2 - Input ERU_0B1 is selected - 0b01 - - - value3 - Input ERU_0B2 is selected - 0b10 - - - value4 - Input ERU_0B3 is selected - 0b11 - - - - - EXS1A - Event Source Select for A1 (ERS1) - 4 - 5 - read-write - - - value1 - Input ERU_1A0 is selected - 0b00 - - - value2 - Input ERU_1A1 is selected - 0b01 - - - value3 - Input ERU_1A2 is selected - 0b10 - - - value4 - Input ERU_1A3 is selected - 0b11 - - - - - EXS1B - Event Source Select for B1 (ERS1) - 6 - 7 - read-write - - - value1 - Input ERU_1B0 is selected - 0b00 - - - value2 - Input ERU_1B1 is selected - 0b01 - - - value3 - Input ERU_1B2 is selected - 0b10 - - - value4 - Input ERU_1B3 is selected - 0b11 - - - - - EXS2A - Event Source Select for A2 (ERS2) - 8 - 9 - read-write - - - value1 - Input ERU_2A0 is selected - 0b00 - - - value2 - Input ERU_2A1 is selected - 0b01 - - - value3 - Input ERU_2A2 is selected - 0b10 - - - value4 - Input ERU_2A3 is selected - 0b11 - - - - - EXS2B - Event Source Select for B2 (ERS2) - 10 - 11 - read-write - - - value1 - Input ERU_2B0 is selected - 0b00 - - - value2 - Input ERU_2B1 is selected - 0b01 - - - value3 - Input ERU_2B2 is selected - 0b10 - - - value4 - Input ERU_2B3 is selected - 0b11 - - - - - EXS3A - Event Source Select for A3 (ERS3) - 12 - 13 - read-write - - - value1 - Input ERU_3A0 is selected - 0b00 - - - value2 - Input ERU_3A1 is selected - 0b01 - - - value3 - Input ERU_3A2 is selected - 0b10 - - - value4 - Input ERU_3A3 is selected - 0b11 - - - - - EXS3B - Event Source Select for B3 (ERS3) - 14 - 15 - read-write - - - value1 - Input ERU_3B0 is selected - 0b00 - - - value2 - Input ERU_3B1 is selected - 0b01 - - - value3 - Input ERU_3B2 is selected - 0b10 - - - value4 - Input ERU_3B3 is selected - 0b11 - - - - - - - 4 - 4 - EXICON[%s] - Event Input Control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PE - Output Trigger Pulse Enable for ETLx - 0 - 0 - read-write - - - value1 - The trigger pulse generation is disabled - 0b0 - - - value2 - The trigger pulse generation is enabled - 0b1 - - - - - LD - Rebuild Level Detection for Status Flag for ETLx - 1 - 1 - read-write - - - value1 - The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software. - 0b0 - - - value2 - The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0. - 0b1 - - - - - RE - Rising Edge Detection Enable ETLx - 2 - 2 - read-write - - - value1 - A rising edge is not considered as edge event - 0b0 - - - value2 - A rising edge is considered as edge event - 0b1 - - - - - FE - Falling Edge Detection Enable ETLx - 3 - 3 - read-write - - - value1 - A falling edge is not considered as edge event - 0b0 - - - value2 - A falling edge is considered as edge event - 0b1 - - - - - OCS - Output Channel Select for ETLx Output Trigger Pulse - 4 - 6 - read-write - - - value1 - Trigger pulses are sent to OGU0 - 0b000 - - - value2 - Trigger pulses are sent to OGU1 - 0b001 - - - value3 - Trigger pulses are sent to OGU2 - 0b010 - - - value4 - Trigger pulses are sent to OGU3 - 0b011 - - - - - FL - Status Flag for ETLx - 7 - 7 - read-write - - - value1 - The enabled edge event has not been detected - 0b0 - - - value2 - The enabled edge event has been detected - 0b1 - - - - - SS - Input Source Select for ERSx - 8 - 9 - read-write - - - value1 - Input A without additional combination - 0b00 - - - value2 - Input B without additional combination - 0b01 - - - value3 - Input A OR input B - 0b10 - - - value4 - Input A AND input B - 0b11 - - - - - NA - Input A Negation Select for ERSx - 10 - 10 - read-write - - - value1 - Input A is used directly - 0b0 - - - value2 - Input A is inverted - 0b1 - - - - - NB - Input B Negation Select for ERSx - 11 - 11 - read-write - - - value1 - Input B is used directly - 0b0 - - - value2 - Input B is inverted - 0b1 - - - - - - - 4 - 4 - EXOCON[%s] - Event Output Trigger Control - 0x20 - 32 - 0x00000008 - 0xFFFFFFFF - - - ISS - Internal Trigger Source Selection - 0 - 1 - read-write - - - value1 - The peripheral trigger function is disabled - 0b00 - - - value2 - Input ERU_OGUy1 is selected - 0b01 - - - value3 - Input ERU_OGUy2 is selected - 0b10 - - - value4 - Input ERU_OGUy3 is selected - 0b11 - - - - - GEEN - Gating Event Enable - 2 - 2 - read-write - - - value1 - The event detection is disabled - 0b0 - - - value2 - The event detection is enabled - 0b1 - - - - - PDR - Pattern Detection Result Flag - 3 - 3 - read-only - - - value1 - A pattern miss is detected - 0b0 - - - value2 - A pattern match is detected - 0b1 - - - - - GP - Gating Selection for Pattern Detection Result - 4 - 5 - read-write - - - value1 - ERU_GOUTy is always disabled and ERU_IOUTy can not be activated - 0b00 - - - value2 - ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy - 0b01 - - - value3 - ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1) - 0b10 - - - value4 - ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0) - 0b11 - - - - - IPEN0 - Pattern Detection Enable for ETL0 - 12 - 12 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - IPEN1 - Pattern Detection Enable for ETL1 - 13 - 13 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - IPEN2 - Pattern Detection Enable for ETL2 - 14 - 14 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - IPEN3 - Pattern Detection Enable for ETL3 - 15 - 15 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - - - - - ERU1 - Event Request Unit 1 - ERU - 0x40044000 - - 0x0 - 0x4000 - registers - - - - GPDMA0 - General Purpose DMA Unit 0 - GPDMA - 0x500142C0 - - 0x0 - 0x3D40 - registers - - - - RAWTFR - Raw IntTfr Status - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWBLOCK - Raw IntBlock Status - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWSRCTRAN - Raw IntSrcTran Status - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWDSTTRAN - Raw IntBlock Status - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWERR - Raw IntErr Status - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - STATUSTFR - IntTfr Status - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSBLOCK - IntBlock Status - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSSRCTRAN - IntSrcTran Status - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSDSTTRAN - IntBlock Status - 0x040 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSERR - IntErr Status - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - MASKTFR - Mask for Raw IntTfr Status - 0x050 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKBLOCK - Mask for Raw IntBlock Status - 0x058 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKSRCTRAN - Mask for Raw IntSrcTran Status - 0x060 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKDSTTRAN - Mask for Raw IntBlock Status - 0x068 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKERR - Mask for Raw IntErr Status - 0x070 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - CLEARTFR - IntTfr Status - 0x078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARBLOCK - IntBlock Status - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARSRCTRAN - IntSrcTran Status - 0x088 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARDSTTRAN - IntBlock Status - 0x090 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARERR - IntErr Status - 0x098 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - STATUSINT - Combined Interrupt Status Register - 0x0A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ERR - OR of the contents of STATUSERR register - 4 - 4 - read-only - - - DSTT - OR of the contents of STATUSDSTTRAN register - 3 - 3 - read-only - - - SRCT - OR of the contents of STATUSSRCTRAN register - 2 - 2 - read-only - - - BLOCK - OR of the contents of STATUSBLOCK register - 1 - 1 - read-only - - - TFR - OR of the contents of STATUSTFR register - 0 - 0 - read-only - - - - - REQSRCREG - Source Software Transaction Request Register - 0x0A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - REQDSTREG - Destination Software Transaction Request Register - 0x0B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - SGLREQSRCREG - Single Source Transaction Request Register - 0x0B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - SGLREQDSTREG - Single Destination Transaction Request Register - 0x0C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - LSTSRCREG - Last Source Transaction Request Register - 0x0C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source last transaction request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source last transaction request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source last transaction request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source last transaction request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Source last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Source last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Source last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH4 - Source last request for channel 4 - 4 - 4 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH5 - Source last request for channel 5 - 5 - 5 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH6 - Source last request for channel 6 - 6 - 6 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH7 - Source last request for channel 7 - 7 - 7 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - LSTDSTREG - Last Destination Transaction Request Register - 0x0D0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Destination last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Destination last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Destination last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Destination last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Destination last transaction request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Destination last transaction request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Destination last transaction request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Destination last transaction request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Destination last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Destination last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Destination last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Destination last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH4 - Destination last request for channel 4 - 4 - 4 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH5 - Destination last request for channel 5 - 5 - 5 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH6 - Destination last request for channel 6 - 6 - 6 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH7 - Destination last request for channel 7 - 7 - 7 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - DMACFGREG - GPDMA Configuration Register - 0x0D8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMA_EN - GPDMA Enable bit. - 0 - 0 - read-write - - - value1 - GPDMA Disabled - 0b0 - - - value2 - GPDMA Enabled. - 0b1 - - - - - - - CHENREG - GPDMA Channel Enable Register - 0x0E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH - Channel enable write enable - 8 - 15 - write-only - - - CH - Enables/Disables the channel - 0 - 7 - read-write - - - value1 - Disable the Channel - 0b0 - - - value2 - Enable the Channel - 0b1 - - - - - - - ID - GPDMA0 ID Register - 0x0E8 - 32 - 0x00AFC000 - 0xFFFFFF00 - - - VALUE - Hardcoded GPDMA Peripheral ID - 0 - 31 - read-only - - - - - TYPE - GPDMA Component Type - 0x138 - 32 - 0x44571110 - 0xFFFFFFFF - - - VALUE - Component Type - 0 - 31 - read-only - - - - - VERSION - DMA Component Version - 0x13C - 32 - 0x3231342A - 0xFFFFFFFF - - - VALUE - Version number of the component - 0 - 31 - read-only - - - - - - - GPDMA0_CH0 - General Purpose DMA Unit 0 - GPDMA - GPDMA0_CH0_1 - 0x50014000 - - 0x0 - 0x55 - registers - - - - SAR - Source Address Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SAR - Current Source Address of DMA transfer - 0 - 31 - read-write - - - - - DAR - Destination Address Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAR - Current Destination address of DMA transfer - 0 - 31 - read-write - - - - - LLP - Linked List Pointer Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - Starting Address In Memory - 2 - 31 - read-write - - - - - CTLL - Control Register Low - 0x18 - 32 - 0x00304801 - 0xFFFFFFFF - - - LLP_SRC_EN - Linked List Pointer for Source Enable - 28 - 28 - read-write - - - LLP_DST_EN - Linked List Pointer for Destination Enable - 27 - 27 - read-write - - - TT_FC - Transfer Type and Flow Control - 20 - 22 - read-write - - - DST_SCATTER_EN - Destination scatter enable - 18 - 18 - read-write - - - value1 - Scatter disabled - 0b0 - - - value2 - Scatter enabled - 0b1 - - - - - SRC_GATHER_EN - Source gather enable - 17 - 17 - read-write - - - value1 - Gather disabled - 0b0 - - - value2 - Gather enabled - 0b1 - - - - - SRC_MSIZE - Source Burst Transaction Length - 14 - 16 - read-write - - - DEST_MSIZE - Destination Burst Transaction Length - 11 - 13 - read-write - - - SINC - Source Address Increment - 9 - 10 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - DINC - Destination Address Increment - 7 - 8 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - SRC_TR_WIDTH - Source Transfer Width - 4 - 6 - read-write - - - DST_TR_WIDTH - Destination Transfer Width - 1 - 3 - read-write - - - INT_EN - Interrupt Enable Bit - 0 - 0 - read-write - - - - - CTLH - Control Register High - 0x1C - 32 - 0x00000002 - 0xFFFFFFFF - - - DONE - Done bit - 12 - 12 - read-write - - - BLOCK_TS - Block Transfer Size - 0 - 11 - read-write - - - - - SSTAT - Source Status Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SSTAT - Source Status - 0 - 31 - read-write - - - - - DSTAT - Destination Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTAT - Destination Status - 0 - 31 - read-write - - - - - SSTATAR - Source Status Address Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - SSTATAR - Source Status Address - 0 - 31 - read-write - - - - - DSTATAR - Destination Status Address Register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTATAR - Destination Status Address - 0 - 31 - read-write - - - - - CFGL - Configuration Register Low - 0x40 - 32 - 0x00000E00 - 0xFFFFFF0F - - - RELOAD_DST - Automatic Destination Reload - 31 - 31 - read-write - - - RELOAD_SRC - Automatic Source Reload - 30 - 30 - read-write - - - MAX_ABRST - Maximum AMBA Burst Length - 20 - 29 - read-write - - - SRC_HS_POL - Source Handshaking Interface Polarity - 19 - 19 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - DST_HS_POL - Destination Handshaking Interface Polarity - 18 - 18 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - LOCK_B - Bus Lock Bit - 17 - 17 - read-write - - - LOCK_CH - Channel Lock Bit - 16 - 16 - read-write - - - LOCK_B_L - Bus Lock Level - 14 - 15 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - LOCK_CH_L - Channel Lock Level - 12 - 13 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - HS_SEL_SRC - Source Software or Hardware Handshaking Select - 11 - 11 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware-initiated transaction requests are ignored. - 0b1 - - - - - HS_SEL_DST - Destination Software or Hardware Handshaking Select - 10 - 10 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware- initiated transaction requests are ignored. - 0b1 - - - - - FIFO_EMPTY - Indicates if there is data left in the channel FIFO - 9 - 9 - read-only - - - value1 - Channel FIFO empty - 0b1 - - - value2 - Channel FIFO not empty - 0b0 - - - - - CH_SUSP - Channel Suspend - 8 - 8 - read-write - - - value1 - Not suspended. - 0b0 - - - value2 - Suspend DMA transfer from the source. - 0b1 - - - - - CH_PRIOR - Channel priority - 5 - 7 - read-write - - - - - CFGH - Configuration Register High - 0x44 - 32 - 0x00000004 - 0xFFFFFFFF - - - DEST_PER - Destination Peripheral - 11 - 14 - read-write - - - SRC_PER - Source Peripheral - 7 - 10 - read-write - - - SS_UPD_EN - Source Status Update Enable - 6 - 6 - read-write - - - DS_UPD_EN - Destination Status Update Enable - 5 - 5 - read-write - - - PROTCTL - Protection Control - 2 - 4 - read-write - - - FIFO_MODE - FIFO Mode Select - 1 - 1 - read-write - - - value1 - Space/data available for single AHB transfer of the specified transfer width. - 0b0 - - - value2 - Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. - 0b1 - - - - - FCMODE - Flow Control Mode - 0 - 0 - read-write - - - value1 - Source transaction requests are serviced when they occur. Data pre-fetching is enabled. - 0b0 - - - value2 - Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. - 0b1 - - - - - - - SGR - Source Gather Register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - SGC - Source gather count - 20 - 31 - read-write - - - SGI - Source gather interval - 0 - 19 - read-write - - - - - DSR - Destination Scatter Register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSC - Destination scatter count - 20 - 31 - read-write - - - DSI - Destination scatter interval - 0 - 19 - read-write - - - - - - - GPDMA0_CH1 - General Purpose DMA Unit 0 - GPDMA - 0x50014058 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH2 - General Purpose DMA Unit 0 - GPDMA - GPDMA0_CH2_7 - 0x500140B0 - - 0x0 - 0x55 - registers - - - - SAR - Source Address Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SAR - Current Source Address of DMA transfer - 0 - 31 - read-write - - - - - DAR - Destination Address Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAR - Current Destination address of DMA transfer - 0 - 31 - read-write - - - - - CTLL - Control Register Low - 0x18 - 32 - 0x00304801 - 0xFFFFFFFF - - - TT_FC - Transfer Type and Flow Control - 20 - 22 - read-write - - - SRC_MSIZE - Source Burst Transaction Length - 14 - 16 - read-write - - - DEST_MSIZE - Destination Burst Transaction Length - 11 - 13 - read-write - - - SINC - Source Address Increment - 9 - 10 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - DINC - Destination Address Increment - 7 - 8 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - SRC_TR_WIDTH - Source Transfer Width - 4 - 6 - read-write - - - DST_TR_WIDTH - Destination Transfer Width - 1 - 3 - read-write - - - INT_EN - Interrupt Enable Bit - 0 - 0 - read-write - - - - - CTLH - Control Register High - 0x1C - 32 - 0x00000002 - 0xFFFFFFFF - - - DONE - Done bit - 12 - 12 - read-write - - - BLOCK_TS - Block Transfer Size - 0 - 11 - read-write - - - - - CFGL - Configuration Register Low - 0x40 - 32 - 0x00000E00 - 0xFFFFFF0F - - - MAX_ABRST - Maximum AMBA Burst Length - 20 - 29 - read-write - - - SRC_HS_POL - Source Handshaking Interface Polarity - 19 - 19 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - DST_HS_POL - Destination Handshaking Interface Polarity - 18 - 18 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - LOCK_B - Bus Lock Bit - 17 - 17 - read-write - - - LOCK_CH - Channel Lock Bit - 16 - 16 - read-write - - - LOCK_B_L - Bus Lock Level - 14 - 15 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - LOCK_CH_L - Channel Lock Level - 12 - 13 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - HS_SEL_SRC - Source Software or Hardware Handshaking Select - 11 - 11 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware-initiated transaction requests are ignored. - 0b1 - - - - - HS_SEL_DST - Destination Software or Hardware Handshaking Select - 10 - 10 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware- initiated transaction requests are ignored. - 0b1 - - - - - FIFO_EMPTY - Indicates if there is data left in the channel FIFO - 9 - 9 - read-only - - - value1 - Channel FIFO empty - 0b1 - - - value2 - Channel FIFO not empty - 0b0 - - - - - CH_SUSP - Channel Suspend - 8 - 8 - read-write - - - value1 - Not suspended. - 0b0 - - - value2 - Suspend DMA transfer from the source. - 0b1 - - - - - CH_PRIOR - Channel priority - 5 - 7 - read-write - - - - - CFGH - Configuration Register High - 0x44 - 32 - 0x00000004 - 0xFFFFFFFF - - - DEST_PER - Destination Peripheral - 11 - 14 - read-write - - - SRC_PER - Source Peripheral - 7 - 10 - read-write - - - PROTCTL - Protection Control - 2 - 4 - read-write - - - FIFO_MODE - FIFO Mode Select - 1 - 1 - read-write - - - value1 - Space/data available for single AHB transfer of the specified transfer width. - 0b0 - - - value2 - Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. - 0b1 - - - - - FCMODE - Flow Control Mode - 0 - 0 - read-write - - - value1 - Source transaction requests are serviced when they occur. Data pre-fetching is enabled. - 0b0 - - - value2 - Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. - 0b1 - - - - - - - - - GPDMA0_CH3 - General Purpose DMA Unit 0 - GPDMA - 0x50014108 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH4 - General Purpose DMA Unit 0 - GPDMA - 0x50014160 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH5 - General Purpose DMA Unit 0 - GPDMA - 0x500141B8 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH6 - General Purpose DMA Unit 0 - GPDMA - 0x50014210 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH7 - General Purpose DMA Unit 0 - GPDMA - 0x50014268 - - 0x0 - 0x55 - registers - - - - GPDMA1 - General Purpose DMA Unit 1 - GPDMA - 0x500182C0 - - 0x0 - 0x7D40 - registers - - - - RAWTFR - Raw IntTfr Status - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWBLOCK - Raw IntBlock Status - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWSRCTRAN - Raw IntSrcTran Status - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWDSTTRAN - Raw IntBlock Status - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWERR - Raw IntErr Status - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - STATUSTFR - IntTfr Status - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSBLOCK - IntBlock Status - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSSRCTRAN - IntSrcTran Status - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSDSTTRAN - IntBlock Status - 0x040 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSERR - IntErr Status - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - MASKTFR - Mask for Raw IntTfr Status - 0x050 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKBLOCK - Mask for Raw IntBlock Status - 0x058 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKSRCTRAN - Mask for Raw IntSrcTran Status - 0x060 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKDSTTRAN - Mask for Raw IntBlock Status - 0x068 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKERR - Mask for Raw IntErr Status - 0x070 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - CLEARTFR - IntTfr Status - 0x078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARBLOCK - IntBlock Status - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARSRCTRAN - IntSrcTran Status - 0x088 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARDSTTRAN - IntBlock Status - 0x090 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARERR - IntErr Status - 0x098 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - STATUSINT - Combined Interrupt Status Register - 0x0A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ERR - OR of the contents of STATUSERR register - 4 - 4 - read-only - - - DSTT - OR of the contents of STATUSDSTTRAN register - 3 - 3 - read-only - - - SRCT - OR of the contents of STATUSSRCTRAN register - 2 - 2 - read-only - - - BLOCK - OR of the contents of STATUSBLOCK register - 1 - 1 - read-only - - - TFR - OR of the contents of STATUSTFR register - 0 - 0 - read-only - - - - - REQSRCREG - Source Software Transaction Request Register - 0x0A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - REQDSTREG - Destination Software Transaction Request Register - 0x0B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - SGLREQSRCREG - Single Source Transaction Request Register - 0x0B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - SGLREQDSTREG - Single Destination Transaction Request Register - 0x0C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - LSTSRCREG - Last Source Transaction Request Register - 0x0C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Source last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Source last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Source last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - LSTDSTREG - Last Destination Transaction Request Register - 0x0D0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Destination last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Destination last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Destination last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Destination last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Destination last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Destination last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Destination last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Destination last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - DMACFGREG - GPDMA Configuration Register - 0x0D8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMA_EN - GPDMA Enable bit. - 0 - 0 - read-write - - - value1 - GPDMA Disabled - 0b0 - - - value2 - GPDMA Enabled. - 0b1 - - - - - - - CHENREG - GPDMA Channel Enable Register - 0x0E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH - Channel enable write enable - 8 - 11 - write-only - - - CH - Enables/Disables the channel - 0 - 3 - read-write - - - value1 - Disable the Channel - 0b0 - - - value2 - Enable the Channel - 0b1 - - - - - - - ID - GPDMA1 ID Register - 0x0E8 - 32 - 0x00B0C000 - 0xFFFFFF00 - - - VALUE - Hardcoded GPDMA Peripheral ID - 0 - 31 - read-only - - - - - TYPE - GPDMA Component Type - 0x138 - 32 - 0x44571110 - 0xFFFFFFFF - - - VALUE - Component Type - 0 - 31 - read-only - - - - - VERSION - DMA Component Version - 0x13C - 32 - 0x3231342A - 0xFFFFFFFF - - - VALUE - Version number of the component - 0 - 31 - read-only - - - - - - - GPDMA1_CH0 - General Purpose DMA Unit 1 - GPDMA - GPDMA1_CH - 0x50018000 - - 0x0 - 0x55 - registers - - - - SAR - Source Address Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SAR - Current Source Address of DMA transfer - 0 - 31 - read-write - - - - - DAR - Destination Address Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAR - Current Destination address of DMA transfer - 0 - 31 - read-write - - - - - CTLL - Control Register Low - 0x18 - 32 - 0x00304801 - 0xFFFFFFFF - - - TT_FC - Transfer Type and Flow Control - 20 - 22 - read-write - - - SRC_MSIZE - Source Burst Transaction Length - 14 - 16 - read-write - - - DEST_MSIZE - Destination Burst Transaction Length - 11 - 13 - read-write - - - SINC - Source Address Increment - 9 - 10 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - DINC - Destination Address Increment - 7 - 8 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - SRC_TR_WIDTH - Source Transfer Width - 4 - 6 - read-write - - - DST_TR_WIDTH - Destination Transfer Width - 1 - 3 - read-write - - - INT_EN - Interrupt Enable Bit - 0 - 0 - read-write - - - - - CTLH - Control Register High - 0x1C - 32 - 0x00000002 - 0xFFFFFFFF - - - DONE - Done bit - 12 - 12 - read-write - - - BLOCK_TS - Block Transfer Size - 0 - 11 - read-write - - - - - CFGL - Configuration Register Low - 0x40 - 32 - 0x00000E00 - 0xFFFFFF0F - - - MAX_ABRST - Maximum AMBA Burst Length - 20 - 29 - read-write - - - SRC_HS_POL - Source Handshaking Interface Polarity - 19 - 19 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - DST_HS_POL - Destination Handshaking Interface Polarity - 18 - 18 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - LOCK_B - Bus Lock Bit - 17 - 17 - read-write - - - LOCK_CH - Channel Lock Bit - 16 - 16 - read-write - - - LOCK_B_L - Bus Lock Level - 14 - 15 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - LOCK_CH_L - Channel Lock Level - 12 - 13 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - HS_SEL_SRC - Source Software or Hardware Handshaking Select - 11 - 11 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware-initiated transaction requests are ignored. - 0b1 - - - - - HS_SEL_DST - Destination Software or Hardware Handshaking Select - 10 - 10 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware- initiated transaction requests are ignored. - 0b1 - - - - - FIFO_EMPTY - Indicates if there is data left in the channel FIFO - 9 - 9 - read-only - - - value1 - Channel FIFO empty - 0b1 - - - value2 - Channel FIFO not empty - 0b0 - - - - - CH_SUSP - Channel Suspend - 8 - 8 - read-write - - - value1 - Not suspended. - 0b0 - - - value2 - Suspend DMA transfer from the source. - 0b1 - - - - - CH_PRIOR - Channel priority - 5 - 7 - read-write - - - - - CFGH - Configuration Register High - 0x44 - 32 - 0x00000004 - 0xFFFFFFFF - - - DEST_PER - Destination Peripheral - 11 - 14 - read-write - - - SRC_PER - Source Peripheral - 7 - 10 - read-write - - - PROTCTL - Protection Control - 2 - 4 - read-write - - - FIFO_MODE - FIFO Mode Select - 1 - 1 - read-write - - - value1 - Space/data available for single AHB transfer of the specified transfer width. - 0b0 - - - value2 - Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. - 0b1 - - - - - FCMODE - Flow Control Mode - 0 - 0 - read-write - - - value1 - Source transaction requests are serviced when they occur. Data pre-fetching is enabled. - 0b0 - - - value2 - Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. - 0b1 - - - - - - - - - GPDMA1_CH1 - General Purpose DMA Unit 1 - GPDMA - 0x50018058 - - 0x0 - 0x55 - registers - - - - GPDMA1_CH2 - General Purpose DMA Unit 1 - GPDMA - 0x500180B0 - - 0x0 - 0x55 - registers - - - - GPDMA1_CH3 - General Purpose DMA Unit 1 - GPDMA - 0x50018108 - - 0x0 - 0x55 - registers - - - - FCE - Flexible CRC Engine - FCE - 0x50020000 - - 0x0 - 0x1D - registers - - - - CLC - Clock Control Register - 0x00 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - - - ID - Module Identification Register - 0x08 - 32 - 0x00CAC001 - 0xFFFFFFFF - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - - - FCE_KE0 - Flexible CRC Engine - FCE - FCE_KE - 0x50020020 - - 0x0 - 0x1D - registers - - - - IR - Input Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - IR - Input Register - 0 - 31 - read-write - - - - - RES - CRC Result Register - 0x04 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RES - Result Register - 0 - 31 - read-only - - - - - CFG - CRC Configuration Register - 0x08 - 32 - 0x00000700 - 0xFFFFFFFF - - - CMI - CRC Mismatch Interrupt - 0 - 0 - read-write - - - value1 - CRC Mismatch Interrupt is disabled - 0b0 - - - value2 - CRC Mismatch Interrupt is enabled - 0b1 - - - - - CEI - Configuration Error Interrupt - 1 - 1 - read-write - - - value1 - Configuration Error Interrupt is disabled - 0b0 - - - value2 - Configuration Error Interrupt is enabled - 0b1 - - - - - LEI - Length Error Interrupt - 2 - 2 - read-write - - - value1 - Length Error Interrupt is disabled - 0b0 - - - value2 - Length Error Interrupt is enabled - 0b1 - - - - - BEI - Bus Error Interrupt - 3 - 3 - read-write - - - value1 - Bus Error Interrupt is disabled - 0b0 - - - value2 - Bus Error Interrupt is enabled - 0b1 - - - - - CCE - CRC Check Comparison - 4 - 4 - read-write - - - value1 - CRC check comparison at the end of a message is disabled - 0b0 - - - value2 - CRC check comparison at the end of a message is enabled - 0b1 - - - - - ALR - Automatic Length Reload - 5 - 5 - read-write - - - value1 - Disables automatic reload of the LENGTH field. - 0b0 - - - value2 - Enables automatic reload of the LENGTH field at the end of a message. - 0b1 - - - - - REFIN - IR Byte Wise Reflection - 8 - 8 - read-write - - - value1 - IR Byte Wise Reflection is disabled - 0b0 - - - value2 - IR Byte Wise Reflection is enabled - 0b1 - - - - - REFOUT - CRC 32-Bit Wise Reflection - 9 - 9 - read-write - - - value1 - CRC 32-bit wise is disabled - 0b0 - - - value2 - CRC 32-bit wise is enabled - 0b1 - - - - - XSEL - Selects the value to be xored with the final CRC - 10 - 10 - read-write - - - value1 - 0x00000000 - 0b0 - - - value2 - 0xFFFFFFFF - 0b1 - - - - - - - STS - CRC Status Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - CMF - CRC Mismatch Flag - 0 - 0 - read-write - - - CEF - Configuration Error Flag - 1 - 1 - read-write - - - LEF - Length Error Flag - 2 - 2 - read-write - - - BEF - Bus Error Flag - 3 - 3 - read-write - - - - - LENGTH - CRC Length Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - LENGTH - Message Length Register - 0 - 15 - read-write - - - - - CHECK - CRC Check Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHECK - CHECK Register - 0 - 31 - read-write - - - - - CRC - CRC Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC - CRC Register - 0 - 31 - read-write - - - - - CTR - CRC Test Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - FCM - Force CRC Mismatch - 0 - 0 - read-write - - - FRM_CFG - Force CFG Register Mismatch - 1 - 1 - read-write - - - FRM_CHECK - Force Check Register Mismatch - 2 - 2 - read-write - - - - - - - FCE_KE1 - Flexible CRC Engine - FCE - 0x50020040 - - 0x0 - 0x1D - registers - - - - FCE_KE2 - Flexible CRC Engine - FCE - 0x50020060 - - 0x0 - 0x1D - registers - - - - FCE_KE3 - Flexible CRC Engine - FCE - 0x50020080 - - 0x0 - 0x1D - registers - - - - PBA0 - Peripheral Bridge AHB 0 - PBA - PBA - 0x40000000 - - 0x0 - 0x4000 - registers - - - - STS - Peripheral Bridge Status Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - WERR - Bufferable Write Access Error - 0 - 0 - read-write - - - value1 - no write error occurred. - 0b0 - - - value2 - write error occurred, interrupt request is pending. - 0b1 - - - - - - - WADDR - PBA Write Error Address Register - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - WADDR - Write Error Address - 0 - 31 - read-only - - - - - - - PBA1 - Peripheral Bridge AHB 1 - PBA - 0x48000000 - - 0x0 - 0x4000 - registers - - - - FLASH0 - Flash Memory Controller - FLASH - 0x58001000 - - 0x0 - 0x1400 - registers - - - - ID - Flash Module Identification Register - 0x1008 - 32 - 0x00A2C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - FSR - Flash Status Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - PBUSY - Program Flash Busy - 0 - 0 - read-only - - - value1 - PFLASH ready, not busy; PFLASH in read mode. - 0b0 - - - value2 - PFLASH busy; PFLASH not in read mode. - 0b1 - - - - - FABUSY - Flash Array Busy - 1 - 1 - read-only - - - PROG - Programming State - 4 - 4 - read-only - - - value1 - There is no program operation requested or in progress or just finished. - 0b0 - - - value2 - Programming operation (write page) requested (from FIM) or in action or finished. - 0b1 - - - - - ERASE - Erase State - 5 - 5 - read-only - - - value1 - There is no erase operation requested or in progress or just finished - 0b0 - - - value2 - Erase operation requested (from FIM) or in action or finished. - 0b1 - - - - - PFPAGE - Program Flash in Page Mode - 6 - 6 - read-only - - - value1 - Program Flash not in page mode - 0b0 - - - value2 - Program Flash in page mode; assembly buffer of PFLASH (256 byte) is in use (being filled up) - 0b1 - - - - - PFOPER - Program Flash Operation Error - 8 - 8 - read-only - - - value1 - No operation error reported by Program Flash - 0b0 - - - value2 - Flash array operation aborted, because of a Flash array failure, e.g. an ECC error in microcode. - 0b1 - - - - - SQER - Command Sequence Error - 10 - 10 - read-only - - - value1 - No sequence error - 0b0 - - - value2 - Command state machine operation unsuccessful because of improper address or command sequence. - 0b1 - - - - - PROER - Protection Error - 11 - 11 - read-only - - - value1 - No protection error - 0b0 - - - value2 - Protection error. - 0b1 - - - - - PFSBER - PFLASH Single-Bit Error and Correction - 12 - 12 - read-only - - - value1 - No Single-Bit Error detected during read access to PFLASH - 0b0 - - - value2 - Single-Bit Error detected and corrected - 0b1 - - - - - PFDBER - PFLASH Double-Bit Error - 14 - 14 - read-only - - - value1 - No Double-Bit Error detected during read access to PFLASH - 0b0 - - - value2 - Double-Bit Error detected in PFLASH - 0b1 - - - - - PROIN - Protection Installed - 16 - 16 - read-only - - - value1 - No protection is installed - 0b0 - - - value2 - Read or/and write protection for one or more users is configured and correctly confirmed in the User Configuration Block(s). - 0b1 - - - - - RPROIN - Read Protection Installed - 18 - 18 - read-only - - - value1 - No read protection installed - 0b0 - - - value2 - Read protection and global write protection is configured and correctly confirmed in the User Configuration Block 0. - 0b1 - - - - - RPRODIS - Read Protection Disable State - 19 - 19 - read-only - - - value1 - Read protection (if installed) is not disabled - 0b0 - - - value2 - Read and global write protection is temporarily disabled. - 0b1 - - - - - WPROIN0 - Sector Write Protection Installed for User 0 - 21 - 21 - read-only - - - value1 - No write protection installed for user 0 - 0b0 - - - value2 - Sector write protection for user 0 is configured and correctly confirmed in the User Configuration Block 0. - 0b1 - - - - - WPROIN1 - Sector Write Protection Installed for User 1 - 22 - 22 - read-only - - - value1 - No write protection installed for user 1 - 0b0 - - - value2 - Sector write protection for user 1 is configured and correctly confirmed in the User Configuration Block 1. - 0b1 - - - - - WPROIN2 - Sector OTP Protection Installed for User 2 - 23 - 23 - read-only - - - value1 - No OTP write protection installed for user 2 - 0b0 - - - value2 - Sector OTP write protection with ROM functionality is configured and correctly confirmed in the UCB2. The protection is locked for ever. - 0b1 - - - - - WPRODIS0 - Sector Write Protection Disabled for User 0 - 25 - 25 - read-only - - - value1 - All protected sectors of user 0 are locked if write protection is installed - 0b0 - - - value2 - All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection. - 0b1 - - - - - WPRODIS1 - Sector Write Protection Disabled for User 1 - 26 - 26 - read-only - - - value1 - All protected sectors of user 1 are locked if write protection is installed - 0b0 - - - value2 - All write-protected sectors of user 1 are temporarily unlocked, if not coincidently locked by user 0 or user 2 or via read protection. - 0b1 - - - - - SLM - Flash Sleep Mode - 28 - 28 - read-only - - - value1 - Flash not in sleep mode - 0b0 - - - value2 - Flash is in sleep or shut down mode - 0b1 - - - - - X - Reserved - 30 - 30 - read-only - - - VER - Verify Error - 31 - 31 - read-only - - - value1 - The page is correctly programmed or the sector correctly erased. All programmed or erased bits have full expected quality. - 0b0 - - - value2 - A program verify error or an erase verify error has been detected. Full quality (retention time) of all programmed ("1") or erased ("0") bits cannot be guaranteed. - 0b1 - - - - - - - FCON - Flash Configuration Register - 0x1014 - 32 - 0x00000006 - 0xFFF0FFFF - - - WSPFLASH - Wait States for read access to PFLASH - 0 - 3 - read-write - - - value1 - PFLASH access in one clock cycle - 0b0000 - - - value2 - PFLASH access in one clock cycle - 0b0001 - - - value3 - PFLASH access in two clock cycles - 0b0010 - - - value4 - PFLASH access in three clock cycles - 0b0011 - - - value5 - PFLASH access in fifteen clock cycles. - 0b1111 - - - - - WSECPF - Wait State for Error Correction of PFLASH - 4 - 4 - read-write - - - value1 - No additional wait state for error correction - 0b0 - - - value2 - One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer. - 0b1 - - - - - IDLE - Dynamic Flash Idle - 13 - 13 - read-write - - - value1 - Normal/standard Flash read operation - 0b0 - - - value2 - Dynamic idle of Program Flash enabled for power saving; static prefetching disabled - 0b1 - - - - - ESLDIS - External Sleep Request Disable - 14 - 14 - read-write - - - value1 - External sleep request signal input is enabled - 0b0 - - - value2 - Externally requested Flash sleep is disabled - 0b1 - - - - - SLEEP - Flash SLEEP - 15 - 15 - read-write - - - value1 - Normal state or wake-up - 0b0 - - - value2 - Flash sleep mode is requested - 0b1 - - - - - RPA - Read Protection Activated - 16 - 16 - read-only - - - value1 - The Flash-internal read protection is not activated. Bits DCF, DDF are not taken into account. Bits DCF, DDFx can be cleared - 0b0 - - - value2 - The Flash-internal read protection is activated. Bits DCF, DDF are enabled and evaluated. - 0b1 - - - - - DCF - Disable Code Fetch from Flash Memory - 17 - 17 - read-write - - - value1 - Code fetching from the Flash memory area is allowed. - 0b0 - - - value2 - Code fetching from the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. - 0b1 - - - - - DDF - Disable Any Data Fetch from Flash - 18 - 18 - read-write - - - value1 - Data read access to the Flash memory area is allowed. - 0b0 - - - value2 - Data read access to the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. - 0b1 - - - - - VOPERM - Verify and Operation Error Interrupt Mask - 24 - 24 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - Flash interrupt because of Verify Error or Operation Error in Flash array (FSI) is enabled - 0b1 - - - - - SQERM - Command Sequence Error Interrupt Mask - 25 - 25 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - Flash interrupt because of Sequence Error is enabled - 0b1 - - - - - PROERM - Protection Error Interrupt Mask - 26 - 26 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - Flash interrupt because of Protection Error is enabled - 0b1 - - - - - PFSBERM - PFLASH Single-Bit Error Interrupt Mask - 27 - 27 - read-write - - - value1 - No Single-Bit Error interrupt enabled - 0b0 - - - value2 - Single-Bit Error interrupt enabled for PFLASH - 0b1 - - - - - PFDBERM - PFLASH Double-Bit Error Interrupt Mask - 29 - 29 - read-write - - - value1 - Double-Bit Error interrupt for PFLASH not enabled - 0b0 - - - value2 - Double-Bit Error interrupt for PFLASH enabled. Especially intended for margin check - 0b1 - - - - - EOBM - End of Busy Interrupt Mask - 31 - 31 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - EOB interrupt is enabled - 0b1 - - - - - - - MARP - Margin Control Register PFLASH - 0x1018 - 32 - 0x00000000 - 0xFFFFFFFF - - - MARGIN - PFLASH Margin Selection - 0 - 3 - read-write - - - value1 - Standard (default) margin. - 0b0000 - - - value2 - Tight margin for 0 (low) level. Suboptimal 0-bits are read as 1s. - 0b0001 - - - value3 - Tight margin for 1 (high) level. Suboptimal 1-bits are read as 0s. - 0b0100 - - - - - TRAPDIS - PFLASH Double-Bit Error Trap Disable - 15 - 15 - read-write - - - value1 - If a double-bit error occurs in PFLASH, a bus error trap is generated. - 0b0 - - - value2 - The double-bit error trap is disabled. Shall be used only during margin check - 0b1 - - - - - - - PROCON0 - Flash Protection Configuration Register User 0 - 0x1020 - 32 - 0x00000000 - 0xFFFF0000 - - - S0L - Sector 0 Locked for Write Protection by User 0 - 0 - 0 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S1L - Sector 1 Locked for Write Protection by User 0 - 1 - 1 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S2L - Sector 2 Locked for Write Protection by User 0 - 2 - 2 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S3L - Sector 3 Locked for Write Protection by User 0 - 3 - 3 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S4L - Sector 4 Locked for Write Protection by User 0 - 4 - 4 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S5L - Sector 5 Locked for Write Protection by User 0 - 5 - 5 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S6L - Sector 6 Locked for Write Protection by User 0 - 6 - 6 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S7L - Sector 7 Locked for Write Protection by User 0 - 7 - 7 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S8L - Sector 8 Locked for Write Protection by User 0 - 8 - 8 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S9L - Sector 9 Locked for Write Protection by User 0 - 9 - 9 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S10_S11L - Sectors 10 and 11 Locked for Write Protection by User 0 - 10 - 10 - read-only - - - value1 - No write protection is configured for sectors 10+11. - 0b0 - - - value2 - Write protection is configured for sectors 10+11. - 0b1 - - - - - RPRO - Read Protection Configuration - 15 - 15 - read-only - - - value1 - No read protection configured - 0b0 - - - value2 - Read protection and global write protection is configured by user 0 (master user) - 0b1 - - - - - - - PROCON1 - Flash Protection Configuration Register User 1 - 0x1024 - 32 - 0x00000000 - 0xFFFF0000 - - - S0L - Sector 0 Locked for Write Protection by User 1 - 0 - 0 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S1L - Sector 1 Locked for Write Protection by User 1 - 1 - 1 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S2L - Sector 2 Locked for Write Protection by User 1 - 2 - 2 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S3L - Sector 3 Locked for Write Protection by User 1 - 3 - 3 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S4L - Sector 4 Locked for Write Protection by User 1 - 4 - 4 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S5L - Sector 5 Locked for Write Protection by User 1 - 5 - 5 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S6L - Sector 6 Locked for Write Protection by User 1 - 6 - 6 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S7L - Sector 7 Locked for Write Protection by User 1 - 7 - 7 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S8L - Sector 8 Locked for Write Protection by User 1 - 8 - 8 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S9L - Sector 9 Locked for Write Protection by User 1 - 9 - 9 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S10_S11L - Sectors 10 and 11 Locked for Write Protection by User 1 - 10 - 10 - read-only - - - value1 - No write protection is configured for sectors 10+11. - 0b0 - - - value2 - Write protection is configured for sectors 10+11. - 0b1 - - - - - - - PROCON2 - Flash Protection Configuration Register User 2 - 0x1028 - 32 - 0x00000000 - 0xFFFF0000 - - - S0ROM - Sector 0 Locked Forever by User 2 - 0 - 0 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S1ROM - Sector 1 Locked Forever by User 2 - 1 - 1 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S2ROM - Sector 2 Locked Forever by User 2 - 2 - 2 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S3ROM - Sector 3 Locked Forever by User 2 - 3 - 3 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S4ROM - Sector 4 Locked Forever by User 2 - 4 - 4 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S5ROM - Sector 5 Locked Forever by User 2 - 5 - 5 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S6ROM - Sector 6 Locked Forever by User 2 - 6 - 6 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S7ROM - Sector 7 Locked Forever by User 2 - 7 - 7 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S8ROM - Sector 8 Locked Forever by User 2 - 8 - 8 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S9ROM - Sector 9 Locked Forever by User 2 - 9 - 9 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S10_S11ROM - Sectors 10 and 11 Locked Forever by User 2 - 10 - 10 - read-only - - - value1 - No ROM functionality is configured for sectors 10+11. - 0b0 - - - value2 - ROM functionality is configured for sectors 10+11. - 0b1 - - - - - - - - - PREF - Prefetch Unit - 0x58004000 - - 0 - 4 - registers - - - - PCON - Prefetch Configuration Register - 0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IBYP - Instruction Prefetch Buffer Bypass - 0 - 0 - read-write - - - value1 - Instruction prefetch buffer not bypassed. - 0b0 - - - value2 - Instruction prefetch buffer bypassed. - 0b1 - - - - - IINV - Instruction Prefetch Buffer Invalidate - 1 - 1 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Initiate invalidation of entire instruction cache. - 0b1 - - - - - - - - - PMU0 - Program Management Unit - PMU - 0x58000508 - - 0 - 4 - registers - - - - ID - PMU0 Identification Register - 0 - 32 - 0x00A1C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - - - WDT - Watch Dog Timer - 0x50008000 - - 0x0 - 0x4000 - registers - - - - ID - WDT ID Register - 0x00 - 32 - 0x00ADC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - CTR - WDT Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENB - Enable - 0 - 0 - read-write - - - PRE - Pre-warning - 1 - 1 - read-write - - - DSP - Debug Suspend - 4 - 4 - read-write - - - SPW - Service Indication Pulse Width - 8 - 15 - read-write - - - - - SRV - WDT Service Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRV - Service - 0 - 31 - write-only - - - - - TIM - WDT Timer Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - TIM - Timer Value - 0 - 31 - read-only - - - - - WLB - WDT Window Lower Bound Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLB - Window Lower Bound - 0 - 31 - read-write - - - - - WUB - WDT Window Upper Bound Register - 0x14 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WUB - Window Upper Bound - 0 - 31 - read-write - - - - - WDTSTS - WDT Status Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALMS - Pre-warning Alarm - 0 - 0 - read-only - - - - - WDTCLR - WDT Clear Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - ALMC - Pre-warning Alarm - 0 - 0 - write-only - - - - - - - RTC - Real Time Clock - 0x50004A00 - - 0x0 - 0x0200 - registers - - - - ID - RTC ID Register - 0x00 - 32 - 0x00A3C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - CTR - RTC Control Register - 0x04 - 32 - 0x7FFF0000 - 0xFFFFFFFF - - - ENB - RTC Module Enable - 0 - 0 - read-write - - - TAE - Timer Alarm Enable for Hibernation Wake-up - 2 - 2 - read-write - - - ESEC - Enable Seconds Comparison for Hibernation Wake-up - 8 - 8 - read-write - - - EMIC - Enable Minutes Comparison for Hibernation Wake-up - 9 - 9 - read-write - - - EHOC - Enable Hours Comparison for Hibernation Wake-up - 10 - 10 - read-write - - - EDAC - Enable Days Comparison for Hibernation Wake-up - 11 - 11 - read-write - - - EMOC - Enable Months Comparison for Hibernation Wake-up - 13 - 13 - read-write - - - EYEC - Enable Years Comparison for Hibernation Wake-up - 14 - 14 - read-write - - - DIV - RTC Clock Divider Value - 16 - 31 - read-write - - - - - RAWSTAT - RTC Raw Service Request Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPSE - Raw Periodic Seconds Service Request - 0 - 0 - read-only - - - RPMI - Raw Periodic Minutes Service Request - 1 - 1 - read-only - - - RPHO - Raw Periodic Hours Service Request - 2 - 2 - read-only - - - RPDA - Raw Periodic Days Service Request - 3 - 3 - read-only - - - RPMO - Raw Periodic Months Service Request - 5 - 5 - read-only - - - RPYE - Raw Periodic Years Service Request - 6 - 6 - read-only - - - RAI - Raw Alarm Service Request - 8 - 8 - read-only - - - - - STSSR - RTC Service Request Status Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - SPSE - Periodic Seconds Service Request Status after Masking - 0 - 0 - read-only - - - SPMI - Periodic Minutes Service Request Status after Masking - 1 - 1 - read-only - - - SPHO - Periodic Hours Service Request Status after Masking - 2 - 2 - read-only - - - SPDA - Periodic Days Service Request Status after Masking - 3 - 3 - read-only - - - SPMO - Periodic Months Service Request Status after Masking - 5 - 5 - read-only - - - SPYE - Periodic Years Service Request Status after Masking - 6 - 6 - read-only - - - SAI - Alarm Service Request Status after Masking - 8 - 8 - read-only - - - - - MSKSR - RTC Service Request Mask Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPSE - Periodic Seconds Interrupt Mask - 0 - 0 - read-write - - - MPMI - Periodic Minutes Interrupt Mask - 1 - 1 - read-write - - - MPHO - Periodic Hours Interrupt Mask - 2 - 2 - read-write - - - MPDA - Periodic Days Interrupt Mask - 3 - 3 - read-write - - - MPMO - Periodic Months Interrupt Mask - 5 - 5 - read-write - - - MPYE - Periodic Years Interrupt Mask - 6 - 6 - read-write - - - MAI - Alarm Interrupt Mask - 8 - 8 - read-write - - - - - CLRSR - RTC Clear Service Request Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPSE - Periodic Seconds Interrupt Clear - 0 - 0 - write-only - - - RPMI - Periodic Minutes Interrupt Clear - 1 - 1 - write-only - - - RPHO - Periodic Hours Interrupt Clear - 2 - 2 - write-only - - - RPDA - Periodic Days Interrupt Clear - 3 - 3 - write-only - - - RPMO - Periodic Months Interrupt Clear - 5 - 5 - write-only - - - RPYE - Periodic Years Interrupt Clear - 6 - 6 - write-only - - - RAI - Alarm Interrupt Clear - 8 - 8 - write-only - - - - - ATIM0 - RTC Alarm Time Register 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ASE - Alarm Seconds Compare Value - 0 - 5 - read-write - - - AMI - Alarm Minutes Compare Value - 8 - 13 - read-write - - - AHO - Alarm Hours Compare Value - 16 - 20 - read-write - - - ADA - Alarm Days Compare Value - 24 - 28 - read-write - - - - - ATIM1 - RTC Alarm Time Register 1 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - AMO - Alarm Month Compare Value - 8 - 11 - read-write - - - AYE - Alarm Year Compare Value - 16 - 31 - read-write - - - - - TIM0 - RTC Time Register 0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SE - Seconds Time Value - 0 - 5 - read-write - - - MI - Minutes Time Value - 8 - 13 - read-write - - - HO - Hours Time Value - 16 - 20 - read-write - - - DA - Days Time Value - 24 - 28 - read-write - - - - - TIM1 - RTC Time Register 1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAWE - Days of Week Time Value - 0 - 2 - read-write - - - MO - Month Time Value - 8 - 11 - read-write - - - YE - Year Time Value - 16 - 31 - read-write - - - - - - - SCU_CLK - System Control Unit - SCU - 0x50004600 - - 0x0 - 0x100 - registers - - - - CLKSTAT - Clock Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBCST - USB Clock Status - 0 - 0 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - MMCCST - MMC Clock Status - 1 - 1 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - ETH0CST - Ethernet Clock Status - 2 - 2 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - EBUCST - EBU Clock Status - 3 - 3 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - CCUCST - CCU Clock Status - 4 - 4 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - WDTCST - WDT Clock Status - 5 - 5 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - - - CLKSET - CLK Set Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBCEN - USB Clock Enable - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - MMCCEN - MMC Clock Enable - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - ETH0CEN - Ethernet Clock Enable - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - EBUCEN - EBU Clock Enable - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - CCUCEN - CCU Clock Enable - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - WDTCEN - WDT Clock Enable - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - - - CLKCLR - CLK Clear Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBCDI - USB Clock Disable - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - MMCCDI - MMC Clock Disable - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - ETH0CDI - Ethernet Clock Disable - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - EBUCDI - EBU Clock Disable - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - CCUCDI - CCU Clock Disable - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - WDTCDI - WDT Clock Disable - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - - - SYSCLKCR - System Clock Control Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSDIV - System Clock Division Value - 0 - 7 - read-write - - - SYSSEL - System Clock Selection Value - 16 - 16 - read-write - - - value1 - fOFI clock - 0b0 - - - value2 - fPLL clock - 0b1 - - - - - - - CPUCLKCR - CPU Clock Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CPUDIV - CPU Clock Divider Enable - 0 - 0 - read-write - - - value1 - fCPU = fSYS - 0b0 - - - value2 - fCPU = fSYS / 2 - 0b1 - - - - - - - PBCLKCR - Peripheral Bus Clock Control Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PBDIV - PB Clock Divider Enable - 0 - 0 - read-write - - - value1 - fPERIPH = fCPU - 0b0 - - - value2 - fPERIPH = fCPU / 2 - 0b1 - - - - - - - USBCLKCR - USB Clock Control Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBDIV - USB Clock Divider Value - 0 - 2 - read-write - - - USBSEL - USB Clock Selection Value - 16 - 16 - read-write - - - value1 - USB PLL Clock - 0b0 - - - value2 - PLL Clock - 0b1 - - - - - - - EBUCLKCR - EBU Clock Control Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - EBUDIV - EBU Clock Divider Value - 0 - 5 - read-write - - - - - CCUCLKCR - CCU Clock Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CCUDIV - CCU Clock Divider Enable - 0 - 0 - read-write - - - value1 - fCCU = fSYS - 0b0 - - - value2 - fCCU = fSYS / 2 - 0b1 - - - - - - - WDTCLKCR - WDT Clock Control Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDTDIV - WDT Clock Divider Value - 0 - 7 - read-write - - - WDTSEL - WDT Clock Selection Value - 16 - 17 - read-write - - - value1 - fOFI clock - 0b00 - - - value2 - fSTDBY clock - 0b01 - - - value3 - fPLL clock - 0b10 - - - value4 - Reserved - 0b11 - - - - - - - EXTCLKCR - External Clock Control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ECKSEL - External Clock Selection Value - 0 - 1 - read-write - - - value1 - fSYS clock - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - fUSB clock - 0b10 - - - value4 - fPLL clock divided according to ECKDIV bit field configuration - 0b11 - - - - - ECKDIV - External Clock Divider Value - 16 - 24 - read-write - - - - - SLEEPCR - Sleep Control Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSSEL - System Clock Selection Value - 0 - 0 - read-write - - - value1 - fOFI clock - 0b0 - - - value2 - fPLL clock - 0b1 - - - - - USBCR - USB Clock Control - 16 - 16 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - MMCCR - MMC Clock Control - 17 - 17 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ETH0CR - Ethernet Clock Control - 18 - 18 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - EBUCR - EBU Clock Control - 19 - 19 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - CCUCR - CCU Clock Control - 20 - 20 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WDTCR - WDT Clock Control - 21 - 21 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - DSLEEPCR - Deep Sleep Control Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSSEL - System Clock Selection Value - 0 - 1 - read-write - - - value1 - fOFI clock - 0b0 - - - value2 - fPLL clock - 0b1 - - - - - FPDN - Flash Power Down - 11 - 11 - read-write - - - value1 - Flash power down module - 0b1 - - - value2 - No effect - 0b0 - - - - - PLLPDN - PLL Power Down - 12 - 12 - read-write - - - value1 - Switch off main PLL - 0b1 - - - value2 - No effect - 0b0 - - - - - VCOPDN - VCO Power Down - 13 - 13 - read-write - - - value1 - Switch off VCO of main PLL - 0b1 - - - value2 - No effect - 0b0 - - - - - USBCR - USB Clock Control - 16 - 16 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - MMCCR - MMC Clock Control - 17 - 17 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ETH0CR - Ethernet Clock Control - 18 - 18 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - EBUCR - EBU Clock Control - 19 - 19 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - CCUCR - CCU Clock Control - 20 - 20 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WDTCR - WDT Clock Control - 21 - 21 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - - - SCU_OSC - System Control Unit - SCU - 0x50004700 - - 0x0 - 0x10 - registers - - - - OSCHPSTAT - OSC_HP Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - X1D - XTAL1 Data Value - 0 - 0 - read-only - - - - - OSCHPCTRL - OSC_HP Control Register - 0x04 - 32 - 0x0000003C - 0xFFFFFFFF - - - X1DEN - XTAL1 Data Enable - 0 - 0 - read-write - - - value1 - Bit X1D is not updated - 0b0 - - - value2 - Bit X1D can be updated - 0b1 - - - - - SHBY - Shaper Bypass - 1 - 1 - read-write - - - value1 - The shaper is not bypassed - 0b0 - - - value2 - The shaper is bypassed - 0b1 - - - - - MODE - Oscillator Mode - 4 - 5 - read-write - - - value1 - External Crystal Mode and External Input Clock Mode. The oscillator Power-Saving Mode is not entered. - 0b00 - - - value2 - OSC is disabled. The oscillator Power-Saving Mode is not entered. - 0b01 - - - value3 - External Input Clock Mode and the oscillator Power-Saving Mode is entered - 0b10 - - - value4 - OSC is disabled. The oscillator Power-Saving Mode is entered. - 0b11 - - - - - OSCVAL - OSC Frequency Value - 16 - 20 - read-write - - - - - CLKCALCONST - Clock Calibration Constant Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - CALIBCONST - Clock Calibration Constant Value - 0 - 3 - read-write - - - - - - - SCU_PLL - System Control Unit - SCU - 0x50004710 - - 0x0 - 0x2C - registers - - - - PLLSTAT - PLL Status Register - 0x00 - 32 - 0x00000002 - 0xFFFFFFFF - - - VCOBYST - VCO Bypass Status - 0 - 0 - read-only - - - value1 - Free-running / Normal Mode is entered - 0b0 - - - value2 - Prescaler Mode is entered - 0b1 - - - - - PWDSTAT - PLL Power-saving Mode Status - 1 - 1 - read-only - - - value1 - PLL Power-saving Mode was not entered - 0b0 - - - value2 - PLL Power-saving Mode was entered - 0b1 - - - - - VCOLOCK - PLL LOCK Status - 2 - 2 - read-only - - - value1 - PLL not locked - 0b0 - - - value2 - PLL locked - 0b1 - - - - - K1RDY - K1 Divider Ready Status - 4 - 4 - read-only - - - value1 - K1-Divider does not operate with the new value - 0b0 - - - value2 - K1-Divider operate with the new value - 0b1 - - - - - K2RDY - K2 Divider Ready Status - 5 - 5 - read-only - - - value1 - K2-Divider does not operate with the new value - 0b0 - - - value2 - K2-Divider operate with the new value - 0b1 - - - - - BY - Bypass Mode Status - 6 - 6 - read-only - - - value1 - Bypass Mode is not entered - 0b0 - - - value2 - Bypass Mode is entered. Input fOSC is selected as output fPLL. - 0b1 - - - - - PLLLV - Oscillator for PLL Valid Low Status Bit - 7 - 7 - read-only - - - value1 - The OSC frequency is not usable. Frequency fREF is too low. - 0b0 - - - value2 - The OSC frequency is usable - 0b1 - - - - - PLLHV - Oscillator for PLL Valid High Status Bit - 8 - 8 - read-only - - - value1 - The OSC frequency is not usable. Frequency fOSC is too high. - 0b0 - - - value2 - The OSC frequency is usable - 0b1 - - - - - PLLSP - Oscillator for PLL Valid Spike Status Bit - 9 - 9 - read-only - - - value1 - The OSC frequency is not usable. Spikes are detected that disturb a locked operation - 0b0 - - - value2 - The OSC frequency is usable - 0b1 - - - - - - - PLLCON0 - PLL Configuration 0 Register - 0x04 - 32 - 0x00030003 - 0xFFFFFFFF - - - VCOBYP - VCO Bypass - 0 - 0 - read-write - - - value1 - Normal operation, VCO is not bypassed - 0b0 - - - value2 - Prescaler Mode, VCO is bypassed - 0b1 - - - - - VCOPWD - VCO Power Saving Mode - 1 - 1 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The VCO is put into a Power Saving Mode and can no longer be used. Only the Bypass and Prescaler Mode are active if previously selected. - 0b1 - - - - - VCOTR - VCO Trim Control - 2 - 2 - read-write - - - value1 - VCO bandwidth is operation in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b0 - - - value2 - VCO bandwidth is operation in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b1 - - - - - FINDIS - Disconnect Oscillator from VCO - 4 - 4 - read-write - - - value1 - connect oscillator to the VCO part - 0b0 - - - value2 - disconnect oscillator from the VCO part. - 0b1 - - - - - OSCDISCDIS - Oscillator Disconnect Disable - 6 - 6 - read-write - - - value1 - In case of a PLL loss-of-lock bit FINDIS is set - 0b0 - - - value2 - In case of a PLL loss-of-lock bit FINDIS is cleared - 0b1 - - - - - PLLPWD - PLL Power Saving Mode - 16 - 16 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The complete PLL block is put into a Power Saving Mode and can no longer be used. Only the Bypass Mode is active if previously selected. - 0b1 - - - - - OSCRES - Oscillator Watchdog Reset - 17 - 17 - read-write - - - value1 - The Oscillator Watchdog of the PLL is not cleared and remains active - 0b0 - - - value2 - The Oscillator Watchdog of the PLL is cleared and restarted - 0b1 - - - - - RESLD - Restart VCO Lock Detection - 18 - 18 - write-only - - - AOTREN - Automatic Oscillator Calibration Enable - 19 - 19 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - FOTR - Factory Oscillator Calibration - 20 - 20 - read-write - - - value1 - No effect - 0b0 - - - value2 - Force fixed-value trimming - 0b1 - - - - - - - PLLCON1 - PLL Configuration 1 Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - K1DIV - K1-Divider Value - 0 - 6 - read-write - - - NDIV - N-Divider Value - 8 - 14 - read-write - - - K2DIV - K2-Divider Value - 16 - 22 - read-write - - - PDIV - P-Divider Value - 24 - 27 - read-write - - - - - PLLCON2 - PLL Configuration 2 Register - 0x0C - 32 - 0x00000001 - 0xFFFFFFFF - - - PINSEL - P-Divider Input Selection - 0 - 0 - read-write - - - value1 - PLL external oscillator selected - 0b0 - - - value2 - Backup clock fofi selected - 0b1 - - - - - K1INSEL - K1-Divider Input Selection - 8 - 8 - read-write - - - value1 - PLL external oscillator selected - 0b0 - - - value2 - Backup clock fofi selected - 0b1 - - - - - - - USBPLLSTAT - USB PLL Status Register - 0x10 - 32 - 0x00000002 - 0xFFFFFFFF - - - VCOBYST - VCO Bypass Status - 0 - 0 - read-only - - - value1 - Normal Mode is entered - 0b0 - - - value2 - Prescaler Mode is entered - 0b1 - - - - - PWDSTAT - PLL Power-saving Mode Status - 1 - 1 - read-only - - - value1 - PLL Power-saving Mode was not entered - 0b0 - - - value2 - PLL Power-saving Mode was entered - 0b1 - - - - - VCOLOCK - PLL VCO Lock Status - 2 - 2 - read-only - - - value1 - The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency. - 0b0 - - - value2 - The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation - 0b1 - - - - - BY - Bypass Mode Status - 6 - 6 - read-only - - - value1 - Bypass Mode is not entered - 0b0 - - - value2 - Bypass Mode is entered. Input fOSC is selected as output fPLL. - 0b1 - - - - - VCOLOCKED - PLL LOCK Status - 7 - 7 - read-only - - - value1 - PLL not locked - 0b0 - - - value2 - PLL locked - 0b1 - - - - - - - USBPLLCON - USB PLL Configuration Register - 0x14 - 32 - 0x00010003 - 0xFFFFFFFF - - - VCOBYP - VCO Bypass - 0 - 0 - read-write - - - value1 - Normal operation, VCO is not bypassed - 0b0 - - - value2 - Prescaler Mode, VCO is bypassed - 0b1 - - - - - VCOPWD - VCO Power Saving Mode - 1 - 1 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The VCO is put into a Power Saving Mode - 0b1 - - - - - VCOTR - VCO Trim Control - 2 - 2 - read-write - - - value1 - VCO bandwidth is operating in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b0 - - - value2 - VCO bandwidth is operating in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b1 - - - - - FINDIS - Disconnect Oscillator from VCO - 4 - 4 - read-write - - - value1 - Connect oscillator to the VCO part - 0b0 - - - value2 - Disconnect oscillator from the VCO part. - 0b1 - - - - - OSCDISCDIS - Oscillator Disconnect Disable - 6 - 6 - read-write - - - value1 - In case of a PLL loss-of-lock bit FINDIS is set - 0b0 - - - value2 - In case of a PLL loss-of-lock bit FINDIS is cleared - 0b1 - - - - - NDIV - N-Divider Value - 8 - 14 - read-write - - - PLLPWD - PLL Power Saving Mode - 16 - 16 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The complete PLL block is put into a Power Saving Mode. Only the Bypass Mode is active if previously selected. - 0b1 - - - - - RESLD - Restart VCO Lock Detection - 18 - 18 - write-only - - - PDIV - P-Divider Value - 24 - 27 - read-write - - - - - CLKMXSTAT - Clock Multiplexing Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSCLKMUX - Status of System Clock Multiplexing Upon Source Switching - 0 - 1 - read-only - - - value1 - fOFI clock active - 0b01 - - - value2 - fPLL clock active - 0b10 - - - - - - - - - SCU_GENERAL - System Control Unit - SCU - 0x50004000 - - 0x0 - 0x100 - registers - - - - ID - SCU Module ID Register - 0x0000 - 32 - 0x00A0C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - IDCHIP - Chip ID Register - 0x0004 - 32 - 0x00000000 - 0x00000000 - - - IDCHIP - Chip ID - 0 - 31 - read-only - - - - - IDMANUF - Manufactory ID Register - 0x0008 - 32 - 0x00001820 - 0xFFFFFFFF - - - DEPT - Department Identification Number - 0 - 4 - read-only - - - MANUF - Manufacturer Identification Number - 5 - 15 - read-only - - - - - STCON - Startup Configuration Register - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - HWCON - HW Configuration - 0 - 1 - read-only - - - value1 - Normal mode, JTAG - 0b00 - - - value2 - ASC BSL enabled - 0b01 - - - value3 - BMI customized boot enabled - 0b10 - - - value4 - CAN BSL enabled - 0b11 - - - - - SWCON - SW Configuration - 8 - 11 - read-write - - - value1 - Normal mode, boot from Boot ROM - 0b0000 - - - value2 - ASC BSL enabled - 0b0001 - - - value3 - BMI customized boot enabled - 0b0010 - - - value4 - CAN BSL enabled - 0b0011 - - - value5 - Boot from Code SRAM - 0b0100 - - - value6 - Boot from alternate Flash Address 0 - 0b1000 - - - value7 - Boot from alternate Flash Address 1 - 0b1100 - - - value8 - Enable fallback Alternate Boot Mode (ABM) - 0b1110 - - - - - - - GPR0 - General Purpose Register 0 - 0x002C - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - User Data - 0 - 31 - read-write - - - - - GPR1 - General Purpose Register 1 - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - User Data - 0 - 31 - read-write - - - - - CCUCON - CCU Control Register - 0x004C - 32 - 0x00000000 - 0xFFFFFFFF - - - GSC40 - Global Start Control CCU40 - 0 - 0 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC41 - Global Start Control CCU41 - 1 - 1 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC42 - Global Start Control CCU42 - 2 - 2 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC43 - Global Start Control CCU43 - 3 - 3 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC80 - Global Start Control CCU80 - 8 - 8 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC81 - Global Start Control CCU81 - 9 - 9 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - DTSCON - Die Temperature Sensor Control Register - 0x008C - 32 - 0x00000001 - 0xFFFFFFFF - - - PWD - Sensor Power Down - 0 - 0 - read-write - - - value1 - The DTS is powered - 0b0 - - - value2 - The DTS is not powered - 0b1 - - - - - START - Sensor Measurement Start - 1 - 1 - write-only - - - value1 - No DTS measurement is started - 0b0 - - - value2 - A DTS measurement is started - 0b1 - - - - - OFFSET - Offset Calibration Value - 4 - 10 - read-write - - - GAIN - Gain Calibration Value - 11 - 16 - read-write - - - REFTRIM - Reference Trim Calibration Value - 17 - 19 - read-write - - - BGTRIM - Bandgap Trim Calibration Value - 20 - 23 - read-write - - - - - DTSSTAT - Die Temperature Sensor Status Register - 0x0090 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of the DTS Measurement - 0 - 9 - read-only - - - RDY - Sensor Ready Status - 14 - 14 - read-only - - - value1 - The DTS is not ready - 0b0 - - - value2 - The DTS is ready - 0b1 - - - - - BUSY - Sensor Busy Status - 15 - 15 - read-only - - - value1 - not busy - 0b0 - - - value2 - busy - 0b1 - - - - - - - SDMMCDEL - SD-MMC Delay Control Register - 0x009C - 32 - 0x00000000 - 0xFFFFFFFF - - - TAPEN - Enable delay on the CMD/DAT out lines - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - TAPDEL - Number of Delay Elements Select - 4 - 7 - read-write - - - - - G0ORCEN - Out of Range Comparator Enable Register 0 - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENORC6 - Enable Out of Range Comparator, Channel 6 - 6 - 6 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ENORC7 - Enable Out of Range Comparator, Channel 7 - 7 - 7 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - G1ORCEN - Out of Range Comparator Enable Register 1 - 0x00A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENORC6 - Enable Out of Range Comparator, Channel 6 - 6 - 6 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ENORC7 - Enable Out of Range Comparator, Channel 7 - 7 - 7 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - MIRRSTS - Mirror Write Status Register - 0x00C4 - 32 - 0x00000000 - 0xFFFFFFFF - - - HDCLR - HDCLR Mirror Register Write Status - 1 - 1 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - HDSET - HDSET Mirror Register Write Status - 2 - 2 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - HDCR - HDCR Mirror Register Write Status - 3 - 3 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Write Status - 5 - 5 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Write Status - 6 - 6 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Write Status - 7 - 7 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Write Status - 8 - 8 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Write Status - 9 - 9 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Write Status - 10 - 10 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Write Status - 11 - 11 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Write Status - 12 - 12 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RMX - Retention Memory Access Register Update Status - 13 - 13 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_MSKSR - RTC MSKSSR Mirror Register Write Status - 14 - 14 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_CLRSR - RTC CLRSR Mirror Register Write Status - 15 - 15 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - - - RMACR - Retention Memory Access Control Register - 0x00C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDWR - Hibernate Retention Memory Register Update Control - 0 - 0 - read-write - - - value1 - transfer data from Retention Memory in Hibernate domain to RMDATA register - 0b0 - - - value2 - transfer data from RMDATA into Retention Memory in Hibernate domain - 0b1 - - - - - ADDR - Hibernate Retention Memory Register Address Select - 16 - 19 - read-write - - - - - RMDATA - Retention Memory Access Data Register - 0x00CC - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Hibernate Retention Memory Data - 0 - 31 - read-write - - - - - - - SCU_INTERRUPT - System Control Unit - SCU - 0x50004074 - - 0x0 - 0x18 - registers - - - - SRSTAT - SCU Service Request Status - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Status - 0 - 0 - read-only - - - value1 - Inactive - 0b0 - - - value2 - Active - 0b1 - - - - - PI - RTC Periodic Interrupt Status - 1 - 1 - read-only - - - AI - Alarm Interrupt Status - 2 - 2 - read-only - - - DLROVR - DLR Request Overrun Interrupt Status - 3 - 3 - read-only - - - HDSTAT - HDSTAT Mirror Register Update Status - 16 - 16 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Status - 17 - 17 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDSET - HDSET Mirror Register Update Status - 18 - 18 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCR - HDCR Mirror Register Update Status - 19 - 19 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Status - 21 - 21 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Status - 22 - 22 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Status - 23 - 23 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Status - 24 - 24 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Status - 25 - 25 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Status - 26 - 26 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Status - 27 - 27 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Status - 28 - 28 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Status - 29 - 29 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - - - SRRAW - SCU Raw Service Request Status - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Status Before Masking - 0 - 0 - read-only - - - value1 - Inactive - 0b0 - - - value2 - Active - 0b1 - - - - - PI - RTC Raw Periodic Interrupt Status Before Masking - 1 - 1 - read-only - - - AI - RTC Raw Alarm Interrupt Status Before Masking - 2 - 2 - read-only - - - DLROVR - DLR Request Overrun Interrupt Status Before Masking - 3 - 3 - read-only - - - HDSTAT - HDSTAT Mirror Register Update Status Before Masking - 16 - 16 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Status Before Masking - 17 - 17 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDSET - HDSET Mirror Register Update Status Before Masking - 18 - 18 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCR - HDCR Mirror Register Update Status Before Masking - 19 - 19 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Status Before Masking - 21 - 21 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Status Before Masking - 22 - 22 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Status Before Masking - 23 - 23 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Status Before Masking - 24 - 24 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Status Before Masking - 25 - 25 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Status Before Masking - 26 - 26 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Before Masking Status - 27 - 27 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Status Before Masking - 28 - 28 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Status Before Masking - 29 - 29 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - - - SRMSK - SCU Service Request Mask - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Mask - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PI - RTC Periodic Interrupt Mask - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - AI - RTC Alarm Interrupt Mask - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - DLROVR - DLR Request Overrun Interrupt Mask - 3 - 3 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDSTAT - HDSTAT Mirror Register Update Mask - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Mask - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDSET - HDSET Mirror Register Update Mask - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDCR - HDCR Mirror Register Update Mask - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Mask - 21 - 21 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Mask - 22 - 22 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Mask - 23 - 23 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Mask - 24 - 24 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Mask - 25 - 25 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Mask - 26 - 26 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Mask - 27 - 27 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Mask - 28 - 28 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Mask - 29 - 29 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - SRCLR - SCU Service Request Clear - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - PI - RTC Periodic Interrupt Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - AI - RTC Alarm Interrupt Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - DLROVR - DLR Request Overrun Interrupt clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDSTAT - HDCTAT Mirror Register Update Clear - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Clear - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDSET - HDSET Mirror Register Update Clear - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDCR - HDCR Mirror Register Update Clear - 19 - 19 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Clear - 21 - 21 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Clear - 22 - 22 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Clear - 23 - 23 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Clear - 24 - 24 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Clear - 25 - 25 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Clear - 26 - 26 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Clear - 27 - 27 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Clear - 28 - 28 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Clear - 29 - 29 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - - - SRSET - SCU Service Request Set - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Set - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - PI - RTC Periodic Interrupt Set - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - AI - RTC Alarm Interrupt Set - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - DLROVR - DLR Request Overrun Interrupt Set - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDSTAT - HDSTAT Mirror Register Update Set - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDCRCLR - HDCRCLR Mirror Register Update Set - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDCRSET - HDCRSET Mirror Register Update Set - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDCR - HDCR Mirror Register Update Set - 19 - 19 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Set - 21 - 21 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Set - 22 - 22 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Set - 23 - 23 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Set - 24 - 24 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Set - 25 - 25 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Set - 26 - 26 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Set - 27 - 27 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Set - 28 - 28 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Set - 29 - 29 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - - - NMIREQEN - SCU Service Request Mask - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - Promote Pre-Warning Interrupt Request to NMI Request - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PI - Promote RTC Periodic Interrupt request to NMI Request - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - AI - Promote RTC Alarm Interrupt Request to NMI Request - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU00 - Promote Channel 0 Interrupt of ERU0 Request to NMI Request - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU01 - Promote Channel 1 Interrupt of ERU0 Request to NMI Request - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU02 - Promote Channel 2 Interrupt of ERU0 Request to NMI Request - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU03 - Promote Channel 3 Interrupt of ERU0 Request to NMI Request - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - - - SCU_PARITY - System Control Unit - SCU - 0x5000413C - - 0x0 - 0x20 - registers - - - - PEEN - Parity Error Enable Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - PEENPS - Parity Error Enable for PSRAM - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENDS1 - Parity Error Enable for DSRAM1 - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENDS2 - Parity Error Enable for DSRAM2 - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENU0 - Parity Error Enable for USIC0 Memory - 8 - 8 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENU1 - Parity Error Enable for USIC1 Memory - 9 - 9 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENU2 - Parity Error Enable for USIC2 Memory - 10 - 10 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENMC - Parity Error Enable for MultiCAN Memory - 12 - 12 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENPPRF - Parity Error Enable for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENUSB - Parity Error Enable for USB Memory - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENETH0TX - Parity Error Enable for ETH TX Memory - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENETH0RX - Parity Error Enable for ETH RX Memory - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENSD0 - Parity Error Enable for SDMMC Memory 0 - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENSD1 - Parity Error Enable for SDMMC Memory 1 - 20 - 20 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - MCHKCON - Memory Checking Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - SELPS - Select Memory Check for PSRAM - 0 - 0 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELDS1 - Select Memory Check for DSRAM1 - 1 - 1 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELDS2 - Select Memory Check for DSRAM2 - 2 - 2 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - USIC0DRA - Select Memory Check for USIC0 - 8 - 8 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - USIC1DRA - Select Memory Check for USIC1 - 9 - 9 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - USIC2DRA - Select Memory Check for USIC2 - 10 - 10 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - MCANDRA - Select Memory Check for MultiCAN - 12 - 12 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - PPRFDRA - Select Memory Check for PMU - 13 - 13 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELUSB - Select Memory Check for USB SRAM - 16 - 16 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELETH0TX - Select Memory Check for ETH0 TX SRAM - 17 - 17 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELETH0RX - Select Memory Check for ETH0 RX SRAM - 18 - 18 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELSD0 - Select Memory Check for SDMMC SRAM 0 - 19 - 19 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELSD1 - Select Memory Check for SDMMC SRAM 1 - 20 - 20 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - - - PETE - Parity Error Trap Enable Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETEPS - Parity Error Trap Enable for PSRAM - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEDS1 - Parity Error Trap Enable for DSRAM1 - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEDS2 - Parity Error Trap Enable for DSRAM2 - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEU0 - Parity Error Trap Enable for USIC0 Memory - 8 - 8 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEU1 - Parity Error Trap Enable for USIC1 Memory - 9 - 9 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEU2 - Parity Error Trap Enable for USIC2 Memory - 10 - 10 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEMC - Parity Error Trap Enable for MultiCAN Memory - 12 - 12 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEPPRF - Parity Error Trap Enable for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEUSB - Parity Error Trap Enable for USB Memory - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEETH0TX - Parity Error Trap Enable for ETH 0TX Memory - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEETH0RX - Parity Error Trap Enable for ETH0 RX Memory - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETESD0 - Parity Error Trap Enable for SDMMC SRAM 0 Memory - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETESD1 - Parity Error Trap Enable for SDMMC SRAM 1 Memory - 20 - 20 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - PERSTEN - Parity Error Reset Enable Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - RSEN - System Reset Enable upon Parity Error Trap - 0 - 0 - read-write - - - value1 - Reset request disabled - 0b0 - - - value2 - Reset request enabled - 0b1 - - - - - - - PEFLAG - Parity Error Flag Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PEFPS - Parity Error Flag for PSRAM - 0 - 0 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFDS1 - Parity Error Flag for DSRAM1 - 1 - 1 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFDS2 - Parity Error Flag for DSRAM2 - 2 - 2 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFU0 - Parity Error Flag for USIC0 Memory - 8 - 8 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFU1 - Parity Error Flag for USIC1 Memory - 9 - 9 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFU2 - Parity Error Flag for USIC2 Memory - 10 - 10 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFMC - Parity Error Flag for MultiCAN Memory - 12 - 12 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFPPRF - Parity Error Flag for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEUSB - Parity Error Flag for USB Memory - 16 - 16 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEETH0TX - Parity Error Flag for ETH TX Memory - 17 - 17 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEETH0RX - Parity Error Flag for ETH RX Memory - 18 - 18 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PESD0 - Parity Error Flag for SDMMC Memory 0 - 19 - 19 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PESD1 - Parity Error Flag for SDMMC Memory 1 - 20 - 20 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - - - PMTPR - Parity Memory Test Pattern Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRD - Parity Read Values for Memory Test - 8 - 15 - read-only - - - PWR - Parity Write Values for Memory Test - 0 - 7 - read-write - - - - - PMTSR - Parity Memory Test Select Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - MTENPS - Test Enable Control for PSRAM - 0 - 0 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTENDS1 - Test Enable Control for DSRAM1 - 1 - 1 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTENDS2 - Test Enable Control for DSRAM2 - 2 - 2 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEU0 - Test Enable Control for USIC0 Memory - 8 - 8 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEU1 - Test Enable Control for USIC1 Memory - 9 - 9 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEU2 - Test Enable Control for USIC2 Memory - 10 - 10 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEMC - Test Enable Control for MultiCAN Memory - 12 - 12 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEPPRF - Test Enable Control for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTUSB - Test Enable Control for USB Memory - 16 - 16 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTETH0TX - Test Enable Control for ETH TX Memory - 17 - 17 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTETH0RX - Test Enable Control for ETH RX Memory - 18 - 18 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTSD0 - Test Enable Control for SDMMC Memory 0 - 19 - 19 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTSD1 - Test Enable Control for SDMMC Memory 1 - 20 - 20 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - - - - - SCU_TRAP - System Control Unit - SCU - 0x50004160 - - 0x0 - 0x14 - registers - - - - TRAPSTAT - Trap Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Status - 0 - 0 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Status - 2 - 2 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Status - 3 - 3 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - PET - Parity Error Trap Status - 4 - 4 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BRWNT - Brown Out Trap Status - 5 - 5 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Status - 6 - 6 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Status - 7 - 7 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Status - 8 - 8 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - - - TRAPRAW - Trap Raw Status Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Raw Status - 0 - 0 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Raw Status - 2 - 2 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Raw Status - 3 - 3 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - PET - Parity Error Trap Raw Status - 4 - 4 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BRWNT - Brown Out Trap Raw Status - 5 - 5 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Raw Status - 6 - 6 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Raw Status - 7 - 7 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Raw Status - 8 - 8 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - - - TRAPDIS - Trap Disable Register - 0x08 - 32 - 0x000001FF - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Disable - 0 - 0 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Disable - 2 - 2 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Disable - 3 - 3 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - PET - Parity Error Trap Disable - 4 - 4 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - BRWNT - Brown Out Trap Disable - 5 - 5 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Disable - 6 - 6 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Disable - 7 - 7 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Disable - 8 - 8 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - - - TRAPCLR - Trap Clear Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - PET - Parity Error Trap Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - BRWNT - Brown Out Trap Clear - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Clear - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Clear - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - - - TRAPSET - Trap Set Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Set - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Set - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Set - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - PET - Parity Error Trap Set - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - BRWNT - Brown Out Trap Set - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - ULPWDT - OSC_ULP Oscillator Watchdog Trap Set - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Set - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Set - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - - - - - SCU_HIBERNATE - System Control Unit - SCU - 0x50004300 - - 0x0 - 0x100 - registers - - - - HDSTAT - Hibernate Domain Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPEV - Wake-up Pin Event Positive Edge - 0 - 0 - read-only - - - value1 - Wake-up on positive edge pin event inactive - 0b0 - - - value2 - Wake-up on positive edge pin event active - 0b1 - - - - - ENEV - Wake-up Pin Event Negative Edge - 1 - 1 - read-only - - - value1 - Wake-up on negative edge pin event inactive - 0b0 - - - value2 - Wake-up on negative edge pin event active - 0b1 - - - - - RTCEV - RTC Event - 2 - 2 - read-only - - - value1 - Wake-up on RTC event inactive - 0b0 - - - value2 - Wake-up on RTC event active - 0b1 - - - - - ULPWDG - ULP WDG Alarm Status - 3 - 3 - read-only - - - value1 - Watchdog alarm did not occur - 0b0 - - - value2 - Watchdog alarm occurred - 0b1 - - - - - HIBNOUT - Hibernate Control Status - 4 - 4 - read-only - - - value1 - Hibernate not driven active to pads - 0b0 - - - value2 - Hibernate driven active to pads - 0b1 - - - - - - - HDCLR - Hibernate Domain Status Clear Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPEV - Wake-up Pin Event Positive Edge Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear wake-up event - 0b1 - - - - - ENEV - Wake-up Pin Event Negative Edge Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear wake-up event - 0b1 - - - - - RTCEV - RTC Event Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear wake-up event - 0b1 - - - - - ULPWDG - ULP WDG Alarm Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear watchdog alarm - 0b1 - - - - - - - HDSET - Hibernate Domain Status Set Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPEV - Wake-up Pin Event Positive Edge Set - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set wake-up event - 0b1 - - - - - ENEV - Wake-up Pin Event Negative Edge Set - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set wake-up event - 0b1 - - - - - RTCEV - RTC Event Set - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set wake-up event - 0b1 - - - - - ULPWDG - ULP WDG Alarm Set - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set watchdog alarm - 0b1 - - - - - - - HDCR - Hibernate Domain Control Register - 0x0C - 32 - 0x000C2000 - 0xFFFFFFFF - - - WKPEP - Wake-Up on Pin Event Positive Edge Enable - 0 - 0 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - WKPEN - Wake-up on Pin Event Negative Edge Enable - 1 - 1 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - RTCE - Wake-up on RTC Event Enable - 2 - 2 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - ULPWDGEN - ULP WDG Alarm Enable - 3 - 3 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - HIB - Hibernate Request Value Set - 4 - 4 - read-write - - - value1 - External hibernate request inactive - 0b0 - - - value2 - External hibernate request active - 0b1 - - - - - RCS - fRTC Clock Selection - 6 - 6 - read-write - - - value1 - fOSI selected - 0b0 - - - value2 - fULP selected - 0b1 - - - - - STDBYSEL - fSTDBY Clock Selection - 7 - 7 - read-write - - - value1 - fOSI selected - 0b0 - - - value2 - fULP selected - 0b1 - - - - - WKUPSEL - Wake-Up from Hibernate Trigger Input Selection - 8 - 8 - read-write - - - value1 - HIB_IO_1 pin selected - 0b0 - - - value2 - HIB_IO_0 pin selected - 0b1 - - - - - GPI0SEL - General Purpose Input 0 Selection - 10 - 10 - read-write - - - value1 - HIB_IO_1 pin selected - 0b0 - - - value2 - HIB_IO_0 pin selected - 0b1 - - - - - HIBIO0POL - HIBIO0 Polarity Set - 12 - 12 - read-write - - - value1 - Direct value - 0b0 - - - value2 - Inverted value - 0b1 - - - - - HIBIO1POL - HIBIO1 Polarity Set - 13 - 13 - read-write - - - value1 - Direct value - 0b0 - - - value2 - Inverted value - 0b1 - - - - - HIBIO0SEL - HIB_IO_0 Pin I/O Control (default HIBOUT) - 16 - 19 - read-write - - - value1 - Direct input, No input pull device connected - 0b0000 - - - value2 - Direct input, Input pull-down device connected - 0b0001 - - - value3 - Direct input, Input pull-up device connected - 0b0010 - - - value4 - Push-pull HIB Control output - 0b1000 - - - value5 - Push-pull WDT service output - 0b1001 - - - value6 - Push-pull GPIO output - 0b1010 - - - value7 - Open-drain HIB Control output - 0b1100 - - - value8 - Open-drain WDT service output - 0b1101 - - - value9 - Open-drain GPIO output - 0b1110 - - - - - HIBIO1SEL - HIB_IO_1 Pin I/O Control (Default WKUP) - 20 - 23 - read-write - - - value1 - Direct input, No input pull device connected - 0b0000 - - - value2 - Direct input, Input pull-down device connected - 0b0001 - - - value3 - Direct input, Input pull-up device connected - 0b0010 - - - value4 - Push-pull HIB Control output - 0b1000 - - - value5 - Push-pull WDT service output - 0b1001 - - - value6 - Push-pull GPIO output - 0b1010 - - - value7 - Open-drain HIB Control output - 0b1100 - - - value8 - Open-drain WDT service output - 0b1101 - - - value9 - Open-drain GPIO output - 0b1110 - - - - - - - OSCSICTRL - fOSI Control Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - PWD - Turn OFF the fOSI Clock Source - 0 - 0 - read-write - - - value1 - Enabled - 0b0 - - - value2 - Disabled - 0b1 - - - - - - - OSCULSTAT - OSC_ULP Status Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - X1D - XTAL1 Data Value - 0 - 0 - read-only - - - - - OSCULCTRL - OSC_ULP Control Register - 0x1C - 32 - 0x00000020 - 0xFFFFFFFF - - - X1DEN - XTAL1 Data General Purpose Input Enable - 0 - 0 - read-write - - - value1 - Data input inactivated, power down - 0b0 - - - value2 - Data input active - 0b1 - - - - - MODE - Oscillator Mode - 4 - 5 - read-write - - - value1 - Oscillator is enabled, in operation - 0b00 - - - value2 - Oscillator is enabled, in bypass mode - 0b01 - - - value3 - Oscillator in power down - 0b10 - - - value4 - Oscillator in power down, can be used as GPI - 0b11 - - - - - - - - - SCU_POWER - System Control Unit - SCU - 0x50004200 - - 0x0 - 0x100 - registers - - - - PWRSTAT - PCU Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIBEN - Hibernate Domain Enable Status - 0 - 0 - read-only - - - value1 - Inactive - 0b0 - - - value2 - Active - 0b1 - - - - - USBPHYPDQ - USB PHY Transceiver State - 16 - 16 - read-only - - - value1 - Power-down - 0b0 - - - value2 - Active - 0b1 - - - - - USBOTGEN - USB On-The-Go Comparators State - 17 - 17 - read-only - - - value1 - Power-down - 0b0 - - - value2 - Active - 0b1 - - - - - USBPUWQ - USB Weak Pull-Up at PADN State - 18 - 18 - read-only - - - value1 - Pull-up active - 0b0 - - - value2 - Pull-up not active - 0b1 - - - - - - - PWRSET - PCU Set Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIB - Set Hibernate Domain Enable - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable Hibernate domain - 0b1 - - - - - USBPHYPDQ - Set USB PHY Transceiver Disable - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Active - 0b1 - - - - - USBOTGEN - Set USB On-The-Go Comparators Enable - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - Active - 0b1 - - - - - USBPUWQ - Set USB Weak Pull-Up at PADN Enable - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - Pull-up not active - 0b1 - - - - - - - PWRCLR - PCU Clear Control Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIB - Clear Disable Hibernate Domain - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable Hibernate domain - 0b1 - - - - - USBPHYPDQ - Clear USB PHY Transceiver Disable - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Power-down - 0b1 - - - - - USBOTGEN - Clear USB On-The-Go Comparators Enable - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - Power-down - 0b1 - - - - - USBPUWQ - Clear USB Weak Pull-Up at PADN Enable - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - Pull-up active - 0b1 - - - - - - - EVRSTAT - EVR Status Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - OV13 - Regulator Overvoltage for 1.3 V - 1 - 1 - read-only - - - value1 - No overvoltage condition - 0b0 - - - value2 - Regulator is in overvoltage - 0b1 - - - - - - - EVRVADCSTAT - EVR VADC Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VADC13V - VADC 1.3 V Conversion Result - 0 - 7 - read-only - - - VADC33V - VADC 3.3 V Conversion Result - 8 - 15 - read-only - - - - - PWRMON - Power Monitor Control - 0x2C - 32 - 0x00000000 - 0xFFFFFFFF - - - THRS - Threshold - 0 - 7 - read-write - - - INTV - Interval - 8 - 15 - read-write - - - ENB - Enable - 16 - 16 - read-write - - - - - - - SCU_RESET - System Control Unit - SCU - 0x50004400 - - 0x0 - 0x100 - registers - - - - RSTSTAT - RCU Reset Status - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSTSTAT - Reset Status Information - 0 - 7 - read-only - - - value1 - PORST reset - 0b00000001 - - - value2 - SWD reset - 0b00000010 - - - value3 - PV reset - 0b00000100 - - - value4 - CPU system reset - 0b00001000 - - - value5 - CPU lockup reset - 0b00010000 - - - value6 - WDT reset - 0b00100000 - - - value7 - Reserved - 0b01000000 - - - value8 - Parity Error reset - 0b10000000 - - - - - HIBWK - Hibernate Wake-up Status - 8 - 8 - read-only - - - value1 - No Wake-up - 0b0 - - - value2 - Wake-up event - 0b1 - - - - - HIBRS - Hibernate Reset Status - 9 - 9 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - LCKEN - Enable Lockup Status - 10 - 10 - read-only - - - value1 - Reset by Lockup disabled - 0b0 - - - value2 - Reset by Lockup enabled - 0b1 - - - - - - - RSTSET - RCU Reset Set Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIBWK - Set Hibernate Wake-up Reset Status - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset status bit - 0b1 - - - - - HIBRS - Set Hibernate Reset - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - LCKEN - Enable Lockup Reset - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable reset when Lockup gets asserted - 0b1 - - - - - - - RSTCLR - RCU Reset Clear Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSCLR - Clear Reset Status - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clears field RSTSTAT.RSTSTAT - 0b1 - - - - - HIBWK - Clear Hibernate Wake-up Reset Status - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset status bit - 0b1 - - - - - HIBRS - Clear Hibernate Reset - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - LCKEN - Enable Lockup Reset - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable reset when Lockup gets asserted - 0b1 - - - - - - - PRSTAT0 - RCU Peripheral 0 Reset Status - 0x0C - 32 - 0x00010F9F - 0xFFFFFFFF - - - VADCRS - VADC Reset Status - 0 - 0 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DSDRS - DSD Reset Status - 1 - 1 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU40RS - CCU40 Reset Status - 2 - 2 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU41RS - CCU41 Reset Status - 3 - 3 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU42RS - CCU42 Reset Status - 4 - 4 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU80RS - CCU80 Reset Status - 7 - 7 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU81RS - CCU81 Reset Status - 8 - 8 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - POSIF0RS - POSIF0 Reset Status - 9 - 9 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - POSIF1RS - POSIF1 Reset Status - 10 - 10 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USIC0RS - USIC0 Reset Status - 11 - 11 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - ERU1RS - ERU1 Reset Status - 16 - 16 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET0 - RCU Peripheral 0 Reset Set - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VADCRS - VADC Reset Assert - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DSDRS - DSD Reset Assert - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU40RS - CCU40 Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU41RS - CCU41 Reset Assert - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU42RS - CCU42 Reset Assert - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU80RS - CCU80 Reset Assert - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU81RS - CCU81 Reset Assert - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - POSIF0RS - POSIF0 Reset Assert - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - POSIF1RS - POSIF1 Reset Assert - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USIC0RS - USIC0 Reset Assert - 11 - 11 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - ERU1RS - ERU1 Reset Assert - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR0 - RCU Peripheral 0 Reset Clear - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VADCRS - VADC Reset Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DSDRS - DSD Reset Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU40RS - CCU40 Reset Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU41RS - CCU41 Reset Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU42RS - CCU42 Reset Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU80RS - CCU80 Reset Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU81RS - CCU81 Reset Clear - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - POSIF0RS - POSIF0 Reset Clear - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - POSIF1RS - POSIF1 Reset Clear - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USIC0RS - USIC0 Reset Clear - 11 - 11 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - ERU1RS - ERU1 Reset Clear - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - PRSTAT1 - RCU Peripheral 1 Reset Status - 0x18 - 32 - 0x000001F9 - 0xFFFFFFFF - - - CCU43RS - CCU43 Reset Status - 0 - 0 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - LEDTSCU0RS - LEDTS Reset Status - 3 - 3 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - MCAN0RS - MultiCAN Reset Status - 4 - 4 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DACRS - DAC Reset Status - 5 - 5 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - MMCIRS - MMC Interface Reset Status - 6 - 6 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USIC1RS - USIC1 Reset Status - 7 - 7 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USIC2RS - USIC2 Reset Status - 8 - 8 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - PPORTSRS - PORTS Reset Status - 9 - 9 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET1 - RCU Peripheral 1 Reset Set - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - CCU43RS - CCU43 Reset Assert - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - LEDTSCU0RS - LEDTS Reset Assert - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - MCAN0RS - MultiCAN Reset Assert - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DACRS - DAC Reset Assert - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - MMCIRS - MMC Interface Reset Assert - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USIC1RS - USIC1 Reset Assert - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USIC2RS - USIC2 Reset Assert - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - PPORTSRS - PORTS Reset Assert - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR1 - RCU Peripheral 1 Reset Clear - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CCU43RS - CCU43 Reset Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - LEDTSCU0RS - LEDTS Reset Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - MCAN0RS - MultiCAN Reset Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DACRS - DAC Reset Clear - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - MMCIRS - MMC Interface Reset Clear - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USIC1RS - USIC1 Reset Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USIC2RS - USIC2 Reset Clear - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - PPORTSRS - PORTS Reset Clear - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - PRSTAT2 - RCU Peripheral 2 Reset Status - 0x24 - 32 - 0x000000F6 - 0xFFFFFFFF - - - WDTRS - WDT Reset Status - 1 - 1 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - ETH0RS - ETH0 Reset Status - 2 - 2 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DMA0RS - DMA0 Reset Status - 4 - 4 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DMA1RS - DMA1 Reset Status - 5 - 5 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - FCERS - FCE Reset Status - 6 - 6 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USBRS - USB Reset Status - 7 - 7 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET2 - RCU Peripheral 2 Reset Set - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDTRS - WDT Reset Assert - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - ETH0RS - ETH0 Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DMA0RS - DMA0 Reset Assert - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DMA1RS - DMA1 Reset Assert - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - FCERS - FCE Reset Assert - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USBRS - USB Reset Assert - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR2 - RCU Peripheral 2 Reset Clear - 0x2C - 32 - 0x00000000 - 0xFFFFFFFF - - - WDTRS - WDT Reset Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - ETH0RS - ETH0 Reset Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DMA0RS - DMA0 Reset Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DMA1RS - DMA1 Reset Clear - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - FCERS - FCE Reset Clear - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USBRS - USB Reset Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - PRSTAT3 - RCU Peripheral 3 Reset Status - 0x30 - 32 - 0x00000004 - 0xFFFFFFFF - - - EBURS - EBU Reset Status - 2 - 2 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET3 - RCU Peripheral 3 Reset Set - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - EBURS - EBU Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR3 - RCU Peripheral 3 Reset Clear - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - EBURS - EBU Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - - - LEDTS0 - LED and Touch Sense Unit 0 - LEDTS - 0x48010000 - - 0x0 - 0x0100 - registers - - - - ID - Module Identification Register - 0x0000 - 32 - 0x00ABC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - GLOBCTL - Global Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - TS_EN - Touch-Sense Function Enable - 0 - 0 - read-write - - - LD_EN - LED Function Enable - 1 - 1 - read-write - - - CMTR - Clock Master Disable - 2 - 2 - read-write - - - value1 - Kernel generates its own clock for LEDTS-counter based on SFR setting - 0b0 - - - value2 - LEDTS-counter takes its clock from another master kernel - 0b1 - - - - - ENSYNC - Enable Autoscan Time Period Synchronization - 3 - 3 - read-write - - - value1 - No synchronization - 0b0 - - - value2 - Synchronization enabled on Kernel0 autoscan time period - 0b1 - - - - - SUSCFG - Suspend Request Configuration - 8 - 8 - read-write - - - value1 - Ignore suspend request - 0b0 - - - value2 - Enable suspend according to request - 0b1 - - - - - MASKVAL - Mask Number of LSB Bits for Event Validation - 9 - 11 - read-write - - - value1 - Mask LSB bit - 0 - - - value2 - Mask 2 LSB bits - 1 - - - value3 - Mask 8 LSB bits - 7 - - - - - FENVAL - Enable (Extended) Time Frame Validation - 12 - 12 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ITS_EN - Enable Time Slice Interrupt - 13 - 13 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ITF_EN - Enable (Extended) Time Frame Interrupt - 14 - 14 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ITP_EN - Enable Autoscan Time Period Interrupt - 15 - 15 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable (valid only for case of hardware-enabled pad turn control) - 0b1 - - - - - CLK_PS - LEDTS-Counter Clock Pre-Scale Factor - 16 - 31 - read-write - - - value1 - No clock - 0 - - - value2 - Divide by 1 - 1 - - - value3 - Divide by 65535 - 65535 - - - - - - - FNCTL - Function Control Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - PADT - Touch-Sense TSIN Pad Turn - 0 - 2 - read-write - - - value1 - TSIN0 - 0 - - - value2 - TSIN7 - 7 - - - - - PADTSW - Software Control for Touch-Sense Pad Turn - 3 - 3 - read-write - - - value1 - The hardware automatically enables the touch-sense inputs in sequence round-robin, starting from TSIN0. - 0b0 - - - value2 - Disable hardware control for software control only. The touch-sense input is configured in bit PADT. - 0b1 - - - - - EPULL - Enable External Pull-up Configuration on Pin COLA - 4 - 4 - read-write - - - value1 - HW over-rule to enable internal pull-up is active on TSIN[x] for set duration in touch-sense time slice. With this setting, it is not specified to assign the COLA to any pin. - 0b0 - - - value2 - Enable external pull-up: Output 1 on pin COLA for whole duration of touch-sense time slice. - 0b1 - - - - - FNCOL - Previous Active Function/LED Column Status - 5 - 7 - read-only - - - ACCCNT - Accumulate Count on Touch-Sense Input - 16 - 19 - read-write - - - value1 - 1 time - 0 - - - value2 - 2 times - 1 - - - value3 - 16 times - 15 - - - - - TSCCMP - Common Compare Enable for Touch-Sense - 20 - 20 - read-write - - - value1 - Disable common compare for touch-sense - 0b0 - - - value2 - Enable common compare for touch-sense - 0b1 - - - - - TSOEXT - Extension for Touch-Sense Output for Pin-Low-Level - 21 - 22 - read-write - - - value1 - Extend by 1 ledts_clk - 0b00 - - - value2 - Extend by 4 ledts_clk - 0b01 - - - value3 - Extend by 8 ledts_clk - 0b10 - - - value4 - Extend by 16 ledts_clk - 0b11 - - - - - TSCTRR - TS-Counter Auto Reset - 23 - 23 - read-write - - - value1 - Disable TS-counter automatic reset - 0b0 - - - value2 - Enable TS-counter automatic reset to 00H on the first pad turn of a new TSIN[x]. Triggered on compare match in time slice. - 0b1 - - - - - TSCTRSAT - Saturation of TS-Counter - 24 - 24 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable. TS-counter stops counting in the touch-sense time slice(s) of the same (extended) frame when it reaches FFH. Counter starts to count again on the first pad turn of a new TSIN[x], triggered on compare match. - 0b1 - - - - - NR_TSIN - Number of Touch-Sense Input - 25 - 27 - read-write - - - value1 - 1 - 0 - - - value2 - 8 - 7 - - - - - COLLEV - Active Level of LED Column - 28 - 28 - read-write - - - value1 - Active low - 0b0 - - - value2 - Active high - 0b1 - - - - - NR_LEDCOL - Number of LED Columns - 29 - 31 - read-write - - - value1 - 1 LED column - 0b000 - - - value2 - 2 LED columns - 0b001 - - - value3 - 3 LED columns - 0b010 - - - value4 - 4 LED columns - 0b011 - - - value5 - 5 LED columns - 0b100 - - - value6 - 6 LED columns - 0b101 - - - value7 - 7 LED columns - 0b110 - - - value8 - 8 LED columns (max. LED columns = 7 if bit TS_EN = 1) - 0b111 - - - - - - - EVFR - Event Flag Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - TSF - Time Slice Interrupt Flag - 0 - 0 - read-only - - - TFF - (Extended) Time Frame Interrupt Flag - 1 - 1 - read-only - - - TPF - Autoscan Time Period Interrupt Flag - 2 - 2 - read-only - - - TSCTROVF - TS-Counter Overflow Indication - 3 - 3 - read-only - - - value1 - No overflow has occurred. - 0b0 - - - value2 - The TS-counter has overflowed at least once. - 0b1 - - - - - CTSF - Clear Time Slice Interrupt Flag - 16 - 16 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TSF is cleared. - 0b1 - - - - - CTFF - Clear (Extended) Time Frame Interrupt Flag - 17 - 17 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TFF is cleared. - 0b1 - - - - - CTPF - Clear Autoscan Time Period Interrupt Flag - 18 - 18 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TPF is cleared. - 0b1 - - - - - - - TSVAL - Touch-sense TS-Counter Value - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSCTRVALR - Shadow TS-Counter (Read) - 0 - 15 - read-only - - - TSCTRVAL - TS-Counter Value - 16 - 31 - read-write - - - - - LINE0 - Line Pattern Register 0 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINE_0 - Output on LINE[x] - 0 - 7 - read-write - - - LINE_1 - Output on LINE[x] - 8 - 15 - read-write - - - LINE_2 - Output on LINE[x] - 16 - 23 - read-write - - - LINE_3 - Output on LINE[x] - 24 - 31 - read-write - - - - - LINE1 - Line Pattern Register 1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINE_4 - Output on LINE[x] - 0 - 7 - read-write - - - LINE_5 - Output on LINE[x] - 8 - 15 - read-write - - - LINE_6 - Output on LINE[x] - 16 - 23 - read-write - - - LINE_A - Output on LINE[x] - 24 - 31 - read-write - - - - - LDCMP0 - LED Compare Register 0 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_LD0 - Compare Value for LED COL[x] - 0 - 7 - read-write - - - CMP_LD1 - Compare Value for LED COL[x] - 8 - 15 - read-write - - - CMP_LD2 - Compare Value for LED COL[x] - 16 - 23 - read-write - - - CMP_LD3 - Compare Value for LED COL[x] - 24 - 31 - read-write - - - - - LDCMP1 - LED Compare Register 1 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_LD4 - Compare Value for LED COL[x] - 0 - 7 - read-write - - - CMP_LD5 - Compare Value for LED COL[x] - 8 - 15 - read-write - - - CMP_LD6 - Compare Value for LED COL[x] - 16 - 23 - read-write - - - CMP_LDA_TSCOM - Compare Value for LED COLA / Common Compare Value for Touch-sense Pad Turns - 24 - 31 - read-write - - - - - TSCMP0 - Touch-sense Compare Register 0 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_TS0 - Compare Value for Touch-Sense TSIN[x] - 0 - 7 - read-write - - - CMP_TS1 - Compare Value for Touch-Sense TSIN[x] - 8 - 15 - read-write - - - CMP_TS2 - Compare Value for Touch-Sense TSIN[x] - 16 - 23 - read-write - - - CMP_TS3 - Compare Value for Touch-Sense TSIN[x] - 24 - 31 - read-write - - - - - TSCMP1 - Touch-sense Compare Register 1 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_TS4 - Compare Value for Touch-Sense TSIN[x] - 0 - 7 - read-write - - - CMP_TS5 - Compare Value for Touch-Sense TSIN[x] - 8 - 15 - read-write - - - CMP_TS6 - Compare Value for Touch-Sense TSIN[x] - 16 - 23 - read-write - - - CMP_TS7 - Compare Value for Touch-Sense TSIN[x] - 24 - 31 - read-write - - - - - - - SDMMC - SD and Multimediacard Interface - 0x4801C000 - - 0x0 - 0x4000 - registers - - - - BLOCK_SIZE - Block Size Register - 0x0004 - 16 - 0x0000 - 0xFFFF - - - TX_BLOCK_SIZE_12 - Transfer Block Size 12th bit. - 15 - 15 - read-write - - - TX_BLOCK_SIZE - Transfer Block Size - 0 - 11 - read-write - - - value1 - No Data Transfer - 0x0000 - - - value2 - 1 Byte - 0x0001 - - - value3 - 2 Bytes - 0x0002 - - - value4 - 3 Bytes - 0x0003 - - - value5 - 4 Bytes - 0x0004 - - - value6 - 511 Bytes - 0x01FF - - - value7 - 512 Bytes (Maximum Block Size) - 0x0200 - - - - - - - BLOCK_COUNT - Block Count Register - 0x0006 - 16 - 0x0000 - 0xFFFF - - - BLOCK_COUNT - Blocks Count for Current Transfer - 0 - 15 - read-write - - - value1 - Stop Count - 0x0000 - - - value2 - 1 block - 0x0001 - - - value3 - 2 blocks - 0x0002 - - - value4 - 65535 blocks - 0xFFFF - - - - - - - ARGUMENT1 - Argument1 Register - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMENT1 - Command Argument - 0 - 31 - read-write - - - - - TRANSFER_MODE - Transfer Mode Register - 0x000C - 16 - 0x0000 - 0xFFFF - - - CMD_COMP_ATA - Command Completion Signal Enable for CE-ATA Device - 6 - 6 - read-write - - - value1 - Device will send command completion Signal - 0b1 - - - value2 - Device will not send command completion Signal - 0b0 - - - - - MULTI_BLOCK_SELECT - Multi / Single Block Select - 5 - 5 - read-write - - - value1 - Single Block - 0b0 - - - value2 - Multiple Block - 0b1 - - - - - TX_DIR_SELECT - Data Transfer Direction Select - 4 - 4 - read-write - - - value1 - Write (Host to Card) - 0b0 - - - value2 - Read (Card to Host) - 0b1 - - - - - ACMD_EN - Auto CMD Enable - 2 - 3 - read-write - - - value1 - Auto Command Disabled - 0b00 - - - value2 - Auto CMD12 Enable - 0b01 - - - - - BLOCK_COUNT_EN - Block Count Enable - 1 - 1 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - COMMAND - Command Register - 0x000E - 16 - 0x0000 - 0xFFFF - - - CMD_IND - Command Index - 8 - 13 - read-write - - - CMD_TYPE - Command Type - 6 - 7 - read-write - - - value1 - Normal - 0b00 - - - value2 - Suspend - 0b01 - - - value3 - Resume - 0b10 - - - value4 - Abort - 0b11 - - - - - DATA_PRESENT_SELECT - Data Present Select - 5 - 5 - read-write - - - value1 - No Data Present - 0b0 - - - value2 - Data Present - 0b1 - - - - - CMD_IND_CHECK_EN - Command Index Check Enable - 4 - 4 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - CMD_CRC_CHECK_EN - Command CRC Check Enable - 3 - 3 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - RESP_TYPE_SELECT - Response Type Select - 0 - 1 - read-write - - - value1 - No Response - 0b00 - - - value2 - Response length 136 - 0b01 - - - value3 - Response length 48 - 0b10 - - - value4 - Response length 48 check Busy after response - 0b11 - - - - - - - RESPONSE0 - Response 0 Register - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE1 - Response1 - 16 - 31 - read-only - - - RESPONSE0 - Response0 - 0 - 15 - read-only - - - - - RESPONSE2 - Response 2 Register - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE3 - Response3 - 16 - 31 - read-only - - - RESPONSE2 - Response2 - 0 - 15 - read-only - - - - - RESPONSE4 - Response 4 Register - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE5 - Response5 - 16 - 31 - read-only - - - RESPONSE4 - Response4 - 0 - 15 - read-only - - - - - RESPONSE6 - Response 6 Register - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE7 - Response7 - 16 - 31 - read-only - - - RESPONSE6 - Response6 - 0 - 15 - read-only - - - - - DATA_BUFFER - Data Buffer Register - 0x0020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_BUFFER - Data Buffer - 0 - 31 - read-write - - - - - PRESENT_STATE - Present State Register - 0x0024 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT_7_4_PIN_LEVEL - Line Signal Level - 25 - 28 - read-only - - - CMD_LINE_LEVEL - CMD Line Signal Level - 24 - 24 - read-only - - - DAT_3_0_PIN_LEVEL - Line Signal Level - 20 - 23 - read-only - - - WRITE_PROTECT_PIN_LEVEL - Write Protect Switch Pin Level - 19 - 19 - read-only - - - value1 - Write protected (SDWP = 1) - 0b0 - - - value2 - Write enabled (SDWP = 0) - 0b1 - - - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level - 18 - 18 - read-only - - - value1 - No Card present (SDCD = 1) - 0b0 - - - value2 - Card present (SDCD = 0) - 0b1 - - - - - CARD_STATE_STABLE - Card State Stable - 17 - 17 - read-only - - - value1 - Reset of Debouncing - 0b0 - - - value2 - No Card or Inserted - 0b1 - - - - - CARD_INSERTED - Card Inserted - 16 - 16 - read-only - - - value1 - Reset or Debouncing or No Card - 0b0 - - - value2 - Card Inserted - 0b1 - - - - - BUFFER_READ_ENABLE - Buffer Read Enable - 11 - 11 - read-only - - - value1 - Read Disable - 0b0 - - - value2 - Read Enable. - 0b1 - - - - - BUFFER_WRITE_ENABLE - Buffer Write Enable - 10 - 10 - read-only - - - value1 - Write Disable - 0b0 - - - value2 - Write Enable. - 0b1 - - - - - READ_TRANSFER_ACTIVE - Read Transfer Active - 9 - 9 - read-only - - - value1 - No valid data - 0b0 - - - value2 - Transferring data - 0b1 - - - - - WRITE_TRANSFER_ACTIVE - Write Transfer Active - 8 - 8 - read-only - - - value1 - No valid data - 0b0 - - - value2 - Transferring data - 0b1 - - - - - DAT_LINE_ACTIVE - DAT Line Active - 2 - 2 - read-only - - - value1 - DAT line inactive - 0b0 - - - value2 - DAT line active - 0b1 - - - - - COMMAND_INHIBIT_DAT - Command Inhibit (DAT) - 1 - 1 - read-only - - - value1 - Can issue command which uses the DAT line - 0b0 - - - value2 - Cannot issue command which uses the DAT line - 0b1 - - - - - COMMAND_INHIBIT_CMD - Command Inhibit (CMD) - 0 - 0 - read-only - - - - - HOST_CTRL - Host Control Register - 0x0028 - 8 - 0x00 - 0xFF - - - CARD_DET_SIGNAL_DETECT - Card detect signal detetction - 7 - 7 - read-write - - - value1 - SDCD is selected (for normal use) - 0b0 - - - value2 - The card detect test level is selected - 0b1 - - - - - CARD_DETECT_TEST_LEVEL - Card Detect Test Level - 6 - 6 - read-write - - - value1 - No Card - 0b0 - - - value2 - Card Inserted - 0b1 - - - - - HIGH_SPEED_EN - High Speed Enable - 2 - 2 - read-write - - - value1 - Normal Speed Mode - 0b0 - - - value2 - High Speed Mode - 0b1 - - - - - DATA_TX_WIDTH - Data Transfer Width (SD1 or SD4) - 1 - 1 - read-write - - - value1 - 1 bit mode - 0b0 - - - value2 - 4-bit mode - 0b1 - - - - - LED_CTRL - LED Control - 0 - 0 - read-write - - - value1 - LED off - 0b0 - - - value2 - LED on - 0b1 - - - - - - - POWER_CTRL - Power Control Register - 0x0029 - 8 - 0x00 - 0xFF - - - HARDWARE_RESET - Hardware reset - 4 - 4 - read-write - - - SD_BUS_VOLTAGE_SEL - SD Bus Voltage Select - 1 - 3 - read-write - - - value1 - 3.3V (Flattop.) - 0b111 - - - - - SD_BUS_POWER - SD Bus Power - 0 - 0 - read-write - - - value1 - Power off - 0b0 - - - value2 - Power on - 0b1 - - - - - - - BLOCK_GAP_CTRL - Block Gap Control Register - 0x002A - 8 - 0x00 - 0xFF - - - SPI_MODE - SPI_MODE - 4 - 4 - read-write - - - value1 - SD mode - 0b0 - - - value2 - SPI mode - 0b1 - - - - - INT_AT_BLOCK_GAP - Interrupt At Block Gap - 3 - 3 - read-write - - - READ_WAIT_CTRL - Read Wait Control - 2 - 2 - read-write - - - value1 - Disable Read Wait Control - 0b0 - - - value2 - Enable Read Wait Control - 0b1 - - - - - CONTINUE_REQ - Continue Request - 1 - 1 - read-write - - - value1 - Ignored - 0b0 - - - value2 - Restart - 0b1 - - - - - STOP_AT_BLOCK_GAP - Stop At Block Gap Request - 0 - 0 - read-write - - - value1 - Transfer - 0b0 - - - value2 - Stop - 0b1 - - - - - - - WAKEUP_CTRL - Wake-up Control Register - 0x002B - 8 - 0x00 - 0xFF - - - WAKEUP_EVENT_EN_REM - Wakeup Event Enable On SD Card Removal - 2 - 2 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WAKEUP_EVENT_EN_INS - Wakeup Event Enable On SD Card Insertion - 1 - 1 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WAKEUP_EVENT_EN_INT - Wakeup Event Enable On Card Interrupt - 0 - 0 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - CLOCK_CTRL - Clock Control Register - 0x002C - 16 - 0x0000 - 0xFFFF - - - SDCLK_FREQ_SEL - SDCLK Frequency Select - 8 - 15 - read-write - - - value1 - base clock(10MHz-63MHz) - 0x00 - - - value2 - base clock divided by 2 - 0x01 - - - value3 - base clock divided by 32 - 0x10 - - - value4 - base clock divided by 4 - 0x02 - - - value5 - base clock divided by 8 - 0x04 - - - value6 - base clock divided by 16 - 0x08 - - - value7 - base clock divided by 64 - 0x20 - - - value8 - base clock divided by 128 - 0x40 - - - value9 - base clock divided by 256 - 0x80 - - - - - SDCLOCK_EN - SD Clock Enable - 2 - 2 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - INTERNAL_CLOCK_STABLE - Internal Clock Stable - 1 - 1 - read-only - - - value1 - Not Ready - 0b0 - - - value2 - Ready - 0b1 - - - - - INTERNAL_CLOCK_EN - Internal Clock Enable - 0 - 0 - read-write - - - value1 - Stop - 0b0 - - - value2 - Oscillate - 0b1 - - - - - - - TIMEOUT_CTRL - Timeout Control Register - 0x002E - 8 - 0x00 - 0xFF - - - DAT_TIMEOUT_CNT_VAL - Data Timeout Counter Value - 0 - 3 - read-write - - - value1 - TMCLK * 2^13 - 0b0000 - - - value2 - TMCLK * 2^14 - 0b0001 - - - value3 - TMCLK * 2^27 - 0b1110 - - - value4 - Reserved - 0b1111 - - - - - - - SW_RESET - Software Reset Register - 0x002F - 8 - 0x00 - 0xFF - - - SW_RST_DAT_LINE - Software Reset for DAT Line - 2 - 2 - read-write - - - value1 - Work - 0b0 - - - value2 - Reset - 0b1 - - - - - SW_RST_CMD_LINE - Software Reset for CMD Line - 1 - 1 - read-write - - - value1 - Work - 0b0 - - - value2 - Reset - 0b1 - - - - - SW_RST_ALL - Software Reset for All - 0 - 0 - read-write - - - - - INT_STATUS_NORM - Normal Interrupt Status Register - 0x0030 - 16 - 0x0000 - 0xFFFF - - - ERR_INT - Error Interrupt - 15 - 15 - read-only - - - value1 - No Error. - 0b0 - - - value2 - Error. - 0b1 - - - - - CARD_INT - Card Interrupt - 8 - 8 - read-only - - - value1 - No Card Interrupt - 0b0 - - - value2 - Generate Card Interrupt - 0b1 - - - - - CARD_REMOVAL - Card Removal - 7 - 7 - read-write - - - value1 - Card State Stable or Debouncing - 0b0 - - - value2 - Card Removed - 0b1 - - - - - CARD_INS - Card Insertion - 6 - 6 - read-write - - - value1 - Card State Stable or Debouncing - 0b0 - - - value2 - Card Inserted - 0b1 - - - - - BUFF_READ_READY - Buffer Read Ready - 5 - 5 - read-write - - - value1 - Not Ready to read Buffer. - 0b0 - - - value2 - Ready to read Buffer. - 0b1 - - - - - BUFF_WRITE_READY - Buffer Write Ready - 4 - 4 - read-write - - - value1 - Not Ready to Write Buffer. - 0b0 - - - value2 - Ready to Write Buffer. - 0b1 - - - - - BLOCK_GAP_EVENT - Block Gap Event - 2 - 2 - read-write - - - value1 - No Block Gap Event - 0b0 - - - value2 - Transaction stopped at Block Gap - 0b1 - - - - - TX_COMPLETE - Transfer Complete - 1 - 1 - read-write - - - value1 - No Data Transfer Complete - 0b0 - - - value2 - Data Transfer Complete - 0b1 - - - - - CMD_COMPLETE - Command Complete - 0 - 0 - read-write - - - value1 - No Command Complete - 0b0 - - - value2 - Command Complete - 0b1 - - - - - - - INT_STATUS_ERR - Error Interrupt Status Register - 0x0032 - 16 - 0x0000 - 0xFFFF - - - CEATA_ERR - Ceata Error Status - 13 - 13 - read-write - - - value1 - no error - 0b0 - - - value2 - error - 0b1 - - - - - ACMD_ERR - Auto CMD Error - 8 - 8 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - CURRENT_LIMIT_ERR - Current Limit Error - 7 - 7 - read-write - - - value1 - No Error - 0b0 - - - value2 - Power Fail - 0b1 - - - - - DATA_END_BIT_ERR - Data End Bit Error - 6 - 6 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - DATA_CRC_ERR - Data CRC Error - 5 - 5 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - DATA_TIMEOUT_ERR - Data Timeout Error - 4 - 4 - read-write - - - value1 - No Error - 0b0 - - - value2 - Timeout - 0b1 - - - - - CMD_IND_ERR - Command Index Error - 3 - 3 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - CMD_END_BIT_ERR - Command End Bit Error - 2 - 2 - read-write - - - value1 - No Error - 0b0 - - - value2 - End Bit Error Generated - 0b1 - - - - - CMD_CRC_ERR - Command CRC Error - 1 - 1 - read-write - - - value1 - No Error - 0b0 - - - value2 - CRC Error Generated - 0b1 - - - - - CMD_TIMEOUT_ERR - Command Timeout Error - 0 - 0 - read-write - - - value1 - No Error - 0b0 - - - value2 - Timeout - 0b1 - - - - - - - EN_INT_STATUS_NORM - Normal Interrupt Status Enable Register - 0x0034 - 16 - 0x0000 - 0xFFFF - - - FIXED_TO_0 - Fixed to 0 - 15 - 15 - read-only - - - CARD_INT_EN - Card Interrupt Status Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_REMOVAL_EN - Card Removal Status Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_INS_EN - Card Insertion Status Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_READ_READY_EN - Buffer Read Ready Status Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_WRITE_READY_EN - Buffer Write Ready Status Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BLOCK_GAP_EVENT_EN - Block Gap Event Status Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TX_COMPLETE_EN - Transfer Complete Status Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_COMPLETE_EN - Command Complete Status Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - EN_INT_STATUS_ERR - Error Interrupt Status Enable Register - 0x0036 - 16 - 0x0000 - 0xFFFF - - - CEATA_ERR_EN - Ceata Error Status Enable - 13 - 13 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TARGET_RESP_ERR_EN - Target Response Error Status Enable - 12 - 12 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - ACMD_ERR_EN - Auto CMD12 Error Status Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CURRENT_LIMIT_ERR_EN - Current Limit Error Status Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_END_BIT_ERR_EN - Data End Bit Error Status Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_CRC_ERR_EN - Data CRC Error Status Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_TIMEOUT_ERR_EN - Data Timeout Error Status Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_IND_ERR_EN - Command Index Error Status Enable - 3 - 3 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_END_BIT_ERR_EN - Command End Bit Error Status Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_CRC_ERR_EN - Command CRC Error Status Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_TIMEOUT_ERR_EN - Command Timeout Error Status Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - EN_INT_SIGNAL_NORM - Normal Interrupt Signal Enable Register - 0x0038 - 16 - 0x0000 - 0xFFFF - - - FIXED_TO_0 - Fixed to 0 - 15 - 15 - read-only - - - CARD_INT_EN - Card Interrupt Signal Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_REMOVAL_EN - Card Removal Signal Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_INS_EN - Card Insertion Signal Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_READ_READY_EN - Buffer Read Ready Signal Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_WRITE_READY_EN - Buffer Write Ready Signal Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BLOCK_GAP_EVENT_EN - Block Gap Event Signal Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TX_COMPLETE_EN - Transfer Complete Signal Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_COMPLETE_EN - Command Complete Signal Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - EN_INT_SIGNAL_ERR - Error Interrupt Signal Enable Register - 0x003A - 16 - 0x0000 - 0xFFFF - - - CEATA_ERR_EN - Ceata Error Signal Enable - 13 - 13 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TARGET_RESP_ERR_EN - Target Response Error Signal Enable - 12 - 12 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - ACMD_ERR_EN - Auto CMD12 Error Signal Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CURRENT_LIMIT_ERR_EN - Current Limit Error Signal Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_END_BIT_ERR_EN - Data End Bit Error Signal Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_CRC_ERR_EN - Data CRC Error Signal Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_TIMEOUT_ERR_EN - Data Timeout Error Signal Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_IND_ERR_EN - Command Index Error Signal Enable - 3 - 3 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_END_BIT_ERR_EN - Command End Bit Error Signal Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_CRC_ERR_EN - Command CRC Error Signal Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_TIMEOUT_ERR_EN - Command Timeout Error Signal Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - ACMD_ERR_STATUS - Auto CMD Error Status Register - 0x003C - 16 - 0x0000 - 0xFFFF - - - CMD_NOT_ISSUED_BY_ACMD12_ERR - Command Not Issued By Auto CMD12 Error - 7 - 7 - read-only - - - value1 - No Error - 0b0 - - - value2 - Not Issued - 0b1 - - - - - ACMD_IND_ERR - Auto CMD Index Error - 4 - 4 - read-only - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - ACMD_END_BIT_ERR - Auto CMD End Bit Error - 3 - 3 - read-only - - - value1 - No Error - 0b0 - - - value2 - End Bit Error Generated - 0b1 - - - - - ACMD_CRC_ERR - Auto CMD CRC Error - 2 - 2 - read-only - - - value1 - No Error - 0b0 - - - value2 - CRC Error Generated - 0b1 - - - - - ACMD_TIMEOUT_ERR - Auto CMD Timeout Error - 1 - 1 - read-only - - - value1 - No Error - 0b0 - - - value2 - Timeout - 0b1 - - - - - ACMD12_NOT_EXEC_ERR - Auto CMD12 Not Executed - 0 - 0 - read-only - - - value1 - Executed - 0b0 - - - value2 - Not Executed - 0b1 - - - - - - - FORCE_EVENT_ACMD_ERR_STATUS - Force Event Register for Auto CMD Error Status - 0x0050 - 16 - 0x0000 - 0xFFFF - - - FE_CMD_NOT_ISSUED_ACMD12_ERR - Force Event for CMD not issued by Auto CMD12 Error - 7 - 7 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_IND_ERR - Force Event for Auto CMD Index Error - 4 - 4 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_END_BIT_ERR - Force Event for Auto CMD End bit Error - 3 - 3 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_CRC_ERR - Force Event for Auto CMD CRC Error - 2 - 2 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_TIMEOUT_ERR - Force Event for Auto CMD timeout Error - 1 - 1 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_NOT_EXEC - Force Event for Auto CMD12 NOT Executed - 0 - 0 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - - - FORCE_EVENT_ERR_STATUS - Force Event Register for Error Interrupt Status - 0x0052 - 16 - 0x0000 - 0xFFFF - - - FE_CEATA_ERR - Force Event for Ceata Error - 13 - 13 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_TARGET_RESPONSE_ERR - Force event for Target Response Error - 12 - 12 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD12_ERR - Force Event for Auto CMD Error - 8 - 8 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CURRENT_LIMIT_ERR - Force Event for Current Limit Error - 7 - 7 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_DATA_END_BIT_ERR - Force Event for Data End Bit Error - 6 - 6 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_DATA_CRC_ERR - Force Event for Data CRC Error - 5 - 5 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_DATA_TIMEOUT_ERR - Force Event for Data Timeout Error - 4 - 4 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_IND_ERR - Force Event for Command Index Error - 3 - 3 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_END_BIT_ERR - Force Event for Command End Bit Error - 2 - 2 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_CRC_ERR - Force Event for Command CRC Error - 1 - 1 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_TIMEOUT_ERR - Force Event for Command Timeout Error - 0 - 0 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - - - DEBUG_SEL - Debug Selection Register - 0x0074 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_SEL - Debug_sel - 0 - 0 - write-only - - - value1 - receiver module and fifo_ctrl module signals are probed out - 0b0 - - - value2 - cmd register, Interrupt status, transmitter module and clk sdcard signals are probed out. - 0b1 - - - - - - - SPI - SPI Interrupt Support Register - 0x00F0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPI_INT_SUPPORT - SPI INT SUPPORT - 0 - 7 - read-write - - - - - SLOT_INT_STATUS - Slot Interrupt Status Register - 0x00FC - 16 - 0x0000 - 0xFFFF - - - SLOT_INT_STATUS - Interrupt Signal for Card Slot - 0 - 7 - read-only - - - value1 - Slot 1 - 0x00 - - - - - - - - - EBU - External Bus Unit - 0x58008000 - - 0x0 - 0x4000 - registers - - - - CLC - EBU Clock Control Register - 0x00 - 32 - 0x00110000 - 0xFFFFFFFF - - - DISR - EBU Disable Request Bit - 0 - 0 - read-write - - - value1 - EBU disable is not requested - 0b0 - - - value2 - EBU disable is requested - 0b1 - - - - - DISS - EBU Disable Status Bit - 1 - 1 - read-only - - - value1 - EBU is enabled (default after reset) - 0b0 - - - value2 - EBU is disabled - 0b1 - - - - - SYNC - EBU Clocking Mode - 16 - 16 - read-write - - - value1 - request EBU to run asynchronously to AHB bus clock and use separate clock source - 0b0 - - - value2 - request EBU to run synchronously to ARM processor (default after reset) - 0b1 - - - - - DIV2 - DIV2 Clocking Mode - 17 - 17 - read-write - - - value1 - standard clocking mode. clock input selected by SYNC bitfield (default after reset). - 0b0 - - - value2 - request EBU to run off AHB bus clock divided by 2. - 0b1 - - - - - EBUDIV - EBU Clock Divide Ratio - 18 - 19 - read-write - - - value1 - request EBU to run off input clock (default after reset) - 0b00 - - - value2 - request EBU to run off input clock divided by 2 - 0b01 - - - value3 - request EBU to run off input clock divided by 3 - 0b10 - - - value4 - request EBU to run off input clock divided by 4 - 0b11 - - - - - SYNCACK - EBU Clocking Mode Status - 20 - 20 - read-only - - - value1 - the EBU is asynchronous to the AHB bus clock and is using a separate clock source - 0b0 - - - value2 - EBU is synchronous to the AHB bus clock (default after reset) - 0b1 - - - - - DIV2ACK - DIV2 Clocking Mode Status - 21 - 21 - read-only - - - value1 - EBU is using standard clocking mode. clock input selected by SYNC bitfield (default after reset). - 0b0 - - - value2 - EBU is running off AHB bus clock divided by 2. - 0b1 - - - - - EBUDIVACK - EBU Clock Divide Ratio Status - 22 - 23 - read-only - - - value1 - EBU is running off input clock (default after reset) - 0b00 - - - value2 - EBU is running off input clock divided by 2 - 0b01 - - - value3 - EBU is running off input clock divided by 3 - 0b10 - - - value4 - EBU is running off input clock divided by 4 - 0b11 - - - - - - - MODCON - EBU Configuration Register - 0x04 - 32 - 0x00000020 - 0xFFFFFFFF - - - STS - Memory Status Bit - 0 - 0 - read-only - - - LCKABRT - Lock Abort - 1 - 1 - read-only - - - SDTRI - SDRAM Tristate - 2 - 2 - read-write - - - value1 - SDRAM control signals are driven by the EBU when the EBU does not own the external bus. SDRAM cannot be shared. - 0b0 - - - value2 - SDRAM control signals are tri-stated by the EBU when the EBU does not own the external bus. The SDRAM can be shared. - 0b1 - - - - - EXTLOCK - External Bus Lock Control - 4 - 4 - read-write - - - value1 - External bus is not locked after the EBU gains ownership - 0b0 - - - value2 - External bus is locked after the EBU gains ownership - 0b1 - - - - - ARBSYNC - Arbitration Signal Synchronization Control - 5 - 5 - read-write - - - value1 - Arbitration inputs are synchronous - 0b0 - - - value2 - Arbitration inputs are asynchronous - 0b1 - - - - - ARBMODE - Arbitration Mode Selection - 6 - 7 - read-write - - - value1 - No Bus arbitration mode selected - 0b00 - - - value2 - Arbiter Mode arbitration mode selected - 0b01 - - - value3 - Participant arbitration mode selected - 0b10 - - - value4 - Sole Master arbitration mode selected - 0b11 - - - - - TIMEOUTC - Bus Time-out Control - 8 - 15 - read-write - - - value1 - Time-out is disabled. - 0x00 - - - value2 - Time-out is generated after 1 8 clock cycles. - 0x01 - - - value3 - Time-out is generated after 255 8 clock cycles. - 0xFF - - - - - LOCKTIMEOUT - Lock Timeout Counter Preload - 16 - 23 - read-write - - - GLOBALCS - Global Chip Select Enable - 24 - 27 - read-write - - - ACCSINH - Access Inhibit request - 28 - 28 - read-write - - - ACCSINHACK - Access inhibit acknowledge - 29 - 29 - read-only - - - ALE - ALE Mode - 31 - 31 - read-write - - - value1 - Output is ADV - 0b0 - - - value2 - Output is ALE - 0b1 - - - - - - - ID - EBU Module Identification Register - 0x08 - 32 - 0x0014C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - USERCON - EBU Test/Control Configuration Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - DIP - Disable Internal Pipelining - 0 - 0 - read-write - - - ADDIO - Address Pins to GPIO Mode - 16 - 24 - read-write - - - value1 - Address Bit is required for addressing memory - 0b0 - - - value2 - Address Bit is available for GPIO function - 0b1 - - - - - ADVIO - ADV Pin to GPIO Mode - 25 - 25 - read-write - - - value1 - ADV pin is required for controlling memory - 0b0 - - - value2 - ADV pin is available for GPIO function - 0b1 - - - - - - - ADDRSEL0 - EBU Address Select Register 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - ADDRSEL1 - EBU Address Select Register 1 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - ADDRSEL2 - EBU Address Select Register 2 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - ADDRSEL3 - EBU Address Select Register 3 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - BUSRCON0 - EBU Bus Configuration Register - 0x28 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP0 - EBU Bus Read Access Parameter Register - 0x2C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON0 - EBU Bus Write Configuration Register - 0x30 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP0 - EBU Bus Write Access Parameter Register - 0x34 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSRCON1 - EBU Bus Configuration Register - 0x38 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP1 - EBU Bus Read Access Parameter Register - 0x3C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON1 - EBU Bus Write Configuration Register - 0x40 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP1 - EBU Bus Write Access Parameter Register - 0x44 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSRCON2 - EBU Bus Configuration Register - 0x48 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP2 - EBU Bus Read Access Parameter Register - 0x4C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON2 - EBU Bus Write Configuration Register - 0x50 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP2 - EBU Bus Write Access Parameter Register - 0x54 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSRCON3 - EBU Bus Configuration Register - 0x58 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP3 - EBU Bus Read Access Parameter Register - 0x5C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON3 - EBU Bus Write Configuration Register - 0x60 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP3 - EBU Bus Write Access Parameter Register - 0x64 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - SDRMCON - EBU SDRAM Control Register - 0x68 - 32 - 0x80000000 - 0xFFFFFFFF - - - SDCMSEL - SDRAM clock mode select - 31 - 31 - read-write - - - value1 - clock disabled between accesses - 0b1 - - - value2 - clock continuously runs - 0b0 - - - - - PWR_MODE - Power Save Mode used for gated clock mode - 29 - 30 - read-write - - - value1 - precharge before clock stop (default after reset) - 0x0 - - - value2 - auto-precharge before clock stop - 0x1 - - - value3 - active power down (stop clock without precharge) - 0x2 - - - value4 - clock stop power down - 0x3 - - - - - CLKDIS - Disable SDRAM clock output - 28 - 28 - read-write - - - value1 - clock enabled - 0b0 - - - value2 - clock disabled - 0b1 - - - - - CRCE - Row cycle time counter extension - 25 - 27 - read-write - - - BANKM - Mask for bank tag - 22 - 24 - read-write - - - value1 - Reserved; (default after reset) - 0x0 - - - value2 - Address bit 21 to 20 - 0x1 - - - value3 - Address bit 22 to 21 - 0x2 - - - value4 - Address bit 23 to 22 - 0x3 - - - value5 - Address bit 24 to 23 - 0x4 - - - value6 - Address bit 25 to 24 - 0x5 - - - value7 - Address bit 26 to 25 - 0x6 - - - value8 - Address bit 26 - 0x7 - - - - - ROWM - Mask for row tag - 19 - 21 - read-write - - - value1 - reserved; (default after reset) - 0x0 - - - value2 - Address bit 26 to 9 - 0x1 - - - value3 - Address bit 26 to 10 - 0x2 - - - value4 - Address bit 26 to 11 - 0x3 - - - value5 - Address bit 26 to 12 - 0x4 - - - value6 - Address bit 26 to 13 - 0x5 - - - value7 - reserved - 0x6 - - - value8 - reserved - 0x7 - - - - - CRC - Row cycle time counter - 16 - 18 - read-write - - - CRCD - Row to column delay counter - 14 - 15 - read-write - - - AWIDTH - Width of column address - 12 - 13 - read-write - - - value1 - do not use - 0x0 - - - value2 - Address(8:0) - 0x1 - - - value3 - Address(9:0) - 0x2 - - - value4 - Address(10:0) - 0x3 - - - - - CRP - Row precharge time counter - 10 - 11 - read-write - - - CRSC - Mode register set-up time - 8 - 9 - read-write - - - CRFSH - Initialization refresh commands counter - 4 - 7 - read-write - - - CRAS - Row to precharge delay counter - 0 - 3 - read-write - - - - - SDRMOD - EBU SDRAM Mode Register - 0x6C - 32 - 0x00000020 - 0xFFFFFFFF - - - XBA - Extended Operation Bank Select - 28 - 31 - read-write - - - XOPM - Extended Operation Mode - 16 - 27 - read-write - - - COLDSTART - SDRAM coldstart - 15 - 15 - write-only - - - OPMODE - Operation Mode - 7 - 13 - read-write - - - value1 - Only this value must be written (default after reset) - 0b000000 - - - - - CASLAT - CAS latency - 4 - 6 - read-write - - - value1 - Two clocks (default after reset) - 2 - - - value2 - Three clocks - 3 - - - - - BTYP - Burst type - 3 - 3 - read-write - - - value1 - Only this value should be written (default after reset) - 0b0 - - - value2 - Reserved - 0b1 - - - - - BURSTL - Burst length - 0 - 2 - read-write - - - value1 - 1 (default after reset) - 0 - - - value2 - 2 - 1 - - - value3 - 4 - 2 - - - value4 - 8 - 3 - - - value5 - 16 - 4 - - - - - - - SDRMREF - EBU SDRAM Refresh Control Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - RES_DLY - Delay on Power Down Exit - 25 - 27 - read-write - - - ARFSH - Auto Refresh on Self refresh Exit - 24 - 24 - read-write - - - SELFREX_DLY - Self Refresh Exit Delay - 16 - 23 - read-write - - - ERFSHC - Extended Refresh Counter Period - 14 - 15 - read-write - - - AUTOSELFR - Automatic Self Refresh - 13 - 13 - read-write - - - SELFREN - Self Refresh Entry - 12 - 12 - read-write - - - SELFRENST - Self Refresh Entry Status. - 11 - 11 - read-only - - - SELFREX - Self Refresh Exit (Power Up). - 10 - 10 - read-write - - - SELFREXST - Self Refresh Exit Status. - 9 - 9 - read-only - - - REFRESHR - Number of refresh commands - 6 - 8 - read-write - - - REFRESHC - Refresh counter period - 0 - 5 - read-write - - - - - SDRSTAT - EBU SDRAM Status Register - 0x74 - 32 - 0x00010000 - 0xFFFFFFFF - - - SDERR - SDRAM read error - 2 - 2 - read-only - - - value1 - Reads running successfully - 0b0 - - - value2 - Read error condition has been detected - 0b1 - - - - - SDRMBUSY - SDRAM Busy - 1 - 1 - read-only - - - value1 - Power-up initialization sequence is not running - 0b0 - - - value2 - Power-up initialization sequence is running - 0b1 - - - - - REFERR - SDRAM Refresh Error - 0 - 0 - read-only - - - value1 - No refresh error. - 0b0 - - - value2 - Refresh error occurred. - 0b1 - - - - - - - - - ETH0_CON - Ethernet Control Register - ETH - 0x50004040 - - 0 - 4 - registers - - - - ETH0_CON - Ethernet 0 Port Control Register - 0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXD0 - MAC Receive Input 0 - 0 - 1 - read-write - - - value1 - Data input RXD0A is selected - 0b00 - - - value2 - Data input RXD0B is selected - 0b01 - - - value3 - Data input RXD0C is selected - 0b10 - - - value4 - Data input RXD0D is selected - 0b11 - - - - - RXD1 - MAC Receive Input 1 - 2 - 3 - read-write - - - value1 - Data input RXD1A is selected - 0b00 - - - value2 - Data input RXD1B is selected - 0b01 - - - value3 - Data input RXD1C is selected - 0b10 - - - value4 - Data input RXD1D is selected - 0b11 - - - - - RXD2 - MAC Receive Input 2 - 4 - 5 - read-write - - - value1 - Data input RXD2A is selected - 0b00 - - - value2 - Data input RXD2B is selected - 0b01 - - - value3 - Data input RXD2C is selected - 0b10 - - - value4 - Data input RXD2D is selected - 0b11 - - - - - RXD3 - MAC Receive Input 3 - 6 - 7 - read-write - - - value1 - Data input RXD3A is selected - 0b00 - - - value2 - Data input RXD3B is selected - 0b01 - - - value3 - Data input RXD3C is selected - 0b10 - - - value4 - Data input RXD3D is selected - 0b11 - - - - - CLK_RMII - RMII clock input - 8 - 9 - read-write - - - value1 - Data input RMIIA is selected - 0b00 - - - value2 - Data input RMIIB is selected - 0b01 - - - value3 - Data input RMIIC is selected - 0b10 - - - value4 - Data input RMIID is selected - 0b11 - - - - - CRS_DV - CRS_DV input - 10 - 11 - read-write - - - value1 - Data input CRS_DVA is selected - 0b00 - - - value2 - Data input CRS_DVB is selected - 0b01 - - - value3 - Data input CRS_DVC is selected - 0b10 - - - value4 - Data input CRS_DVD is selected - 0b11 - - - - - CRS - CRS input - 12 - 13 - read-write - - - value1 - Data input CRSA - 0b00 - - - value2 - Data input CRSB - 0b01 - - - value3 - Data input CRSC - 0b10 - - - value4 - Data input CRSD - 0b11 - - - - - RXER - RXER Input - 14 - 15 - read-write - - - value1 - Data input RXERA is selected - 0b00 - - - value2 - Data input RXERB is selected - 0b01 - - - value3 - Data input RXERC is selected - 0b10 - - - value4 - Data input RXERD is selected - 0b11 - - - - - COL - COL input - 16 - 17 - read-write - - - value1 - Data input COLA is selected - 0b00 - - - value2 - Data input COLB is selected - 0b01 - - - value3 - Data input COLC is selected - 0b10 - - - value4 - Data input COLD is selected - 0b11 - - - - - CLK_TX - CLK_TX input - 18 - 19 - read-write - - - value1 - Data input CLK_TXA is selected - 0b00 - - - value2 - Data input CLK_TXB is selected - 0b01 - - - value3 - Data input CLK_TXC is selected - 0b10 - - - value4 - Data input CLK_TXD is selected - 0b11 - - - - - MDIO - MDIO Input Select - 22 - 23 - read-write - - - value1 - Data input MDIA is selected - 0b00 - - - value2 - Data input MDIB is selected - 0b01 - - - value3 - Data input MDIC is selected - 0b10 - - - value4 - Data input MDID is selected - 0b11 - - - - - INFSEL - Ethernet MAC Interface Selection - 26 - 26 - read-write - - - value1 - MII - 0b0 - - - value2 - RMII - 0b1 - - - - - - - - - ETH0 - Ethernet Unit 0 - ETH - ETH - 0x5000C000 - - 0x0 - 0x4000 - registers - - - - MAC_CONFIGURATION - MAC Configuration Register - 0x0000 - 32 - 0x00008000 - 0xFFFFFFFF - - - PRELEN - Preamble Length for Transmit Frames - 0 - 1 - read-write - - - RE - Receiver Enable - 2 - 2 - read-write - - - TE - Transmitter Enable - 3 - 3 - read-write - - - DC - Deferral Check - 4 - 4 - read-write - - - BL - Back-Off Limit - 5 - 6 - read-write - - - ACS - Automatic Pad or CRC Stripping - 7 - 7 - read-write - - - Reserved_8 - Reserved - 8 - 8 - read-only - - - DR - Disable Retry - 9 - 9 - read-write - - - IPC - Checksum Offload - 10 - 10 - read-write - - - DM - Duplex Mode - 11 - 11 - read-write - - - LM - Loopback Mode - 12 - 12 - read-write - - - DO - Disable Receive Own - 13 - 13 - read-write - - - FES - Speed - 14 - 14 - read-write - - - Reserved - Reserved - 15 - 15 - read-only - - - DCRS - Disable Carrier Sense During Transmission - 16 - 16 - read-write - - - IFG - Inter-Frame Gap - 17 - 19 - read-write - - - JE - Jumbo Frame Enable - 20 - 20 - read-write - - - BE - Frame Burst Enable - 21 - 21 - read-only - - - JD - Jabber Disable - 22 - 22 - read-write - - - WD - Watchdog Disable - 23 - 23 - read-write - - - TC - Transmit Configuration in RMII - 24 - 24 - read-only - - - CST - CRC Stripping of Type Frames - 25 - 25 - read-write - - - Reserved_26 - Reserved - 26 - 26 - read-only - - - TWOKPE - IEEE 802.3as support for 2K packets Enable - 27 - 27 - read-write - - - SARC - Source Address Insertion or Replacement Control - 28 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - MAC_FRAME_FILTER - MAC Frame Filter - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - PR - Promiscuous Mode - 0 - 0 - read-write - - - HUC - Hash Unicast - 1 - 1 - read-write - - - HMC - Hash Multicast - 2 - 2 - read-write - - - DAIF - DA Inverse Filtering - 3 - 3 - read-write - - - PM - Pass All Multicast - 4 - 4 - read-write - - - DBF - Disable Broadcast Frames - 5 - 5 - read-write - - - PCF - Pass Control Frames - 6 - 7 - read-write - - - SAIF - SA Inverse Filtering - 8 - 8 - read-write - - - SAF - Source Address Filter Enable - 9 - 9 - read-write - - - HPF - Hash or Perfect Filter - 10 - 10 - read-write - - - Reserved_15_11 - Reserved - 11 - 15 - read-only - - - VTFE - VLAN Tag Filter Enable - 16 - 16 - read-write - - - Reserved_19_17 - Reserved - 17 - 19 - read-only - - - IPFE - Layer 3 and Layer 4 Filter Enable - 20 - 20 - read-only - - - DNTU - Drop non-TCP/UDP over IP Frames - 21 - 21 - read-only - - - Reserved_30_22 - Reserved - 22 - 30 - read-only - - - RA - Receive All - 31 - 31 - read-write - - - - - HASH_TABLE_HIGH - Hash Table High Register - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - 0 - 31 - read-write - - - - - HASH_TABLE_LOW - Hash Table Low Register - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - 0 - 31 - read-write - - - - - GMII_ADDRESS - MII Address Register - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - MB - MII Busy - 0 - 0 - read-write - - - MW - MII Write - 1 - 1 - read-write - - - CR - CSR Clock Range - 2 - 5 - read-write - - - MR - MII Register - 6 - 10 - read-write - - - PA - Physical Layer Address - 11 - 15 - read-write - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - GMII_DATA - MII Data Register - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - MD - MII Data - 0 - 15 - read-write - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - FLOW_CONTROL - Flow Control Register - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - FCA_BPA - Flow Control Busy or Backpressure Activate - 0 - 0 - read-write - - - TFE - Transmit Flow Control Enable - 1 - 1 - read-write - - - RFE - Receive Flow Control Enable - 2 - 2 - read-write - - - UP - Unicast Pause Frame Detect - 3 - 3 - read-write - - - PLT - Pause Low Threshold - 4 - 5 - read-write - - - Reserved_6 - Reserved - 6 - 6 - read-only - - - DZPQ - Disable Zero-Quanta Pause - 7 - 7 - read-write - - - Reserved_15_8 - Reserved - 8 - 15 - read-only - - - PT - Pause Time - 16 - 31 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - VL - VLAN Tag Identifier for Receive Frames - 0 - 15 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - 16 - 16 - read-write - - - VTIM - VLAN Tag Inverse Match Enable - 17 - 17 - read-write - - - ESVL - Enable S-VLAN - 18 - 18 - read-write - - - VTHM - VLAN Tag Hash Table Match Enable - 19 - 19 - read-only - - - Reserved_31_20 - Reserved - 20 - 31 - read-only - - - - - VERSION - Version Register - 0x0020 - 32 - 0x00001037 - 0xFFFFFFFF - - - SNPSVER - Synopsys-defined Version (3.7) - 0 - 7 - read-only - - - USERVER - User-defined Version (Configured with the coreConsultant) - 8 - 15 - read-only - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - DEBUG - Debug Register - 0x0024 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPESTS - MAC MII Receive Protocol Engine Status - 0 - 0 - read-only - - - RFCFCSTS - MAC Receive Frame Controller FIFO Status - 1 - 2 - read-only - - - Reserved_3 - Reserved - 3 - 3 - read-only - - - RWCSTS - MTL Rx FIFO Write Controller Active Status - 4 - 4 - read-only - - - RRCSTS - MTL Rx FIFO Read Controller State - 5 - 6 - read-only - - - Reserved_7 - Reserved - 7 - 7 - read-only - - - RXFSTS - MTL Rx FIFO Fill-level Status - 8 - 9 - read-only - - - Reserved_15_10 - Reserved - 10 - 15 - read-only - - - TPESTS - MAC MII Transmit Protocol Engine Status - 16 - 16 - read-only - - - TFCSTS - MAC Transmit Frame Controller Status - 17 - 18 - read-only - - - TXPAUSED - MAC transmitter in PAUSE - 19 - 19 - read-only - - - TRCSTS - MTL Tx FIFO Read Controller Status - 20 - 21 - read-only - - - TWCSTS - MTL Tx FIFO Write Controller Active Status - 22 - 22 - read-only - - - Reserved_23 - Reserved - 23 - 23 - read-only - - - TXFSTS - MTL Tx FIFO Not Empty Status - 24 - 24 - read-only - - - TXSTSFSTS - MTL TxStatus FIFO Full Status - 25 - 25 - read-only - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - REMOTE_WAKE_UP_FRAME_FILTER - Remote Wake Up Frame Filter Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFTR - Remote Wake-Up Frame Filter - 0 - 31 - read-write - - - - - PMT_CONTROL_STATUS - PMT Control and Status Register - 0x002C - 32 - 0x00000000 - 0xFFFFFFFF - - - PWRDWN - Power Down - 0 - 0 - read-write - - - MGKPKTEN - Magic Packet Enable - 1 - 1 - read-write - - - RWKPKTEN - Wake-Up Frame Enable - 2 - 2 - read-write - - - Reserved_4_3 - Reserved - 3 - 4 - read-only - - - MGKPRCVD - Magic Packet Received - 5 - 5 - read-only - - - RWKPRCVD - Wake-Up Frame Received - 6 - 6 - read-only - - - Reserved_8_7 - Reserved - 7 - 8 - read-only - - - GLBLUCAST - Global Unicast - 9 - 9 - read-write - - - Reserved_30_10 - Reserved - 10 - 30 - read-only - - - RWKFILTRST - Wake-Up Frame Filter Register Pointer Reset - 31 - 31 - read-write - - - - - INTERRUPT_STATUS - Interrupt Register - 0x0038 - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_2_0 - Reserved - 0 - 2 - read-only - - - PMTIS - PMT Interrupt Status - 3 - 3 - read-only - - - MMCIS - MMC Interrupt Status - 4 - 4 - read-only - - - MMCRXIS - MMC Receive Interrupt Status - 5 - 5 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status - 6 - 6 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status - 7 - 7 - read-only - - - Reserved_8 - Reserved - 8 - 8 - read-only - - - TSIS - Timestamp Interrupt Status - 9 - 9 - read-only - - - Reserved_10 - Reserved - 10 - 10 - read-only - - - Reserved_31_11 - Reserved - 11 - 31 - read-only - - - - - INTERRUPT_MASK - Interrupt Mask Register - 0x003C - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_2_0 - Reserved - 0 - 2 - read-only - - - PMTIM - PMT Interrupt Mask - 3 - 3 - read-write - - - Reserved_8_4 - Reserved - 4 - 8 - read-only - - - TSIM - Timestamp Interrupt Mask - 9 - 9 - read-write - - - Reserved_31_10 - Reserved - 10 - 31 - read-only - - - - - MAC_ADDRESS0_HIGH - MAC Address0 High Register - 0x0040 - 32 - 0x8000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address0 [47:32] - 0 - 15 - read-write - - - Reserved_30_16 - Reserved - 16 - 30 - read-only - - - AE - Address Enable - 31 - 31 - read-only - - - - - MAC_ADDRESS0_LOW - MAC Address0 Low Register - 0x0044 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - 0 - 31 - read-write - - - - - MAC_ADDRESS1_HIGH - MAC Address1 High Register - 0x0048 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address1 [47:32] - 0 - 15 - read-write - - - Reserved_23_16 - Reserved - 16 - 23 - read-only - - - MBC - Mask Byte Control - 24 - 29 - read-write - - - SA - Source Address - 30 - 30 - read-write - - - AE - Address Enable - 31 - 31 - read-write - - - - - MAC_ADDRESS1_LOW - MAC Address1 Low Register - 0x004C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] - 0 - 31 - read-write - - - - - MAC_ADDRESS2_HIGH - MAC Address2 High Register - 0x0050 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address2 [47:32] - 0 - 15 - read-write - - - Reserved_23_16 - Reserved - 16 - 23 - read-only - - - MBC - Mask Byte Control - 24 - 29 - read-write - - - SA - Source Address - 30 - 30 - read-write - - - AE - Address Enable - 31 - 31 - read-write - - - - - MAC_ADDRESS2_LOW - MAC Address2 Low Register - 0x0054 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address2 [31:0] - 0 - 31 - read-write - - - - - MAC_ADDRESS3_HIGH - MAC Address3 High Register - 0x0058 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address3 [47:32] - 0 - 15 - read-write - - - Reserved_23_16 - Reserved - 16 - 23 - read-only - - - MBC - Mask Byte Control - 24 - 29 - read-write - - - SA - Source Address - 30 - 30 - read-write - - - AE - Address Enable - 31 - 31 - read-write - - - - - MAC_ADDRESS3_LOW - MAC Address3 Low Register - 0x005C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address3 [31:0] - 0 - 31 - read-write - - - - - MMC_CONTROL - MMC Control Register - 0x0100 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTRST - Counters Reset - 0 - 0 - read-write - - - CNTSTOPRO - Counters Stop Rollover - 1 - 1 - read-write - - - RSTONRD - Reset on Read - 2 - 2 - read-write - - - CNTFREEZ - MMC Counter Freeze - 3 - 3 - read-write - - - CNTPRST - Counters Preset - 4 - 4 - read-write - - - CNTPRSTLVL - Full-Half Preset - 5 - 5 - read-write - - - Reserved_7_6 - Reserved - 6 - 7 - read-only - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames - 8 - 8 - read-write - - - Reserved_31_9 - Reserved - 9 - 31 - read-only - - - - - MMC_RECEIVE_INTERRUPT - MMC Receive Interrupt Register - 0x0104 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status - 0 - 0 - read-only - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status - 1 - 1 - read-only - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status. - 2 - 2 - read-only - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status. - 3 - 3 - read-only - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status - 4 - 4 - read-only - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status - 5 - 5 - read-only - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status - 6 - 6 - read-only - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status - 7 - 7 - read-only - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status - 8 - 8 - read-only - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status - 9 - 9 - read-only - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status - 10 - 10 - read-only - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - 11 - 11 - read-only - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - 12 - 12 - read-only - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - 13 - 13 - read-only - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - 14 - 14 - read-only - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - 15 - 15 - read-only - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - 16 - 16 - read-only - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status - 17 - 17 - read-only - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status - 18 - 18 - read-only - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status - 19 - 19 - read-only - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status - 20 - 20 - read-only - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status - 21 - 21 - read-only - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status - 22 - 22 - read-only - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status - 23 - 23 - read-only - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status - 24 - 24 - read-only - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status - 25 - 25 - read-only - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - MMC_TRANSMIT_INTERRUPT - MMC Transmit Interrupt Register - 0x0108 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status - 0 - 0 - read-only - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status - 1 - 1 - read-only - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status - 2 - 2 - read-only - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status - 3 - 3 - read-only - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. - 4 - 4 - read-only - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - 5 - 5 - read-only - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - 6 - 6 - read-only - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - 7 - 7 - read-only - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - 8 - 8 - read-only - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - 9 - 9 - read-only - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - 10 - 10 - read-only - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - 11 - 11 - read-only - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - 12 - 12 - read-only - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status - 13 - 13 - read-only - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status - 14 - 14 - read-only - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - 15 - 15 - read-only - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status - 16 - 16 - read-only - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status - 17 - 17 - read-only - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status - 18 - 18 - read-only - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status - 19 - 19 - read-only - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status - 20 - 20 - read-only - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status - 21 - 21 - read-only - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status - 22 - 22 - read-only - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status - 23 - 23 - read-only - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status - 24 - 24 - read-only - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status - 25 - 25 - read-only - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - MMC_RECEIVE_INTERRUPT_MASK - MMC Reveive Interrupt Mask Register - 0x010C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXGBFRMIM - MMC Receive Good Bad Frame Counter Interrupt Mask - 0 - 0 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask - 1 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask - 2 - 2 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask - 3 - 3 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask - 4 - 4 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask - 5 - 5 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask - 6 - 6 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask - 7 - 7 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask - 8 - 8 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask - 9 - 9 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask - 10 - 10 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - 11 - 11 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - 12 - 12 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - 13 - 13 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - 14 - 14 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - 15 - 15 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - 16 - 16 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask - 17 - 17 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask - 18 - 18 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask - 19 - 19 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask - 20 - 20 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask - 21 - 21 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - 22 - 22 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask - 23 - 23 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask - 24 - 24 - read-write - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask - 25 - 25 - read-write - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - MMC_TRANSMIT_INTERRUPT_MASK - MMC Transmit Interrupt Mask Register - 0x0110 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask - 0 - 0 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask - 1 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask - 2 - 2 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask - 3 - 3 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - 4 - 4 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - 5 - 5 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - 6 - 6 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - 7 - 7 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - 8 - 8 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - 9 - 9 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - 10 - 10 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - 11 - 11 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - 12 - 12 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask - 13 - 13 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask - 14 - 14 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - 15 - 15 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask - 16 - 16 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask - 17 - 17 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask - 18 - 18 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask - 19 - 19 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask - 20 - 20 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask - 21 - 21 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - 22 - 22 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask - 23 - 23 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask - 24 - 24 - read-write - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask - 25 - 25 - read-write - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - TX_OCTET_COUNT_GOOD_BAD - Transmit Octet Count for Good and Bad Frames Register - 0x0114 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXOCTGB - This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes. - 0 - 31 - read-only - - - - - TX_FRAME_COUNT_GOOD_BAD - Transmit Frame Count for Goodand Bad Frames Register - 0x0118 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFRMGB - This field indicates the number of good and bad frames transmitted, exclusive of retried frames - 0 - 31 - read-only - - - - - TX_BROADCAST_FRAMES_GOOD - Transmit Frame Count for Good Broadcast Frames - 0x011C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBCASTG - This field indicates the number of transmitted good broadcast frames. - 0 - 31 - read-only - - - - - TX_MULTICAST_FRAMES_GOOD - Transmit Frame Count for Good Multicast Frames - 0x0120 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXMCASTG - This field indicates the number of transmitted good multicast frames. - 0 - 31 - read-only - - - - - TX_64OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 64 Byte Frames - 0x0124 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX64OCTGB - This field indicates the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_65TO127OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames - 0x0128 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX65_127OCTGB - This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_128TO255OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames - 0x012C - 32 - 0x00000000 - 0xFFFFFFFF - - - TX128_255OCTGB - This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_256TO511OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames - 0x0130 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX256_511OCTGB - This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_512TO1023OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames - 0x0134 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX512_1023OCTGB - This field indicates the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames - 0x0138 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX1024_MAXOCTGB - This field indicates the number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_UNICAST_FRAMES_GOOD_BAD - Transmit Frame Count for Good and Bad Unicast Frames - 0x013C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXUCASTGB - This field indicates the number of transmitted good and bad unicast frames. - 0 - 31 - read-only - - - - - TX_MULTICAST_FRAMES_GOOD_BAD - Transmit Frame Count for Good and Bad Multicast Frames - 0x0140 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXMCASTGB - This field indicates the number of transmitted good and bad multicast frames. - 0 - 31 - read-only - - - - - TX_BROADCAST_FRAMES_GOOD_BAD - Transmit Frame Count for Good and Bad Broadcast Frames - 0x0144 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBCASTGB - This field indicates the number of transmitted good and bad broadcast frames. - 0 - 31 - read-only - - - - - TX_UNDERFLOW_ERROR_FRAMES - Transmit Frame Count for Underflow Error Frames - 0x0148 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXUNDRFLW - This field indicates the number of frames aborted because of frame underflow error. - 0 - 31 - read-only - - - - - TX_SINGLE_COLLISION_GOOD_FRAMES - Transmit Frame Count for Frames Transmitted after Single Collision - 0x014C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXSNGLCOLG - This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode. - 0 - 31 - read-only - - - - - TX_MULTIPLE_COLLISION_GOOD_FRAMES - Transmit Frame Count for Frames Transmitted after Multiple Collision - 0x0150 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXMULTCOLG - This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode. - 0 - 31 - read-only - - - - - TX_DEFERRED_FRAMES - Tx Deferred Frames Register - 0x0154 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXDEFRD - This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode. - 0 - 31 - read-only - - - - - TX_LATE_COLLISION_FRAMES - Transmit Frame Count for Late Collision Error Frames - 0x0158 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXLATECOL - This field indicates the number of frames aborted because of late collision error. - 0 - 31 - read-only - - - - - TX_EXCESSIVE_COLLISION_FRAMES - Transmit Frame Count for Excessive Collision Error Frames - 0x015C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXEXSCOL - This field indicates the number of frames aborted because of excessive (16) collision error. - 0 - 31 - read-only - - - - - TX_CARRIER_ERROR_FRAMES - Transmit Frame Count for Carrier Sense Error Frames - 0x0160 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXCARR - This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier). - 0 - 31 - read-only - - - - - TX_OCTET_COUNT_GOOD - Tx Octet Count Good Register - 0x0164 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXOCTG - This field indicates the number of bytes transmitted, exclusive of preamble, in good frames. - 0 - 31 - read-only - - - - - TX_FRAME_COUNT_GOOD - Tx Frame Count Good Register - 0x0168 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFRMG - This field indicates the number of transmitted good frames, exclusive of preamble. - 0 - 31 - read-only - - - - - TX_EXCESSIVE_DEFERRAL_ERROR - Transmit Frame Count for Excessive Deferral Error Frames - 0x016C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXEXSDEF - This field indicates the number of frames aborted because of excessive deferral error, that is, frames deferred for more than two max-sized frame times. - 0 - 31 - read-only - - - - - TX_PAUSE_FRAMES - Transmit Frame Count for Good PAUSE Frames - 0x0170 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXPAUSE - This field indicates the number of transmitted good PAUSE frames. - 0 - 31 - read-only - - - - - TX_VLAN_FRAMES_GOOD - Transmit Frame Count for Good VLAN Frames - 0x0174 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXVLANG - This register maintains the number of transmitted good VLAN frames, exclusive of retried frames. - 0 - 31 - read-only - - - - - TX_OSIZE_FRAMES_GOOD - Transmit Frame Count for Good Oversize Frames - 0x0178 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXOSIZG - This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled by setting MAC Configuration.2KPE). - 0 - 31 - read-only - - - - - RX_FRAMES_COUNT_GOOD_BAD - Receive Frame Count for Good and Bad Frames - 0x0180 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFRMGB - This field indicates the number of received good and bad frames. - 0 - 31 - read-only - - - - - RX_OCTET_COUNT_GOOD_BAD - Receive Octet Count for Good and Bad Frames - 0x0184 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOCTGB - This field indicates the number of bytes received, exclusive of preamble, in good and bad frames. - 0 - 31 - read-only - - - - - RX_OCTET_COUNT_GOOD - Rx Octet Count Good Register - 0x0188 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOCTG - This field indicates the number of bytes received, exclusive of preamble, only in good frames. - 0 - 31 - read-only - - - - - RX_BROADCAST_FRAMES_GOOD - Receive Frame Count for Good Broadcast Frames - 0x018C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXBCASTG - This field indicates the number of received good broadcast frames. - 0 - 31 - read-only - - - - - RX_MULTICAST_FRAMES_GOOD - Receive Frame Count for Good Multicast Frames - 0x0190 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXMCASTG - This field indicates the number of received good multicast frames. - 0 - 31 - read-only - - - - - RX_CRC_ERROR_FRAMES - Receive Frame Count for CRC Error Frames - 0x0194 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXCRCERR - This field indicates the number of frames received with CRC error. - 0 - 31 - read-only - - - - - RX_ALIGNMENT_ERROR_FRAMES - Receive Frame Count for Alignment Error Frames - 0x0198 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXALGNERR - This field indicates the number of frames received with alignment (dribble) error. - 0 - 31 - read-only - - - - - RX_RUNT_ERROR_FRAMES - Receive Frame Count for Runt Error Frames - 0x019C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXRUNTERR - This field indicates the number of frames received with runt error(<64 bytes and CRC error). - 0 - 31 - read-only - - - - - RX_JABBER_ERROR_FRAMES - Receive Frame Count for Jabber Error Frames - 0x01A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXJABERR - This field indicates the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - 0 - 31 - read-only - - - - - RX_UNDERSIZE_FRAMES_GOOD - Receive Frame Count for Undersize Frames - 0x01A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUNDERSZG - This field indicates the number of frames received with length less than 64 bytes and without errors. - 0 - 31 - read-only - - - - - RX_OVERSIZE_FRAMES_GOOD - Rx Oversize Frames Good Register - 0x01A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOVERSZG - This field indicates the number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled by setting MAC Configuration.2KPE). - 0 - 31 - read-only - - - - - RX_64OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 64 Byte Frames - 0x01AC - 32 - 0x00000000 - 0xFFFFFFFF - - - RX64OCTGB - This field indicates the number of received good and bad frames with length 64 bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_65TO127OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 65 to 127 Bytes Frames - 0x01B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX65_127OCTGB - This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_128TO255OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 128 to 255 Bytes Frames - 0x01B4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX128_255OCTGB - This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_256TO511OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 256 to 511 Bytes Frames - 0x01B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX256_511OCTGB - This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_512TO1023OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames - 0x01BC - 32 - 0x00000000 - 0xFFFFFFFF - - - RX512_1023OCTGB - This field indicates the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX1024_MAXOCTGB - This field indicates the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - RX_UNICAST_FRAMES_GOOD - Receive Frame Count for Good Unicast Frames - 0x01C4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUCASTG - This field indicates the number of received good unicast frames. - 0 - 31 - read-only - - - - - RX_LENGTH_ERROR_FRAMES - Receive Frame Count for Length Error Frames - 0x01C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXLENERR - This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field. - 0 - 31 - read-only - - - - - RX_OUT_OF_RANGE_TYPE_FRAMES - Receive Frame Count for Out of Range Frames - 0x01CC - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOUTOFRNG - This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - 0 - 31 - read-only - - - - - RX_PAUSE_FRAMES - Receive Frame Count for PAUSE Frames - 0x01D0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXPAUSEFRM - This field indicates the number of received good and valid PAUSE frames. - 0 - 31 - read-only - - - - - RX_FIFO_OVERFLOW_FRAMES - Receive Frame Count for FIFO Overflow Frames - 0x01D4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFOOVFL - This field indicates the number of received frames missed because of FIFO overflow. - 0 - 31 - read-only - - - - - RX_VLAN_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad VLAN Frames - 0x01D8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXVLANFRGB - This field indicates the number of received good and bad VLAN frames. - 0 - 31 - read-only - - - - - RX_WATCHDOG_ERROR_FRAMES - Receive Frame Count for Watchdog Error Frames - 0x01DC - 32 - 0x00000000 - 0xFFFFFFFF - - - RXWDGERR - This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). - 0 - 31 - read-only - - - - - RX_RECEIVE_ERROR_FRAMES - Receive Frame Count for Receive Error Frames - 0x01E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXRCVERR - This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). - 0 - 31 - read-only - - - - - RX_CONTROL_FRAMES_GOOD - Receive Frame Count for Good Control Frames Frames - 0x01E4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXCTRLG - This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). - 0 - 31 - read-only - - - - - MMC_IPC_RECEIVE_INTERRUPT_MASK - MMC Receive Checksum Offload Interrupt Mask Register - 0x0200 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask - 0 - 0 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - 1 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - 2 - 2 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - 3 - 3 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - 4 - 4 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask - 5 - 5 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - 6 - 6 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - 7 - 7 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask - 8 - 8 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask - 9 - 9 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask - 10 - 10 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask - 11 - 11 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask - 12 - 12 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask - 13 - 13 - read-write - - - Reserved_15_14 - Reserved - 14 - 15 - read-only - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask - 16 - 16 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - 17 - 17 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - 18 - 18 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - 19 - 19 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - 20 - 20 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask - 21 - 21 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - 22 - 22 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - 23 - 23 - read-write - - - RXUDPGOIM - MMC Receive UDP Good Octet Counter Interrupt Mask - 24 - 24 - read-write - - - RXUDPEROIM - MMC Receive UDP Error Octet Counter Interrupt Mask - 25 - 25 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask - 26 - 26 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask - 27 - 27 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask - 28 - 28 - read-write - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask - 29 - 29 - read-write - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - MMC_IPC_RECEIVE_INTERRUPT - MMC Receive Checksum Offload Interrupt Register - 0x0208 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status - 0 - 0 - read-only - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status - 1 - 1 - read-only - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status - 2 - 2 - read-only - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - 3 - 3 - read-only - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - 4 - 4 - read-only - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status - 5 - 5 - read-only - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status - 6 - 6 - read-only - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status - 7 - 7 - read-only - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status - 8 - 8 - read-only - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status - 9 - 9 - read-only - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status - 10 - 10 - read-only - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status - 11 - 11 - read-only - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status - 12 - 12 - read-only - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status - 13 - 13 - read-only - - - Reserved_15_14 - Reserved - 14 - 15 - read-only - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status - 16 - 16 - read-only - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status - 17 - 17 - read-only - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status - 18 - 18 - read-only - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - 19 - 19 - read-only - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - 20 - 20 - read-only - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status - 21 - 21 - read-only - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status - 22 - 22 - read-only - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status - 23 - 23 - read-only - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status - 24 - 24 - read-only - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status - 25 - 25 - read-only - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status - 26 - 26 - read-only - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status - 27 - 27 - read-only - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status - 28 - 28 - read-only - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status - 29 - 29 - read-only - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - RXIPV4_GOOD_FRAMES - RxIPv4 Good Frames Register - 0x0210 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GDFRM - This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. - 0 - 31 - read-only - - - - - RXIPV4_HEADER_ERROR_FRAMES - Receive IPV4 Header Error Frame Counter Register - 0x0214 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4HDRERRFRM - This field indicates the number of IPv4 datagrams received with header errors (checksum, length, or version mismatch). - 0 - 31 - read-only - - - - - RXIPV4_NO_PAYLOAD_FRAMES - Receive IPV4 No Payload Frame Counter Register - 0x0218 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4NOPAYFRM - This field indicates the number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine. - 0 - 31 - read-only - - - - - RXIPV4_FRAGMENTED_FRAMES - Receive IPV4 Fragmented Frame Counter Register - 0x021C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4FRAGFRM - This field indicates the number of good IPv4 datagrams received with fragmentation. - 0 - 31 - read-only - - - - - RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES - Receive IPV4 UDP Checksum Disabled Frame Counter Register - 0x0220 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4UDSBLFRM - This field indicates the number of received good IPv4 datagrams which have the UDP payload with checksum disabled. - 0 - 31 - read-only - - - - - RXIPV6_GOOD_FRAMES - RxIPv6 Good Frames Register - 0x0224 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6GDFRM - This field indicates the number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads. - 0 - 31 - read-only - - - - - RXIPV6_HEADER_ERROR_FRAMES - Receive IPV6 Header Error Frame Counter Register - 0x0228 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6HDRERRFRM - This field indicates the number of IPv6 datagrams received with header errors (length or version mismatch). - 0 - 31 - read-only - - - - - RXIPV6_NO_PAYLOAD_FRAMES - Receive IPV6 No Payload Frame Counter Register - 0x022C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6NOPAYFRM - This field indicates the number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers. - 0 - 31 - read-only - - - - - RXUDP_GOOD_FRAMES - RxUDP Good Frames Register - 0x0230 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPGDFRM - This field indicates the number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented. - 0 - 31 - read-only - - - - - RXUDP_ERROR_FRAMES - RxUDP Error Frames Register - 0x0234 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPERRFRM - This field indicates the number of good IP datagrams whose UDP payload has a checksum error. - 0 - 31 - read-only - - - - - RXTCP_GOOD_FRAMES - RxTCP Good Frames Register - 0x0238 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPGDFRM - This field indicates the number of good IP datagrams with a good TCP payload. - 0 - 31 - read-only - - - - - RXTCP_ERROR_FRAMES - RxTCP Error Frames Register - 0x023C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPERRFRM - This field indicates the number of good IP datagrams whose TCP payload has a checksum error. - 0 - 31 - read-only - - - - - RXICMP_GOOD_FRAMES - RxICMP Good Frames Register - 0x0240 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPGDFRM - This field indicates the number of good IP datagrams with a good ICMP payload. - 0 - 31 - read-only - - - - - RXICMP_ERROR_FRAMES - RxICMP Error Frames Register - 0x0244 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPERRFRM - This field indicates the number of good IP datagrams whose ICMP payload has a checksum error. - 0 - 31 - read-only - - - - - RXIPV4_GOOD_OCTETS - RxIPv4 Good Octets Register - 0x0250 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GDOCT - This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. The Ethernet header, FCS, pad, or IP pad - 0 - 31 - read-only - - - - - RXIPV4_HEADER_ERROR_OCTETS - Receive IPV4 Header Error Octet Counter Register - 0x0254 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4HDRERROCT - This field indicates the number of bytes received in the IPv4 datagrams with header errors (checksum, length, or version mismatch). The value in the Length field of IPv4 header is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV4_NO_PAYLOAD_OCTETS - Receive IPV4 No Payload Octet Counter Register - 0x0258 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4NOPAYOCT - This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV4_FRAGMENTED_OCTETS - Receive IPV4 Fragmented Octet Counter Register - 0x025C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4FRAGOCT - This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Receive IPV4 Fragmented Octet Counter Register - 0x0260 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4UDSBLOCT - This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXIPV6_GOOD_OCTETS - RxIPv6 Good Octets Register - 0x0264 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6GDOCT - Thsi field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data. - 0 - 31 - read-only - - - - - RXIPV6_HEADER_ERROR_OCTETS - Receive IPV6 Header Error Octet Counter Register - 0x0268 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6HDRERROCT - This field indicates the number of bytes received in IPv6 datagrams with header errors (length or version mismatch). The value in the IPv6 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV6_NO_PAYLOAD_OCTETS - Receive IPV6 No Payload Octet Counter Register - 0x026C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6NOPAYOCT - This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXUDP_GOOD_OCTETS - Receive UDP Good Octets Register - 0x0270 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPGDOCT - This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXUDP_ERROR_OCTETS - Receive UDP Error Octets Register - 0x0274 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPERROCT - This field indicates the number of bytes received in a UDP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXTCP_GOOD_OCTETS - Receive TCP Good Octets Register - 0x0278 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPGDOCT - This field indicates the number of bytes received in a good TCP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXTCP_ERROR_OCTETS - Receive TCP Error Octets Register - 0x027C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPERROCT - Thsi field indicates the number of bytes received in a TCP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXICMP_GOOD_OCTETS - Receive ICMP Good Octets Register - 0x0280 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPGDOCT - This field indicates the number of bytes received in a good ICMP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXICMP_ERROR_OCTETS - Receive ICMP Error Octets Register - 0x0284 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPERROCT - Number of bytes received in an ICMP segment with checksum errors - 0 - 31 - read-only - - - - - TIMESTAMP_CONTROL - Timestamp Control Register - 0x0700 - 32 - 0x00002000 - 0xFFFFFFFF - - - TSENA - Timestamp Enable - 0 - 0 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update - 1 - 1 - read-write - - - TSINIT - Timestamp Initialize - 2 - 2 - read-write - - - TSUPDT - Timestamp Update - 3 - 3 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable - 4 - 4 - read-write - - - TSADDREG - Addend Reg Update - 5 - 5 - read-write - - - Reserved_7_6 - Reserved - 6 - 7 - read-only - - - TSENALL - Enable Timestamp for All Frames - 8 - 8 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control - 9 - 9 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format - 10 - 10 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames - 11 - 11 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent Over IPv6-UDP - 12 - 12 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - 13 - 13 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages - 14 - 14 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master - 15 - 15 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - 16 - 17 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering - 18 - 18 - read-write - - - Reserved_23_19 - Reserved - 19 - 31 - read-only - - - - - SUB_SECOND_INCREMENT - Sub-Second Increment Register - 0x0704 - 32 - 0x00000000 - 0xFFFFFFFF - - - SSINC - Sub-second Increment Value - 0 - 7 - read-write - - - Reserved_31_8 - Reserved - 8 - 31 - read-only - - - - - SYSTEM_TIME_SECONDS - System Time - Seconds Register - 0x0708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - 0 - 31 - read-only - - - - - SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds Register - 0x070C - 32 - 0x00000000 - 0xFFFFFFFF - - - TSSS - Timestamp Sub Seconds - 0 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - SYSTEM_TIME_SECONDS_UPDATE - System Time - Seconds Update Register - 0x0710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - 0 - 31 - read-write - - - - - SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update Register - 0x0714 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSSS - Timestamp Sub Second - 0 - 30 - read-write - - - ADDSUB - Add or subtract time - 31 - 31 - read-write - - - - - TIMESTAMP_ADDEND - Timestamp Addend Register - 0x0718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register - 0 - 31 - read-write - - - - - TARGET_TIME_SECONDS - Target Time Seconds Register - 0x071C - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - 0 - 31 - read-write - - - - - TARGET_TIME_NANOSECONDS - Target Time Nanoseconds Register - 0x0720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTSLO - Target Timestamp Low Register - 0 - 30 - read-write - - - TRGTBUSY - Target Time Register Busy - 31 - 31 - read-only - - - - - SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds Register - 0x0724 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSHWR - Timestamp Higher Word Register - 0 - 15 - read-write - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - TIMESTAMP_STATUS - Timestamp Status Register - 0x0728 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSSOVF - Timestamp Seconds Overflow - 0 - 0 - read-only - - - TSTARGT - Timestamp Target Time Reached - 1 - 1 - read-only - - - Reserved_2 - Reserved - 2 - 2 - read-only - - - TSTRGTERR - Timestamp Target Time Error - 3 - 3 - read-only - - - TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 - 4 - 4 - read-only - - - TSTRGTERR1 - Timestamp Target Time Error - 5 - 5 - read-only - - - TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 - 6 - 6 - read-only - - - TSTRGTERR2 - Timestamp Target Time Error - 7 - 7 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 - 8 - 8 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error - 9 - 9 - read-only - - - Reserved_15_10 - Reserved - 10 - 15 - read-only - - - Reserved_19_16 - Reserved - 16 - 19 - read-only - - - Reserved_23_20 - Reserved - 20 - 23 - read-only - - - Reserved_24 - Reserved - 24 - 24 - read-only - - - Reserved_29_25 - Reserved - 25 - 29 - read-only - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - PPS_CONTROL - PPS Control Register - 0x072C - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSCTRL_PPSCMD - PPSCTRL0 or PPSCMD0 - 0 - 3 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable - 4 - 4 - read-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - 5 - 6 - read-only - - - Reserved_7 - Reserved - 7 - 7 - read-only - - - PPSCMD1 - Flexible PPS1 Output Control - 8 - 10 - read-only - - - Reserved_12_11 - Reserved - 11 - 12 - read-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output - 13 - 14 - read-only - - - Reserved_15 - Reserved - 15 - 15 - read-only - - - PPSCMD2 - Flexible PPS2 Output Control - 16 - 18 - read-only - - - Reserved_20_19 - Reserved - 19 - 20 - read-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output - 21 - 22 - read-only - - - Reserved_23 - Reserved - 23 - 23 - read-only - - - PPSCMD3 - Flexible PPS3 Output Control - 24 - 26 - read-only - - - Reserved_28_27 - Reserved - 27 - 28 - read-only - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output - 29 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00020101 - 0xFFFFFFFF - - - SWR - Software Reset - 0 - 0 - read-write - - - DA - DMA Arbitration Scheme - 1 - 1 - read-write - - - DSL - Descriptor Skip Length - 2 - 6 - read-write - - - Reserved_7 - Reserved - 7 - 7 - read-write - - - PBL - Programmable Burst Length - 8 - 13 - read-write - - - PR - Priority Ratio - 14 - 15 - read-write - - - FB - Fixed Burst - 16 - 16 - read-write - - - RPBL - Rx DMA PBL - 17 - 22 - read-write - - - USP - Use Seperate PBL - 23 - 23 - read-write - - - EIGHTxPBL - 8xPBL Mode - 24 - 24 - read-write - - - AAL - Address Aligned Beats - 25 - 25 - read-write - - - MB - Mixed Burst - 26 - 26 - read-write - - - TXPR - Transmit Priority - 27 - 27 - read-write - - - PRWG - Channel Priority Weights - 28 - 29 - read-only - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - TRANSMIT_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand - 0 - 31 - read-write - - - - - RECEIVE_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand - 0 - 31 - read-write - - - - - RECEIVE_DESCRIPTOR_LIST_ADDRESS - Receive Descriptor Address Register - 0x100C - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_1_0 - Reserved - 0 - 1 - read-only - - - RDESLA_32bit - Start of Receive List - 2 - 31 - read-write - - - - - TRANSMIT_DESCRIPTOR_LIST_ADDRESS - Transmit descripter Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_1_0 - Reserved - 0 - 1 - read-only - - - TDESLA_32bit - Start of Transmit List - 2 - 31 - read-write - - - - - STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0xFFFFFFFF - - - TI - Transmit Interrupt - 0 - 0 - read-write - - - TPS - Transmit Process Stopped - 1 - 1 - read-write - - - TU - Transmit Buffer Unavailable - 2 - 2 - read-write - - - TJT - Transmit Jabber Timeout - 3 - 3 - read-write - - - OVF - Receive Overflow - 4 - 4 - read-write - - - UNF - Transmit Underflow - 5 - 5 - read-write - - - RI - Receive Interrupt - 6 - 6 - read-write - - - RU - Receive Buffer Unavailable - 7 - 7 - read-write - - - RPS - Receive Process Stopped - 8 - 8 - read-write - - - RWT - Receive Watchdog Timeout - 9 - 9 - read-write - - - ETI - Early Transmit Interrupt - 10 - 10 - read-write - - - Reserved_12_11 - Reserved - 11 - 12 - read-only - - - FBI - Fatal Bus Error Interrupt - 13 - 13 - read-write - - - ERI - Early Receive Interrupt - 14 - 14 - read-write - - - AIS - Abnormal Interrupt Summary - 15 - 15 - read-write - - - NIS - Normal Interrupt Summary - 16 - 16 - read-write - - - RS - Received Process State - 17 - 19 - read-only - - - TS - Transmit Process State - 20 - 22 - read-only - - - EB - Error Bits - 23 - 25 - read-only - - - Reserved_26 - Reserved - 26 - 26 - read-only - - - EMI - ETH MMC Interrupt - 27 - 27 - read-only - - - EPI - ETH PMT Interrupt - 28 - 28 - read-only - - - TTI - Timestamp Trigger Interrupt - 29 - 29 - read-only - - - Reserved_30 - Reserved - 30 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - OPERATION_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_0 - Reserved - 0 - 0 - read-only - - - SR - Start or Stop Receive - 1 - 1 - read-write - - - OSF - Operate on Second Frame - 2 - 2 - read-write - - - RTC - Receive Threshold Control - 3 - 4 - read-write - - - Reserved_5 - Reserved - 5 - 5 - read-only - - - FUF - Forward Undersized Good Frames - 6 - 6 - read-write - - - FEF - Forward Error Frames - 7 - 7 - read-write - - - Reserved_12_8 - Reserved - 8 - 12 - read-only - - - ST - Start or Stop Transmission Command - 13 - 13 - read-write - - - TTC - Transmit Threshold Control - 14 - 16 - read-write - - - Reserved_19_17 - Reserved - 17 - 19 - read-only - - - FTF - Flush Transmit FIFO - 20 - 20 - read-write - - - TSF - Transmit Store and Forward - 21 - 21 - read-write - - - Reserved_23_22 - Reserved - 22 - 23 - read-only - - - DFF - Disable Flushing of Received Frames - 24 - 24 - read-write - - - RSF - Receive Store and Forward - 25 - 25 - read-write - - - DT - Disable Dropping of TCP/IP Checksum Error Frames - 26 - 26 - read-write - - - Reserved_31_27 - Reserved - 27 - 31 - read-only - - - - - INTERRUPT_ENABLE - Interrupt Enable Register - 0x101C - 32 - 0x00000000 - 0xFFFFFFFF - - - TIE - Transmit Interrupt Enable - 0 - 0 - read-write - - - TSE - Transmit Stopped Enable - 1 - 1 - read-write - - - TUE - Transmit Buffer Unvailable Enable - 2 - 2 - read-write - - - TJE - Transmit Jabber Timeout Enable - 3 - 3 - read-write - - - OVE - Overflow Interrupt Enable - 4 - 4 - read-write - - - UNE - Underflow Interrupt Enable - 5 - 5 - read-write - - - RIE - Receive Interrupt Enable - 6 - 6 - read-write - - - RUE - Receive Buffer Unavailable Enable - 7 - 7 - read-write - - - RSE - Receive Stopped Enable - 8 - 8 - read-write - - - RWE - Receive Watchdog Timeout Enable - 9 - 9 - read-write - - - ETE - Early Transmit Interrupt Enable - 10 - 10 - read-write - - - Reserved_12_11 - Reserved - 11 - 12 - read-only - - - FBE - Fatal Bus Error Enable - 13 - 13 - read-write - - - ERE - Early Receive Interrupt Enable - 14 - 14 - read-write - - - AIE - Abnormal Interrupt Summary Enable - 15 - 15 - read-write - - - NIE - Normal Interrupt Summary Enable - 16 - 16 - read-write - - - Reserved_31_17 - Reserved - 17 - 31 - read-only - - - - - MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER - Missed Frame and Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0xFFFFFFFF - - - MISFRMCNT - This field indicates the number of frames missed by the controller because of the RAM Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read. - 0 - 15 - read-only - - - MISCNTOVF - Overflow bit for Missed Frame Counter - 16 - 16 - read-only - - - OVFFRMCNT - This field indicates the number of frames missed by the application. The counter is cleared when this register is read. - 17 - 27 - read-only - - - OVFCNTOVF - Overflow bit for FIFO Overflow Counter - 28 - 28 - read-only - - - Reserved_31_29 - Reserved - 29 - 31 - read-only - - - - - RECEIVE_INTERRUPT_WATCHDOG_TIMER - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0xFFFFFFFF - - - RIWT - RI Watchdog Timer Count - 0 - 7 - read-write - - - Reserved_31_8 - Reserved - 8 - 31 - read-only - - - - - AHB_STATUS - AHB Status Register - 0x102C - 32 - 0x00000000 - 0xFFFFFFFF - - - AHBMS - AHB Master Status - 0 - 0 - read-only - - - Reserved_1 - Reserved - 1 - 1 - read-only - - - Reserved_31_2 - Reserved - 2 - 31 - read-only - - - - - CURRENT_HOST_TRANSMIT_DESCRIPTOR - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer - 0 - 31 - read-only - - - - - CURRENT_HOST_RECEIVE_DESCRIPTOR - Current Host Receive Descriptor Register - 0x104C - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer - 0 - 31 - read-only - - - - - CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer - 0 - 31 - read-only - - - - - CURRENT_HOST_RECEIVE_BUFFER_ADDRESS - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer - 0 - 31 - read-only - - - - - HW_FEATURE - HW Feature Register - 0x1058 - 32 - 0x03052F35 - 0xFFFFFFFF - - - MIISEL - 10 or 100 Mbps support - 0 - 0 - read-only - - - GMIISEL - 1000 Mbps support - 1 - 1 - read-only - - - HDSEL - Half-Duplex support - 2 - 2 - read-only - - - EXTHASHEN - Expanded DA Hash Filter - 3 - 3 - read-only - - - HASHSEL - HASH Filter - 4 - 4 - read-only - - - ADDMACADRSEL - Multiple MAC Address Registers - 5 - 5 - read-only - - - PCSSEL - PCS registers (TBI, SGMII, or RTBI PHY interface) - 6 - 6 - read-only - - - L3L4FLTREN - Layer 3 and Layer 4 Filter Feature - 7 - 7 - read-only - - - SMASEL - SMA (MDIO) Interface - 8 - 8 - read-only - - - RWKSEL - PMT Remote Wakeup - 9 - 9 - read-only - - - MGKSEL - PMT Magic Packet - 10 - 10 - read-only - - - MMCSEL - RMON Module - 11 - 11 - read-only - - - TSVER1SEL - Only IEEE 1588-2002 Timestamp - 12 - 12 - read-only - - - TSVER2SEL - IEEE 1588-2008 Advanced Timestamp - 13 - 13 - read-only - - - EEESEL - Energy Efficient Ethernet - 14 - 14 - read-only - - - AVSEL - AV Feature - 15 - 15 - read-only - - - TXCOESEL - Checksum Offload in Tx - 16 - 16 - read-only - - - RXTYP1COE - IP Checksum Offload (Type 1) in Rx - 17 - 17 - read-only - - - RXTYP2COE - IP Checksum Offload (Type 2) in Rx - 18 - 18 - read-only - - - RXFIFOSIZE - Rx FIFO > 2,048 Bytes - 19 - 19 - read-write - - - RXCHCNT - Number of additional Rx channels - 20 - 21 - read-only - - - TXCHCNT - Number of additional Tx channels - 22 - 23 - read-only - - - ENHDESSEL - Alternate (Enhanced Descriptor) - 24 - 24 - read-only - - - INTTSEN - Timestamping with Internal System Time - 25 - 25 - read-only - - - FLEXIPPSEN - Flexible Pulse-Per-Second Output - 26 - 26 - read-only - - - SAVLANINS - Source Address or VLAN Insertion - 27 - 27 - read-only - - - ACTPHYIF - Active or Selected PHY interface - 28 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - - - USB0 - Universal Serial Bus - USB - USB - 0x50040000 - - 0x0 - 0x040000 - registers - - - - GOTGCTL - Control and Status Register - 0x000 - 32 - 0x00010000 - 0xFFFFFFFF - - - SesReqScs - Session Request Success - 0 - 0 - read-only - - - value1 - Session request failure - 0b0 - - - value2 - Session request success - 0b1 - - - - - SesReq - Session Request - 1 - 1 - read-write - - - value1 - No session request - 0b0 - - - value2 - Session request - 0b1 - - - - - VbvalidOvEn - VBUS Valid Override Enable - 2 - 2 - read-write - - - value1 - Override is disabled and vbus valid signal from the PHY is used internally by the core. - 0b0 - - - value2 - Internally vbus valid received from the PHY is overridden with GOTGCTL.VbvalidOvVal. - 0b1 - - - - - VbvalidOvVal - VBUS Valid Override Value - 3 - 3 - read-write - - - value1 - vbusvalid value is 0# when GOTGCTL.VbvalidOvEn = 1 - 0b0 - - - value2 - vbusvalid value is 1# when GOTGCTL.VbvalidOvEn = 1 - 0b1 - - - - - AvalidOvEn - A-Peripheral Session Valid Override Enable - 4 - 4 - read-write - - - value1 - Override is disabled and Avalid signal from the PHY is used internally by the core. - 0b0 - - - value2 - Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal. - 0b1 - - - - - AvalidOvVal - A-Peripheral Session Valid Override Value - 5 - 5 - read-write - - - value1 - Avalid value is 0# when GOTGCTL.AvalidOvEn = 1 - 0b0 - - - value2 - Avalid value is 1# when GOTGCTL.AvalidOvEn = 1 - 0b1 - - - - - BvalidOvEn - B-Peripheral Session Valid Override Enable - 6 - 6 - read-write - - - value1 - Override is disabled and Bvalid signal from the PHY is used internally by the core. - 0b0 - - - value2 - Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal. - 0b1 - - - - - BvalidOvVal - B-Peripheral Session Valid Override Value - 7 - 7 - read-write - - - value1 - Bvalid value is 0# when GOTGCTL.BvalidOvEn = 1 - 0b0 - - - value2 - Bvalid value is 1# when GOTGCTL.BvalidOvEn = 1 - 0b1 - - - - - HstNegScs - Host Negotiation Success - 8 - 8 - read-only - - - value1 - Host negotiation failure - 0b0 - - - value2 - Host negotiation success - 0b1 - - - - - HNPReq - HNP Request - 9 - 9 - read-write - - - value1 - No HNP request - 0b0 - - - value2 - HNP request - 0b1 - - - - - HstSetHNPEn - Host Set HNP Enable - 10 - 10 - read-write - - - value1 - Host Set HNP is not enabled - 0b0 - - - value2 - Host Set HNP is enabled - 0b1 - - - - - DevHNPEn - Device HNP Enabled - 11 - 11 - read-write - - - value1 - HNP is not enabled in the application - 0b0 - - - value2 - HNP is enabled in the application - 0b1 - - - - - ConlDSts - Connector ID Status - 16 - 16 - read-only - - - value1 - The USB core is in A-Device mode - 0b0 - - - value2 - The USB core is in B-Device mode - 0b1 - - - - - DbncTime - Long/Short Debounce Time - 17 - 17 - read-only - - - value1 - Long debounce time, used for physical connections (100 ms + 2.5 us) - 0b0 - - - value2 - Short debounce time, used for soft connections (2.5 us) - 0b1 - - - - - ASesVId - A-Session Valid - 18 - 18 - read-only - - - value1 - A-session is not valid - 0b0 - - - value2 - A-session is valid - 0b1 - - - - - BSesVld - B-Session Valid - 19 - 19 - read-only - - - value1 - B-session is not valid. - 0b0 - - - value2 - B-session is valid. - 0b1 - - - - - OTGVer - OTG Version - 20 - 20 - read-write - - - value1 - OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP. - 0b0 - - - value2 - OTG Version 2.0. In this version the core supports only Data line pulsing for SRP. - 0b1 - - - - - - - GOTGINT - OTG Interrupt Register - 0x004 - 32 - 0x00000000 - 0xFFFFFFFF - - - SesEndDet - Session End Detected - 2 - 2 - read-write - - - SesReqSucStsChng - Session Request Success Status Change - 8 - 8 - read-write - - - HstNegSucStsChng - Host Negotiation Success Status Change - 9 - 9 - read-write - - - HstNegDet - Host Negotiation Detected - 17 - 17 - read-write - - - ADevTOUTChg - A-Device Timeout Change - 18 - 18 - read-write - - - DbnceDone - Debounce Done - 19 - 19 - read-write - - - - - GAHBCFG - AHB Configuration Register - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - GlblIntrMsk - Global Interrupt Mask - 0 - 0 - read-write - - - value1 - Mask the interrupt assertion to the application. - 0b0 - - - value2 - Unmask the interrupt assertion to the application. - 0b1 - - - - - HBstLen - Burst Length/Type - 1 - 4 - read-write - - - value1 - Single - 0b0000 - - - value2 - INCR - 0b0001 - - - value3 - INCR4 - 0b0011 - - - value4 - INCR8 - 0b0101 - - - value5 - INCR16 - 0b0111 - - - - - DMAEn - DMA Enable - 5 - 5 - read-write - - - value1 - Core operates in Slave mode - 0b0 - - - value2 - Core operates in a DMA mode - 0b1 - - - - - NPTxFEmpLvl - Non-Periodic TxFIFO Empty Level - 7 - 7 - read-write - - - value1 - DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty - 0b0 - - - value2 - DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty - 0b1 - - - - - PTxFEmpLvl - Periodic TxFIFO Empty Level - 8 - 8 - read-write - - - value1 - GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty - 0b0 - - - value2 - GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty - 0b1 - - - - - - - GUSBCFG - USB Configuration Register - 0x00C - 32 - 0x00001440 - 0xFFFFFFFF - - - TOutCal - FS Timeout Calibration - 0 - 2 - read-write - - - PHYSel - USB 1.1 Full-Speed Serial Transceiver Select - 6 - 6 - read-only - - - value1 - Reserved - 0b0 - - - value2 - USB 1.1 full-speed serial transceiver - 0b1 - - - - - SRPCap - SRP-Capable - 8 - 8 - read-write - - - value1 - SRP capability is not enabled. - 0b0 - - - value2 - SRP capability is enabled. - 0b1 - - - - - HNPCap - HNP-Capable - 9 - 9 - read-write - - - value1 - HNP capability is not enabled. - 0b0 - - - value2 - HNP capability is enabled. - 0b1 - - - - - USBTrdTim - USB Turnaround Time - 10 - 13 - read-write - - - OtgI2CSel - UTMIFS Interface Select - 16 - 16 - read-write - - - value1 - UTMI USB 1.1 Full-Speed interface for OTG signals - 0b0 - - - value2 - Reserved - 0b1 - - - - - TxEndDelay - Tx End Delay - 28 - 28 - read-write - - - value1 - Normal mode - 0b0 - - - value2 - Introduce Tx end delay timers - 0b1 - - - - - ForceHstMode - Force Host Mode - 29 - 29 - read-write - - - value1 - Normal Mode - 0b0 - - - value2 - Force Host Mode - 0b1 - - - - - ForceDevMode - Force Device Mode - 30 - 30 - read-write - - - value1 - Normal Mode - 0b0 - - - value2 - Force Device Mode - 0b1 - - - - - CTP - Corrupt Tx packet - 31 - 31 - read-write - - - - - GRSTCTL - Reset Register - 0x010 - 32 - 0x10000000 - 0xFFFFFFFF - - - CSftRst - Core Soft Reset - 0 - 0 - read-write - - - FrmCntrRst - Host Frame Counter Reset - 2 - 2 - read-write - - - RxFFlsh - RxFIFO Flush - 4 - 4 - read-write - - - TxFFlsh - TxFIFO Flush - 5 - 5 - read-write - - - TxFNum - TxFIFO Number - 6 - 10 - read-write - - - value1 - Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode - 0x00 - - - value2 - Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode - 0x01 - - - value3 - Tx FIFO 2 flush in device mode - 0x02 - - - value4 - Tx FIFO 15 flush in device mode - 0x0F - - - value5 - Flush all the transmit FIFOs in device or host mode. - 0x10 - - - - - DMAReq - DMA Request Signal - 30 - 30 - read-only - - - AHBIdle - AHB Master Idle - 31 - 31 - read-only - - - - - GINTSTS_HOSTMODE - Interrupt Register [HOSTMODE] - 0x014 - 32 - 0x14000020 - 0xFFFFFFFF - - - CurMod - Current Mode of Operation - 0 - 0 - read-only - - - value1 - Device mode - 0b0 - - - value2 - Host mode - 0b1 - - - - - ModeMis - Mode Mismatch Interrupt - 1 - 1 - read-write - - - OTGInt - OTG Interrupt - 2 - 2 - read-only - - - Sof - Start of Frame - 3 - 3 - read-write - - - RxFLvl - RxFIFO Non-Empty - 4 - 4 - read-only - - - incomplP - Incomplete Periodic Transfer - 21 - 21 - read-write - - - PrtInt - Host Port Interrupt - 24 - 24 - read-only - - - HChInt - Host Channels Interrupt - 25 - 25 - read-only - - - PTxFEmp - Periodic TxFIFO Empty - 26 - 26 - read-only - - - ConIDStsChng - Connector ID Status Change - 28 - 28 - read-write - - - DisconnInt - Disconnect Detected Interrupt - 29 - 29 - read-write - - - SessReqInt - Session Request/New Session Detected Interrupt - 30 - 30 - read-write - - - WkUpInt - Resume/Remote Wakeup Detected Interrupt - 31 - 31 - read-write - - - - - GINTSTS_DEVICEMODE - Interrupt Register [DEVICEMODE] - GINTSTS_HOSTMODE - 0x014 - 32 - 0x14000020 - 0xFFFFFFFF - - - CurMod - Current Mode of Operation - 0 - 0 - read-only - - - value1 - Device mode - 0b0 - - - value2 - Host mode - 0b1 - - - - - ModeMis - Mode Mismatch Interrupt - 1 - 1 - read-write - - - OTGInt - OTG Interrupt - 2 - 2 - read-only - - - Sof - Start of Frame - 3 - 3 - read-write - - - RxFLvl - RxFIFO Non-Empty - 4 - 4 - read-only - - - GINNakEff - Global IN Non-Periodic NAK Effective - 6 - 6 - read-only - - - GOUTNakEff - Global OUT NAK Effective - 7 - 7 - read-only - - - ErlySusp - Early Suspend - 10 - 10 - read-write - - - USBSusp - USB Suspend - 11 - 11 - read-write - - - USBRst - USB Reset - 12 - 12 - read-write - - - EnumDone - Enumeration Done - 13 - 13 - read-write - - - ISOOutDrop - Isochronous OUT Packet Dropped Interrupt - 14 - 14 - read-write - - - EOPF - End of Periodic Frame Interrupt - 15 - 15 - read-write - - - IEPInt - IN Endpoints Interrupt - 18 - 18 - read-only - - - OEPInt - OUT Endpoints Interrupt - 19 - 19 - read-only - - - incompISOIN - Incomplete Isochronous IN Transfer - 20 - 20 - read-write - - - incomplSOOUT - Incomplete Isochronous OUT Transfer - 21 - 21 - read-write - - - ConIDStsChng - Connector ID Status Change - 28 - 28 - read-write - - - SessReqInt - Session Request/New Session Detected Interrupt - 30 - 30 - read-write - - - WkUpInt - Resume/Remote Wakeup Detected Interrupt - 31 - 31 - read-write - - - - - GINTMSK_HOSTMODE - Interrupt Mask Register [HOSTMODE] - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - ModeMisMsk - Mode Mismatch Interrupt Mask - 1 - 1 - read-write - - - OTGIntMsk - OTG Interrupt Mask - 2 - 2 - read-write - - - SofMsk - Start of Frame Mask - 3 - 3 - read-write - - - RxFLvlMsk - Receive FIFO Non-Empty Mask - 4 - 4 - read-write - - - incomplPMsk - Incomplete Periodic Transfer Mask - 21 - 21 - read-write - - - PrtIntMsk - Host Port Interrupt Mask - 24 - 24 - read-write - - - HChIntMsk - Host Channels Interrupt Mask - 25 - 25 - read-write - - - PTxFEmpMsk - Periodic TxFIFO Empty Mask - 26 - 26 - read-write - - - ConIDStsChngMsk - Connector ID Status Change Mask - 28 - 28 - read-write - - - DisconnIntMsk - Disconnect Detected Interrupt Mask - 29 - 29 - read-write - - - SessReqIntMsk - Session Request/New Session Detected Interrupt Mask - 30 - 30 - read-write - - - WkUpIntMsk - Resume/Remote Wakeup Detected Interrupt Mask - 31 - 31 - read-write - - - - - GINTMSK_DEVICEMODE - Interrupt Mask Register [DEVICEMODE] - GINTMSK_HOSTMODE - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - ModeMisMsk - Mode Mismatch Interrupt Mask - 1 - 1 - read-write - - - OTGIntMsk - OTG Interrupt Mask - 2 - 2 - read-write - - - SofMsk - Start of Frame Mask - 3 - 3 - read-write - - - RxFLvlMsk - Receive FIFO Non-Empty Mask - 4 - 4 - read-write - - - GINNakEffMsk - Global Non-periodic IN NAK Effective Mask - 6 - 6 - read-write - - - GOUTNakEffMsk - Global OUT NAK Effective Mask - 7 - 7 - read-write - - - ErlySuspMsk - Early Suspend Mask - 10 - 10 - read-write - - - USBSuspMsk - USB Suspend Mask - 11 - 11 - read-write - - - USBRstMsk - USB Reset Mask - 12 - 12 - read-write - - - EnumDoneMsk - Enumeration Done Mask - 13 - 13 - read-write - - - ISOOutDropMsk - Isochronous OUT Packet Dropped Interrupt Mask - 14 - 14 - read-write - - - EOPFMsk - End of Periodic Frame Interrupt Mask - 15 - 15 - read-write - - - IEPIntMsk - IN Endpoints Interrupt Mask - 18 - 18 - read-write - - - OEPIntMsk - OUT Endpoints Interrupt Mask - 19 - 19 - read-write - - - incompISOINMsk - Incomplete Isochronous IN Transfer Mask - 20 - 20 - read-write - - - incomplSOOUTMsk - Incomplete Isochronous OUT Transfer Mask - 21 - 21 - read-write - - - ConIDStsChngMsk - Connector ID Status Change Mask - 28 - 28 - read-write - - - SessReqIntMsk - Session Request/New Session Detected Interrupt Mask - 30 - 30 - read-write - - - WkUpIntMsk - Resume/Remote Wakeup Detected Interrupt Mask - 31 - 31 - read-write - - - - - GRXSTSR_HOSTMODE - Receive Status Debug Read Register [HOSTMODE] - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - ChNum - Channel Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - IN data packet received - 0b0010 - - - value2 - IN transfer completed (triggers an interrupt) - 0b0011 - - - value3 - Data toggle error (triggers an interrupt) - 0b0101 - - - value4 - Channel halted (triggers an interrupt) - 0b0111 - - - - - - - GRXSTSR_DEVICEMODE - Receive Status Debug Read Register [DEVICEMODE] - GRXSTSR_HOSTMODE - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - EPNum - Endpoint Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - Global OUT NAK (triggers an interrupt) - 0b0001 - - - value2 - OUT data packet received - 0b0010 - - - value3 - OUT transfer completed (triggers an interrupt) - 0b0011 - - - value4 - SETUP transaction completed (triggers an interrupt) - 0b0100 - - - value5 - SETUP data packet received - 0b0110 - - - - - FN - Frame Number - 21 - 24 - read-only - - - - - GRXSTSP_HOSTMODE - Receive Status Read and Pop Register [HOSTMODE] - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - ChNum - Channel Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - IN data packet received - 0b0010 - - - value2 - IN transfer completed (triggers an interrupt) - 0b0011 - - - value3 - Data toggle error (triggers an interrupt) - 0b0101 - - - value4 - Channel halted (triggers an interrupt) - 0b0111 - - - - - - - GRXSTSP_DEVICEMODE - Receive Status Read and Pop Register [DEVICEMODE] - GRXSTSP_HOSTMODE - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPNum - Endpoint Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - Global OUT NAK (triggers an interrupt) - 0b0001 - - - value2 - OUT data packet received - 0b0010 - - - value3 - OUT transfer completed (triggers an interrupt) - 0b0011 - - - value4 - SETUP transaction completed (triggers an interrupt) - 0b0100 - - - value5 - SETUP data packet received - 0b0110 - - - - - FN - Frame Number - 21 - 24 - read-only - - - - - GRXFSIZ - Receive FIFO Size Register - 0x024 - 32 - 0x0000011A - 0xFFFFFFFF - - - RxFDep - RxFIFO Depth - 0 - 15 - read-write - - - - - GNPTXFSIZ_HOSTMODE - Non-Periodic Transmit FIFO Size Register [HOSTMODE] - 0x028 - 32 - 0x0010011A - 0xFFFFFFFF - - - NPTxFStAddr - Non-periodic Transmit RAM Start Address - 0 - 15 - read-write - - - NPTxFDep - Non-periodic TxFIFO Depth - 16 - 31 - read-write - - - - - GNPTXFSIZ_DEVICEMODE - Non-Periodic Transmit FIFO Size Register [DEVICEMODE] - GNPTXFSIZ_HOSTMODE - 0x028 - 32 - 0x00100000 - 0xFFFFFFFF - - - INEPTxF0StAddr - IN Endpoint FIFO0 Transmit RAM Start Address - 0 - 15 - read-write - - - INEPTxF0Dep - IN Endpoint TxFIFO 0 Depth - 16 - 31 - read-write - - - - - GNPTXSTS - Non-Periodic Transmit FIFO/Queue Status Register - 0x02C - 32 - 0x00080010 - 0xFFFFFFFF - - - NPTxFSpcAvail - Non-periodic TxFIFO Space Avail - 0 - 15 - read-only - - - value1 - Non-periodic TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - NPTxQSpcAvail - Non-periodic Transmit Request Queue Space Available - 16 - 23 - read-only - - - value1 - Non-periodic Transmit Request Queue is full - 0x0 - - - value2 - 1 location available - 0x1 - - - value3 - 2 locations available - 0x2 - - - - - NPTxQTop - Top of the Non-periodic Transmit Request Queue - 24 - 30 - read-only - - - value1 - IN/OUT token - 0b00 - - - value2 - Zero-length transmit packet (device IN/host OUT) - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Channel halt command - 0b11 - - - - - - - GUID - USB Module Identification Register - 0x03C - 32 - 0x00AEC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-write - - - MOD_TYPE - Module Type - 8 - 15 - read-write - - - MOD_NUMBER - Module Number - 16 - 31 - read-write - - - - - GDFIFOCFG - Global DFIFO Software Config Register - 0x05C - 32 - 0x027A02B2 - 0xFFFFFFFF - - - GDFIFOCfg - GDFIFOCfg - 0 - 15 - read-write - - - EPInfoBaseAddr - EPInfoBaseAddr - 16 - 31 - read-write - - - - - HPTXFSIZ - Host Periodic Transmit FIFO Size Register - 0x100 - 32 - 0x0100012A - 0xFFFFFFFF - - - PTxFStAddr - Host Periodic TxFIFO Start Address - 0 - 15 - read-write - - - PTxFSize - Host Periodic TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF1 - Device IN Endpoint 1 Transmit FIFO Size Register - 0x104 - 32 - 0x0100012A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF2 - Device IN Endpoint 2 Transmit FIFO Size Register - 0x108 - 32 - 0x0100022A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF3 - Device IN Endpoint 3 Transmit FIFO Size Register - 0x10C - 32 - 0x0100032A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF4 - Device IN Endpoint 4 Transmit FIFO Size Register - 0x110 - 32 - 0x0100042A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF5 - Device IN Endpoint 5 Transmit FIFO Size Register - 0x114 - 32 - 0x0100052A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF6 - Device IN Endpoint 6 Transmit FIFO Size Register - 0x118 - 32 - 0x0100062A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - HCFG - Host Configuration Register - 0x400 - 32 - 0x00000200 - 0xFFFFFFFF - - - FSLSPclkSel - FS PHY Clock Select - 0 - 1 - read-write - - - value1 - PHY clock is running at 48 MHz - 0b01 - - - - - FSLSSupp - FS-Only Support - 2 - 2 - read-write - - - value1 - FS-only, connected device can supports also only FS. - 0b0 - - - value2 - FS-only, even if the connected device can support HS - 0b1 - - - - - DescDMA - Enable Scatter/gather DMA in Host mode - 23 - 23 - read-write - - - FrListEn - Frame List Entries - 24 - 25 - read-write - - - value1 - 8 Entries - 0b00 - - - value2 - 16 Entries - 0b01 - - - value3 - 32 Entries - 0b10 - - - value4 - 64 Entries - 0b11 - - - - - PerSchedEna - Enable Periodic Scheduling - 26 - 26 - read-write - - - - - HFIR - Host Frame Interval Register - 0x404 - 32 - 0x0000EA60 - 0xFFFFFFFF - - - FrInt - Frame Interval - 0 - 15 - read-write - - - HFIRRldCtrl - Reload Control - 16 - 16 - read-write - - - value1 - HFIR cannot be reloaded dynamically - 0b0 - - - value2 - HFIR can be dynamically reloaded during runtime - 0b1 - - - - - - - HFNUM - Host Frame Number/Frame Time Remaining Register - 0x408 - 32 - 0x00003FFF - 0xFFFFFFFF - - - FrNum - Frame Number - 0 - 15 - read-write - - - FrRem - Frame Time Remaining - 16 - 31 - read-only - - - - - HPTXSTS - Host Periodic Transmit FIFO/ Queue Status Register - 0x410 - 32 - 0x00080100 - 0xFFFFFFFF - - - PTxFSpcAvail - Periodic Transmit Data FIFO Space Available - 0 - 15 - read-write - - - value1 - Periodic TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - PTxQSpcAvail - Periodic Transmit Request Queue Space Available - 16 - 23 - read-only - - - value1 - Periodic Transmit Request Queue is full - 0x0 - - - value2 - 1 location available - 0x1 - - - value3 - 2 locations available - 0x2 - - - - - PTxQTop - Top of the Periodic Transmit Request Queue - 24 - 31 - read-only - - - - - HAINT - Host All Channels Interrupt Register - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - HAINT - Channel Interrupts - 0 - 13 - read-only - - - - - HAINTMSK - Host All Channels Interrupt Mask Register - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - HAINTMsk - Channel Interrupt Mask - 0 - 13 - read-write - - - - - HFLBADDR - Host Frame List Base Address Register - 0x41C - 32 - 0x00000000 - 0xFFFFFFFF - - - Starting_Address - Starting Address - 0 - 31 - read-write - - - - - HPRT - Host Port Control and Status Register - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - PrtConnSts - Port Connect Status - 0 - 0 - read-only - - - value1 - No device is attached to the port. - 0b0 - - - value2 - A device is attached to the port. - 0b1 - - - - - PrtConnDet - Port Connect Detected - 1 - 1 - read-write - - - PrtEna - Port Enable - 2 - 2 - read-write - - - value1 - Port disabled - 0b0 - - - value2 - Port enabled - 0b1 - - - - - PrtEnChng - Port Enable/Disable Change - 3 - 3 - read-write - - - PrtOvrCurrAct - Port Overcurrent Active - 4 - 4 - read-only - - - value1 - No overcurrent condition - 0b0 - - - value2 - Overcurrent condition - 0b1 - - - - - PrtOvrCurrChng - Port Overcurrent Change - 5 - 5 - read-write - - - PrtRes - Port Resume - 6 - 6 - read-write - - - value1 - No resume driven - 0b0 - - - value2 - Resume driven - 0b1 - - - - - PrtSusp - Port Suspend - 7 - 7 - read-write - - - value1 - Port not in Suspend mode - 0b0 - - - value2 - Port in Suspend mode - 0b1 - - - - - PrtRst - Port Reset - 8 - 8 - read-write - - - value1 - Port not in reset - 0b0 - - - value2 - Port in reset - 0b1 - - - - - PrtLnSts - Port Line Status - 10 - 11 - read-only - - - PrtPwr - Port Power - 12 - 12 - read-write - - - value1 - Power off - 0b0 - - - value2 - Power on - 0b1 - - - - - PrtSpd - Port Speed - 17 - 18 - read-only - - - value1 - Full speed - 0b01 - - - - - - - DCFG - Device Configuration Register - 0x800 - 32 - 0x08200000 - 0xFFFFFFFF - - - DevSpd - Device Speed - 0 - 1 - read-write - - - value1 - Reserved - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Full speed (USB 1.1 transceiver clock is 48 MHz) - 0b11 - - - - - NZStsOUTHShk - Non-Zero-Length Status OUT Handshake - 2 - 2 - read-write - - - value1 - Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. - 0b1 - - - value2 - Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register. - 0b0 - - - - - DevAddr - Device Address - 4 - 10 - read-write - - - PerFrInt - Periodic Frame Interval - 11 - 12 - read-write - - - value1 - 80% of the frame interval - 0b00 - - - value2 - 85% - 0b01 - - - value3 - 90% - 0b10 - - - value4 - 95% - 0b11 - - - - - DescDMA - Enable Scatter/Gather DMA in Device mode. - 23 - 23 - read-write - - - PerSchIntvl - Periodic Scheduling Interval - 24 - 25 - read-write - - - value1 - 25% of frame. - 0b00 - - - value2 - 50% of frame. - 0b01 - - - value3 - 75% of frame. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - DCTL - Device Control Register - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - RmtWkUpSig - Remote Wakeup Signaling - 0 - 0 - read-write - - - SftDiscon - Soft Disconnect - 1 - 1 - read-write - - - value1 - Normal operation. When this bit is cleared after a soft disconnect, the core drives a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. - 0b0 - - - value2 - The core drives a device disconnect event to the USB host. - 0b1 - - - - - GNPINNakSts - Global Non-periodic IN NAK Status - 2 - 2 - read-only - - - value1 - A handshake is sent out based on the data availability in the transmit FIFO. - 0b0 - - - value2 - A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. - 0b1 - - - - - GOUTNakSts - Global OUT NAK Status - 3 - 3 - read-only - - - value1 - A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. - 0b0 - - - value2 - No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. - 0b1 - - - - - SGNPInNak - Set Global Non-periodic IN NAK - 7 - 7 - write-only - - - CGNPInNak - Clear Global Non-periodic IN NAK - 8 - 8 - write-only - - - SGOUTNak - Set Global OUT NAK - 9 - 9 - write-only - - - CGOUTNak - Clear Global OUT NAK - 10 - 10 - write-only - - - GMC - Global Multi Count - 13 - 14 - read-write - - - value1 - Invalid. - 0b00 - - - value2 - 1 packet. - 0b01 - - - value3 - 2 packets. - 0b10 - - - value4 - 3 packets. - 0b11 - - - - - IgnrFrmNum - Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA - 15 - 15 - read-write - - - value1 - Scatter/Gather enabled: The core transmits the packets only in the frame number in which they are intended to be transmitted. Scatter/Gather disabled: Periodic transfer interrupt feature is disabled; the application must program transfers for periodic endpoints every frame - 0b0 - - - value2 - Scatter/Gather enabled: The core ignores the frame number, sending packets immediately as the packets are ready. Scatter/Gather disabled: Periodic transfer interrupt feature is enabled; the application can program transfers for multiple frames for periodic endpoints. - 0b1 - - - - - NakOnBble - Set NAK automatically on babble - 16 - 16 - read-write - - - - - DSTS - Device Status Register - 0x808 - 32 - 0x00000002 - 0xFFFFFFFF - - - SuspSts - Suspend Status - 0 - 0 - read-only - - - EnumSpd - Enumerated Speed - 1 - 2 - read-only - - - value1 - Reserved - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Full speed (PHY clock is running at 48 MHz) - 0b11 - - - - - ErrticErr - Erratic Error - 3 - 3 - read-only - - - SOFFN - Frame Number of the Received SOF - 8 - 21 - read-only - - - - - DIEPMSK - Device IN Endpoint Common Interrupt Mask Register - 0x810 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferComplMsk - Transfer Completed Interrupt Mask - 0 - 0 - read-write - - - EPDisbldMsk - Endpoint Disabled Interrupt Mask - 1 - 1 - read-write - - - AHBErrMsk - AHB Error Mask - 2 - 2 - read-write - - - TimeOUTMsk - Timeout Condition Mask - 3 - 3 - read-write - - - INTknTXFEmpMsk - IN Token Received When TxFIFO Empty Mask - 4 - 4 - read-write - - - INEPNakEffMsk - IN Endpoint NAK Effective Mask - 6 - 6 - read-write - - - TxfifoUndrnMsk - Fifo Underrun Mask - 8 - 8 - read-write - - - BNAInIntrMsk - BNA Interrupt Mask - 9 - 9 - read-write - - - NAKMsk - NAK interrupt Mask - 13 - 13 - read-write - - - - - DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register - 0x814 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferComplMsk - Transfer Completed Interrupt Mask - 0 - 0 - read-write - - - EPDisbldMsk - Endpoint Disabled Interrupt Mask - 1 - 1 - read-write - - - AHBErrMsk - AHB Error - 2 - 2 - read-write - - - SetUPMsk - SETUP Phase Done Mask - 3 - 3 - read-write - - - OUTTknEPdisMsk - OUT Token Received when Endpoint Disabled Mask - 4 - 4 - read-write - - - Back2BackSETup - Back-to-Back SETUP Packets Received Mask - 6 - 6 - read-write - - - OutPktErrMsk - OUT Packet Error Mask - 8 - 8 - read-write - - - BnaOutIntrMsk - BNA interrupt Mask - 9 - 9 - read-write - - - BbleErrMsk - Babble Interrupt Mask - 12 - 12 - read-write - - - NAKMsk - NAK Interrupt Mask - 13 - 13 - read-write - - - NYETMsk - NYET Interrupt Mask - 14 - 14 - read-write - - - - - DAINT - Device All Endpoints Interrupt Register - 0x818 - 32 - 0x00000000 - 0xFFFFFFFF - - - InEpInt - IN Endpoint Interrupt Bits - 0 - 15 - read-only - - - OutEPInt - OUT Endpoint Interrupt Bits - 16 - 31 - read-only - - - - - DAINTMSK - Device All Endpoints Interrupt Mask Register - 0x81C - 32 - 0x00000000 - 0xFFFFFFFF - - - InEpMsk - IN EP Interrupt Mask Bits - 0 - 15 - read-write - - - OutEpMsk - OUT EP Interrupt Mask Bits - 16 - 31 - read-write - - - - - DVBUSDIS - Device VBUS Discharge Time Register - 0x828 - 32 - 0x000017D7 - 0xFFFFFFFF - - - DVBUSDis - Device Vbus Discharge Time - 0 - 15 - read-write - - - - - DVBUSPULSE - Device VBUS Pulsing Time Register - 0x82C - 32 - 0x000005B8 - 0xFFFFFFFF - - - DVBUSPulse - Device Vbus Pulsing Time - 0 - 11 - read-write - - - - - DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register - 0x834 - 32 - 0x00000000 - 0xFFFFFFFF - - - InEpTxfEmpMsk - IN EP Tx FIFO Empty Interrupt Mask Bits - 0 - 15 - read-write - - - - - PCGCCTL - Power and Clock Gating Control Register - 0xE00 - 32 - 0x00000100 - 0xFFFFFFFF - - - StopPclk - Stop Pclk - 0 - 0 - read-write - - - GateHclk - Gate Hclk - 1 - 1 - read-write - - - - - - - USB0_EP0 - Universal Serial Bus - USB - 0x50040900 - - 0x0 - 0x0400 - registers - - - - DIEPCTL0 - Device Control IN Endpoint 0 Control Register - 0x000 - 32 - 0x00008000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 1 - read-write - - - value1 - 64 bytes - 0b00 - - - value2 - 32 bytes - 0b01 - - - value3 - 16 bytes - 0b10 - - - value4 - 8 bytes - 0b11 - - - - - USBActEP - USB Active Endpoint - 15 - 15 - read-only - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-only - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DIEPINT0 - Device Endpoint-0 Interrupt Register - 0x008 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - TimeOUT - Timeout Condition - 3 - 3 - read-write - - - INTknTXFEmp - IN Token Received When TxFIFO is Empty - 4 - 4 - read-write - - - INEPNakEff - IN Endpoint NAK Effective - 6 - 6 - read-write - - - TxFEmp - Transmit FIFO Empty - 7 - 7 - read-only - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - - - DIEPTSIZ0 - Device IN Endpoint 0 Transfer Size Register - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 6 - read-write - - - PktCnt - Packet Count - 19 - 20 - read-write - - - - - DIEPDMA0 - Device Endpoint-0 DMA Address Register - 0x014 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DTXFSTS0 - Device IN Endpoint Transmit FIFO Status Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - INEPTxFSpcAvail - IN Endpoint TxFIFO Space Avail - 0 - 15 - read-only - - - value1 - Endpoint TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - - - DIEPDMAB0 - Device Endpoint-0 DMA Buffer Address Register - 0x01C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - DOEPCTL0 - Device Control OUT Endpoint 0 Control Register - 0x200 - 32 - 0x00008000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 1 - read-only - - - value1 - 64 bytes - 0b00 - - - value2 - 32 bytes - 0b01 - - - value3 - 16 bytes - 0b10 - - - value4 - 8 bytes - 0b11 - - - - - USBActEP - USB Active Endpoint - 15 - 15 - read-only - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-only - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-only - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DOEPINT0 - Device Endpoint-0 Interrupt Register - 0x208 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - SetUp - SETUP Phase Done - 3 - 3 - read-write - - - OUTTknEPdis - OUT Token Received When Endpoint Disabled - 4 - 4 - read-write - - - StsPhseRcvd - Status Phase Received For Control Write - 5 - 5 - read-write - - - Back2BackSETup - Back-to-Back SETUP Packets Received - 6 - 6 - read-write - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - PktDrpSts - Packet Dropped Status - 11 - 11 - read-write - - - BbleErrIntrpt - BbleErr (Babble Error) interrupt - 12 - 12 - read-write - - - NAKIntrpt - NAK interrupt - 13 - 13 - read-write - - - NYETIntrpt - NYET interrupt - 14 - 14 - read-write - - - - - DOEPTSIZ0 - Device OUT Endpoint 0 Transfer Size Register - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 6 - read-write - - - PktCnt - Packet Count - 19 - 20 - read-write - - - SUPCnt - SETUP Packet Count - 29 - 30 - read-write - - - value1 - 1 packet - 0b01 - - - value2 - 2 packets - 0b10 - - - value3 - 3 packets - 0b11 - - - - - - - DOEPDMA0 - Device Endpoint-0 DMA Address Register - 0x214 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DOEPDMAB0 - Device Endpoint-0 DMA Buffer Address Register - 0x21C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - - - USB0_EP1 - Universal Serial Bus - USB - USB_EP - 0x50040920 - - 0x0 - 0x0400 - registers - - - - DIEPCTL_ISOCONT - Device Endpoint Control Register [ISOCONT] - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - EO_FrNum - Even/Odd Frame - 16 - 16 - read-only - - - value1 - Even frame - 0b0 - - - value2 - Odd rame - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetEvenFr - In non-Scatter/Gather DMA mode: Set Even frame - 28 - 28 - write-only - - - SetOddFr - Set Odd frame - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DIEPCTL_INTBULK - Device Endpoint Control Register [INTBULK] - DIEPCTL_ISOCONT - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - DPID - Endpoint Data PID - 16 - 16 - read-only - - - value1 - DATA0 - 0b0 - - - value2 - DATA1 - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetD0PID - Set DATA0 PID - 28 - 28 - write-only - - - SetD1PID - 29 Set DATA1 PID - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DIEPINT - Device Endpoint Interrupt Register - 0x008 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - TimeOUT - Timeout Condition - 3 - 3 - read-write - - - INTknTXFEmp - IN Token Received When TxFIFO is Empty - 4 - 4 - read-write - - - INEPNakEff - IN Endpoint NAK Effective - 6 - 6 - read-write - - - TxFEmp - Transmit FIFO Empty - 7 - 7 - read-only - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - - - DIEPTSIZ - Device Endpoint Transfer Size Register - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - - - DIEPDMA - Device Endpoint DMA Address Register - 0x014 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DTXFSTS - Device IN Endpoint Transmit FIFO Status Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - INEPTxFSpcAvail - IN Endpoint TxFIFO Space Avail - 0 - 15 - read-only - - - value1 - Endpoint TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - - - DIEPDMAB - Device Endpoint DMA Buffer Address Register - 0x01C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - DOEPCTL_ISOCONT - Device Endpoint Control Register [ISOCONT] - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - EO_FrNum - Even/Odd Frame - 16 - 16 - read-only - - - value1 - Even frame - 0b0 - - - value2 - Odd rame - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetEvenFr - In non-Scatter/Gather DMA mode: Set Even frame - 28 - 28 - write-only - - - SetOddFr - Set Odd frame - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DOEPCTL_INTBULK - Device Endpoint Control Register [INTBULK] - DOEPCTL_ISOCONT - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - DPID - Endpoint Data PID - 16 - 16 - read-only - - - value1 - DATA0 - 0b0 - - - value2 - DATA1 - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetD0PID - Set DATA0 PID - 28 - 28 - write-only - - - SetD1PID - 29 Set DATA1 PID - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DOEPINT - Device Endpoint Interrupt Register - 0x208 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - SetUp - SETUP Phase Done - 3 - 3 - read-write - - - OUTTknEPdis - OUT Token Received When Endpoint Disabled - 4 - 4 - read-write - - - StsPhseRcvd - Status Phase Received For Control Write - 5 - 5 - read-write - - - Back2BackSETup - Back-to-Back SETUP Packets Received - 6 - 6 - read-write - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - PktDrpSts - Packet Dropped Status - 11 - 11 - read-write - - - BbleErrIntrpt - BbleErr (Babble Error) interrupt - 12 - 12 - read-write - - - NAKIntrpt - NAK interrupt - 13 - 13 - read-write - - - NYETIntrpt - NYET interrupt - 14 - 14 - read-write - - - - - DOEPTSIZ_ISO - Device Endpoint Transfer Size Register [ISO] - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - RxDPID - Received Data PID - 29 - 30 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA2 - 0b01 - - - value3 - DATA1 - 0b10 - - - value4 - MDATA - 0b11 - - - - - - - DOEPTSIZ_CONTROL - Device Endpoint Transfer Size Register [CONT] - DOEPTSIZ_ISO - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - SUPCnt - SETUP Packet Count - 29 - 30 - read-write - - - value1 - 1 packet - 0b01 - - - value2 - 2 packets - 0b10 - - - value3 - 3 packets - 0b11 - - - - - - - DOEPDMA - Device Endpoint DMA Address Register - 0x214 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DOEPDMAB - Device Endpoint DMA Buffer Address Register - 0x21C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - - - USB0_EP2 - Universal Serial Bus - USB - 0x50040940 - - 0x0 - 0x0400 - registers - - - - USB0_EP3 - Universal Serial Bus - USB - 0x50040960 - - 0x0 - 0x0400 - registers - - - - USB0_EP4 - Universal Serial Bus - USB - 0x50040980 - - 0x0 - 0x0400 - registers - - - - USB0_EP5 - Universal Serial Bus - USB - 0x500409A0 - - 0x0 - 0x0400 - registers - - - - USB0_EP6 - Universal Serial Bus - USB - 0x500409C0 - - 0x0 - 0x0400 - registers - - - - USB0_CH0 - Universal Serial Bus - USB - USB_CH - 0x50040500 - - 0x0 - 0x20 - registers - - - - HCCHAR - Host Channel Characteristics Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - EPNum - Endpoint Number - 11 - 14 - read-write - - - EPDir - Endpoint Direction - 15 - 15 - read-write - - - value1 - OUT - 0b0 - - - value2 - IN - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - MC_EC - Multi Count / Error Count - 20 - 21 - read-write - - - value1 - Reserved. This field yields undefined results. - 0b00 - - - value2 - 1 transaction - 0b01 - - - value3 - 2 transactions to be issued for this endpoint per frame - 0b10 - - - value4 - 3 transactions to be issued for this endpoint per frame - 0b11 - - - - - DevAddr - Device Address - 22 - 28 - read-write - - - OddFrm - Odd Frame - 29 - 29 - read-write - - - value1 - Even frame - 0b0 - - - value2 - Odd frame - 0b1 - - - - - ChDis - Channel Disable - 30 - 30 - read-write - - - ChEna - Channel Enable - 31 - 31 - read-write - - - value1 - Scatter/Gather mode enabled: Indicates that the descriptor structure is not yet ready. Scatter/Gather mode disabled: Channel disabled - 0b0 - - - value2 - Scatter/Gather mode enabled: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor. Scatter/Gather mode disabled: Channel enabled - 0b1 - - - - - - - HCINT - Host Channel Interrupt Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferCompl - Transfer Completed - 0 - 0 - read-write - - - ChHltd - Channel Halted - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - STALL - STALL Response Received Interrupt - 3 - 3 - read-write - - - NAK - NAK Response Received Interrupt - 4 - 4 - read-write - - - ACK - ACK Response Received/Transmitted Interrupt - 5 - 5 - read-write - - - NYET - NYET Response Received Interrupt - 6 - 6 - read-write - - - XactErr - Transaction Error - 7 - 7 - read-write - - - BblErr - Babble Error - 8 - 8 - read-write - - - FrmOvrun - Frame Overrun - 9 - 9 - read-write - - - DataTglErr - Data Toggle Error - 10 - 10 - read-write - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 11 - 11 - read-write - - - XCS_XACT_ERR - Excessive Transaction Error - 12 - 12 - read-write - - - DESC_LST_ROLLIntr - Descriptor rollover interrupt - 13 - 13 - read-write - - - - - HCINTMSK - Host Channel Interrupt Mask Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - XferComplMsk - Transfer Completed Mask - 0 - 0 - read-write - - - ChHltdMsk - Channel Halted Mask - 1 - 1 - read-write - - - AHBErrMsk - AHB Error Mask - 2 - 2 - read-write - - - StallMsk - STALL Response Received Interrupt Mask - 3 - 3 - read-write - - - NakMsk - NAK Response Received Interrupt Mask - 4 - 4 - read-write - - - AckMsk - ACK Response Received/Transmitted Interrupt Mask - 5 - 5 - read-write - - - NyetMsk - NYET Response Received Interrupt Mask - 6 - 6 - read-write - - - XactErrMsk - Transaction Error Mask - 7 - 7 - read-write - - - BblErrMsk - Babble Error Mask - 8 - 8 - read-write - - - FrmOvrunMsk - Frame Overrun Mask - 9 - 9 - read-write - - - DataTglErrMsk - Data Toggle Error Mask - 10 - 10 - read-write - - - BNAIntrMsk - BNA (Buffer Not Available) Interrupt mask register - 11 - 11 - read-write - - - DESC_LST_ROLLIntrMsk - Descriptor rollover interrupt Mask register - 13 - 13 - read-write - - - - - HCTSIZ_BUFFERMODE - Host Channel Transfer Size Register [BUFFERMODE] - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - Pid - PID - 29 - 30 - read-write - - - value1 - DATA0 - 0b00 - - - value2 - DATA2 - 0b01 - - - value3 - DATA1 - 0b10 - - - value4 - MDATA (non-control)/SETUP (control) - 0b11 - - - - - - - HCTSIZ_SCATGATHER - Host Channel Transfer Size Register [SCATGATHER] - HCTSIZ_BUFFERMODE - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCHED_INFO - Schedule information - 0 - 7 - read-write - - - NTD - Number of Transfer Descriptors - 8 - 15 - read-write - - - Pid - PID - 29 - 30 - read-write - - - value1 - DATA0 - 0b00 - - - value2 - DATA2 - 0b01 - - - value3 - DATA1 - 0b10 - - - value4 - MDATA (non-control) - 0b11 - - - - - - - HCDMA_BUFFERMODE - Host Channel DMA Address Register [BUFFERMODE] - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - HCDMA_SCATGATHER - Host Channel DMA Address Register [SCATGATHER] - HCDMA_BUFFERMODE - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CTD - Current Transfer Desc: - 3 - 8 - read-write - - - value1 - 1 descriptor - 0 - - - value2 - 64 descriptors - 63 - - - - - DMAAddr - DMA Address - 9 - 31 - read-write - - - - - HCDMAB - Host Channel DMA Buffer Address Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - Buffer_Address - Buffer Address - 0 - 31 - read-only - - - - - - - USB0_CH1 - Universal Serial Bus - USB - 0x50040520 - - 0x0 - 0x20 - registers - - - - USB0_CH2 - Universal Serial Bus - USB - 0x50040540 - - 0x0 - 0x20 - registers - - - - USB0_CH3 - Universal Serial Bus - USB - 0x50040560 - - 0x0 - 0x20 - registers - - - - USB0_CH4 - Universal Serial Bus - USB - 0x50040580 - - 0x0 - 0x20 - registers - - - - USB0_CH5 - Universal Serial Bus - USB - 0x500405A0 - - 0x0 - 0x20 - registers - - - - USB0_CH6 - Universal Serial Bus - USB - 0x500405C0 - - 0x0 - 0x20 - registers - - - - USB0_CH7 - Universal Serial Bus - USB - 0x500405E0 - - 0x0 - 0x20 - registers - - - - USB0_CH8 - Universal Serial Bus - USB - 0x50040600 - - 0x0 - 0x20 - registers - - - - USB0_CH9 - Universal Serial Bus - USB - 0x50040620 - - 0x0 - 0x20 - registers - - - - USB0_CH10 - Universal Serial Bus - USB - 0x50040640 - - 0x0 - 0x20 - registers - - - - USB0_CH11 - Universal Serial Bus - USB - 0x50040660 - - 0x0 - 0x20 - registers - - - - USB0_CH12 - Universal Serial Bus - USB - 0x50040680 - - 0x0 - 0x20 - registers - - - - USB0_CH13 - Universal Serial Bus - USB - 0x500406A0 - - 0x0 - 0x20 - registers - - - - USIC0 - Universal Serial Interface Controller 0 - USIC - USIC - 0x40030008 - - 0 - 4 - registers - - - - ID - Module Identification Register - 0 - 32 - 0x00AAC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - - - USIC1 - Universal Serial Interface Controller 1 - USIC - 0x48020008 - - 0 - 4 - registers - - - - USIC2 - Universal Serial Interface Controller 2 - USIC - 0x48024008 - - 0 - 4 - registers - - - - USIC0_CH0 - Universal Serial Interface Controller 0 - USIC - USIC_CH - 0x40030000 - - 0x0 - 0x0200 - registers - - - - CCFG - Channel Configuration Register - 0x004 - 32 - 0x000000CF - 0xFFFFFFFF - - - SSC - SSC Protocol Available - 0 - 0 - read-only - - - value1 - The SSC protocol is not available. - 0b0 - - - value2 - The SSC protocol is available. - 0b1 - - - - - ASC - ASC Protocol Available - 1 - 1 - read-only - - - value1 - The ASC protocol is not available. - 0b0 - - - value2 - The ASC protocol is available. - 0b1 - - - - - IIC - IIC Protocol Available - 2 - 2 - read-only - - - value1 - The IIC protocol is not available. - 0b0 - - - value2 - The IIC protocol is available. - 0b1 - - - - - IIS - IIS Protocol Available - 3 - 3 - read-only - - - value1 - The IIS protocol is not available. - 0b0 - - - value2 - The IIS protocol is available. - 0b1 - - - - - RB - Receive FIFO Buffer Available - 6 - 6 - read-only - - - value1 - A receive FIFO buffer is not available. - 0b0 - - - value2 - A receive FIFO buffer is available. - 0b1 - - - - - TB - Transmit FIFO Buffer Available - 7 - 7 - read-only - - - value1 - A transmit FIFO buffer is not available. - 0b0 - - - value2 - A transmit FIFO buffer is available. - 0b1 - - - - - - - KSCFG - Kernel State Configuration Register - 0x00C - 32 - 0x00000000 - 0xFFFFFFFF - - - MODEN - Module Enable - 0 - 0 - read-write - - - value1 - The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). - 0b0 - - - value2 - The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other GPDMA registers. - 0b1 - - - - - BPMODEN - Bit Protection for MODEN - 1 - 1 - write-only - - - value1 - MODEN is not changed. - 0b0 - - - value2 - MODEN is updated with the written value. - 0b1 - - - - - NOMCFG - Normal Operation Mode Configuration - 4 - 5 - read-write - - - value1 - Run mode 0 is selected. - 0b00 - - - value2 - Run mode 1 is selected. - 0b01 - - - value3 - Stop mode 0 is selected. - 0b10 - - - value4 - Stop mode 1 is selected. - 0b11 - - - - - BPNOM - Bit Protection for NOMCFG - 7 - 7 - write-only - - - value1 - NOMCFG is not changed. - 0b0 - - - value2 - NOMCFG is updated with the written value. - 0b1 - - - - - SUMCFG - Suspend Mode Configuration - 8 - 9 - read-write - - - BPSUM - Bit Protection for SUMCFG - 11 - 11 - write-only - - - value1 - SUMCFG is not changed. - 0b0 - - - value2 - SUMCFG is updated with the written value. - 0b1 - - - - - - - FDR - Fractional Divider Register - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - STEP - Step Value - 0 - 9 - read-write - - - DM - Divider Mode - 14 - 15 - read-write - - - value1 - The divider is switched off, fFD = 0. - 0b00 - - - value2 - Normal divider mode selected. - 0b01 - - - value3 - Fractional divider mode selected. - 0b10 - - - value4 - The divider is switched off, fFD = 0. - 0b11 - - - - - RESULT - Result Value - 16 - 25 - read-only - - - - - BRG - Baud Rate Generator Register - 0x014 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLKSEL - Clock Selection - 0 - 1 - read-write - - - value1 - The fractional divider frequency fFD is selected. - 0b00 - - - value2 - Reserved, no action - 0b01 - - - value3 - The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. - 0b10 - - - value4 - Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. - 0b11 - - - - - TMEN - Timing Measurement Enable - 3 - 3 - read-write - - - value1 - Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored. - 0b0 - - - value2 - Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. - 0b1 - - - - - PPPEN - Enable 2:1 Divider for fPPP - 4 - 4 - read-write - - - value1 - The 2:1 divider for fPPP is disabled. fPPP = fPIN - 0b0 - - - value2 - The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. - 0b1 - - - - - CTQSEL - Input Selection for CTQ - 6 - 7 - read-write - - - value1 - fCTQIN = fPDIV - 0b00 - - - value2 - fCTQIN = fPPP - 0b01 - - - value3 - fCTQIN = fSCLK - 0b10 - - - value4 - fCTQIN = fMCLK - 0b11 - - - - - PCTQ - Pre-Divider for Time Quanta Counter - 8 - 9 - read-write - - - DCTQ - Denominator for Time Quanta Counter - 10 - 14 - read-write - - - PDIV - Divider Mode: Divider Factor to Generate fPDIV - 16 - 25 - read-write - - - SCLKOSEL - Shift Clock Output Select - 28 - 28 - read-write - - - value1 - SCLK from the baud rate generator is selected as the SCLKOUT input source. - 0b0 - - - value2 - The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. - 0b1 - - - - - MCLKCFG - Master Clock Configuration - 29 - 29 - read-write - - - value1 - The passive level is 0. - 0b0 - - - value2 - The passive level is 1. - 0b1 - - - - - SCLKCFG - Shift Clock Output Configuration - 30 - 31 - read-write - - - value1 - The passive level is 0 and the delay is disabled. - 0b00 - - - value2 - The passive level is 1 and the delay is disabled. - 0b01 - - - value3 - The passive level is 0 and the delay is enabled. - 0b10 - - - value4 - The passive level is 1 and the delay is enabled. - 0b11 - - - - - - - INPR - Interrupt Node Pointer Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSINP - Transmit Shift Interrupt Node Pointer - 0 - 2 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - TBINP - Transmit Buffer Interrupt Node Pointer - 4 - 6 - read-write - - - RINP - Receive Interrupt Node Pointer - 8 - 10 - read-write - - - AINP - Alternative Receive Interrupt Node Pointer - 12 - 14 - read-write - - - PINP - Protocol Interrupt Node Pointer - 16 - 18 - read-write - - - - - DX0CR - Input Control Register 0 - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX1CR - Input Control Register 1 - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DX1A is selected. - 0b000 - - - value2 - The data input DX1B is selected. - 0b001 - - - value3 - The data input DX1C is selected. - 0b010 - - - value4 - The data input DX1D is selected. - 0b011 - - - value5 - The data input DX1E is selected. - 0b100 - - - value6 - The data input DX1F is selected. - 0b101 - - - value7 - The data input DX1G is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - DCEN - Delay Compensation Enable - 3 - 3 - read-write - - - value1 - The receive shift clock is dependent on INSW selection. - 0b0 - - - value2 - The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. - 0b1 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DX1T. - 0b01 - - - value3 - A falling edge activates DX1T. - 0b10 - - - value4 - Both edges activate DX1T. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DX1S is 0. - 0b0 - - - value2 - The current value of DX1S is 1. - 0b1 - - - - - - - DX2CR - Input Control Register 2 - 0x024 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX3CR - Input Control Register 3 - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX4CR - Input Control Register 4 - 0x02C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX5CR - Input Control Register 5 - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - SCTR - Shift Control Register - 0x034 - 32 - 0x00000000 - 0xFFFFFFFF - - - SDIR - Shift Direction - 0 - 0 - read-write - - - value1 - Shift LSB first. The first data bit of a data word is located at bit position 0. - 0b0 - - - value2 - Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE. - 0b1 - - - - - PDL - Passive Data Level - 1 - 1 - read-write - - - value1 - The passive data level is 0. - 0b0 - - - value2 - The passive data level is 1. - 0b1 - - - - - DSM - Data Shift Mode - 2 - 3 - read-write - - - value1 - Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0. - 0b00 - - - value2 - Reserved. - 0b01 - - - value3 - Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively. - 0b10 - - - value4 - Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively. - 0b11 - - - - - HPCDIR - Port Control Direction - 4 - 4 - read-write - - - value1 - The pin(s) with hardware pin control enabled are selected to be in input mode. - 0b0 - - - value2 - The pin(s) with hardware pin control enabled are selected to be in output mode. - 0b1 - - - - - DOCFG - Data Output Configuration - 6 - 7 - read-write - - - value1 - DOUTx = shift data value - 0b00 - - - value2 - DOUTx = inverted shift data value - 0b01 - - - - - TRM - Transmission Mode - 8 - 9 - read-write - - - value1 - The shift control signal is considered as inactive and data frame transfers are not possible. - 0b00 - - - value2 - The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. - 0b01 - - - value3 - The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. - 0b10 - - - value4 - The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. - 0b11 - - - - - FLE - Frame Length - 16 - 21 - read-write - - - WLE - Word Length - 24 - 27 - read-write - - - value1 - The data word contains 1 data bit located at bit position 0. - 0x0 - - - value2 - The data word contains 2 data bits located at bit positions [1:0]. - 0x1 - - - value3 - The data word contains 15 data bits located at bit positions [14:0]. - 0xE - - - value4 - The data word contains 16 data bits located at bit positions [15:0]. - 0xF - - - - - - - TCSR - Transmit Control/Status Register - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLEMD - WLE Mode - 0 - 0 - read-write - - - value1 - The automatic update of SCTR.WLE and TCSR.EOF is disabled. - 0b0 - - - value2 - The automatic update of SCTR.WLE and TCSR.EOF is enabled. - 0b1 - - - - - SELMD - Select Mode - 1 - 1 - read-write - - - value1 - The automatic update of PCR.CTR[23:16] is disabled. - 0b0 - - - value2 - The automatic update of PCR.CTR[23:16] is disabled. - 0b1 - - - - - FLEMD - FLE Mode - 2 - 2 - read-write - - - value1 - The automatic update of FLE is disabled. - 0b0 - - - value2 - The automatic update of FLE is enabled. - 0b1 - - - - - WAMD - WA Mode - 3 - 3 - read-write - - - value1 - The automatic update of bit WA is disabled. - 0b0 - - - value2 - The automatic update of bit WA is enabled. - 0b1 - - - - - HPCMD - Hardware Port Control Mode - 4 - 4 - read-write - - - value1 - The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled. - 0b0 - - - value2 - The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled. - 0b1 - - - - - SOF - Start Of Frame - 5 - 5 - read-write - - - value1 - The data word in TBUF is not considered as first word of a frame. - 0b0 - - - value2 - The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). - 0b1 - - - - - EOF - End Of Frame - 6 - 6 - read-write - - - value1 - The data word in TBUF is not considered as last word of an SSC frame. - 0b0 - - - value2 - The data word in TBUF is considered as last word of an SSC frame. - 0b1 - - - - - TDV - Transmit Data Valid - 7 - 7 - read-only - - - value1 - The data word in TBUF is not valid for transmission. - 0b0 - - - value2 - The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. - 0b1 - - - - - TDSSM - TBUF Data Single Shot Mode - 8 - 8 - read-write - - - value1 - The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. - 0b0 - - - value2 - The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. - 0b1 - - - - - TDEN - TBUF Data Enable - 10 - 11 - read-write - - - value1 - A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. - 0b00 - - - value2 - A transmission of the data word in TBUF can be started if TDV = 1. - 0b01 - - - value3 - A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. - 0b10 - - - value4 - A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. - 0b11 - - - - - TDVTR - TBUF Data Valid Trigger - 12 - 12 - read-write - - - value1 - Bit TCSR.TE is permanently set. - 0b0 - - - value2 - Bit TCSR.TE is set if DX2T becomes active while TDV = 1. - 0b1 - - - - - WA - Word Address - 13 - 13 - read-write - - - value1 - The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA). - 0b0 - - - value2 - The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA). - 0b1 - - - - - TSOF - Transmitted Start Of Frame - 24 - 24 - read-only - - - value1 - The latest data word transmission has not been started for the first word of a data frame. - 0b0 - - - value2 - The latest data word transmission has been started for the first word of a data frame. - 0b1 - - - - - TV - Transmission Valid - 26 - 26 - read-only - - - value1 - The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started. - 0b0 - - - value2 - The latest start of a data word transmission has taken place with valid data from TBUF. - 0b1 - - - - - TVC - Transmission Valid Cumulated - 27 - 27 - read-only - - - value1 - Since TVC has been set, at least one data buffer underflow condition has occurred. - 0b0 - - - value2 - Since TVC has been set, no data buffer underflow condition has occurred. - 0b1 - - - - - TE - Trigger Event - 28 - 28 - read-only - - - value1 - The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started. - 0b0 - - - value2 - The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can be started. - 0b1 - - - - - - - PCR - Protocol Control Register - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - CTR0 - Protocol Control Bit 0 - 0 - 0 - read-write - - - CTR1 - Protocol Control Bit 1 - 1 - 1 - read-write - - - CTR2 - Protocol Control Bit 2 - 2 - 2 - read-write - - - CTR3 - Protocol Control Bit 3 - 3 - 3 - read-write - - - CTR4 - Protocol Control Bit 4 - 4 - 4 - read-write - - - CTR5 - Protocol Control Bit 5 - 5 - 5 - read-write - - - CTR6 - Protocol Control Bit 6 - 6 - 6 - read-write - - - CTR7 - Protocol Control Bit 7 - 7 - 7 - read-write - - - CTR8 - Protocol Control Bit 8 - 8 - 8 - read-write - - - CTR9 - Protocol Control Bit 9 - 9 - 9 - read-write - - - CTR10 - Protocol Control Bit 10 - 10 - 10 - read-write - - - CTR11 - Protocol Control Bit 11 - 11 - 11 - read-write - - - CTR12 - Protocol Control Bit 12 - 12 - 12 - read-write - - - CTR13 - Protocol Control Bit 13 - 13 - 13 - read-write - - - CTR14 - Protocol Control Bit 14 - 14 - 14 - read-write - - - CTR15 - Protocol Control Bit 15 - 15 - 15 - read-write - - - CTR16 - Protocol Control Bit 16 - 16 - 16 - read-write - - - CTR17 - Protocol Control Bit 17 - 17 - 17 - read-write - - - CTR18 - Protocol Control Bit 18 - 18 - 18 - read-write - - - CTR19 - Protocol Control Bit 19 - 19 - 19 - read-write - - - CTR20 - Protocol Control Bit 20 - 20 - 20 - read-write - - - CTR21 - Protocol Control Bit 21 - 21 - 21 - read-write - - - CTR22 - Protocol Control Bit 22 - 22 - 22 - read-write - - - CTR23 - Protocol Control Bit 23 - 23 - 23 - read-write - - - CTR24 - Protocol Control Bit 24 - 24 - 24 - read-write - - - CTR25 - Protocol Control Bit 25 - 25 - 25 - read-write - - - CTR26 - Protocol Control Bit 26 - 26 - 26 - read-write - - - CTR27 - Protocol Control Bit 27 - 27 - 27 - read-write - - - CTR28 - Protocol Control Bit 28 - 28 - 28 - read-write - - - CTR29 - Protocol Control Bit 29 - 29 - 29 - read-write - - - CTR30 - Protocol Control Bit 30 - 30 - 30 - read-write - - - CTR31 - Protocol Control Bit 31 - 31 - 31 - read-write - - - - - PCR_ASCMode - Protocol Control Register [ASC Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - SMD - Sample Mode - 0 - 0 - read-write - - - value1 - Only one sample is taken per bit time. The current input value is sampled. - 0b0 - - - value2 - Three samples are taken per bit time and a majority decision is made. - 0b1 - - - - - STPB - Stop Bits - 1 - 1 - read-write - - - value1 - The number of stop bits is 1. - 0b0 - - - value2 - The number of stop bits is 2. - 0b1 - - - - - IDM - Idle Detection Mode - 2 - 2 - read-write - - - value1 - The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. - 0b0 - - - value2 - The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). - 0b1 - - - - - SBIEN - Synchronization Break Interrupt Enable - 3 - 3 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - CDEN - Collision Detection Enable - 4 - 4 - read-write - - - value1 - The collision detection is disabled. - 0b0 - - - value2 - If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software. - 0b1 - - - - - RNIEN - Receiver Noise Detection Interrupt Enable - 5 - 5 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - FEIEN - Format Error Interrupt Enable - 6 - 6 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - FFIEN - Frame Finished Interrupt Enable - 7 - 7 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - SP - Sample Point - 8 - 12 - read-write - - - PL - Pulse Length - 13 - 15 - read-write - - - value1 - The pulse length is equal to the bit length (no shortened 0). - 0b000 - - - value2 - The pulse length of a 0 bit is 2 time quanta. - 0b001 - - - value3 - The pulse length of a 0 bit is 3 time quanta. - 0b010 - - - value4 - The pulse length of a 0 bit is 8 time quanta. - 0b111 - - - - - RSTEN - Receiver Status Enable - 16 - 16 - read-write - - - value1 - Flag PSR[9] is not modified depending on the receiver status. - 0b0 - - - value2 - Flag PSR[9] is set during the complete reception of a frame. - 0b1 - - - - - TSTEN - Transmitter Status Enable - 17 - 17 - read-write - - - value1 - Flag PSR[9] is not modified depending on the transmitter status. - 0b0 - - - value2 - Flag PSR[9] is set during the complete transmission of a frame. - 0b1 - - - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and the MCLK signal is 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - PCR_SSCMode - Protocol Control Register [SSC Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - MSLSEN - MSLS Enable - 0 - 0 - read-write - - - value1 - The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. - 0b0 - - - value2 - The MSLS generation is enabled. This is the setting for SSC master mode. - 0b1 - - - - - SELCTR - Select Control - 1 - 1 - read-write - - - value1 - The coded select mode is enabled. - 0b0 - - - value2 - The direct select mode is enabled. - 0b1 - - - - - SELINV - Select Inversion - 2 - 2 - read-write - - - value1 - The SELO outputs have the same polarity as the MSLS signal (active high). - 0b0 - - - value2 - The SELO outputs have the inverted polarity to the MSLS signal (active low). - 0b1 - - - - - FEM - Frame End Mode - 3 - 3 - read-write - - - value1 - The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). - 0b0 - - - value2 - The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. - 0b1 - - - - - CTQSEL1 - Input Frequency Selection - 4 - 5 - read-write - - - value1 - fCTQIN = fPDIV - 0b00 - - - value2 - fCTQIN = fPPP - 0b01 - - - value3 - fCTQIN = fSCLK - 0b10 - - - value4 - fCTQIN = fMCLK - 0b11 - - - - - PCTQ1 - Divider Factor PCTQ1 for Tiw and Tnf - 6 - 7 - read-write - - - DCTQ1 - Divider Factor DCTQ1 for Tiw and Tnf - 8 - 12 - read-write - - - PARIEN - Parity Error Interrupt Enable - 13 - 13 - read-write - - - value1 - A protocol interrupt is not generated with the detection of a parity error. - 0b0 - - - value2 - A protocol interrupt is generated with the detection of a parity error. - 0b1 - - - - - MSLSIEN - MSLS Interrupt Enable - 14 - 14 - read-write - - - value1 - A protocol interrupt is not generated if a change of signal MSLS is detected. - 0b0 - - - value2 - A protocol interrupt is generated if a change of signal MSLS is detected. - 0b1 - - - - - DX2TIEN - DX2T Interrupt Enable - 15 - 15 - read-write - - - value1 - A protocol interrupt is not generated if DX2T is activated. - 0b0 - - - value2 - A protocol interrupt is generated if DX2T is activated. - 0b1 - - - - - SELO - Select Output - 16 - 23 - read-write - - - value1 - The corresponding SELOx line cannot be activated. - 0b0 - - - value2 - The corresponding SELOx line can be activated (according to the mode selected by SELCTR). - 0b1 - - - - - TIWEN - Enable Inter-Word Delay Tiw - 24 - 24 - read-write - - - value1 - No delay between data words of the same frame. - 0b0 - - - value2 - The inter-word delay Tiw is enabled and introduced between data words of the same frame. - 0b1 - - - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and output MCLK = 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - PCR_IICMode - Protocol Control Register [IIC Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - SLAD - Slave Address - 0 - 15 - read-write - - - ACK00 - Acknowledge 00H - 16 - 16 - read-write - - - value1 - The slave device is not sensitive to this address. - 0b0 - - - value2 - The slave device is sensitive to this address. - 0b1 - - - - - STIM - Symbol Timing - 17 - 17 - read-write - - - value1 - A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud). - 0b0 - - - value2 - A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud). - 0b1 - - - - - SCRIEN - Start Condition Received Interrupt Enable - 18 - 18 - read-write - - - value1 - The start condition interrupt is disabled. - 0b0 - - - value2 - The start condition interrupt is enabled. - 0b1 - - - - - RSCRIEN - Repeated Start Condition Received Interrupt Enable - 19 - 19 - read-write - - - value1 - The repeated start condition interrupt is disabled. - 0b0 - - - value2 - The repeated start condition interrupt is enabled. - 0b1 - - - - - PCRIEN - Stop Condition Received Interrupt Enable - 20 - 20 - read-write - - - value1 - The stop condition interrupt is disabled. - 0b0 - - - value2 - The stop condition interrupt is enabled. - 0b1 - - - - - NACKIEN - Non-Acknowledge Interrupt Enable - 21 - 21 - read-write - - - value1 - The non-acknowledge interrupt is disabled. - 0b0 - - - value2 - The non-acknowledge interrupt is enabled. - 0b1 - - - - - ARLIEN - Arbitration Lost Interrupt Enable - 22 - 22 - read-write - - - value1 - The arbitration lost interrupt is disabled. - 0b0 - - - value2 - The arbitration lost interrupt is enabled. - 0b1 - - - - - SRRIEN - Slave Read Request Interrupt Enable - 23 - 23 - read-write - - - value1 - The slave read request interrupt is disabled. - 0b0 - - - value2 - The slave read request interrupt is enabled. - 0b1 - - - - - ERRIEN - Error Interrupt Enable - 24 - 24 - read-write - - - value1 - The error interrupt is disabled. - 0b0 - - - value2 - The error interrupt is enabled. - 0b1 - - - - - SACKDIS - Slave Acknowledge Disable - 25 - 25 - read-write - - - value1 - The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received). - 0b0 - - - value2 - The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped). - 0b1 - - - - - HDEL - Hardware Delay - 26 - 29 - read-write - - - ACKIEN - Acknowledge Interrupt Enable - 30 - 30 - read-write - - - value1 - The acknowledge interrupt is disabled. - 0b0 - - - value2 - The acknowledge interrupt is enabled. - 0b1 - - - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and MCLK is 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - PCR_IISMode - Protocol Control Register [IIS Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - WAGEN - WA Generation Enable - 0 - 0 - read-write - - - value1 - The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. - 0b0 - - - value2 - The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. - 0b1 - - - - - DTEN - Data Transfers Enable - 1 - 1 - read-write - - - value1 - The changes of the WA input signal are ignored and no transfers take place. - 0b0 - - - value2 - Transfers are enabled. - 0b1 - - - - - SELINV - Select Inversion - 2 - 2 - read-write - - - value1 - The SELOx outputs have the same polarity as the WA signal. - 0b0 - - - value2 - The SELOx outputs have the inverted polarity to the WA signal. - 0b1 - - - - - WAFEIEN - WA Falling Edge Interrupt Enable - 4 - 4 - read-write - - - value1 - A protocol interrupt is not activated if a falling edge of WA is generated. - 0b0 - - - value2 - A protocol interrupt is activated if a falling edge of WA is generated. - 0b1 - - - - - WAREIEN - WA Rising Edge Interrupt Enable - 5 - 5 - read-write - - - value1 - A protocol interrupt is not activated if a rising edge of WA is generated. - 0b0 - - - value2 - A protocol interrupt is activated if a rising edge of WA is generated. - 0b1 - - - - - ENDIEN - END Interrupt Enable - 6 - 6 - read-write - - - value1 - A protocol interrupt is not activated. - 0b0 - - - value2 - A protocol interrupt is activated. - 0b1 - - - - - DX2TIEN - DX2T Interrupt Enable - 15 - 15 - read-write - - - value1 - A protocol interrupt is not generated if DX2T is active. - 0b0 - - - value2 - A protocol interrupt is generated if DX2T is active. - 0b1 - - - - - TDEL - Transfer Delay - 16 - 21 - read-write - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and MCLK is 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - CCR - Channel Control Register - 0x040 - 32 - 0x00000000 - 0xFFFFFFFF - - - MODE - Operating Mode - 0 - 3 - read-write - - - value1 - The USIC channel is disabled. All protocol-related state machines are set to an idle state. - 0x0 - - - value2 - The SSC (SPI) protocol is selected. - 0x1 - - - value3 - The ASC (SCI, UART) protocol is selected. - 0x2 - - - value4 - The IIS protocol is selected. - 0x3 - - - value5 - The IIC protocol is selected. - 0x4 - - - - - HPCEN - Hardware Port Control Enable - 6 - 7 - read-write - - - value1 - The hardware port control is disabled. - 0b00 - - - value2 - The hardware port control is enabled for DX0 and DOUT0. - 0b01 - - - value3 - The hardware port control is enabled for DX3, DX0 and DOUT[1:0]. - 0b10 - - - value4 - The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0]. - 0b11 - - - - - PM - Parity Mode - 8 - 9 - read-write - - - value1 - The parity generation is disabled. - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). - 0b10 - - - value4 - Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). - 0b11 - - - - - RSIEN - Receiver Start Interrupt Enable - 10 - 10 - read-write - - - value1 - The receiver start interrupt is disabled. - 0b0 - - - value2 - The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated. - 0b1 - - - - - DLIEN - Data Lost Interrupt Enable - 11 - 11 - read-write - - - value1 - The data lost interrupt is disabled. - 0b0 - - - value2 - The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated. - 0b1 - - - - - TSIEN - Transmit Shift Interrupt Enable - 12 - 12 - read-write - - - value1 - The transmit shift interrupt is disabled. - 0b0 - - - value2 - The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated. - 0b1 - - - - - TBIEN - Transmit Buffer Interrupt Enable - 13 - 13 - read-write - - - value1 - The transmit buffer interrupt is disabled. - 0b0 - - - value2 - The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated. - 0b1 - - - - - RIEN - Receive Interrupt Enable - 14 - 14 - read-write - - - value1 - The receive interrupt is disabled. - 0b0 - - - value2 - The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated. - 0b1 - - - - - AIEN - Alternative Receive Interrupt Enable - 15 - 15 - read-write - - - value1 - The alternative receive interrupt is disabled. - 0b0 - - - value2 - The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated. - 0b1 - - - - - BRGIEN - Baud Rate Generator Interrupt Enable - 16 - 16 - read-write - - - value1 - The baud rate generator interrupt is disabled. - 0b0 - - - value2 - The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated. - 0b1 - - - - - - - CMTR - Capture Mode Timer Register - 0x044 - 32 - 0x00000000 - 0xFFFFFFFF - - - CTV - Captured Timer Value - 0 - 9 - read-write - - - - - PSR - Protocol Status Register - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - ST0 - Protocol Status Flag 0 - 0 - 0 - read-write - - - ST1 - Protocol Status Flag 1 - 1 - 1 - read-write - - - ST2 - Protocol Status Flag 2 - 2 - 2 - read-write - - - ST3 - Protocol Status Flag 3 - 3 - 3 - read-write - - - ST4 - Protocol Status Flag 4 - 4 - 4 - read-write - - - ST5 - Protocol Status Flag 5 - 5 - 5 - read-write - - - ST6 - Protocol Status Flag 6 - 6 - 6 - read-write - - - ST7 - Protocol Status Flag 7 - 7 - 7 - read-write - - - ST8 - Protocol Status Flag 8 - 8 - 8 - read-write - - - ST9 - Protocol Status Flag 9 - 9 - 9 - read-write - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_ASCMode - Protocol Status Register [ASC Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXIDLE - Transmission Idle - 0 - 0 - read-write - - - value1 - The transmitter line has not yet been idle. - 0b0 - - - value2 - The transmitter line has been idle and frame transmission is possible. - 0b1 - - - - - RXIDLE - Reception Idle - 1 - 1 - read-write - - - value1 - The receiver line has not yet been idle. - 0b0 - - - value2 - The receiver line has been idle and frame reception is possible. - 0b1 - - - - - SBD - Synchronization Break Detected - 2 - 2 - read-write - - - value1 - A synchronization break has not yet been detected. - 0b0 - - - value2 - A synchronization break has been detected. - 0b1 - - - - - COL - Collision Detected - 3 - 3 - read-write - - - value1 - A collision has not yet been detected and frame transmission is possible. - 0b0 - - - value2 - A collision has been detected and frame transmission is not possible. - 0b1 - - - - - RNS - Receiver Noise Detected - 4 - 4 - read-write - - - value1 - Receiver noise has not been detected. - 0b0 - - - value2 - Receiver noise has been detected. - 0b1 - - - - - FER0 - Format Error in Stop Bit 0 - 5 - 5 - read-write - - - value1 - A format error 0 has not been detected. - 0b0 - - - value2 - A format error 0 has been detected. - 0b1 - - - - - FER1 - Format Error in Stop Bit 1 - 6 - 6 - read-write - - - value1 - A format error 1 has not been detected. - 0b0 - - - value2 - A format error 1 has been detected. - 0b1 - - - - - RFF - Receive Frame Finished - 7 - 7 - read-write - - - value1 - The received frame is not yet finished. - 0b0 - - - value2 - The received frame is finished. - 0b1 - - - - - TFF - Transmitter Frame Finished - 8 - 8 - read-write - - - value1 - The transmitter frame is not yet finished. - 0b0 - - - value2 - The transmitter frame is finished. - 0b1 - - - - - BUSY - Transfer Status BUSY - 9 - 9 - read-only - - - value1 - A data transfer does not take place. - 0b0 - - - value2 - A data transfer currently takes place. - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_SSCMode - Protocol Status Register [SSC Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - MSLS - MSLS Status - 0 - 0 - read-write - - - value1 - The internal signal MSLS is inactive (0). - 0b0 - - - value2 - The internal signal MSLS is active (1). - 0b1 - - - - - DX2S - DX2S Status - 1 - 1 - read-write - - - value1 - DX2S is 0. - 0b0 - - - value2 - DX2S is 1. - 0b1 - - - - - MSLSEV - MSLS Event Detected - 2 - 2 - read-write - - - value1 - The MSLS signal has not changed its state. - 0b0 - - - value2 - The MSLS signal has changed its state. - 0b1 - - - - - DX2TEV - DX2T Event Detected - 3 - 3 - read-write - - - value1 - The DX2T signal has not been activated. - 0b0 - - - value2 - The DX2T signal has been activated. - 0b1 - - - - - PARERR - Parity Error Event Detected - 4 - 4 - read-write - - - value1 - A parity error event has not been activated. - 0b0 - - - value2 - A parity error event has been activated. - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_IICMode - Protocol Status Register [IIC Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLSEL - Slave Select - 0 - 0 - read-write - - - value1 - The device is not selected as slave. - 0b0 - - - value2 - The device is selected as slave. - 0b1 - - - - - WTDF - Wrong TDF Code Found - 1 - 1 - read-write - - - value1 - A wrong TDF code has not been found. - 0b0 - - - value2 - A wrong TDF code has been found. - 0b1 - - - - - SCR - Start Condition Received - 2 - 2 - read-write - - - value1 - A start condition has not yet been detected. - 0b0 - - - value2 - A start condition has been detected. - 0b1 - - - - - RSCR - Repeated Start Condition Received - 3 - 3 - read-write - - - value1 - A repeated start condition has not yet been detected. - 0b0 - - - value2 - A repeated start condition has been detected. - 0b1 - - - - - PCR - Stop Condition Received - 4 - 4 - read-write - - - value1 - A stop condition has not yet been detected. - 0b0 - - - value2 - A stop condition has been detected. - 0b1 - - - - - NACK - Non-Acknowledge Received - 5 - 5 - read-write - - - value1 - A non-acknowledge has not been received. - 0b0 - - - value2 - A non-acknowledge has been received. - 0b1 - - - - - ARL - Arbitration Lost - 6 - 6 - read-write - - - value1 - An arbitration has not been lost. - 0b0 - - - value2 - An arbitration has been lost. - 0b1 - - - - - SRR - Slave Read Request - 7 - 7 - read-write - - - value1 - A slave read request has not been detected. - 0b0 - - - value2 - A slave read request has been detected. - 0b1 - - - - - ERR - Error - 8 - 8 - read-write - - - value1 - An IIC error has not been detected. - 0b0 - - - value2 - An IIC error has been detected. - 0b1 - - - - - ACK - Acknowledge Received - 9 - 9 - read-write - - - value1 - An acknowledge has not been received. - 0b0 - - - value2 - An acknowledge has been received. - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_IISMode - Protocol Status Register [IIS Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - WA - Word Address - 0 - 0 - read-write - - - value1 - WA has been sampled 0. - 0b0 - - - value2 - WA has been sampled 1. - 0b1 - - - - - DX2S - DX2S Status - 1 - 1 - read-write - - - value1 - DX2S is 0. - 0b0 - - - value2 - DX2S is 1. - 0b1 - - - - - DX2TEV - DX2T Event Detected - 3 - 3 - read-write - - - value1 - The DX2T signal has not been activated. - 0b0 - - - value2 - The DX2T signal has been activated. - 0b1 - - - - - WAFE - WA Falling Edge Event - 4 - 4 - read-write - - - value1 - A WA falling edge has not been generated. - 0b0 - - - value2 - A WA falling edge has been generated. - 0b1 - - - - - WARE - WA Rising Edge Event - 5 - 5 - read-write - - - value1 - A WA rising edge has not been generated. - 0b0 - - - value2 - A WA rising edge has been generated. - 0b1 - - - - - END - WA Generation End - 6 - 6 - read-write - - - value1 - The WA generation has not yet ended (if it is running and WAGEN has been cleared). - 0b0 - - - value2 - The WA generation has ended (if it has been running). - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSCR - Protocol Status Clear Register - 0x04C - 32 - 0x00000000 - 0xFFFFFFFF - - - CST0 - Clear Status Flag 0 in PSR - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST1 - Clear Status Flag 1 in PSR - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST2 - Clear Status Flag 2 in PSR - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST3 - Clear Status Flag 3 in PSR - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST4 - Clear Status Flag 4 in PSR - 4 - 4 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST5 - Clear Status Flag 5 in PSR - 5 - 5 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST6 - Clear Status Flag 6 in PSR - 6 - 6 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST7 - Clear Status Flag 7 in PSR - 7 - 7 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST8 - Clear Status Flag 8 in PSR - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST9 - Clear Status Flag 9 in PSR - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CRSIF - Clear Receiver Start Indication Flag - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.RSIF is cleared. - 0b1 - - - - - CDLIF - Clear Data Lost Indication Flag - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.DLIF is cleared. - 0b1 - - - - - CTSIF - Clear Transmit Shift Indication Flag - 12 - 12 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.TSIF is cleared. - 0b1 - - - - - CTBIF - Clear Transmit Buffer Indication Flag - 13 - 13 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.TBIF is cleared. - 0b1 - - - - - CRIF - Clear Receive Indication Flag - 14 - 14 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.RIF is cleared. - 0b1 - - - - - CAIF - Clear Alternative Receive Indication Flag - 15 - 15 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.AIF is cleared. - 0b1 - - - - - CBRGIF - Clear Baud Rate Generator Indication Flag - 16 - 16 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.BRGIF is cleared. - 0b1 - - - - - - - RBUFSR - Receiver Buffer Status Register - 0x050 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLEN - Received Data Word Length in RBUF or RBUFD - 0 - 3 - read-only - - - SOF - Start of Frame in RBUF or RBUFD - 6 - 6 - read-only - - - PAR - Protocol-Related Argument in RBUF or RBUFD - 8 - 8 - read-only - - - PERR - Protocol-related Error in RBUF or RBUFD - 9 - 9 - read-only - - - RDV0 - Receive Data Valid in RBUF or RBUFD - 13 - 13 - read-only - - - RDV1 - Receive Data Valid in RBUF or RBUFD - 14 - 14 - read-only - - - DS - Data Source of RBUF or RBUFD - 15 - 15 - read-only - - - - - RBUF - Receiver Buffer Register - 0x054 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Received Data - 0 - 15 - read-only - - - - - RBUFD - Receiver Buffer Register for Debugger - 0x058 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Data from Shift Register - 0 - 15 - read-only - - - - - RBUF0 - Receiver Buffer Register 0 - 0x05C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR0 - Data of Shift Registers 0[3:0] - 0 - 15 - read-only - - - - - RBUF1 - Receiver Buffer Register 1 - 0x060 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR1 - Data of Shift Registers 1[3:0] - 0 - 15 - read-only - - - - - RBUF01SR - Receiver Buffer 01 Status Register - 0x064 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLEN0 - Received Data Word Length in RBUF0 - 0 - 3 - read-only - - - SOF0 - Start of Frame in RBUF0 - 6 - 6 - read-only - - - value1 - The data in RBUF0 has not been the first data word of a data frame. - 0b0 - - - value2 - The data in RBUF0 has been the first data word of a data frame. - 0b1 - - - - - PAR0 - Protocol-Related Argument in RBUF0 - 8 - 8 - read-only - - - PERR0 - Protocol-related Error in RBUF0 - 9 - 9 - read-only - - - value1 - The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. - 0b0 - - - value2 - The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. - 0b1 - - - - - RDV00 - Receive Data Valid in RBUF0 - 13 - 13 - read-only - - - value1 - Register RBUF0 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF0 contains data that has not yet been read out. - 0b1 - - - - - RDV01 - Receive Data Valid in RBUF1 - 14 - 14 - read-only - - - value1 - Register RBUF1 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF1 contains data that has not yet been read out. - 0b1 - - - - - DS0 - Data Source - 15 - 15 - read-only - - - value1 - The register RBUF contains the data of RBUF0 (same for associated status information). - 0b0 - - - value2 - The register RBUF contains the data of RBUF1 (same for associated status information). - 0b1 - - - - - WLEN1 - Received Data Word Length in RBUF1 - 16 - 19 - read-only - - - SOF1 - Start of Frame in RBUF1 - 22 - 22 - read-only - - - value1 - The data in RBUF1 has not been the first data word of a data frame. - 0b0 - - - value2 - The data in RBUF1 has been the first data word of a data frame. - 0b1 - - - - - PAR1 - Protocol-Related Argument in RBUF1 - 24 - 24 - read-only - - - PERR1 - Protocol-related Error in RBUF1 - 25 - 25 - read-only - - - value1 - The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. - 0b0 - - - value2 - The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. - 0b1 - - - - - RDV10 - Receive Data Valid in RBUF0 - 29 - 29 - read-only - - - value1 - Register RBUF0 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF0 contains data that has not yet been read out. - 0b1 - - - - - RDV11 - Receive Data Valid in RBUF1 - 30 - 30 - read-only - - - value1 - Register RBUF1 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF1 contains data that has not yet been read out. - 0b1 - - - - - DS1 - Data Source - 31 - 31 - read-only - - - value1 - The register RBUF contains the data of RBUF0 (same for associated status information). - 0b0 - - - value2 - The register RBUF contains the data of RBUF1 (same for associated status information). - 0b1 - - - - - - - FMR - Flag Modification Register - 0x068 - 32 - 0x00000000 - 0xFFFFFFFF - - - MTDV - Modify Transmit Data Valid - 0 - 1 - write-only - - - value1 - No action. - 0b00 - - - value2 - Bit TDV is set, TE is unchanged. - 0b01 - - - value3 - Bits TDV and TE are cleared. - 0b10 - - - value4 - Reserved - 0b11 - - - - - ATVC - Activate Bit TVC - 4 - 4 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TCSR.TVC is set. - 0b1 - - - - - CRDV0 - Clear Bits RDV for RBUF0 - 14 - 14 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared. - 0b1 - - - - - CRDV1 - Clear Bit RDV for RBUF1 - 15 - 15 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared. - 0b1 - - - - - SIO0 - Set Interrupt Output SRx - 16 - 16 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO1 - Set Interrupt Output SRx - 17 - 17 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO2 - Set Interrupt Output SRx - 18 - 18 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO3 - Set Interrupt Output SRx - 19 - 19 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO4 - Set Interrupt Output SRx - 20 - 20 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO5 - Set Interrupt Output SRx - 21 - 21 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - - - 32 - 4 - TBUF[%s] - Transmit Buffer - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDATA - Transmit Data - 0 - 15 - read-write - - - - - BYP - Bypass Data Register - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - BDATA - Bypass Data - 0 - 15 - read-write - - - - - BYPCR - Bypass Control Register - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - BWLE - Bypass Word Length - 0 - 3 - read-write - - - BDSSM - Bypass Data Single Shot Mode - 8 - 8 - read-write - - - value1 - The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. - 0b0 - - - value2 - The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV. - 0b1 - - - - - BDEN - Bypass Data Enable - 10 - 11 - read-write - - - value1 - The transfer of bypass data is disabled. - 0b00 - - - value2 - The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. - 0b01 - - - value3 - Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. - 0b10 - - - value4 - Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. - 0b11 - - - - - BDVTR - Bypass Data Valid Trigger - 12 - 12 - read-write - - - value1 - Bit BDV is not influenced by DX2T. - 0b0 - - - value2 - Bit BDV is set if DX2T is active. - 0b1 - - - - - BPRIO - Bypass Priority - 13 - 13 - read-write - - - value1 - The transmit FIFO data has a higher priority than the bypass data. - 0b0 - - - value2 - The bypass data has a higher priority than the transmit FIFO data. - 0b1 - - - - - BDV - Bypass Data Valid - 15 - 15 - read-only - - - value1 - The bypass data is not valid. - 0b0 - - - value2 - The bypass data is valid. - 0b1 - - - - - BSELO - Bypass Select Outputs - 16 - 20 - read-write - - - BHPC - Bypass Hardware Port Control - 21 - 23 - read-write - - - - - TBCTR - Transmitter Buffer Control Register - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPTR - Data Pointer - 0 - 5 - write-only - - - LIMIT - Limit For Interrupt Generation - 8 - 13 - read-write - - - STBTM - Standard Transmit Buffer Trigger Mode - 14 - 14 - read-write - - - value1 - Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT. - 0b0 - - - value2 - Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE. - 0b1 - - - - - STBTEN - Standard Transmit Buffer Trigger Enable - 15 - 15 - read-write - - - value1 - The standard transmit buffer event trigger through bit TRBSR.STBT is disabled. - 0b0 - - - value2 - The standard transmit buffer event trigger through bit TRBSR.STBT is enabled. - 0b1 - - - - - STBINP - Standard Transmit Buffer Interrupt Node Pointer - 16 - 18 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - ATBINP - Alternative Transmit Buffer Interrupt Node Pointer - 19 - 21 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - SIZE - Buffer Size - 24 - 26 - read-write - - - value1 - The FIFO mechanism is disabled. The buffer does not accept any request for data. - 0b000 - - - value2 - The FIFO buffer contains 2 entries. - 0b001 - - - value3 - The FIFO buffer contains 4 entries. - 0b010 - - - value4 - The FIFO buffer contains 8 entries. - 0b011 - - - value5 - The FIFO buffer contains 16 entries. - 0b100 - - - value6 - The FIFO buffer contains 32 entries. - 0b101 - - - value7 - The FIFO buffer contains 64 entries. - 0b110 - - - value8 - Reserved - 0b111 - - - - - LOF - Buffer Event on Limit Overflow - 28 - 28 - read-write - - - value1 - A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word. - 0b0 - - - value2 - A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. - 0b1 - - - - - STBIEN - Standard Transmit Buffer Interrupt Enable - 30 - 30 - read-write - - - value1 - The standard transmit buffer interrupt generation is disabled. - 0b0 - - - value2 - The standard transmit buffer interrupt generation is enabled. - 0b1 - - - - - TBERIEN - Transmit Buffer Error Interrupt Enable - 31 - 31 - read-write - - - value1 - The transmit buffer error interrupt generation is disabled. - 0b0 - - - value2 - The transmit buffer error interrupt generation is enabled. - 0b1 - - - - - - - RBCTR - Receiver Buffer Control Register - 0x10C - 32 - 0x00000000 - 0xFFFFFFFF - - - DPTR - Data Pointer - 0 - 5 - write-only - - - LIMIT - Limit For Interrupt Generation - 8 - 13 - read-write - - - SRBTM - Standard Receive Buffer Trigger Mode - 14 - 14 - read-write - - - value1 - Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. - 0b0 - - - value2 - Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. - 0b1 - - - - - SRBTEN - Standard Receive Buffer Trigger Enable - 15 - 15 - read-write - - - value1 - The standard receive buffer event trigger through bit TRBSR.SRBT is disabled. - 0b0 - - - value2 - The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. - 0b1 - - - - - SRBINP - Standard Receive Buffer Interrupt Node Pointer - 16 - 18 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - ARBINP - Alternative Receive Buffer Interrupt Node Pointer - 19 - 21 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - RCIM - Receiver Control Information Mode - 22 - 23 - read-write - - - value1 - RCI[4] = PERR, RCI[3:0] = WLEN - 0b00 - - - value2 - RCI[4] = SOF, RCI[3:0] = WLEN - 0b01 - - - value3 - RCI[4] = 0, RCI[3:0] = WLEN - 0b10 - - - value4 - RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF - 0b11 - - - - - SIZE - Buffer Size - 24 - 26 - read-write - - - value1 - The FIFO mechanism is disabled. The buffer does not accept any request for data. - 0b000 - - - value2 - The FIFO buffer contains 2 entries. - 0b001 - - - value3 - The FIFO buffer contains 4 entries. - 0b010 - - - value4 - The FIFO buffer contains 8 entries. - 0b011 - - - value5 - The FIFO buffer contains 16 entries. - 0b100 - - - value6 - The FIFO buffer contains 32 entries. - 0b101 - - - value7 - The FIFO buffer contains 64 entries. - 0b110 - - - value8 - Reserved - 0b111 - - - - - RNM - Receiver Notification Mode - 27 - 27 - read-write - - - value1 - Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). - 0b0 - - - value2 - RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. - 0b1 - - - - - LOF - Buffer Event on Limit Overflow - 28 - 28 - read-write - - - value1 - A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR. - 0b0 - - - value2 - A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. - 0b1 - - - - - ARBIEN - Alternative Receive Buffer Interrupt Enable - 29 - 29 - read-write - - - value1 - The alternative receive buffer interrupt generation is disabled. - 0b0 - - - value2 - The alternative receive buffer interrupt generation is enabled. - 0b1 - - - - - SRBIEN - Standard Receive Buffer Interrupt Enable - 30 - 30 - read-write - - - value1 - The standard receive buffer interrupt generation is disabled. - 0b0 - - - value2 - The standard receive buffer interrupt generation is enabled. - 0b1 - - - - - RBERIEN - Receive Buffer Error Interrupt Enable - 31 - 31 - read-write - - - value1 - The receive buffer error interrupt generation is disabled. - 0b0 - - - value2 - The receive buffer error interrupt generation is enabled. - 0b1 - - - - - - - TRBPTR - Transmit/Receive Buffer Pointer Register - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDIPTR - Transmitter Data Input Pointer - 0 - 5 - read-only - - - TDOPTR - Transmitter Data Output Pointer - 8 - 13 - read-only - - - RDIPTR - Receiver Data Input Pointer - 16 - 21 - read-only - - - RDOPTR - Receiver Data Output Pointer - 24 - 29 - read-only - - - - - TRBSR - Transmit/Receive Buffer Status Register - 0x114 - 32 - 0x00000808 - 0xFFFFFFFF - - - SRBI - Standard Receive Buffer Event - 0 - 0 - read-write - - - value1 - A standard receive buffer event has not been detected. - 0b0 - - - value2 - A standard receive buffer event has been detected. - 0b1 - - - - - RBERI - Receive Buffer Error Event - 1 - 1 - read-write - - - value1 - A receive buffer error event has not been detected. - 0b0 - - - value2 - A receive buffer error event has been detected. - 0b1 - - - - - ARBI - Alternative Receive Buffer Event - 2 - 2 - read-write - - - value1 - An alternative receive buffer event has not been detected. - 0b0 - - - value2 - An alternative receive buffer event has been detected. - 0b1 - - - - - REMPTY - Receive Buffer Empty - 3 - 3 - read-only - - - value1 - The receive buffer is not empty. - 0b0 - - - value2 - The receive buffer is empty. - 0b1 - - - - - RFULL - Receive Buffer Full - 4 - 4 - read-only - - - value1 - The receive buffer is not full. - 0b0 - - - value2 - The receive buffer is full. - 0b1 - - - - - RBUS - Receive Buffer Busy - 5 - 5 - read-only - - - value1 - The receive buffer information has been completely updated. - 0b0 - - - value2 - The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. - 0b1 - - - - - SRBT - Standard Receive Buffer Event Trigger - 6 - 6 - read-only - - - value1 - A standard receive buffer event is not triggered using this bit. - 0b0 - - - value2 - A standard receive buffer event is triggered using this bit. - 0b1 - - - - - STBI - Standard Transmit Buffer Event - 8 - 8 - read-write - - - value1 - A standard transmit buffer event has not been detected. - 0b0 - - - value2 - A standard transmit buffer event has been detected. - 0b1 - - - - - TBERI - Transmit Buffer Error Event - 9 - 9 - read-write - - - value1 - A transmit buffer error event has not been detected. - 0b0 - - - value2 - A transmit buffer error event has been detected. - 0b1 - - - - - TEMPTY - Transmit Buffer Empty - 11 - 11 - read-only - - - value1 - The transmit buffer is not empty. - 0b0 - - - value2 - The transmit buffer is empty. - 0b1 - - - - - TFULL - Transmit Buffer Full - 12 - 12 - read-only - - - value1 - The transmit buffer is not full. - 0b0 - - - value2 - The transmit buffer is full. - 0b1 - - - - - TBUS - Transmit Buffer Busy - 13 - 13 - read-only - - - value1 - The transmit buffer information has been completely updated. - 0b0 - - - value2 - The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. - 0b1 - - - - - STBT - Standard Transmit Buffer Event Trigger - 14 - 14 - read-only - - - value1 - A standard transmit buffer event is not triggered using this bit. - 0b0 - - - value2 - A standard transmit buffer event is triggered using this bit. - 0b1 - - - - - RBFLVL - Receive Buffer Filling Level - 16 - 22 - read-only - - - TBFLVL - Transmit Buffer Filling Level - 24 - 30 - read-only - - - - - TRBSCR - Transmit/Receive Buffer Status Clear Register - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - CSRBI - Clear Standard Receive Buffer Event - 0 - 0 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.SRBI. - 0b1 - - - - - CRBERI - Clear Receive Buffer Error Event - 1 - 1 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.RBERI. - 0b1 - - - - - CARBI - Clear Alternative Receive Buffer Event - 2 - 2 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.ARBI. - 0b1 - - - - - CSTBI - Clear Standard Transmit Buffer Event - 8 - 8 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.STBI. - 0b1 - - - - - CTBERI - Clear Transmit Buffer Error Event - 9 - 9 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.TBERI. - 0b1 - - - - - CBDV - Clear Bypass Data Valid - 10 - 10 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear BYPCR.BDV. - 0b1 - - - - - FLUSHRB - Flush Receive Buffer - 14 - 14 - write-only - - - value1 - No effect. - 0b0 - - - value2 - The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. - 0b1 - - - - - FLUSHTB - Flush Transmit Buffer - 15 - 15 - write-only - - - value1 - No effect. - 0b0 - - - value2 - The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. - 0b1 - - - - - - - OUTR - Receiver Buffer Output Register - 0x11C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Received Data - 0 - 15 - read-only - - - RCI - Receiver Control Information - 16 - 20 - read-only - - - - - OUTDR - Receiver Buffer Output Register L for Debugger - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Data from Shift Register - 0 - 15 - read-only - - - RCI - Receive Control Information from Shift Register - 16 - 20 - read-only - - - - - 32 - 4 - IN[%s] - Transmit FIFO Buffer - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDATA - Transmit Data - 0 - 15 - write-only - - - - - - - USIC0_CH1 - Universal Serial Interface Controller 0 - USIC - 0x40030200 - - 0x0 - 0x0200 - registers - - - - USIC1_CH0 - Universal Serial Interface Controller 0 - USIC - 0x48020000 - - 0x0 - 0x0200 - registers - - - - USIC1_CH1 - Universal Serial Interface Controller 0 - USIC - 0x48020200 - - 0x0 - 0x0200 - registers - - - - USIC2_CH0 - Universal Serial Interface Controller 0 - USIC - 0x48024000 - - 0x0 - 0x0200 - registers - - - - USIC2_CH1 - Universal Serial Interface Controller 0 - USIC - 0x48024200 - - 0x0 - 0x0200 - registers - - - - CAN - Controller Area Networks - CAN - 0x48014000 - - 0x0 - 0x4000 - registers - - - - CLC - CAN Clock Control Register - 0x0000 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - EDIS - Sleep Mode Enable Control - 3 - 3 - read-write - - - SBWE - Module Suspend Bit Write Enable for OCDS - 4 - 4 - write-only - - - - - ID - Module Identification Register - 0x0008 - 32 - 0x002BC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - value1 - Define the module as a 32-bit module. - 0xC0 - - - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - FDR - CAN Fractional Divider Register - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - STEP - Step Value - 0 - 9 - read-write - - - SM - Suspend Mode - 11 - 11 - read-write - - - SC - Suspend Control - 12 - 13 - read-write - - - DM - Divider Mode - 14 - 15 - read-write - - - RESULT - Result Value - 16 - 25 - read-only - - - SUSACK - Suspend Mode Acknowledge - 28 - 28 - read-only - - - SUSREQ - Suspend Mode Request - 29 - 29 - read-only - - - ENHW - Enable Hardware Clock Control - 30 - 30 - read-write - - - DISCLK - Disable Clock - 31 - 31 - read-write - - - - - 8 - 4 - LIST[%s] - List Register - 0x0100 - 32 - 0x00000000 - 0x00000000 - - - BEGIN - List Begin - 0 - 7 - read-only - - - END - List End - 8 - 15 - read-only - - - SIZE - List Size - 16 - 23 - read-only - - - EMPTY - List Empty Indication - 24 - 24 - read-only - - - value1 - At least one message object is allocated to list i. - 0b0 - - - value2 - No message object is allocated to the list x. List x is empty. - 0b1 - - - - - - - 8 - 4 - MSPND[%s] - Message Pending Register - 0x0140 - 32 - 0x00000000 - 0xFFFFFFFF - - - PND - Message Pending - 0 - 31 - read-write - - - - - 8 - 4 - MSID[%s] - Message Index Register - 0x0180 - 32 - 0x00000020 - 0xFFFFFFFF - - - INDEX - Message Pending Index - 0 - 5 - read-only - - - - - MSIMASK - Message Index Mask Register - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IM - Message Index Mask - 0 - 31 - read-write - - - - - PANCTR - Panel Control Register - 0x01C4 - 32 - 0x00000301 - 0xFFFFFFFF - - - PANCMD - Panel Command - 0 - 7 - read-write - - - BUSY - Panel Busy Flag - 8 - 8 - read-only - - - value1 - Panel has finished command and is ready to accept a new command. - 0b0 - - - value2 - Panel operation is in progress. - 0b1 - - - - - RBUSY - Result Busy Flag - 9 - 9 - read-only - - - value1 - No update of PANAR1 and PANAR2 is scheduled by the list controller. - 0b0 - - - value2 - A list command is running (BUSY = 1) that will write results to PANAR1 and PANAR2, but the results are not yet available. - 0b1 - - - - - PANAR1 - Panel Argument 1 - 16 - 23 - read-write - - - PANAR2 - Panel Argument 2 - 24 - 31 - read-write - - - - - MCR - Module Control Register - 0x01C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPSEL - Message Pending Selector - 12 - 15 - read-write - - - - - MITR - Module Interrupt Trigger Register - 0x01CC - 32 - 0x00000000 - 0xFFFFFFFF - - - IT - Interrupt Trigger - 0 - 7 - write-only - - - - - - - CAN_NODE0 - Controller Area Networks - CAN - CAN_NODE - 0x48014200 - - 0x0 - 0x4000 - registers - - - - NCR - Node Control Register - 0x00 - 32 - 0x00000001 - 0xFFFFFFFF - - - INIT - Node Initialization - 0 - 0 - read-write - - - value1 - Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic. - 0b0 - - - value2 - Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set. - 0b1 - - - - - TRIE - Transfer Interrupt Enable - 1 - 1 - read-write - - - value1 - Transfer interrupt is disabled. - 0b0 - - - value2 - Transfer interrupt is enabled. - 0b1 - - - - - LECIE - LEC Indicated Error Interrupt Enable - 2 - 2 - read-write - - - value1 - Last error code interrupt is disabled. - 0b0 - - - value2 - Last error code interrupt is enabled. - 0b1 - - - - - ALIE - Alert Interrupt Enable - 3 - 3 - read-write - - - value1 - Alert interrupt is disabled. - 0b0 - - - value2 - Alert interrupt is enabled. - 0b1 - - - - - CANDIS - CAN Disable - 4 - 4 - read-write - - - CCE - Configuration Change Enable - 6 - 6 - read-write - - - value1 - The Bit Timing Register, the Port Control Register, and the Error Counter Register may only be read. All attempts to modify them are ignored. - 0b0 - - - value2 - The Bit Timing Register, the Port Control Register, and the Error Counter Register may be read and written. - 0b1 - - - - - CALM - CAN Analyzer Mode - 7 - 7 - read-write - - - SUSEN - Suspend Enable - 8 - 8 - read-write - - - value1 - An OCDS suspend trigger is ignored by the CAN node. - 0b0 - - - value2 - An OCDS suspend trigger disables the CAN node: As soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. The actual value of bit INIT remains unchanged. - 0b1 - - - - - - - NSR - Node Status Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - LEC - Last Error Code - 0 - 2 - read-write - - - TXOK - Message Transmitted Successfully - 3 - 3 - read-write - - - value1 - No successful transmission since last (most recent) flag reset. - 0b0 - - - value2 - A message has been transmitted successfully (error-free and acknowledged by at least another node). - 0b1 - - - - - RXOK - Message Received Successfully - 4 - 4 - read-write - - - value1 - No successful reception since last (most recent) flag reset. - 0b0 - - - value2 - A message has been received successfully. - 0b1 - - - - - ALERT - Alert Warning - 5 - 5 - read-write - - - EWRN - Error Warning Status - 6 - 6 - read-only - - - value1 - No warning limit exceeded. - 0b0 - - - value2 - One of the error counters REC or TEC reached the warning limit EWRNLVL. - 0b1 - - - - - BOFF - Bus-off Status - 7 - 7 - read-only - - - value1 - CAN controller is not in the bus-off state. - 0b0 - - - value2 - CAN controller is in the bus-off state. - 0b1 - - - - - LLE - List Length Error - 8 - 8 - read-write - - - value1 - No List Length Error since last (most recent) flag reset. - 0b0 - - - value2 - A List Length Error has been detected during message acceptance filtering. The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list termination pointer. - 0b1 - - - - - LOE - List Object Error - 9 - 9 - read-write - - - value1 - No List Object Error since last (most recent) flag reset. - 0b0 - - - value2 - A List Object Error has been detected during message acceptance filtering. A message object with wrong LIST index entry in the Message Object Control Register has been detected. - 0b1 - - - - - SUSACK - Suspend Acknowledge - 10 - 10 - read-only - - - value1 - The CAN node is not in Suspend Mode or a suspend request is pending, but the CAN node has not yet reached bus-idle or bus-off. - 0b0 - - - value2 - The CAN node is in Suspend Mode: The CAN node is inactive (bit NCR.INIT internally forced to 1) due to an OCDS suspend request. - 0b1 - - - - - - - NIPR - Node Interrupt Pointer Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALINP - Alert Interrupt Node Pointer - 0 - 2 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - LECINP - Last Error Code Interrupt Node Pointer - 4 - 6 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - TRINP - Transfer OK Interrupt Node Pointer - 8 - 10 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - CFCINP - Frame Counter Interrupt Node Pointer - 12 - 14 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - - - NPCR - Node Port Control Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXSEL - Receive Select - 0 - 2 - read-write - - - LBM - Loop-Back Mode - 8 - 8 - read-write - - - value1 - Loop-Back Mode is disabled. - 0b0 - - - value2 - Loop-Back Mode is enabled. This node is connected to an internal (virtual) loop-back CAN bus. All CAN nodes which are in Loop-Back Mode are connected to this virtual CAN bus so that they can communicate with each other internally. The external transmit line is forced recessive in Loop-Back Mode. - 0b1 - - - - - - - NBTR - Node Bit Timing Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - BRP - Baud Rate Prescaler - 0 - 5 - read-write - - - SJW - (Re) Synchronization Jump Width - 6 - 7 - read-write - - - TSEG1 - Time Segment Before Sample Point - 8 - 11 - read-write - - - TSEG2 - Time Segment After Sample Point - 12 - 14 - read-write - - - DIV8 - Divide Prescaler Clock by 8 - 15 - 15 - read-write - - - value1 - A time quantum lasts (BRP+1) clock cycles. - 0b0 - - - value2 - A time quantum lasts 8 (BRP+1) clock cycles. - 0b1 - - - - - - - NECNT - Node Error Counter Register - 0x14 - 32 - 0x00600000 - 0xFFFFFFFF - - - REC - Receive Error Counter - 0 - 7 - read-write - - - TEC - Transmit Error Counter - 8 - 15 - read-write - - - EWRNLVL - Error Warning Level - 16 - 23 - read-write - - - LETD - Last Error Transfer Direction - 24 - 24 - read-only - - - value1 - The last error occurred while the CAN node x was receiver (REC has been incremented). - 0b0 - - - value2 - The last error occurred while the CAN node x was transmitter (TEC has been incremented). - 0b1 - - - - - LEINC - Last Error Increment - 25 - 25 - read-only - - - value1 - The last error led to an error counter increment of 1. - 0b0 - - - value2 - The last error led to an error counter increment of 8. - 0b1 - - - - - - - NFCR - Node Frame Counter Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFC - CAN Frame Counter - 0 - 15 - read-write - - - CFSEL - CAN Frame Count Selection - 16 - 18 - read-write - - - value1 - The frame counter is incremented (internally) at the beginning of a new bit time. The value is sampled during the SOF bit of a new frame. The sampled value is visible in the CFC field. - 0b000 - - - - - CFMOD - CAN Frame Counter Mode - 19 - 20 - read-write - - - value1 - Frame Count Mode: The frame counter is incremented upon the reception and transmission of frames. - 0b00 - - - value2 - Time Stamp Mode: The frame counter is used to count bit times. - 0b01 - - - value3 - Bit Timing Mode: The frame counter is used for analysis of the bit timing. - 0b10 - - - - - CFCIE - CAN Frame Count Interrupt Enable - 22 - 22 - read-write - - - value1 - CAN frame counter overflow interrupt is disabled. - 0b0 - - - value2 - CAN frame counter overflow interrupt is enabled. - 0b1 - - - - - CFCOV - CAN Frame Counter Overflow Flag - 23 - 23 - read-write - - - value1 - No overflow has occurred since last flag reset. - 0b0 - - - value2 - An overflow has occurred since last flag reset. - 0b1 - - - - - - - - - CAN_NODE1 - Controller Area Networks - CAN - 0x48014300 - - 0x0 - 0x4000 - registers - - - - CAN_NODE2 - Controller Area Networks - CAN - 0x48014400 - - 0x0 - 0x4000 - registers - - - - CAN_MO0 - Controller Area Networks - CAN - CAN_MO - 0x48015000 - - 0x0 - 0x20 - registers - - - - MOFCR - Message Object Function Control Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - MMC - Message Mode Control - 0 - 3 - read-write - - - value1 - Standard Message Object - 0b0000 - - - value2 - Receive FIFO Base Object - 0b0001 - - - value3 - Transmit FIFO Base Object - 0b0010 - - - value4 - Transmit FIFO Slave Object - 0b0011 - - - value5 - Gateway Source Object - 0b0100 - - - - - GDFS - Gateway Data Frame Send - 8 - 8 - read-write - - - value1 - TXRQ is unchanged in the destination object. - 0b0 - - - value2 - TXRQ is set in the gateway destination object after the internal transfer from the gateway source to the gateway destination object. - 0b1 - - - - - IDC - Identifier Copy - 9 - 9 - read-write - - - value1 - The identifier of the gateway source object is not copied. - 0b0 - - - value2 - The identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. - 0b1 - - - - - DLCC - Data Length Code Copy - 10 - 10 - read-write - - - value1 - Data length code is not copied. - 0b0 - - - value2 - Data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. - 0b1 - - - - - DATC - Data Copy - 11 - 11 - read-write - - - value1 - Data fields are not copied. - 0b0 - - - value2 - Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) are copied to the gateway destination. - 0b1 - - - - - RXIE - Receive Interrupt Enable - 16 - 16 - read-write - - - value1 - Message receive interrupt is disabled. - 0b0 - - - value2 - Message receive interrupt is enabled. - 0b1 - - - - - TXIE - Transmit Interrupt Enable - 17 - 17 - read-write - - - value1 - Message transmit interrupt is disabled. - 0b0 - - - value2 - Message transmit interrupt is enabled. - 0b1 - - - - - OVIE - Overflow Interrupt Enable - 18 - 18 - read-write - - - value1 - FIFO full interrupt is disabled. - 0b0 - - - value2 - FIFO full interrupt is enabled. - 0b1 - - - - - FRREN - Foreign Remote Request Enable - 20 - 20 - read-write - - - value1 - TXRQ of message object n is set on reception of a matching Remote Frame. - 0b0 - - - value2 - TXRQ of the message object referenced by the pointer CUR is set on reception of a matching Remote Frame. - 0b1 - - - - - RMM - Transmit Object Remote Monitoring - 21 - 21 - read-write - - - value1 - Remote monitoring is disabled: Identifier, IDE bit, and DLC of message object n remain unchanged upon the reception of a matching Remote Frame. - 0b0 - - - value2 - Remote monitoring is enabled: Identifier, IDE bit, and DLC of a matching Remote Frame are copied to transmit object n in order to monitor incoming Remote Frames. - 0b1 - - - - - SDT - Single Data Transfer - 22 - 22 - read-write - - - STT - Single Transmit Trial - 23 - 23 - read-write - - - DLC - Data Length Code - 24 - 27 - read-write - - - - - MOFGPR - Message Object FIFO/Gateway Pointer Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOT - Bottom Pointer - 0 - 7 - read-write - - - TOP - Top Pointer - 8 - 15 - read-write - - - CUR - Current Object Pointer - 16 - 23 - read-write - - - SEL - Object Select Pointer - 24 - 31 - read-write - - - - - MOIPR - Message Object Interrupt Pointer Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXINP - Receive Interrupt Node Pointer - 0 - 2 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - TXINP - Transmit Interrupt Node Pointer - 4 - 6 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - MPN - Message Pending Number - 8 - 15 - read-write - - - CFCVAL - CAN Frame Counter Value - 16 - 31 - read-write - - - - - MOAMR - Message Object Acceptance Mask Register - 0x0C - 32 - 0x3FFFFFFF - 0xFFFFFFFF - - - AM - Acceptance Mask for Message Identifier - 0 - 28 - read-write - - - MIDE - Acceptance Mask Bit for Message IDE Bit - 29 - 29 - read-write - - - value1 - Message object n accepts the reception of both, standard and extended frames. - 0b0 - - - value2 - Message object n receives frames only with matching IDE bit. - 0b1 - - - - - - - MODATAL - Message Object Data Register Low - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DB0 - Data Byte 0 of Message Object n - 0 - 7 - read-write - - - DB1 - Data Byte 1 of Message Object n - 8 - 15 - read-write - - - DB2 - Data Byte 2 of Message Object n - 16 - 23 - read-write - - - DB3 - Data Byte 3 of Message Object n - 24 - 31 - read-write - - - - - MODATAH - Message Object Data Register High - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DB4 - Data Byte 4 of Message Object n - 0 - 7 - read-write - - - DB5 - Data Byte 5 of Message Object n - 8 - 15 - read-write - - - DB6 - Data Byte 6 of Message Object n - 16 - 23 - read-write - - - DB7 - Data Byte 7 of Message Object n - 24 - 31 - read-write - - - - - MOAR - Message Object Arbitration Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ID - CAN Identifier of Message Object n - 0 - 28 - read-write - - - IDE - Identifier Extension Bit of Message Object n - 29 - 29 - read-write - - - value1 - Message object n handles standard frames with 11-bit identifier. - 0b0 - - - value2 - Message object n handles extended frames with 29-bit identifier. - 0b1 - - - - - PRI - Priority Class - 30 - 31 - read-write - - - value1 - Applicable only if TTCAN is available. - 0b00 - - - value2 - Transmit acceptance filtering is based on the list order. This means that message object n is considered for transmission only if there is no other message object with valid transmit request (MSGVAL & TXEN0 & TXEN1 = 1) somewhere before this object in the list. - 0b01 - - - value3 - Transmit acceptance filtering is based on the CAN identifier. This means, message object n is considered for transmission only if there is no other message object with higher priority identifier + IDE + DIR (with respect to CAN arbitration rules) somewhere in the list (see ). - 0b10 - - - value4 - Transmit acceptance filtering is based on the list order (as PRI = 01B). - 0b11 - - - - - - - MOCTR - Message Object Control Register - 0x1C - 32 - 0x00000000 - 0x0000FFFF - - - RESRXPND - Reset/Set Receive Pending - 0 - 0 - write-only - - - SETRXPND - Reset/Set Receive Pending - 16 - 16 - write-only - - - RESTXPND - Reset/Set Transmit Pending - 1 - 1 - write-only - - - SETTXPND - Reset/Set Transmit Pending - 17 - 17 - write-only - - - RESRXUPD - Reset/Set Receive Updating - 2 - 2 - write-only - - - SETRXUPD - Reset/Set Receive Updating - 18 - 18 - write-only - - - RESNEWDAT - Reset/Set New Data - 3 - 3 - write-only - - - SETNEWDAT - Reset/Set New Data - 19 - 19 - write-only - - - RESMSGLST - Reset/Set Message Lost - 4 - 4 - write-only - - - SETMSGLST - Reset/Set Message Lost - 20 - 20 - write-only - - - RESMSGVAL - Reset/Set Message Valid - 5 - 5 - write-only - - - SETMSGVAL - Reset/Set Message Valid - 21 - 21 - write-only - - - RESRTSEL - Reset/Set Receive/Transmit Selected - 6 - 6 - write-only - - - SETRTSEL - Reset/Set Receive/Transmit Selected - 22 - 22 - write-only - - - RESRXEN - Reset/Set Receive Enable - 7 - 7 - write-only - - - SETRXEN - Reset/Set Receive Enable - 23 - 23 - write-only - - - RESTXRQ - Reset/Set Transmit Request - 8 - 8 - write-only - - - SETTXRQ - Reset/Set Transmit Request - 24 - 24 - write-only - - - RESTXEN0 - Reset/Set Transmit Enable 0 - 9 - 9 - write-only - - - SETTXEN0 - Reset/Set Transmit Enable 0 - 25 - 25 - write-only - - - RESTXEN1 - Reset/Set Transmit Enable 1 - 10 - 10 - write-only - - - SETTXEN1 - Reset/Set Transmit Enable 1 - 26 - 26 - write-only - - - RESDIR - Reset/Set Message Direction - 11 - 11 - write-only - - - SETDIR - Reset/Set Message Direction - 27 - 27 - write-only - - - - - MOSTAT - Message Object Status Register - MOCTR - 0x1C - 32 - 0x00000000 - 0x0000FFFF - - - RXPND - Receive Pending - 0 - 0 - read-only - - - value1 - No CAN message has been received. - 0b0 - - - value2 - A CAN message has been received by the message object n, either directly or via gateway copy action. - 0b1 - - - - - TXPND - Transmit Pending - 1 - 1 - read-only - - - value1 - No CAN message has been transmitted. - 0b0 - - - value2 - A CAN message from message object n has been transmitted successfully over the CAN bus. - 0b1 - - - - - RXUPD - Receive Updating - 2 - 2 - read-only - - - value1 - No receive update ongoing. - 0b0 - - - value2 - Message identifier, DLC, and data of the message object are currently updated. - 0b1 - - - - - NEWDAT - New Data - 3 - 3 - read-only - - - value1 - No update of the message object n since last flag reset. - 0b0 - - - value2 - Message object n has been updated. - 0b1 - - - - - MSGLST - Message Lost - 4 - 4 - read-only - - - value1 - No CAN message is lost. - 0b0 - - - value2 - A CAN message is lost because NEWDAT has become set again when it has already been set. - 0b1 - - - - - MSGVAL - Message Valid - 5 - 5 - read-only - - - value1 - Message object n is not valid. - 0b0 - - - value2 - Message object n is valid. - 0b1 - - - - - RTSEL - Receive/Transmit Selected - 6 - 6 - read-only - - - value1 - Message object n is not selected for receive or transmit operation. - 0b0 - - - value2 - Message object n is selected for receive or transmit operation. - 0b1 - - - - - RXEN - Receive Enable - 7 - 7 - read-only - - - value1 - Message object n is not enabled for frame reception. - 0b0 - - - value2 - Message object n is enabled for frame reception. - 0b1 - - - - - TXRQ - Transmit Request - 8 - 8 - read-only - - - value1 - No transmission of message object n is requested. - 0b0 - - - value2 - Transmission of message object n on the CAN bus is requested. - 0b1 - - - - - TXEN0 - Transmit Enable 0 - 9 - 9 - read-only - - - value1 - Message object n is not enabled for frame transmission. - 0b0 - - - value2 - Message object n is enabled for frame transmission. - 0b1 - - - - - TXEN1 - Transmit Enable 1 - 10 - 10 - read-only - - - value1 - Message object n is not enabled for frame transmission. - 0b0 - - - value2 - Message object n is enabled for frame transmission. - 0b1 - - - - - DIR - Message Direction - 11 - 11 - read-only - - - value1 - Receive Object selected: With TXRQ = 1, a Remote Frame with the identifier of message object n is scheduled for transmission. On reception of a Data Frame with matching identifier, the message is stored in message object n. - 0b0 - - - value2 - Transmit Object selected: If TXRQ = 1, message object n is scheduled for transmission of a Data Frame. On reception of a Remote Frame with matching identifier, bit TXRQ is set. - 0b1 - - - - - LIST - List Allocation - 12 - 15 - read-only - - - PPREV - Pointer to Previous Message Object - 16 - 23 - read-only - - - PNEXT - Pointer to Next Message Object - 24 - 31 - read-only - - - - - - - CAN_MO1 - Controller Area Networks - CAN - 0x48015020 - - 0x0 - 0x20 - registers - - - - CAN_MO2 - Controller Area Networks - CAN - 0x48015040 - - 0x0 - 0x20 - registers - - - - CAN_MO3 - Controller Area Networks - CAN - 0x48015060 - - 0x0 - 0x20 - registers - - - - CAN_MO4 - Controller Area Networks - CAN - 0x48015080 - - 0x0 - 0x20 - registers - - - - CAN_MO5 - Controller Area Networks - CAN - 0x480150A0 - - 0x0 - 0x20 - registers - - - - CAN_MO6 - Controller Area Networks - CAN - 0x480150C0 - - 0x0 - 0x20 - registers - - - - CAN_MO7 - Controller Area Networks - CAN - 0x480150E0 - - 0x0 - 0x20 - registers - - - - CAN_MO8 - Controller Area Networks - CAN - 0x48015100 - - 0x0 - 0x20 - registers - - - - CAN_MO9 - Controller Area Networks - CAN - 0x48015120 - - 0x0 - 0x20 - registers - - - - CAN_MO10 - Controller Area Networks - CAN - 0x48015140 - - 0x0 - 0x20 - registers - - - - CAN_MO11 - Controller Area Networks - CAN - 0x48015160 - - 0x0 - 0x20 - registers - - - - CAN_MO12 - Controller Area Networks - CAN - 0x48015180 - - 0x0 - 0x20 - registers - - - - CAN_MO13 - Controller Area Networks - CAN - 0x480151A0 - - 0x0 - 0x20 - registers - - - - CAN_MO14 - Controller Area Networks - CAN - 0x480151C0 - - 0x0 - 0x20 - registers - - - - CAN_MO15 - Controller Area Networks - CAN - 0x480151E0 - - 0x0 - 0x20 - registers - - - - CAN_MO16 - Controller Area Networks - CAN - 0x48015200 - - 0x0 - 0x20 - registers - - - - CAN_MO17 - Controller Area Networks - CAN - 0x48015220 - - 0x0 - 0x20 - registers - - - - CAN_MO18 - Controller Area Networks - CAN - 0x48015240 - - 0x0 - 0x20 - registers - - - - CAN_MO19 - Controller Area Networks - CAN - 0x48015260 - - 0x0 - 0x20 - registers - - - - CAN_MO20 - Controller Area Networks - CAN - 0x48015280 - - 0x0 - 0x20 - registers - - - - CAN_MO21 - Controller Area Networks - CAN - 0x480152A0 - - 0x0 - 0x20 - registers - - - - CAN_MO22 - Controller Area Networks - CAN - 0x480152C0 - - 0x0 - 0x20 - registers - - - - CAN_MO23 - Controller Area Networks - CAN - 0x480152E0 - - 0x0 - 0x20 - registers - - - - CAN_MO24 - Controller Area Networks - CAN - 0x48015300 - - 0x0 - 0x20 - registers - - - - CAN_MO25 - Controller Area Networks - CAN - 0x48015320 - - 0x0 - 0x20 - registers - - - - CAN_MO26 - Controller Area Networks - CAN - 0x48015340 - - 0x0 - 0x20 - registers - - - - CAN_MO27 - Controller Area Networks - CAN - 0x48015360 - - 0x0 - 0x20 - registers - - - - CAN_MO28 - Controller Area Networks - CAN - 0x48015380 - - 0x0 - 0x20 - registers - - - - CAN_MO29 - Controller Area Networks - CAN - 0x480153A0 - - 0x0 - 0x20 - registers - - - - CAN_MO30 - Controller Area Networks - CAN - 0x480153C0 - - 0x0 - 0x20 - registers - - - - CAN_MO31 - Controller Area Networks - CAN - 0x480153E0 - - 0x0 - 0x20 - registers - - - - CAN_MO32 - Controller Area Networks - CAN - 0x48015400 - - 0x0 - 0x20 - registers - - - - CAN_MO33 - Controller Area Networks - CAN - 0x48015420 - - 0x0 - 0x20 - registers - - - - CAN_MO34 - Controller Area Networks - CAN - 0x48015440 - - 0x0 - 0x20 - registers - - - - CAN_MO35 - Controller Area Networks - CAN - 0x48015460 - - 0x0 - 0x20 - registers - - - - CAN_MO36 - Controller Area Networks - CAN - 0x48015480 - - 0x0 - 0x20 - registers - - - - CAN_MO37 - Controller Area Networks - CAN - 0x480154A0 - - 0x0 - 0x20 - registers - - - - CAN_MO38 - Controller Area Networks - CAN - 0x480154C0 - - 0x0 - 0x20 - registers - - - - CAN_MO39 - Controller Area Networks - CAN - 0x480154E0 - - 0x0 - 0x20 - registers - - - - CAN_MO40 - Controller Area Networks - CAN - 0x48015500 - - 0x0 - 0x20 - registers - - - - CAN_MO41 - Controller Area Networks - CAN - 0x48015520 - - 0x0 - 0x20 - registers - - - - CAN_MO42 - Controller Area Networks - CAN - 0x48015540 - - 0x0 - 0x20 - registers - - - - CAN_MO43 - Controller Area Networks - CAN - 0x48015560 - - 0x0 - 0x20 - registers - - - - CAN_MO44 - Controller Area Networks - CAN - 0x48015580 - - 0x0 - 0x20 - registers - - - - CAN_MO45 - Controller Area Networks - CAN - 0x480155A0 - - 0x0 - 0x20 - registers - - - - CAN_MO46 - Controller Area Networks - CAN - 0x480155C0 - - 0x0 - 0x20 - registers - - - - CAN_MO47 - Controller Area Networks - CAN - 0x480155E0 - - 0x0 - 0x20 - registers - - - - CAN_MO48 - Controller Area Networks - CAN - 0x48015600 - - 0x0 - 0x20 - registers - - - - CAN_MO49 - Controller Area Networks - CAN - 0x48015620 - - 0x0 - 0x20 - registers - - - - CAN_MO50 - Controller Area Networks - CAN - 0x48015640 - - 0x0 - 0x20 - registers - - - - CAN_MO51 - Controller Area Networks - CAN - 0x48015660 - - 0x0 - 0x20 - registers - - - - CAN_MO52 - Controller Area Networks - CAN - 0x48015680 - - 0x0 - 0x20 - registers - - - - CAN_MO53 - Controller Area Networks - CAN - 0x480156A0 - - 0x0 - 0x20 - registers - - - - CAN_MO54 - Controller Area Networks - CAN - 0x480156C0 - - 0x0 - 0x20 - registers - - - - CAN_MO55 - Controller Area Networks - CAN - 0x480156E0 - - 0x0 - 0x20 - registers - - - - CAN_MO56 - Controller Area Networks - CAN - 0x48015700 - - 0x0 - 0x20 - registers - - - - CAN_MO57 - Controller Area Networks - CAN - 0x48015720 - - 0x0 - 0x20 - registers - - - - CAN_MO58 - Controller Area Networks - CAN - 0x48015740 - - 0x0 - 0x20 - registers - - - - CAN_MO59 - Controller Area Networks - CAN - 0x48015760 - - 0x0 - 0x20 - registers - - - - CAN_MO60 - Controller Area Networks - CAN - 0x48015780 - - 0x0 - 0x20 - registers - - - - CAN_MO61 - Controller Area Networks - CAN - 0x480157A0 - - 0x0 - 0x20 - registers - - - - CAN_MO62 - Controller Area Networks - CAN - 0x480157C0 - - 0x0 - 0x20 - registers - - - - CAN_MO63 - Controller Area Networks - CAN - 0x480157E0 - - 0x0 - 0x20 - registers - - - - VADC - Analog to Digital Converter - VADC - 0x40004000 - - 0x0 - 0x4000 - registers - - - - CLC - Clock Control Register - 0x0000 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - value1 - On request: enable the module clock - 0b0 - - - value2 - Off request: stop the module clock - 0b1 - - - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - value1 - Module clock is enabled - 0b0 - - - value2 - Off: module is not clocked - 0b1 - - - - - EDIS - Sleep Mode Enable Control - 3 - 3 - read-write - - - value1 - Sleep mode request is enabled and functional - 0b0 - - - value2 - Module disregards the sleep mode control signal - 0b1 - - - - - - - ID - Module Identification Register - 0x0008 - 32 - 0x00C5C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - OCS - OCDS Control and Status Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - TGS - Trigger Set for OTGB0/1 - 0 - 1 - read-write - - - value1 - No Trigger Set output - 0b00 - - - value2 - Trigger Set 1: TS16_SSIG, input sample signals - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Reserved - 0b11 - - - - - TGB - OTGB0/1 Bus Select - 2 - 2 - read-write - - - value1 - Trigger Set is output on OTGB0 - 0b0 - - - value2 - Trigger Set is output on OTGB1 - 0b1 - - - - - TG_P - TGS, TGB Write Protection - 3 - 3 - write-only - - - SUS - OCDS Suspend Control - 24 - 27 - read-write - - - value1 - Will not suspend - 0b0000 - - - value2 - Hard suspend: Clock is switched off immediately. - 0b0001 - - - value3 - Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter. - 0b0010 - - - value4 - Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round. - 0b0011 - - - - - SUS_P - SUS Write Protection - 28 - 28 - write-only - - - SUSSTA - Suspend State - 29 - 29 - read-only - - - value1 - Module is not (yet) suspended - 0b0 - - - value2 - Module is suspended - 0b1 - - - - - - - GLOBCFG - Global Configuration Register - 0x0080 - 32 - 0x0000000F - 0xFFFFFFFF - - - DIVA - Divider Factor for the Analog Internal Clock - 0 - 4 - read-write - - - value1 - fADCI = fADC / 2 - 0x00 - - - value2 - fADCI = fADC / 2 - 0x01 - - - value3 - fADCI = fADC / 3 - 0x02 - - - value4 - fADCI = fADC / 32 - 0x1F - - - - - DCMSB - Double Clock for the MSB Conversion - 7 - 7 - read-write - - - value1 - 1 clock cycles for the MSB (standard) - 0b0 - - - value2 - 2 clock cycles for the MSB (fADCI > 20 MHz) - 0b1 - - - - - DIVD - Divider Factor for the Arbiter Clock - 8 - 9 - read-write - - - value1 - fADCD = fADC - 0b00 - - - value2 - fADCD = fADC / 2 - 0b01 - - - value3 - fADCD = fADC / 3 - 0b10 - - - value4 - fADCD = fADC / 4 - 0b11 - - - - - DIVWC - Write Control for Divider Parameters - 15 - 15 - write-only - - - value1 - No write access to divider parameters - 0b0 - - - value2 - Bitfields DIVA, DCMSB, DIVD can be written - 0b1 - - - - - DPCAL0 - Disable Post-Calibration - 16 - 16 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - DPCAL1 - Disable Post-Calibration - 17 - 17 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - DPCAL2 - Disable Post-Calibration - 18 - 18 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - DPCAL3 - Disable Post-Calibration - 19 - 19 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - SUCAL - Start-Up Calibration - 31 - 31 - write-only - - - value1 - No action - 0b0 - - - value2 - Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL) - 0b1 - - - - - - - 2 - 4 - GLOBICLASS[%s] - Input Class Register, Global - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STCS - Sample Time Control for Standard Conversions - 0 - 4 - read-write - - - CMS - Conversion Mode for Standard Conversions - 8 - 10 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - STCE - Sample Time Control for EMUX Conversions - 16 - 20 - read-write - - - CME - Conversion Mode for EMUX Conversions - 24 - 26 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - - - GLOBBOUND - Global Boundary Select Register - 0x00B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOUNDARY0 - Boundary Value 0 for Limit Checking - 0 - 11 - read-write - - - BOUNDARY1 - Boundary Value 1 for Limit Checking - 16 - 27 - read-write - - - - - GLOBEFLAG - Global Event Flag Register - 0x00E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEVGLB - Source Event (Background) - 0 - 0 - read-write - - - value1 - No source event - 0b0 - - - value2 - A source event has occurred - 0b1 - - - - - REVGLB - Global Result Event - 8 - 8 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GLOBRES - 0b1 - - - - - SEVGLBCLR - Clear Source Event (Background) - 16 - 16 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the source event flag SEVGLB - 0b1 - - - - - REVGLBCLR - Clear Global Result Event - 24 - 24 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag REVGLB - 0b1 - - - - - - - GLOBEVNP - Global Event Node Pointer Register - 0x0140 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0NP - Service Request Node Pointer Backgr. Source - 0 - 3 - read-write - - - value1 - Select shared service request line 0 of common service request group 0 - 0b0000 - - - value2 - Select shared service request line 3 of common service request group 0 - 0b0011 - - - value3 - Select shared service request line 0 of common service request group 1 - 0b0100 - - - value4 - Select shared service request line 3 of common service request group 1 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV0NP - Service Request Node Pointer Backgr. Result - 16 - 19 - read-write - - - value1 - Select shared service request line 0 of common service request group 0 - 0b0000 - - - value2 - Select shared service request line 3 of common service request group 0 - 0b0011 - - - value3 - Select shared service request line 0 of common service request group 1 - 0b0100 - - - value4 - Select shared service request line 3 of common service request group 1 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - GLOBTF - Global Test Functions Register - 0x0160 - 32 - 0x00000000 - 0xFFFFFFFF - - - CDGR - Converter Diagnostics Group - 4 - 7 - read-write - - - CDEN - Converter Diagnostics Enable - 8 - 8 - read-write - - - value1 - All diagnostic pull devices are disconnected - 0b0 - - - value2 - Diagnostic pull devices connected as selected by bitfield CDSEL - 0b1 - - - - - CDSEL - Converter Diagnostics Pull-Devices Select - 9 - 10 - read-write - - - value1 - Connected to VAREF - 0b00 - - - value2 - Connected to VAGND - 0b01 - - - value3 - Connected to 1/3rd VAREF - 0b10 - - - value4 - Connected to 2/3rd VAREF - 0b11 - - - - - CDWC - Write Control for Conversion Diagnostics - 15 - 15 - write-only - - - value1 - No write access to parameters - 0b0 - - - value2 - Bitfields CDSEL, CDEN, CDGR can be written - 0b1 - - - - - PDD - Pull-Down Diagnostics Enable - 16 - 16 - read-write - - - value1 - Disconnected - 0b0 - - - value2 - The pull-down diagnostics device is active - 0b1 - - - - - MDWC - Write Control for Multiplexer Diagnostics - 23 - 23 - write-only - - - value1 - No write access to parameters - 0b0 - - - value2 - Bitfield PDD can be written - 0b1 - - - - - - - 4 - 4 - BRSSEL[%s] - Background Request Source Channel Select Register - 0x0180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHSELG0 - Channel Selection Group x - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG1 - Channel Selection Group x - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG2 - Channel Selection Group x - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG3 - Channel Selection Group x - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG4 - Channel Selection Group x - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG5 - Channel Selection Group x - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG6 - Channel Selection Group x - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG7 - Channel Selection Group x - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - - - 4 - 4 - BRSPND[%s] - Background Request Source Pending Register - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHPNDG0 - Channels Pending Group x - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG1 - Channels Pending Group x - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG2 - Channels Pending Group x - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG3 - Channels Pending Group x - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG4 - Channels Pending Group x - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG5 - Channels Pending Group x - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG6 - Channels Pending Group x - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG7 - Channels Pending Group x - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - - - BRSCTRL - Background Request Source Control Register - 0x0200 - 32 - 0x00000000 - 0xFFFFFFFF - - - XTSEL - External Trigger Input Selection - 8 - 11 - read-write - - - XTLVL - External Trigger Level - 12 - 12 - read-only - - - XTMODE - Trigger Operating Mode - 13 - 14 - read-write - - - value1 - No external trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon any edge - 0b11 - - - - - XTWC - Write Control for Trigger Configuration - 15 - 15 - write-only - - - value1 - No write access to trigger configuration - 0b0 - - - value2 - Bitfields XTMODE and XTSEL can be written - 0b1 - - - - - GTSEL - Gate Input Selection - 16 - 19 - read-write - - - GTLVL - Gate Input Level - 20 - 20 - read-only - - - GTWC - Write Control for Gate Configuration - 23 - 23 - write-only - - - value1 - No write access to gate configuration - 0b0 - - - value2 - Bitfield GTSEL can be written - 0b1 - - - - - - - BRSMR - Background Request Source Mode Register - 0x0204 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENGT - Enable Gate - 0 - 1 - read-write - - - value1 - No conversion requests are issued - 0b00 - - - value2 - Conversion requests are issued if at least one pending bit is set - 0b01 - - - value3 - Conversion requests are issued if at least one pending bit is set and REQGTx = 1. - 0b10 - - - value4 - Conversion requests are issued if at least one pending bit is set and REQGTx = 0. - 0b11 - - - - - ENTR - Enable External Trigger - 2 - 2 - read-write - - - value1 - External trigger disabled - 0b0 - - - value2 - The selected edge at the selected trigger input signal REQTR generates the load event - 0b1 - - - - - ENSI - Enable Source Interrupt - 3 - 3 - read-write - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source interrupt is generated upon a request source event (last pending conversion is finished) - 0b1 - - - - - SCAN - Autoscan Enable - 4 - 4 - read-write - - - value1 - No autoscan - 0b0 - - - value2 - Autoscan functionality enabled: a request source event automatically generates a load event - 0b1 - - - - - LDM - Autoscan Source Load Event Mode - 5 - 5 - read-write - - - value1 - Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event - 0b0 - - - value2 - Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) - 0b1 - - - - - REQGT - Request Gate Level - 7 - 7 - read-only - - - value1 - The gate input is low - 0b0 - - - value2 - The gate input is high - 0b1 - - - - - CLRPND - Clear Pending Bits - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - The bits in registers BRSPNDx are cleared - 0b1 - - - - - LDEV - Generate Load Event - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - A load event is generated - 0b1 - - - - - RPTDIS - Repeat Disable - 16 - 16 - read-write - - - value1 - A cancelled conversion is repeated - 0b0 - - - value2 - A cancelled conversion is discarded - 0b1 - - - - - - - GLOBRCR - Global Result Control Register - 0x0280 - 32 - 0x00000000 - 0xFFFFFFFF - - - DRCTR - Data Reduction Control - 16 - 19 - read-write - - - value1 - Data reduction disabled - 0b0000 - - - - - WFR - Wait-for-Read Mode Enable - 24 - 24 - read-write - - - value1 - Overwrite mode - 0b0 - - - value2 - Wait-for-read mode enabled for this register - 0b1 - - - - - SRGEN - Service Request Generation Enable - 31 - 31 - read-write - - - value1 - No service request - 0b0 - - - value2 - Service request after a result event - 0b1 - - - - - - - GLOBRES - Global Result Register - 0x0300 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-write - - - GNR - Group Number - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) - 0b1 - - - - - - - GLOBRESD - Global Result Register, Debug - 0x0380 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-write - - - GNR - Group Number - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) - 0b1 - - - - - - - EMUXSEL - External Multiplexer Select Register - 0x03F0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EMUXGRP0 - External Multiplexer Group for Interface x - 0 - 3 - read-write - - - EMUXGRP1 - External Multiplexer Group for Interface x - 4 - 7 - read-write - - - - - - - VADC_G0 - Analog to Digital Converter - VADC - VADC_G - 0x40004400 - - 0x0 - 0x400 - registers - - - - ARBCFG - Arbitration Configuration Register - 0x0080 - 32 - 0x00000000 - 0xFFFFFFFF - - - ANONC - Analog Converter Control - 0 - 1 - read-write - - - ARBRND - Arbitration Round Length - 4 - 5 - read-write - - - value1 - 4 arbitration slots per round (tARB = 4 / fADCD) - 0b00 - - - value2 - 8 arbitration slots per round (tARB = 8 / fADCD) - 0b01 - - - value3 - 16 arbitration slots per round (tARB = 16 / fADCD) - 0b10 - - - value4 - 20 arbitration slots per round (tARB = 20 / fADCD) - 0b11 - - - - - ARBM - Arbitration Mode - 7 - 7 - read-write - - - value1 - The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ). - 0b0 - - - value2 - The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported. - 0b1 - - - - - ANONS - Analog Converter Control Status - 16 - 17 - read-only - - - value1 - Analog converter off - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Normal operation (permanently on) - 0b11 - - - - - CAL - Start-Up Calibration Active Indication - 28 - 28 - read-only - - - value1 - Completed or not yet started - 0b0 - - - value2 - Start-up calibration phase is active - 0b1 - - - - - BUSY - Converter Busy Flag - 30 - 30 - read-only - - - value1 - Not busy - 0b0 - - - value2 - Converter is busy with a conversion - 0b1 - - - - - SAMPLE - Sample Phase Flag - 31 - 31 - read-only - - - value1 - Converting or idle - 0b0 - - - value2 - Input signal is currently sampled - 0b1 - - - - - - - ARBPR - Arbitration Priority Register - 0x0084 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIO0 - Priority of Request Source x - 0 - 1 - read-write - - - value1 - Lowest priority is selected. - 0b00 - - - value2 - Highest priority is selected. - 0b11 - - - - - PRIO1 - Priority of Request Source x - 4 - 5 - read-write - - - value1 - Lowest priority is selected. - 0b00 - - - value2 - Highest priority is selected. - 0b11 - - - - - PRIO2 - Priority of Request Source x - 8 - 9 - read-write - - - value1 - Lowest priority is selected. - 0b00 - - - value2 - Highest priority is selected. - 0b11 - - - - - CSM0 - Conversion Start Mode of Request Source x - 3 - 3 - read-write - - - value1 - Wait-for-start mode - 0b0 - - - value2 - Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. - 0b1 - - - - - CSM1 - Conversion Start Mode of Request Source x - 7 - 7 - read-write - - - value1 - Wait-for-start mode - 0b0 - - - value2 - Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. - 0b1 - - - - - CSM2 - Conversion Start Mode of Request Source x - 11 - 11 - read-write - - - value1 - Wait-for-start mode - 0b0 - - - value2 - Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. - 0b1 - - - - - ASEN0 - Arbitration Slot 0 Enable - 24 - 24 - read-write - - - value1 - The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. - 0b0 - - - value2 - The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. - 0b1 - - - - - ASEN1 - Arbitration Slot 1 Enable - 25 - 25 - read-write - - - value1 - The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. - 0b0 - - - value2 - The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. - 0b1 - - - - - ASEN2 - Arbitration Slot 2 Enable - 26 - 26 - read-write - - - value1 - The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. - 0b0 - - - value2 - The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. - 0b1 - - - - - - - CHASS - Channel Assignment Register - 0x0088 - 32 - 0x00000000 - 0xFFFFFFFF - - - ASSCH0 - Assignment for Channel 0 - 0 - 0 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH1 - Assignment for Channel 1 - 1 - 1 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH2 - Assignment for Channel 2 - 2 - 2 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH3 - Assignment for Channel 3 - 3 - 3 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH4 - Assignment for Channel 4 - 4 - 4 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH5 - Assignment for Channel 5 - 5 - 5 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH6 - Assignment for Channel 6 - 6 - 6 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH7 - Assignment for Channel 7 - 7 - 7 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - - - 2 - 4 - ICLASS[%s] - Input Class Register - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STCS - Sample Time Control for Standard Conversions - 0 - 4 - read-write - - - CMS - Conversion Mode for Standard Conversions - 8 - 10 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - STCE - Sample Time Control for EMUX Conversions - 16 - 20 - read-write - - - CME - Conversion Mode for EMUX Conversions - 24 - 26 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - - - ALIAS - Alias Register - 0x00B0 - 32 - 0x00000100 - 0xFFFFFFFF - - - ALIAS0 - Alias Value for CH0 Conversion Requests - 0 - 4 - read-write - - - ALIAS1 - Alias Value for CH1 Conversion Requests - 8 - 12 - read-write - - - - - BOUND - Boundary Select Register - 0x00B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOUNDARY0 - Boundary Value 0 for Limit Checking - 0 - 11 - read-write - - - BOUNDARY1 - Boundary Value 1 for Limit Checking - 16 - 27 - read-write - - - - - SYNCTR - Synchronization Control Register - 0x00C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STSEL - Start Selection - 0 - 1 - read-write - - - value1 - Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC - 0b00 - - - value2 - Kernel is synchronization slave: Control information from input CI1 - 0b01 - - - value3 - Kernel is synchronization slave: Control information from input CI2 - 0b10 - - - value4 - Kernel is synchronization slave: Control information from input CI3 - 0b11 - - - - - EVALR1 - Evaluate Ready Input Rx - 4 - 4 - read-write - - - value1 - No ready input control - 0b0 - - - value2 - Ready input Rx is considered for the start of a parallel conversion of this conversion group - 0b1 - - - - - EVALR2 - Evaluate Ready Input Rx - 5 - 5 - read-write - - - value1 - No ready input control - 0b0 - - - value2 - Ready input Rx is considered for the start of a parallel conversion of this conversion group - 0b1 - - - - - EVALR3 - Evaluate Ready Input Rx - 6 - 6 - read-write - - - value1 - No ready input control - 0b0 - - - value2 - Ready input Rx is considered for the start of a parallel conversion of this conversion group - 0b1 - - - - - - - BFL - Boundary Flag Register - 0x00C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BFL0 - Boundar0 Flag y - 0 - 0 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFL1 - Boundar1 Flag y - 1 - 1 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFL2 - Boundar2 Flag y - 2 - 2 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFL3 - Boundar3 Flag y - 3 - 3 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFE0 - Enable Bit for Boundar0 Flag y - 16 - 16 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - BFE1 - Enable Bit for Boundar1 Flag y - 17 - 17 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - BFE2 - Enable Bit for Boundar2 Flag y - 18 - 18 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - BFE3 - Enable Bit for Boundar3 Flag y - 19 - 19 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - - - QCTRL0 - Queue 0 Source Control Register - 0x0100 - 32 - 0x00000000 - 0xFFFFFFFF - - - XTSEL - External Trigger Input Selection - 8 - 11 - read-write - - - XTLVL - External Trigger Level - 12 - 12 - read-only - - - XTMODE - Trigger Operating Mode - 13 - 14 - read-write - - - value1 - No external trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon any edge - 0b11 - - - - - XTWC - Write Control for Trigger Configuration - 15 - 15 - write-only - - - value1 - No write access to trigger configuration - 0b0 - - - value2 - Bitfields XTMODE and XTSEL can be written - 0b1 - - - - - GTSEL - Gate Input Selection - 16 - 19 - read-write - - - GTLVL - Gate Input Level - 20 - 20 - read-only - - - GTWC - Write Control for Gate Configuration - 23 - 23 - write-only - - - value1 - No write access to gate configuration - 0b0 - - - value2 - Bitfield GTSEL can be written - 0b1 - - - - - TMEN - Timer Mode Enable - 28 - 28 - read-write - - - value1 - No timer mode: standard gating mechanism can be used - 0b0 - - - value2 - Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled - 0b1 - - - - - TMWC - Write Control for Timer Mode - 31 - 31 - write-only - - - value1 - No write access to timer mode - 0b0 - - - value2 - Bitfield TMEN can be written - 0b1 - - - - - - - QMR0 - Queue 0 Mode Register - 0x0104 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENGT - Enable Gate - 0 - 1 - read-write - - - value1 - No conversion requests are issued - 0b00 - - - value2 - Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register - 0b01 - - - value3 - Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1 - 0b10 - - - value4 - Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0 - 0b11 - - - - - ENTR - Enable External Trigger - 2 - 2 - read-write - - - value1 - External trigger disabled - 0b0 - - - value2 - The selected edge at the selected trigger input signal REQTR generates the trigger event - 0b1 - - - - - CLRV - Clear Valid Bit - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. - 0b1 - - - - - TREV - Trigger Event - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Generate a trigger event by software - 0b1 - - - - - FLUSH - Flush Queue - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry. - 0b1 - - - - - CEV - Clear Event Flag - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit EV - 0b1 - - - - - RPTDIS - Repeat Disable - 16 - 16 - read-write - - - value1 - A cancelled conversion is repeated - 0b0 - - - value2 - A cancelled conversion is discarded - 0b1 - - - - - - - QSR0 - Queue 0 Status Register - 0x0108 - 32 - 0x00000020 - 0xFFFFFFFF - - - FILL - Filling Level for Queue 2 - 0 - 3 - read-only - - - value1 - There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue - 0b0000 - - - value2 - There are 2 valid entries in the queue - 0b0001 - - - value3 - There are 3 valid entries in the queue - 0b0010 - - - value4 - There are 8 valid entries in the queue - 0b0111 - - - - - EMPTY - Queue Empty - 5 - 5 - read-only - - - value1 - There are valid entries in the queue (see FILL) - 0b0 - - - value2 - No valid entries (queue is empty) - 0b1 - - - - - REQGT - Request Gate Level - 7 - 7 - read-only - - - value1 - The gate input is low - 0b0 - - - value2 - The gate input is high - 0b1 - - - - - EV - Event Detected - 8 - 8 - read-only - - - value1 - No trigger event - 0b0 - - - value2 - A trigger event has been detected - 0b1 - - - - - - - Q0R0 - Queue 0 Register 0 - 0x010C - 32 - 0x00000000 - 0xFFFFFFFF - - - REQCHNR - Request Channel Number - 0 - 4 - read-only - - - RF - Refill - 5 - 5 - read-only - - - value1 - The request is discarded after the conversion start. - 0b0 - - - value2 - The request is automatically refilled into the queue after the conversion start. - 0b1 - - - - - ENSI - Enable Source Interrupt - 6 - 6 - read-only - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source event interrupt is generated upon a request source event (related conversion is finished) - 0b1 - - - - - EXTR - External Trigger - 7 - 7 - read-only - - - value1 - A valid queue entry immediately leads to a conversion request - 0b0 - - - value2 - The request handler waits for a trigger event - 0b1 - - - - - V - Request Channel Number Valid - 8 - 8 - read-only - - - value1 - No valid queue entry - 0b0 - - - value2 - The queue entry is valid and leads to a conversion request - 0b1 - - - - - - - QINR0 - Queue 0 Input Register - 0x0110 - 32 - 0x00000000 - 0xFFFFFFFF - - - REQCHNR - Request Channel Number - 0 - 4 - write-only - - - RF - Refill - 5 - 5 - write-only - - - value1 - No refill: this queue entry is converted once and then invalidated - 0b0 - - - value2 - Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started - 0b1 - - - - - ENSI - Enable Source Interrupt - 6 - 6 - write-only - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source event interrupt is generated upon a request source event (related conversion is finished) - 0b1 - - - - - EXTR - External Trigger - 7 - 7 - write-only - - - value1 - A valid queue entry immediately leads to a conversion request. - 0b0 - - - value2 - A valid queue entry waits for a trigger event to occur before issuing a conversion request. - 0b1 - - - - - - - QBUR0 - Queue 0 Backup Register - QINR0 - 0x0110 - 32 - 0x00000000 - 0xFFFFFFFF - - - REQCHNR - Request Channel Number - 0 - 4 - read-only - - - RF - Refill - 5 - 5 - read-only - - - ENSI - Enable Source Interrupt - 6 - 6 - read-only - - - EXTR - External Trigger - 7 - 7 - read-only - - - V - Request Channel Number Valid - 8 - 8 - read-only - - - value1 - Backup register not valid - 0b0 - - - value2 - Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested. - 0b1 - - - - - - - ASCTRL - Autoscan Source Control Register - 0x0120 - 32 - 0x00000000 - 0xFFFFFFFF - - - XTSEL - External Trigger Input Selection - 8 - 11 - read-write - - - XTLVL - External Trigger Level - 12 - 12 - read-only - - - XTMODE - Trigger Operating Mode - 13 - 14 - read-write - - - value1 - No external trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon any edge - 0b11 - - - - - XTWC - Write Control for Trigger Configuration - 15 - 15 - write-only - - - value1 - No write access to trigger configuration - 0b0 - - - value2 - Bitfields XTMODE and XTSEL can be written - 0b1 - - - - - GTSEL - Gate Input Selection - 16 - 19 - read-write - - - GTLVL - Gate Input Level - 20 - 20 - read-only - - - GTWC - Write Control for Gate Configuration - 23 - 23 - write-only - - - value1 - No write access to gate configuration - 0b0 - - - value2 - Bitfield GTSEL can be written - 0b1 - - - - - TMEN - Timer Mode Enable - 28 - 28 - read-write - - - value1 - No timer mode: standard gating mechanism can be used - 0b0 - - - value2 - Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled - 0b1 - - - - - TMWC - Write Control for Timer Mode - 31 - 31 - write-only - - - value1 - No write access to timer mode - 0b0 - - - value2 - Bitfield TMEN can be written - 0b1 - - - - - - - ASMR - Autoscan Source Mode Register - 0x0124 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENGT - Enable Gate - 0 - 1 - read-write - - - value1 - No conversion requests are issued - 0b00 - - - value2 - Conversion requests are issued if at least one pending bit is set - 0b01 - - - value3 - Conversion requests are issued if at least one pending bit is set and REQGTx = 1. - 0b10 - - - value4 - Conversion requests are issued if at least one pending bit is set and REQGTx = 0. - 0b11 - - - - - ENTR - Enable External Trigger - 2 - 2 - read-write - - - value1 - External trigger disabled - 0b0 - - - value2 - The selected edge at the selected trigger input signal REQTR generates the load event - 0b1 - - - - - ENSI - Enable Source Interrupt - 3 - 3 - read-write - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source interrupt is generated upon a request source event (last pending conversion is finished) - 0b1 - - - - - SCAN - Autoscan Enable - 4 - 4 - read-write - - - value1 - No autoscan - 0b0 - - - value2 - Autoscan functionality enabled: a request source event automatically generates a load event - 0b1 - - - - - LDM - Autoscan Source Load Event Mode - 5 - 5 - read-write - - - value1 - Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event - 0b0 - - - value2 - Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) - 0b1 - - - - - REQGT - Request Gate Level - 7 - 7 - read-only - - - value1 - The gate input is low - 0b0 - - - value2 - The gate input is high - 0b1 - - - - - CLRPND - Clear Pending Bits - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - The bits in register GxASPNDx are cleared - 0b1 - - - - - LDEV - Generate Load Event - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - A load event is generated - 0b1 - - - - - RPTDIS - Repeat Disable - 16 - 16 - read-write - - - value1 - A cancelled conversion is repeated - 0b0 - - - value2 - A cancelled conversion is discarded - 0b1 - - - - - - - ASSEL - Autoscan Source Channel Select Register - 0x0128 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHSEL0 - Channel Selection - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL1 - Channel Selection - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL2 - Channel Selection - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL3 - Channel Selection - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL4 - Channel Selection - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL5 - Channel Selection - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL6 - Channel Selection - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL7 - Channel Selection - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - - - ASPND - Autoscan Source Pending Register - 0x012C - 32 - 0x00000000 - 0xFFFFFFFF - - - CHPND0 - Channels Pending - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND1 - Channels Pending - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND2 - Channels Pending - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND3 - Channels Pending - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND4 - Channels Pending - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND5 - Channels Pending - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND6 - Channels Pending - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND7 - Channels Pending - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - - - CEFLAG - Channel Event Flag Register - 0x0180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CEV0 - Channel Event for Channel 0 - 0 - 0 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV1 - Channel Event for Channel 1 - 1 - 1 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV2 - Channel Event for Channel 2 - 2 - 2 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV3 - Channel Event for Channel 3 - 3 - 3 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV4 - Channel Event for Channel 4 - 4 - 4 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV5 - Channel Event for Channel 5 - 5 - 5 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV6 - Channel Event for Channel 6 - 6 - 6 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV7 - Channel Event for Channel 7 - 7 - 7 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - - - REFLAG - Result Event Flag Register - 0x0184 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV0 - Result Event for Result Register 0 - 0 - 0 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV1 - Result Event for Result Register 1 - 1 - 1 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV2 - Result Event for Result Register 2 - 2 - 2 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV3 - Result Event for Result Register 3 - 3 - 3 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV4 - Result Event for Result Register 4 - 4 - 4 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV5 - Result Event for Result Register 5 - 5 - 5 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV6 - Result Event for Result Register 6 - 6 - 6 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV7 - Result Event for Result Register 7 - 7 - 7 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV8 - Result Event for Result Register 8 - 8 - 8 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV9 - Result Event for Result Register 9 - 9 - 9 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV10 - Result Event for Result Register 10 - 10 - 10 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV11 - Result Event for Result Register 11 - 11 - 11 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV12 - Result Event for Result Register 12 - 12 - 12 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV13 - Result Event for Result Register 13 - 13 - 13 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV14 - Result Event for Result Register 14 - 14 - 14 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV15 - Result Event for Result Register 15 - 15 - 15 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - - - SEFLAG - Source Event Flag Register - 0x0188 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0 - Source Event 0/1 - 0 - 0 - read-write - - - value1 - No source event - 0b0 - - - value2 - A source event has occurred - 0b1 - - - - - SEV1 - Source Event 0/1 - 1 - 1 - read-write - - - value1 - No source event - 0b0 - - - value2 - A source event has occurred - 0b1 - - - - - - - CEFCLR - Channel Event Flag Clear Register - 0x0190 - 32 - 0x00000000 - 0xFFFFFFFF - - - CEV0 - Clear Channel Event for Channel 0 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV1 - Clear Channel Event for Channel 1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV2 - Clear Channel Event for Channel 2 - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV3 - Clear Channel Event for Channel 3 - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV4 - Clear Channel Event for Channel 4 - 4 - 4 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV5 - Clear Channel Event for Channel 5 - 5 - 5 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV6 - Clear Channel Event for Channel 6 - 6 - 6 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV7 - Clear Channel Event for Channel 7 - 7 - 7 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - - - REFCLR - Result Event Flag Clear Register - 0x0194 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV0 - Clear Result Event for Result Register 0 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV1 - Clear Result Event for Result Register 1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV2 - Clear Result Event for Result Register 2 - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV3 - Clear Result Event for Result Register 3 - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV4 - Clear Result Event for Result Register 4 - 4 - 4 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV5 - Clear Result Event for Result Register 5 - 5 - 5 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV6 - Clear Result Event for Result Register 6 - 6 - 6 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV7 - Clear Result Event for Result Register 7 - 7 - 7 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV8 - Clear Result Event for Result Register 8 - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV9 - Clear Result Event for Result Register 9 - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV10 - Clear Result Event for Result Register 10 - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV11 - Clear Result Event for Result Register 11 - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV12 - Clear Result Event for Result Register 12 - 12 - 12 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV13 - Clear Result Event for Result Register 13 - 13 - 13 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV14 - Clear Result Event for Result Register 14 - 14 - 14 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV15 - Clear Result Event for Result Register 15 - 15 - 15 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - - - SEFCLR - Source Event Flag Clear Register - 0x0198 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0 - Clear Source Event 0/1 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the source event flag in GxSEFLAG - 0b1 - - - - - SEV1 - Clear Source Event 0/1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the source event flag in GxSEFLAG - 0b1 - - - - - - - CEVNP0 - Channel Event Node Pointer Register 0 - 0x01A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CEV0NP - Service Request Node Pointer Channel Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV1NP - Service Request Node Pointer Channel Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV2NP - Service Request Node Pointer Channel Event i - 8 - 11 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV3NP - Service Request Node Pointer Channel Event i - 12 - 15 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV4NP - Service Request Node Pointer Channel Event i - 16 - 19 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV5NP - Service Request Node Pointer Channel Event i - 20 - 23 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV6NP - Service Request Node Pointer Channel Event i - 24 - 27 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV7NP - Service Request Node Pointer Channel Event i - 28 - 31 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - REVNP0 - Result Event Node Pointer Register 0 - 0x01B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV0NP - Service Request Node Pointer Result Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV1NP - Service Request Node Pointer Result Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV2NP - Service Request Node Pointer Result Event i - 8 - 11 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV3NP - Service Request Node Pointer Result Event i - 12 - 15 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV4NP - Service Request Node Pointer Result Event i - 16 - 19 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV5NP - Service Request Node Pointer Result Event i - 20 - 23 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV6NP - Service Request Node Pointer Result Event i - 24 - 27 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV7NP - Service Request Node Pointer Result Event i - 28 - 31 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - REVNP1 - Result Event Node Pointer Register 1 - 0x01B4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV8NP - Service Request Node Pointer Result Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV9NP - Service Request Node Pointer Result Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV10NP - Service Request Node Pointer Result Event i - 8 - 11 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV11NP - Service Request Node Pointer Result Event i - 12 - 15 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV12NP - Service Request Node Pointer Result Event i - 16 - 19 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV13NP - Service Request Node Pointer Result Event i - 20 - 23 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV14NP - Service Request Node Pointer Result Event i - 24 - 27 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV15NP - Service Request Node Pointer Result Event i - 28 - 31 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - SEVNP - Source Event Node Pointer Register - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0NP - Service Request Node Pointer Source Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - SEV1NP - Service Request Node Pointer Source Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - SRACT - Service Request Software Activation Trigger - 0x01C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - AGSR0 - Activate Group Service Request Node 0 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - AGSR1 - Activate Group Service Request Node 1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - AGSR2 - Activate Group Service Request Node 2 - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - AGSR3 - Activate Group Service Request Node 3 - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR0 - Activate Shared Service Request Node 0 - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR1 - Activate Shared Service Request Node 1 - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR2 - Activate Shared Service Request Node 2 - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR3 - Activate Shared Service Request Node 3 - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - - - EMUXCTR - External Multiplexer Control Register - 0x01F0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EMUXSET - External Multiplexer Start Selection - 0 - 2 - read-write - - - EMUXACT - External Multiplexer Actual Selection - 8 - 10 - read-only - - - EMUXCH - External Multiplexer Channel Select - 16 - 20 - read-write - - - EMUXMODE - External Multiplexer Mode - 26 - 27 - read-write - - - value1 - Software control (no hardware action) - 0b00 - - - value2 - Steady mode (use EMUXSET value) - 0b01 - - - value3 - Single-step mode - 0b10 - - - value4 - Sequence mode - 0b11 - - - - - EMXCOD - External Multiplexer Coding Scheme - 28 - 28 - read-write - - - value1 - Output the channel number in binary code - 0b0 - - - value2 - Output the channel number in Gray code - 0b1 - - - - - EMXST - External Multiplexer Sample Time Control - 29 - 29 - read-write - - - value1 - Use STCE whenever the setting changes - 0b0 - - - value2 - Use STCE for each conversion of an external channel - 0b1 - - - - - EMXWC - Write Control for EMUX Configuration - 31 - 31 - write-only - - - value1 - No write access to EMUX cfg. - 0b0 - - - value2 - Bitfields EMXMODE, EMXCOD, EMXST can be written - 0b1 - - - - - - - VFR - Valid Flag Register - 0x01F8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VF0 - Valid Flag of Result Register x - 0 - 0 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF1 - Valid Flag of Result Register x - 1 - 1 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF2 - Valid Flag of Result Register x - 2 - 2 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF3 - Valid Flag of Result Register x - 3 - 3 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF4 - Valid Flag of Result Register x - 4 - 4 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF5 - Valid Flag of Result Register x - 5 - 5 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF6 - Valid Flag of Result Register x - 6 - 6 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF7 - Valid Flag of Result Register x - 7 - 7 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF8 - Valid Flag of Result Register x - 8 - 8 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF9 - Valid Flag of Result Register x - 9 - 9 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF10 - Valid Flag of Result Register x - 10 - 10 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF11 - Valid Flag of Result Register x - 11 - 11 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF12 - Valid Flag of Result Register x - 12 - 12 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF13 - Valid Flag of Result Register x - 13 - 13 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF14 - Valid Flag of Result Register x - 14 - 14 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF15 - Valid Flag of Result Register x - 15 - 15 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - - - 8 - 4 - CHCTR[%s] - Channel Ctrl. Reg. - 0x0200 - 32 - 0x00000000 - 0xFFFFFFFF - - - ICLSEL - Input Class Select - 0 - 1 - read-write - - - value1 - Use group-specific class 0 - 0b00 - - - value2 - Use group-specific class 1 - 0b01 - - - value3 - Use global class 0 - 0b10 - - - value4 - Use global class 1 - 0b11 - - - - - BNDSELL - Lower Boundary Select - 4 - 5 - read-write - - - value1 - Use group-specific boundary 0 - 0b00 - - - value2 - Use group-specific boundary 1 - 0b01 - - - value3 - Use global boundary 0 - 0b10 - - - value4 - Use global boundary 1 - 0b11 - - - - - BNDSELU - Upper Boundary Select - 6 - 7 - read-write - - - value1 - Use group-specific boundary 0 - 0b00 - - - value2 - Use group-specific boundary 1 - 0b01 - - - value3 - Use global boundary 0 - 0b10 - - - value4 - Use global boundary 1 - 0b11 - - - - - CHEVMODE - Channel Event Mode - 8 - 9 - read-write - - - value1 - Never - 0b00 - - - value2 - NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) - 0b01 - - - value3 - NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) - 0b10 - - - value4 - NCM: Always (ignore band) FCM: If result switches to either level - 0b11 - - - - - SYNC - Synchronization Request - 10 - 10 - read-write - - - value1 - No synchroniz. request, standalone operation - 0b0 - - - value2 - Request a synchronized conversion of this channel (only taken into account for a master) - 0b1 - - - - - REFSEL - Reference Input Selection - 11 - 11 - read-write - - - value1 - Standard reference input VAREF - 0b0 - - - value2 - Alternate reference input from CH0 - 0b1 - - - - - RESREG - Result Register - 16 - 19 - read-write - - - value1 - Store result in group result register GxRES0 - 0b0000 - - - value2 - Store result in group result register GxRES15 - 0b1111 - - - - - RESTBS - Result Target for Background Source - 20 - 20 - read-write - - - value1 - Store results in the selected group result register - 0b0 - - - value2 - Store results in the global result register - 0b1 - - - - - RESPOS - Result Position - 21 - 21 - read-write - - - value1 - Store results left-aligned - 0b0 - - - value2 - Store results right-aligned - 0b1 - - - - - BWDCH - Broken Wire Detection Channel - 28 - 29 - read-write - - - value1 - Select VAGND - 0b00 - - - value2 - Select VAREF - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Reserved - 0b11 - - - - - BWDEN - Broken Wire Detection Enable - 30 - 30 - read-write - - - value1 - Normal operation - 0b0 - - - value2 - Additional preparation phase is enabled - 0b1 - - - - - - - 16 - 4 - RCR[%s] - Result Control Register - 0x0280 - 32 - 0x00000000 - 0xFFFFFFFF - - - DRCTR - Data Reduction Control - 16 - 19 - read-write - - - DMM - Data Modification Mode - 20 - 21 - read-write - - - value1 - Standard data reduction (accumulation) - 0b00 - - - value2 - Result filtering mode - 0b01 - - - value3 - Difference mode - 0b10 - - - value4 - Reserved - 0b11 - - - - - WFR - Wait-for-Read Mode Enable - 24 - 24 - read-write - - - value1 - Overwrite mode - 0b0 - - - value2 - Wait-for-read mode enabled for this register - 0b1 - - - - - FEN - FIFO Mode Enable - 25 - 26 - read-write - - - value1 - Separate result register - 0b00 - - - value2 - Part of a FIFO structure: copy each new valid result - 0b01 - - - value3 - Reserved - 0b10 - - - - - SRGEN - Service Request Generation Enable - 31 - 31 - read-write - - - value1 - No service request - 0b0 - - - value2 - Service request after a result event - 0b1 - - - - - - - 16 - 4 - RES[%s] - Result Register - 0x0300 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of Most Recent Conversion - 0 - 15 - read-write - - - DRC - Data Reduction Counter - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - value1 - Request source 0 - 0b00 - - - value2 - Request source 1 - 0b01 - - - value3 - Request source 2 - 0b10 - - - value4 - Reserved - 0b11 - - - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-only - - - value1 - No new result available - 0b0 - - - value2 - Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated - 0b1 - - - - - - - 16 - 4 - RESD[%s] - Result Register, Debug - 0x0380 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of Most Recent Conversion - 0 - 15 - read-only - - - DRC - Data Reduction Counter - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - value1 - Request source 0 - 0b00 - - - value2 - Request source 1 - 0b01 - - - value3 - Request source 2 - 0b10 - - - value4 - Reserved - 0b11 - - - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-only - - - value1 - No new result available - 0b0 - - - value2 - Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated - 0b1 - - - - - - - - - VADC_G1 - Analog to Digital Converter - VADC - 0x40004800 - - 0x0 - 0x400 - registers - - - - VADC_G2 - Analog to Digital Converter - VADC - 0x40004C00 - - 0x0 - 0x400 - registers - - - - VADC_G3 - Analog to Digital Converter - VADC - 0x40005000 - - 0x0 - 0x400 - registers - - - - DSD - Delta Sigma Demodulator - DSD - 0x40008000 - - 0x0 - 0x4000 - registers - - - - CLC - Clock Control Register - 0x0000 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - value1 - On request: enable the module clock - 0b0 - - - value2 - Off request: stop the module clock - 0b1 - - - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - value1 - Module clock is enabled - 0b0 - - - value2 - Off: module is not clocked - 0b1 - - - - - EDIS - Sleep Mode Enable Control - 3 - 3 - read-write - - - value1 - Sleep mode request is enabled and functional - 0b0 - - - value2 - Module disregards the sleep mode control signal - 0b1 - - - - - - - ID - Module Identification Register - 0x0008 - 32 - 0x00A4C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - OCS - OCDS Control and Status Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUS - OCDS Suspend Control - 24 - 27 - read-write - - - value1 - Will not suspend - 0b0000 - - - value2 - Hard suspend: Clock is switched off immediately. - 0b0001 - - - value3 - Soft suspend channel 0 - 0b0010 - - - value4 - Soft suspend channel 1 - 0b0011 - - - value5 - Soft suspend channel 3 - 0b0101 - - - - - SUS_P - SUS Write Protection - 28 - 28 - write-only - - - SUSSTA - Suspend State - 29 - 29 - read-only - - - value1 - Module is not (yet) suspended - 0b0 - - - value2 - Module is suspended - 0b1 - - - - - - - GLOBCFG - Global Configuration Register - 0x0080 - 32 - 0x00000000 - 0xFFFFFFFF - - - MCSEL - Modulator Clock Select - 0 - 2 - read-write - - - value1 - Internal clock off, no source selected - 0b000 - - - value2 - fDSD - 0b001 - - - - - - - GLOBRC - Global Run Control Register - 0x0088 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0RUN - Channel 0 Run Control - 0 - 0 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - CH1RUN - Channel 1 Run Control - 1 - 1 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - CH2RUN - Channel 2 Run Control - 2 - 2 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - CH3RUN - Channel 3 Run Control - 3 - 3 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - - - CGCFG - Carrier Generator Configuration Register - 0x00A0 - 32 - 0x07100000 - 0xFFFFFFFF - - - CGMOD - Carrier Generator Operating Mode - 0 - 1 - read-write - - - value1 - Stopped - 0b00 - - - value2 - Square wave - 0b01 - - - value3 - Triangle - 0b10 - - - value4 - Sine wave - 0b11 - - - - - BREV - Bit-Reverse PWM Generation - 2 - 2 - read-write - - - value1 - Normal mode - 0b0 - - - value2 - Bit-reverse mode - 0b1 - - - - - SIGPOL - Signal Polarity - 3 - 3 - read-write - - - value1 - Normal: carrier signal begins with +1 - 0b0 - - - value2 - Inverted: carrier signal begins with -1 - 0b1 - - - - - DIVCG - Divider Factor for the PWM Pattern Signal Generator - 4 - 7 - read-write - - - value1 - fCG = fCLK / 2 - 0x0 - - - value2 - fCG = fCLK / 4 - 0x1 - - - value3 - fCG = fCLK / 6 - 0x2 - - - value4 - fCG = fCLK / 32 - 0xF - - - - - RUN - Run Indicator - 15 - 15 - read-only - - - value1 - Stopped (cleared at the end of a period) - 0b0 - - - value2 - Running - 0b1 - - - - - BITCOUNT - Bit Counter - 16 - 20 - read-only - - - STEPCOUNT - Step Counter - 24 - 27 - read-only - - - STEPS - Step Counter Sign - 28 - 28 - read-only - - - value1 - Step counter value is positive - 0b0 - - - value2 - Step counter value is negative - 0b1 - - - - - STEPD - Step Counter Direction - 29 - 29 - read-only - - - value1 - Step counter is counting up - 0b0 - - - value2 - Step counter is counting down - 0b1 - - - - - SGNCG - Sign Signal from Carrier Generator - 30 - 30 - read-only - - - value1 - Positive values - 0b0 - - - value2 - Negative values - 0b1 - - - - - - - EVFLAG - Event Flag Register - 0x00E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESEV0 - Result Event - 0 - 0 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - RESEV1 - Result Event - 1 - 1 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - RESEV2 - Result Event - 2 - 2 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - RESEV3 - Result Event - 3 - 3 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - ALEV0 - Alarm Event - 16 - 16 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV1 - Alarm Event - 17 - 17 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV2 - Alarm Event - 18 - 18 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV3 - Alarm Event - 19 - 19 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV4 - Alarm Event - 20 - 20 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV5 - Alarm Event - 21 - 21 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV6 - Alarm Event - 22 - 22 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV7 - Alarm Event - 23 - 23 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV8 - Alarm Event - 24 - 24 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV9 - Alarm Event - 25 - 25 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - - - EVFLAGCLR - Event Flag Clear Register - 0x00E4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESEC0 - Result Event Clear - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - RESEC1 - Result Event Clear - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - RESEC2 - Result Event Clear - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - RESEC3 - Result Event Clear - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - ALEC0 - Alarm Event Clear - 16 - 16 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - ALEC1 - Alarm Event Clear - 17 - 17 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - ALEC2 - Alarm Event Clear - 18 - 18 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - ALEC3 - Alarm Event Clear - 19 - 19 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - - - - - DSD_CH0 - Delta Sigma Demodulator - DSD - DSD_CH - 0x40008100 - - 0x0 - 0x100 - registers - - - - MODCFG - Modulator Configuration Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIVM - Divider Factor for Modulator Clock - 16 - 19 - read-write - - - value1 - fMOD = fCLK / 2 - 0x0 - - - value2 - fMOD = fCLK / 4 - 0x1 - - - value3 - fMOD = fCLK / 6 - 0x2 - - - value4 - fMOD = fCLK / 32 - 0xF - - - - - DWC - Write Control for Divider Factor - 23 - 23 - write-only - - - value1 - No write access to divider factor - 0b0 - - - value2 - Bitfield DIVM can be written - 0b1 - - - - - - - DICFG - Demodulator Input Configuration Register - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSRC - Input Data Source Select - 0 - 3 - read-write - - - value1 - Disconnected - 0b000X - - - value2 - External, from input A, direct - 0b0010 - - - value3 - External, from input A, inverted - 0b0011 - - - value4 - External, from input B, direct - 0b0100 - - - value5 - External, from input B, inverted - 0b0101 - - - - - DSWC - Write Control for Data Selection - 7 - 7 - write-only - - - value1 - No write access to data parameters - 0b0 - - - value2 - Bitfield DSRC can be written - 0b1 - - - - - ITRMODE - Integrator Trigger Mode - 8 - 9 - read-write - - - value1 - No integration trigger, integrator bypassed - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - No trigger, integrator active all the time - 0b11 - - - - - TSTRMODE - Timestamp Trigger Mode - 10 - 11 - read-write - - - value1 - No timestamp trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon each edge - 0b11 - - - - - TRSEL - Trigger Select - 12 - 14 - read-write - - - TRWC - Write Control for Trigger Parameters - 15 - 15 - write-only - - - value1 - No write access to trigger parameters - 0b0 - - - value2 - Bitfields TRSEL, TSTRMODE, ITRMODE can be written - 0b1 - - - - - CSRC - Sample Clock Source Select - 16 - 19 - read-write - - - value1 - Reserved - 0b0000 - - - value2 - External, from input A - 0b0001 - - - value3 - External, from input B - 0b0010 - - - value4 - Internal clock - 0b1111 - - - - - STROBE - Data Strobe Generatoion Mode - 20 - 23 - read-write - - - value1 - No data strobe - 0b0000 - - - value2 - Direct clock, a sample trigger is generated at each rising clock edge - 0b0001 - - - value3 - Direct clock, a sample trigger is generated at each falling clock edge - 0b0010 - - - value4 - Double data, a sample trigger is generated at each rising and falling clock edge - 0b0011 - - - value5 - Reserved - 0b0100 - - - value6 - Double clock, a sample trigger is generated at every 2nd rising clock edge - 0b0101 - - - value7 - Double clock, a sample trigger is generated at every 2nd falling clock edge - 0b0110 - - - value8 - Reserved - 0b0111 - - - - - SCWC - Write Control for Strobe/Clock Selection - 31 - 31 - write-only - - - value1 - No write access to strobe/clock parameters - 0b0 - - - value2 - Bitfields STROBE, CSRC can be written - 0b1 - - - - - - - FCFGC - Filter Configuration Register, Main Comb Filter - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFMDF - CIC Filter (Main Chain) Decimation Factor - 0 - 7 - read-write - - - CFMC - CIC Filter (Main Chain) Configuration - 8 - 9 - read-write - - - value1 - CIC1 - 0b00 - - - value2 - CIC2 - 0b01 - - - value3 - CIC3 - 0b10 - - - value4 - CICF - 0b11 - - - - - CFEN - CIC Filter Enable - 10 - 10 - read-write - - - value1 - CIC filter disabled and bypassed - 0b0 - - - value2 - Enable CIC filter - 0b1 - - - - - SRGM - Service Request Generation Main Chain - 14 - 15 - read-write - - - value1 - Never, service requests disabled - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Always, for each new result value - 0b11 - - - - - CFMSV - CIC Filter (Main Chain) Start Value - 16 - 23 - read-write - - - CFMDCNT - CIC Filter (Main Chain) Decimation Counter - 24 - 31 - read-only - - - - - FCFGA - Filter Configuration Register, Auxiliary Filter - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFADF - CIC Filter (Auxiliary) Decimation Factor - 0 - 7 - read-write - - - CFAC - CIC Filter (Auxiliary) Configuration - 8 - 9 - read-write - - - value1 - CIC1 - 0b00 - - - value2 - CIC2 - 0b01 - - - value3 - CIC3 - 0b10 - - - value4 - CICF - 0b11 - - - - - SRGA - Service Request Generation Auxiliary Filter - 10 - 11 - read-write - - - value1 - Never, service requests disabled - 0b00 - - - value2 - Auxiliary filter: As selected by bitfield ESEL - 0b01 - - - value3 - Alternate source: Capturing of a sign delay value to register CGSYNCx (x = 0 - 3) - 0b10 - - - value4 - Reserved - 0b11 - - - - - ESEL - Event Select - 12 - 13 - read-write - - - value1 - Always, for each new result value - 0b00 - - - value2 - If result is inside the boundary band - 0b01 - - - value3 - If result is outside the boundary band - 0b10 - - - value4 - Reserved - 0b11 - - - - - EGT - Event Gating - 14 - 14 - read-write - - - value1 - Separate: generate events according to ESEL - 0b0 - - - value2 - Coupled: generate events only when the integrator is enabled and after the discard phase defined by bitfield NVALDIS - 0b1 - - - - - CFADCNT - CIC Filter (Auxiliary) Decimation Counter - 24 - 31 - read-only - - - - - IWCTR - Integration Window Control Register - 0x0020 - 32 - 0x00000000 - 0xFFFFFFFF - - - NVALCNT - Number of Values Counted - 0 - 5 - read-only - - - INTEN - Integration Enable - 7 - 7 - read-only - - - value1 - Integration stopped. INTEN is cleared at the end of the integration window, i.e. upon the inverse trigger event transition of the external trigger signal. - 0b0 - - - value2 - Integration enabled. INTEN is set upon the defined trigger event. - 0b1 - - - - - REPCNT - Integration Cycle Counter - 8 - 11 - read-only - - - REPVAL - Number of Integration Cycles - 12 - 15 - read-write - - - NVALDIS - Number of Values Discarded - 16 - 21 - read-write - - - IWS - Integration Window SIze - 23 - 23 - read-write - - - value1 - Internal control: stop integrator after REPVAL+1 integration cycles - 0b0 - - - value2 - External control: stop integrator when bit INTEN becomes 0 - 0b1 - - - - - NVALINT - Number of Values Integrated - 24 - 29 - read-write - - - - - BOUNDSEL - Boundary Select Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOUNDARYL - Lower Boundary Value for Limit Checking - 0 - 15 - read-write - - - BOUNDARYU - Upper Boundary Value for Limit Checking - 16 - 31 - read-write - - - - - RESM - Result Register, Main Filter - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-only - - - - - OFFM - Offset Register, Main Filter - 0x0038 - 32 - 0x00000000 - 0xFFFFFFFF - - - OFFSET - Offset Value - 0 - 15 - read-write - - - - - RESA - Result Register, Auxiliary Filter - 0x0040 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-only - - - - - TSTMP - Time-Stamp Register - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-only - - - CFMDCNT - CIC Filter (Main Chain) Decimation Counter - 16 - 23 - read-only - - - NVALCNT - Number of Values Counted - 24 - 29 - read-only - - - - - CGSYNC - Carrier Generator Synchronization Register - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SDCOUNT - Sign Delay Counter - 0 - 7 - read-only - - - SDCAP - Sign Delay Capture Value - 8 - 15 - read-only - - - SDPOS - Sign Delay Value for Positive Halfwave - 16 - 23 - read-write - - - SDNEG - Sign Delay Value for Negative Halfwave - 24 - 31 - read-write - - - - - RECTCFG - Rectification Configuration Register - 0x00A8 - 32 - 0x80000000 - 0xFFFFFFFF - - - RFEN - Rectification Enable - 0 - 0 - read-write - - - value1 - No rectification, data not altered - 0b0 - - - value2 - Data are rectified according to SGND - 0b1 - - - - - SSRC - Sign Source - 4 - 5 - read-write - - - value1 - On-chip carrier generator - 0b00 - - - value2 - Sign of result of next channel - 0b01 - - - value3 - External sign signal A - 0b10 - - - value4 - External sign signal B - 0b11 - - - - - SDVAL - Valid Flag - 15 - 15 - read-only - - - value1 - No new result available - 0b0 - - - value2 - Bitfield SDCAP has been updated with a new captured value and has not yet been read - 0b1 - - - - - SGNCS - Selected Carrier Sign Signal - 30 - 30 - read-only - - - value1 - Positive values - 0b0 - - - value2 - Negative values - 0b1 - - - - - SGND - Sign Signal Delayed - 31 - 31 - read-only - - - value1 - Positive values - 0b0 - - - value2 - Negative values - 0b1 - - - - - - - - - DSD_CH1 - Delta Sigma Demodulator - DSD - 0x40008200 - - 0x0 - 0x100 - registers - - - - DSD_CH2 - Delta Sigma Demodulator - DSD - 0x40008300 - - 0x0 - 0x100 - registers - - - - DSD_CH3 - Delta Sigma Demodulator - DSD - 0x40008400 - - 0x0 - 0x100 - registers - - - - DAC - Digital to Analog Converter - 0x48018000 - - 0x0 - 0x4000 - registers - - - - ID - Module Identification Register - 0x000 - 32 - 0x00A5C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - DAC0CFG0 - DAC0 Configuration Register 0 - 0x004 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQ - Integer Frequency Divider Value - 0 - 19 - read-write - - - MODE - Enables and Sets the Mode for DAC0 - 20 - 22 - read-write - - - value1 - disable/switch-off DAC - 0b000 - - - value2 - Single Value Mode - 0b001 - - - value3 - Data Mode - 0b010 - - - value4 - Patgen Mode - 0b011 - - - value5 - Noise Mode - 0b100 - - - value6 - Ramp Mode - 0b101 - - - value7 - na - 0b110 - - - value8 - na - 0b111 - - - - - SIGN - Selects Between Signed and Unsigned DAC0 Mode - 23 - 23 - read-write - - - value1 - DAC expects unsigned input data - 0b0 - - - value2 - DAC expects signed input data - 0b1 - - - - - FIFOIND - Current write position inside the data FIFO - 24 - 25 - read-only - - - FIFOEMP - Indicate if the FIFO is empty - 26 - 26 - read-only - - - value1 - FIFO not empty - 0b0 - - - value2 - FIFO empty - 0b1 - - - - - FIFOFUL - Indicate if the FIFO is full - 27 - 27 - read-only - - - value1 - FIFO not full - 0b0 - - - value2 - FIFO full - 0b1 - - - - - SIGNEN - Enable Sign Output of DAC0 Pattern Generator - 29 - 29 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - SREN - Enable DAC0 service request interrupt generation - 30 - 30 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - RUN - RUN indicates the current DAC0 operation status - 31 - 31 - read-only - - - value1 - DAC0 channel disabled - 0b0 - - - value2 - DAC0 channel in operation - 0b1 - - - - - - - DAC0CFG1 - DAC0 Configuration Register 1 - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCALE - Scale value for up- or downscale of the DAC0 input data in steps by the power of 2 (=shift operation) - 0 - 2 - read-write - - - value1 - no shift = multiplication/division by 1 - 0b000 - - - value2 - shift by 1 = multiplication/division by 2 - 0b001 - - - value3 - shift by 2 = multiplication/division by 4 - 0b010 - - - value4 - shift left by 3 = multiplication/division by 8 - 0b011 - - - value5 - shift left by 4 = multiplication/division by 16 - 0b100 - - - value6 - shift left by 5 = multiplication/division by 32 - 0b101 - - - value7 - shift left by 6 = multiplication/division by 64 - 0b110 - - - value8 - shift left by 7 = multiplication/division by 128 - 0b111 - - - - - MULDIV - Switch between up- and downscale of the DAC0 input data values - 3 - 3 - read-write - - - value1 - downscale = division (shift SCALE positions to the right) - 0b0 - - - value2 - upscale = multiplication (shift SCALE positions to the left) - 0b1 - - - - - OFFS - 8-bit offset value addition - 4 - 11 - read-write - - - TRIGSEL - Selects one of the eight external trigger sources for DAC0 - 12 - 14 - read-write - - - DATMOD - Switch between independent or simultaneous DAC mode and select the input data register for DAC0 and DAC1 - 15 - 15 - read-write - - - value1 - independent data handling - process data from DATA0 register (bits 11:0) to DAC0 and data from DATA1 register (bits 11:0) to DAC1 - 0b0 - - - value2 - simultaneous data handling - process data from DAC01 register to both DACs (bits 11:0 to DAC0 and bits 23:12 to DAC1). - 0b1 - - - - - SWTRIG - Software Trigger - 16 - 16 - read-write - - - TRIGMOD - Select the trigger source for channel 0 - 17 - 18 - read-write - - - value1 - internal Trigger (integer divided clock - see FREQ parameter) - 0b00 - - - value2 - external Trigger (preselected trigger by TRIGSEL parameter) - 0b01 - - - value3 - software Trigger (see SWTRIG parameter) - 0b10 - - - value4 - reserved - 0b11 - - - - - ANACFG - DAC0 analog configuration/calibration parameters - 19 - 23 - read-write - - - ANAEN - Enable analog DAC for channel 0 - 24 - 24 - read-write - - - value1 - DAC0 is set to standby (analog output only) - 0b0 - - - value2 - enable DAC0 (analog output only) - 0b1 - - - - - REFCFGL - Lower 4 band-gap configuration/calibration parameters - 28 - 31 - read-write - - - - - DAC1CFG0 - DAC1 Configuration Register 0 - 0x00C - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQ - Integer Frequency Divider Value - 0 - 19 - read-write - - - MODE - Enables and sets the Mode for DAC1 - 20 - 22 - read-write - - - value1 - disable/switch-off DAC - 0b000 - - - value2 - Single Value Mode - 0b001 - - - value3 - Data Mode - 0b010 - - - value4 - Patgen Mode - 0b011 - - - value5 - Noise Mode - 0b100 - - - value6 - Ramp Mode - 0b101 - - - value7 - na - 0b110 - - - value8 - na - 0b111 - - - - - SIGN - Selects between signed and unsigned DAC1 mode - 23 - 23 - read-write - - - value1 - DAC expects unsigned input data - 0b0 - - - value2 - DAC expects signed input data - 0b1 - - - - - FIFOIND - Current write position inside the data FIFO - 24 - 25 - read-only - - - FIFOEMP - Indicate if the FIFO is empty - 26 - 26 - read-only - - - value1 - FIFO not empty - 0b0 - - - value2 - FIFO empty - 0b1 - - - - - FIFOFUL - Indicate if the FIFO is full - 27 - 27 - read-only - - - value1 - FIFO not full - 0b0 - - - value2 - FIFO full - 0b1 - - - - - SIGNEN - Enable sign output of DAC1 pattern generator - 29 - 29 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - SREN - Enable DAC1 service request interrupt generation - 30 - 30 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - RUN - RUN indicates the current DAC1 operation status - 31 - 31 - read-only - - - value1 - DAC1 channel disabled - 0b0 - - - value2 - DAC1 channel in operation - 0b1 - - - - - - - DAC1CFG1 - DAC1 Configuration Register 1 - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCALE - Scale value for up- or downscale of the DAC1 input data in steps by the power of 2 (=shift operation) - 0 - 2 - read-write - - - value1 - no shift = multiplication/division by 1 - 0b000 - - - value2 - shift by 1 = multiplication/division by 2 - 0b001 - - - value3 - shift by 2 = multiplication/division by 4 - 0b010 - - - value4 - shift left by 3 = multiplication/division by 8 - 0b011 - - - value5 - shift left by 4 = multiplication/division by 16 - 0b100 - - - value6 - shift left by 5 = multiplication/division by 32 - 0b101 - - - value7 - shift left by 6 = multiplication/division by 64 - 0b110 - - - value8 - shift left by 7 = multiplication/division by 128 - 0b111 - - - - - MULDIV - Switch between up- and downscale of the DAC1 input data values - 3 - 3 - read-write - - - value1 - downscale = division (shift SCALE positions to the right) - 0b0 - - - value2 - upscale = multiplication (shift SCALE positions to the left) - 0b1 - - - - - OFFS - 8-bit offset value addition - 4 - 11 - read-write - - - TRIGSEL - Selects one of the eight external trigger sources for DAC1 - 12 - 14 - read-write - - - SWTRIG - Software Trigger - 16 - 16 - read-write - - - TRIGMOD - Select the trigger source for channel 1 - 17 - 18 - read-write - - - value1 - internal Trigger (integer divided clock - see FREQ parameter) - 0b00 - - - value2 - external Trigger (preselected trigger by TRIGSEL parameter) - 0b01 - - - value3 - software Trigger (see SWTRIG parameter) - 0b10 - - - value4 - reserved - 0b11 - - - - - ANACFG - DAC1 analog configuration/calibration parameters - 19 - 23 - read-write - - - ANAEN - Enable analog DAC for channel 1 - 24 - 24 - read-write - - - value1 - DAC1 is set to standby (analog output only) - 0b0 - - - value2 - enable DAC1 (analog output only) - 0b1 - - - - - REFCFGH - Higher 4 band-gap configuration/calibration parameters - 28 - 31 - read-write - - - - - DAC0DATA - DAC0 Data Register - 0x014 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA0 - DAC0 Data Bits - 0 - 11 - read-write - - - - - DAC1DATA - DAC1 Data Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA1 - DAC1 Data Bits - 0 - 11 - read-write - - - - - DAC01DATA - DAC01 Data Register - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA0 - DAC0 Data Bits - 0 - 11 - read-write - - - DATA1 - DAC1 Data Bits - 16 - 27 - read-write - - - - - DAC0PATL - DAC0 Lower Pattern Register - 0x020 - 32 - 0x3568B0C0 - 0xFFFFFFFF - - - PAT0 - Pattern Number 0 for PATGEN of DAC0 - 0 - 4 - read-write - - - PAT1 - Pattern Number 1 for PATGEN of DAC0 - 5 - 9 - read-write - - - PAT2 - Pattern Number 2 for PATGEN of DAC0 - 10 - 14 - read-write - - - PAT3 - Pattern Number 3 for PATGEN of DAC0 - 15 - 19 - read-write - - - PAT4 - Pattern Number 4 for PATGEN of DAC0 - 20 - 24 - read-write - - - PAT5 - Pattern Number 5 for PATGEN of DAC0 - 25 - 29 - read-write - - - - - DAC0PATH - DAC0 Higher Pattern Register - 0x024 - 32 - 0x00007FDD - 0xFFFFFFFF - - - PAT6 - Pattern Number 6 for PATGEN of DAC0 - 0 - 4 - read-write - - - PAT7 - Pattern Number 7 for PATGEN of DAC0 - 5 - 9 - read-write - - - PAT8 - Pattern Number 8 for PATGEN of DAC0 - 10 - 14 - read-write - - - - - DAC1PATL - DAC1 Lower Pattern Register - 0x028 - 32 - 0x3568B0C0 - 0xFFFFFFFF - - - PAT0 - Pattern Number 0 for PATGEN of DAC1 - 0 - 4 - read-write - - - PAT1 - Pattern Number 1 for PATGEN of DAC1 - 5 - 9 - read-write - - - PAT2 - Pattern Number 2 for PATGEN of DAC1 - 10 - 14 - read-write - - - PAT3 - Pattern Number 3 for PATGEN of DAC1 - 15 - 19 - read-write - - - PAT4 - Pattern Number 4 for PATGEN of DAC1 - 20 - 24 - read-write - - - PAT5 - Pattern Number 5 for PATGEN of DAC1 - 25 - 29 - read-write - - - - - DAC1PATH - DAC1 Higher Pattern Register - 0x02C - 32 - 0x00007FDD - 0xFFFFFFFF - - - PAT6 - Pattern Number 6 for PATGEN of DAC1 - 0 - 4 - read-write - - - PAT7 - Pattern Number 7 for PATGEN of DAC1 - 5 - 9 - read-write - - - PAT8 - Pattern Number 8 for PATGEN of DAC1 - 10 - 14 - read-write - - - - - - - CCU40 - Capture Compare Unit 4 - Unit 0 - CCU4 - CCU4 - 0x4000C000 - - 0x0 - 0x4000 - registers - - - - GCTRL - Global Control Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRBC - Prescaler Clear Configuration - 0 - 2 - read-write - - - value1 - SW only - 0b000 - - - value2 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared. - 0b001 - - - value3 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared. - 0b010 - - - value4 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared. - 0b011 - - - value5 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared. - 0b100 - - - - - PCIS - Prescaler Input Clock Selection - 4 - 5 - read-write - - - value1 - Module clock - 0b00 - - - value2 - CCU4x.ECLKA - 0b01 - - - value3 - CCU4x.ECLKB - 0b10 - - - value4 - CCU4x.ECLKC - 0b11 - - - - - SUSCFG - Suspend Mode Configuration - 8 - 9 - read-write - - - value1 - Suspend request ignored. The module never enters in suspend - 0b00 - - - value2 - Stops all the running slices immediately. Safe stop is not applied. - 0b01 - - - value3 - Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. - 0b10 - - - value4 - Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. - 0b11 - - - - - MSE0 - Slice 0 Multi Channel shadow transfer enable - 10 - 10 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSE1 - Slice 1 Multi Channel shadow transfer enable - 11 - 11 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSE2 - Slice 2 Multi Channel shadow transfer enable - 12 - 12 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSE3 - Slice 3 Multi Channel shadow transfer enable - 13 - 13 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSDE - Multi Channel shadow transfer request configuration - 14 - 15 - read-write - - - value1 - Only the shadow transfer for period and compare values is requested - 0b00 - - - value2 - Shadow transfer for the compare, period and prescaler compare values is requested - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Shadow transfer for the compare, period, prescaler and dither compare values is requested - 0b11 - - - - - - - GSTAT - Global Status Register - 0x0004 - 32 - 0x0000000F - 0xFFFFFFFF - - - S0I - CC40 IDLE status - 0 - 0 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S1I - CC41 IDLE status - 1 - 1 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S2I - CC42 IDLE status - 2 - 2 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S3I - CC43 IDLE status - 3 - 3 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - PRB - Prescaler Run Bit - 8 - 8 - read-only - - - value1 - Prescaler is stopped - 0b0 - - - value2 - Prescaler is running - 0b1 - - - - - - - GIDLS - Global Idle Set - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SS0I - CC40 IDLE mode set - 0 - 0 - write-only - - - SS1I - CC41 IDLE mode set - 1 - 1 - write-only - - - SS2I - CC42 IDLE mode set - 2 - 2 - write-only - - - SS3I - CC43 IDLE mode set - 3 - 3 - write-only - - - CPRB - Prescaler Run Bit Clear - 8 - 8 - write-only - - - PSIC - Prescaler clear - 9 - 9 - write-only - - - - - GIDLC - Global Idle Clear - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - CS0I - CC40 IDLE mode clear - 0 - 0 - write-only - - - CS1I - CC41 IDLE mode clear - 1 - 1 - write-only - - - CS2I - CC42 IDLE mode clear - 2 - 2 - write-only - - - CS3I - CC43 IDLE mode clear - 3 - 3 - write-only - - - SPRB - Prescaler Run Bit Set - 8 - 8 - write-only - - - - - GCSS - Global Channel Set - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SE - Slice 0 shadow transfer set enable - 0 - 0 - write-only - - - S0DSE - Slice 0 Dither shadow transfer set enable - 1 - 1 - write-only - - - S0PSE - Slice 0 Prescaler shadow transfer set enable - 2 - 2 - write-only - - - S1SE - Slice 1 shadow transfer set enable - 4 - 4 - write-only - - - S1DSE - Slice 1 Dither shadow transfer set enable - 5 - 5 - write-only - - - S1PSE - Slice 1 Prescaler shadow transfer set enable - 6 - 6 - write-only - - - S2SE - Slice 2 shadow transfer set enable - 8 - 8 - write-only - - - S2DSE - Slice 2 Dither shadow transfer set enable - 9 - 9 - write-only - - - S2PSE - Slice 2 Prescaler shadow transfer set enable - 10 - 10 - write-only - - - S3SE - Slice 3 shadow transfer set enable - 12 - 12 - write-only - - - S3DSE - Slice 3 Dither shadow transfer set enable - 13 - 13 - write-only - - - S3PSE - Slice 3 Prescaler shadow transfer set enable - 14 - 14 - write-only - - - S0STS - Slice 0 status bit set - 16 - 16 - write-only - - - S1STS - Slice 1 status bit set - 17 - 17 - write-only - - - S2STS - Slice 2 status bit set - 18 - 18 - write-only - - - S3STS - Slice 3 status bit set - 19 - 19 - write-only - - - - - GCSC - Global Channel Clear - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SC - Slice 0 shadow transfer clear - 0 - 0 - write-only - - - S0DSC - Slice 0 Dither shadow transfer clear - 1 - 1 - write-only - - - S0PSC - Slice 0 Prescaler shadow transfer clear - 2 - 2 - write-only - - - S1SC - Slice 1 shadow transfer clear - 4 - 4 - write-only - - - S1DSC - Slice 1 Dither shadow transfer clear - 5 - 5 - write-only - - - S1PSC - Slice 1 Prescaler shadow transfer clear - 6 - 6 - write-only - - - S2SC - Slice 2 shadow transfer clear - 8 - 8 - write-only - - - S2DSC - Slice 2 Dither shadow transfer clear - 9 - 9 - write-only - - - S2PSC - Slice 2 Prescaler shadow transfer clear - 10 - 10 - write-only - - - S3SC - Slice 3 shadow transfer clear - 12 - 12 - write-only - - - S3DSC - Slice 3 Dither shadow transfer clear - 13 - 13 - write-only - - - S3PSC - Slice 3 Prescaler shadow transfer clear - 14 - 14 - write-only - - - S0STC - Slice 0 status bit clear - 16 - 16 - write-only - - - S1STC - Slice 1 status bit clear - 17 - 17 - write-only - - - S2STC - Slice 2 status bit clear - 18 - 18 - write-only - - - S3STC - Slice 3 status bit clear - 19 - 19 - write-only - - - - - GCST - Global Channel Status - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SS - Slice 0 shadow transfer status - 0 - 0 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S0DSS - Slice 0 Dither shadow transfer status - 1 - 1 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S0PSS - Slice 0 Prescaler shadow transfer status - 2 - 2 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S1SS - Slice 1 shadow transfer status - 4 - 4 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S1DSS - Slice 1 Dither shadow transfer status - 5 - 5 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S1PSS - Slice 1 Prescaler shadow transfer status - 6 - 6 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S2SS - Slice 2 shadow transfer status - 8 - 8 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S2DSS - Slice 2 Dither shadow transfer status - 9 - 9 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S2PSS - Slice 2 Prescaler shadow transfer status - 10 - 10 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S3SS - Slice 3 shadow transfer status - 12 - 12 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S3DSS - Slice 3 Dither shadow transfer status - 13 - 13 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S3PSS - Slice 3 Prescaler shadow transfer status - 14 - 14 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - CC40ST - Slice 0 status bit - 16 - 16 - read-only - - - CC41ST - Slice 1 status bit - 17 - 17 - read-only - - - CC42ST - Slice 2 status bit - 18 - 18 - read-only - - - CC43ST - Slice 3 status bit - 19 - 19 - read-only - - - - - ECRD - Extended Capture Mode Read - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPV - Timer Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Capture value - 16 - 19 - read-only - - - SPTR - Slice pointer - 20 - 21 - read-only - - - value1 - CC40 - 0b00 - - - value2 - CC41 - 0b01 - - - value3 - CC42 - 0b10 - - - value4 - CC43 - 0b11 - - - - - VPTR - Capture register pointer - 22 - 23 - read-only - - - value1 - Capture register 0 - 0b00 - - - value2 - Capture register 1 - 0b01 - - - value3 - Capture register 2 - 0b10 - - - value4 - Capture register 3 - 0b11 - - - - - FFL - Full Flag - 24 - 24 - read-only - - - value1 - No new value was captured into this register - 0b0 - - - value2 - A new value has been captured into this register - 0b1 - - - - - - - MIDR - Module Identification - 0x0080 - 32 - 0x00A6C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - - - CCU41 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010000 - - 0x0 - 0x4000 - registers - - - - CCU42 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014000 - - 0x0 - 0x4000 - registers - - - - CCU43 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004000 - - 0x0 - 0x4000 - registers - - - - CCU40_CC40 - Capture Compare Unit 4 - Unit 0 - CCU4 - CCU4_CC4 - 0x4000C100 - - 0x0 - 0x100 - registers - - - - INS - Input Selector Configuration - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - EV0IS - Event 0 signal selection - 0 - 3 - read-write - - - value1 - CCU4x.INyA - 0b0000 - - - value2 - CCU4x.INyB - 0b0001 - - - value3 - CCU4x.INyC - 0b0010 - - - value4 - CCU4x.INyD - 0b0011 - - - value5 - CCU4x.INyE - 0b0100 - - - value6 - CCU4x.INyF - 0b0101 - - - value7 - CCU4x.INyG - 0b0110 - - - value8 - CCU4x.INyH - 0b0111 - - - value9 - CCU4x.INyI - 0b1000 - - - value10 - CCU4x.INyJ - 0b1001 - - - value11 - CCU4x.INyK - 0b1010 - - - value12 - CCU4x.INyL - 0b1011 - - - value13 - CCU4x.INyM - 0b1100 - - - value14 - CCU4x.INyN - 0b1101 - - - value15 - CCU4x.INyO - 0b1110 - - - value16 - CCU4x.INyP - 0b1111 - - - - - EV1IS - Event 1 signal selection - 4 - 7 - read-write - - - EV2IS - Event 2 signal selection - 8 - 11 - read-write - - - EV0EM - Event 0 Edge Selection - 16 - 17 - read-write - - - value1 - No action - 0b00 - - - value2 - Signal active on rising edge - 0b01 - - - value3 - Signal active on falling edge - 0b10 - - - value4 - Signal active on both edges - 0b11 - - - - - EV1EM - Event 1 Edge Selection - 18 - 19 - read-write - - - EV2EM - Event 2 Edge Selection - 20 - 21 - read-write - - - EV0LM - Event 0 Level Selection - 22 - 22 - read-write - - - value1 - Active on HIGH level - 0b0 - - - value2 - Active on LOW level - 0b1 - - - - - EV1LM - Event 1 Level Selection - 23 - 23 - read-write - - - EV2LM - Event 2 Level Selection - 24 - 24 - read-write - - - LPF0M - Event 0 Low Pass Filter Configuration - 25 - 26 - read-write - - - value1 - LPF is disabled - 0b00 - - - value2 - 3 clock cycles of fCCU4 - 0b01 - - - value3 - 5 clock cycles of fCCU4 - 0b10 - - - value4 - 7 clock cycles of fCCU4 - 0b11 - - - - - LPF1M - Event 1 Low Pass Filter Configuration - 27 - 28 - read-write - - - LPF2M - Event 2 Low Pass Filter Configuration - 29 - 30 - read-write - - - - - CMC - Connection Matrix Control - 0x004 - 32 - 0x00000000 - 0xFFFFFFFF - - - STRTS - External Start Functionality Selector - 0 - 1 - read-write - - - value1 - External Start Function deactivated - 0b00 - - - value2 - External Start Function triggered by Event 0 - 0b01 - - - value3 - External Start Function triggered by Event 1 - 0b10 - - - value4 - External Start Function triggered by Event 2 - 0b11 - - - - - ENDS - External Stop Functionality Selector - 2 - 3 - read-write - - - value1 - External Stop Function deactivated - 0b00 - - - value2 - External Stop Function triggered by Event 0 - 0b01 - - - value3 - External Stop Function triggered by Event 1 - 0b10 - - - value4 - External Stop Function triggered by Event 2 - 0b11 - - - - - CAP0S - External Capture 0 Functionality Selector - 4 - 5 - read-write - - - value1 - External Capture 0 Function deactivated - 0b00 - - - value2 - External Capture 0 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 0 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 0 Function triggered by Event 2 - 0b11 - - - - - CAP1S - External Capture 1 Functionality Selector - 6 - 7 - read-write - - - value1 - External Capture 1 Function deactivated - 0b00 - - - value2 - External Capture 1 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 1 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 1 Function triggered by Event 2 - 0b11 - - - - - GATES - External Gate Functionality Selector - 8 - 9 - read-write - - - value1 - External Gating Function deactivated - 0b00 - - - value2 - External Gating Function triggered by Event 0 - 0b01 - - - value3 - External Gating Function triggered by Event 1 - 0b10 - - - value4 - External Gating Function triggered by Event 2 - 0b11 - - - - - UDS - External Up/Down Functionality Selector - 10 - 11 - read-write - - - value1 - External Up/Down Function deactivated - 0b00 - - - value2 - External Up/Down Function triggered by Event 0 - 0b01 - - - value3 - External Up/Down Function triggered by Event 1 - 0b10 - - - value4 - External Up/Down Function triggered by Event 2 - 0b11 - - - - - LDS - External Timer Load Functionality Selector - 12 - 13 - read-write - - - CNTS - External Count Selector - 14 - 15 - read-write - - - value1 - External Count Function deactivated - 0b00 - - - value2 - External Count Function triggered by Event 0 - 0b01 - - - value3 - External Count Function triggered by Event 1 - 0b10 - - - value4 - External Count Function triggered by Event 2 - 0b11 - - - - - OFS - Override Function Selector - 16 - 16 - read-write - - - value1 - Override functionality disabled - 0b0 - - - value2 - Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 - 0b1 - - - - - TS - Trap Function Selector - 17 - 17 - read-write - - - value1 - Trap function disabled - 0b0 - - - value2 - TRAP function connected to Event 2 - 0b1 - - - - - MOS - External Modulation Functionality Selector - 18 - 19 - read-write - - - TCE - Timer Concatenation Enable - 20 - 20 - read-write - - - value1 - Timer concatenation is disabled - 0b0 - - - value2 - Timer concatenation is enabled - 0b1 - - - - - - - TCST - Slice Timer Status - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRB - Timer Run Bit - 0 - 0 - read-only - - - value1 - Timer is stopped - 0b0 - - - value2 - Timer is running - 0b1 - - - - - CDIR - Timer Counting Direction - 1 - 1 - read-only - - - value1 - Timer is counting up - 0b0 - - - value2 - Timer is counting down - 0b1 - - - - - - - TCSET - Slice Timer Run Set - 0x00C - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBS - Timer Run Bit set - 0 - 0 - write-only - - - - - TCCLR - Slice Timer Clear - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBC - Timer Run Bit Clear - 0 - 0 - write-only - - - TCC - Timer Clear - 1 - 1 - write-only - - - DITC - Dither Counter Clear - 2 - 2 - write-only - - - - - TC - Slice Timer Control - 0x014 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCM - Timer Counting Mode - 0 - 0 - read-write - - - value1 - Edge aligned mode - 0b0 - - - value2 - Center aligned mode - 0b1 - - - - - TSSM - Timer Single Shot Mode - 1 - 1 - read-write - - - value1 - Single shot mode is disabled - 0b0 - - - value2 - Single shot mode is enabled - 0b1 - - - - - CLST - Shadow Transfer on Clear - 2 - 2 - read-write - - - CMOD - Capture Compare Mode - 3 - 3 - read-only - - - value1 - Compare Mode - 0b0 - - - value2 - Capture Mode - 0b1 - - - - - ECM - Extended Capture Mode - 4 - 4 - read-write - - - value1 - Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. - 0b0 - - - value2 - Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared. - 0b1 - - - - - CAPC - Clear on Capture Control - 5 - 6 - read-write - - - value1 - Timer is never cleared on a capture event - 0b00 - - - value2 - Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) - 0b01 - - - value3 - Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) - 0b10 - - - value4 - Timer is always cleared in a capture event. - 0b11 - - - - - ENDM - Extended Stop Function Control - 8 - 9 - read-write - - - value1 - Clears the timer run bit only (default stop) - 0b00 - - - value2 - Clears the timer only (flush) - 0b01 - - - value3 - Clears the timer and run bit (flush/stop) - 0b10 - - - value4 - Reserved - 0b11 - - - - - STRM - Extended Start Function Control - 10 - 10 - read-write - - - value1 - Sets run bit only (default start) - 0b0 - - - value2 - Clears the timer and sets run bit (flush/start) - 0b1 - - - - - SCE - Equal Capture Event enable - 11 - 11 - read-write - - - value1 - Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b0 - - - value2 - Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b1 - - - - - CCS - Continuous Capture Enable - 12 - 12 - read-write - - - value1 - The capture into a specific capture register is done with the rules linked with the full flags, described at . - 0b0 - - - value2 - The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). - 0b1 - - - - - DITHE - Dither Enable - 13 - 14 - read-write - - - value1 - Dither is disabled - 0b00 - - - value2 - Dither is applied to the Period - 0b01 - - - value3 - Dither is applied to the Compare - 0b10 - - - value4 - Dither is applied to the Period and Compare - 0b11 - - - - - DIM - Dither input selector - 15 - 15 - read-write - - - value1 - Slice is using its own dither unit - 0b0 - - - value2 - Slice is connected to the dither unit of slice 0. - 0b1 - - - - - FPE - Floating Prescaler enable - 16 - 16 - read-write - - - value1 - Floating prescaler mode is disabled - 0b0 - - - value2 - Floating prescaler mode is enabled - 0b1 - - - - - TRAPE - TRAP enable - 17 - 17 - read-write - - - value1 - TRAP functionality has no effect on the output - 0b0 - - - value2 - TRAP functionality affects the output - 0b1 - - - - - TRPSE - TRAP Synchronization Enable - 21 - 21 - read-write - - - value1 - Exiting from TRAP state isn't synchronized with the PWM signal - 0b0 - - - value2 - Exiting from TRAP state is synchronized with the PWM signal - 0b1 - - - - - TRPSW - TRAP State Clear Control - 22 - 22 - read-write - - - value1 - The slice exits the TRAP state automatically when the TRAP condition is not present - 0b0 - - - value2 - The TRAP state can only be exited by a SW request. - 0b1 - - - - - EMS - External Modulation Synchronization - 23 - 23 - read-write - - - value1 - External Modulation functionality is not synchronized with the PWM signal - 0b0 - - - value2 - External Modulation functionality is synchronized with the PWM signal - 0b1 - - - - - EMT - External Modulation Type - 24 - 24 - read-write - - - value1 - External Modulation functionality is clearing the CC4yST bit. - 0b0 - - - value2 - External Modulation functionality is gating the outputs. - 0b1 - - - - - MCME - Multi Channel Mode Enable - 25 - 25 - read-write - - - value1 - Multi Channel Mode is disabled - 0b0 - - - value2 - Multi Channel Mode is enabled - 0b1 - - - - - - - PSL - Passive Level Config - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSL - Output Passive Level - 0 - 0 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - - - DIT - Dither Config - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - DCV - Dither compare Value - 0 - 3 - read-only - - - DCNT - Dither counter actual value - 8 - 11 - read-only - - - - - DITS - Dither Shadow Register - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCVS - Dither Shadow Compare Value - 0 - 3 - read-write - - - - - PSC - Prescaler Control - 0x024 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSIV - Prescaler Initial Value - 0 - 3 - read-write - - - - - FPC - Floating Prescaler Control - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Compare Value - 0 - 3 - read-only - - - PVAL - Actual Prescaler Value - 8 - 11 - read-write - - - - - FPCS - Floating Prescaler Shadow - 0x02C - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Shadow Compare Value - 0 - 3 - read-write - - - - - PR - Timer Period Value - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - PR - Period Register - 0 - 15 - read-only - - - - - PRS - Timer Shadow Period Value - 0x034 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRS - Period Register - 0 - 15 - read-write - - - - - CR - Timer Compare Value - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR - Compare Register - 0 - 15 - read-only - - - - - CRS - Timer Shadow Compare Value - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - CRS - Compare Register - 0 - 15 - read-write - - - - - TIMER - Timer Value - 0x070 - 32 - 0x00000000 - 0xFFFFFFFF - - - TVAL - Timer Value - 0 - 15 - read-write - - - - - C0V - Capture Register 0 - 0x074 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C1V - Capture Register 1 - 0x078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C2V - Capture Register 2 - 0x07C - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C3V - Capture Register 3 - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - INTS - Interrupt Status - 0x0A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PMUS - Period Match while Counting Up - 0 - 0 - read-only - - - value1 - Period match while counting up not detected - 0b0 - - - value2 - Period match while counting up detected - 0b1 - - - - - OMDS - One Match while Counting Down - 1 - 1 - read-only - - - value1 - One match while counting down not detected - 0b0 - - - value2 - One match while counting down detected - 0b1 - - - - - CMUS - Compare Match while Counting Up - 2 - 2 - read-only - - - value1 - Compare match while counting up not detected - 0b0 - - - value2 - Compare match while counting up detected - 0b1 - - - - - CMDS - Compare Match while Counting Down - 3 - 3 - read-only - - - value1 - Compare match while counting down not detected - 0b0 - - - value2 - Compare match while counting down detected - 0b1 - - - - - E0AS - Event 0 Detection Status - 8 - 8 - read-only - - - value1 - Event 0 not detected - 0b0 - - - value2 - Event 0 detected - 0b1 - - - - - E1AS - Event 1 Detection Status - 9 - 9 - read-only - - - value1 - Event 1 not detected - 0b0 - - - value2 - Event 1 detected - 0b1 - - - - - E2AS - Event 2 Detection Status - 10 - 10 - read-only - - - value1 - Event 2 not detected - 0b0 - - - value2 - Event 2 detected - 0b1 - - - - - TRPF - Trap Flag Status - 11 - 11 - read-only - - - - - INTE - Interrupt Enable Control - 0x0A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - PME - Period match while counting up enable - 0 - 0 - read-write - - - value1 - Period Match interrupt is disabled - 0b0 - - - value2 - Period Match interrupt is enabled - 0b1 - - - - - OME - One match while counting down enable - 1 - 1 - read-write - - - value1 - One Match interrupt is disabled - 0b0 - - - value2 - One Match interrupt is enabled - 0b1 - - - - - CMUE - Compare match while counting up enable - 2 - 2 - read-write - - - value1 - Compare Match while counting up interrupt is disabled - 0b0 - - - value2 - Compare Match while counting up interrupt is enabled - 0b1 - - - - - CMDE - Compare match while counting down enable - 3 - 3 - read-write - - - value1 - Compare Match while counting down interrupt is disabled - 0b0 - - - value2 - Compare Match while counting down interrupt is enabled - 0b1 - - - - - E0AE - Event 0 interrupt enable - 8 - 8 - read-write - - - value1 - Event 0 detection interrupt is disabled - 0b0 - - - value2 - Event 0 detection interrupt is enabled - 0b1 - - - - - E1AE - Event 1 interrupt enable - 9 - 9 - read-write - - - value1 - Event 1 detection interrupt is disabled - 0b0 - - - value2 - Event 1 detection interrupt is enabled - 0b1 - - - - - E2AE - Event 2 interrupt enable - 10 - 10 - read-write - - - value1 - Event 2 detection interrupt is disabled - 0b0 - - - value2 - Event 2 detection interrupt is enabled - 0b1 - - - - - - - SRS - Service Request Selector - 0x0A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSR - Period/One match Service request selector - 0 - 1 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - CMSR - Compare match Service request selector - 2 - 3 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - E0SR - Event 0 Service request selector - 8 - 9 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - E1SR - Event 1 Service request selector - 10 - 11 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - E2SR - Event 2 Service request selector - 12 - 13 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - - - SWS - Interrupt Status Set - 0x0AC - 32 - 0x00000000 - 0xFFFFFFFF - - - SPM - Period match while counting up set - 0 - 0 - write-only - - - SOM - One match while counting down set - 1 - 1 - write-only - - - SCMU - Compare match while counting up set - 2 - 2 - write-only - - - SCMD - Compare match while counting down set - 3 - 3 - write-only - - - SE0A - Event 0 detection set - 8 - 8 - write-only - - - SE1A - Event 1 detection set - 9 - 9 - write-only - - - SE2A - Event 2 detection set - 10 - 10 - write-only - - - STRPF - Trap Flag status set - 11 - 11 - write-only - - - - - SWR - Interrupt Status Clear - 0x0B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPM - Period match while counting up clear - 0 - 0 - write-only - - - ROM - One match while counting down clear - 1 - 1 - write-only - - - RCMU - Compare match while counting up clear - 2 - 2 - write-only - - - RCMD - Compare match while counting down clear - 3 - 3 - write-only - - - RE0A - Event 0 detection clear - 8 - 8 - write-only - - - RE1A - Event 1 detection clear - 9 - 9 - write-only - - - RE2A - Event 2 detection clear - 10 - 10 - write-only - - - RTRPF - Trap Flag status clear - 11 - 11 - write-only - - - - - - - CCU40_CC41 - Capture Compare Unit 4 - Unit 0 - CCU4 - 0x4000C200 - - 0x0 - 0x100 - registers - - - - CCU40_CC42 - Capture Compare Unit 4 - Unit 0 - CCU4 - 0x4000C300 - - 0x0 - 0x100 - registers - - - - CCU40_CC43 - Capture Compare Unit 4 - Unit 0 - CCU4 - 0x4000C400 - - 0x0 - 0x100 - registers - - - - CCU41_CC40 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010100 - - 0x0 - 0x100 - registers - - - - CCU41_CC41 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010200 - - 0x0 - 0x100 - registers - - - - CCU41_CC42 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010300 - - 0x0 - 0x100 - registers - - - - CCU41_CC43 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010400 - - 0x0 - 0x100 - registers - - - - CCU42_CC40 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014100 - - 0x0 - 0x100 - registers - - - - CCU42_CC41 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014200 - - 0x0 - 0x100 - registers - - - - CCU42_CC42 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014300 - - 0x0 - 0x100 - registers - - - - CCU42_CC43 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014400 - - 0x0 - 0x100 - registers - - - - CCU43_CC40 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004100 - - 0x0 - 0x100 - registers - - - - CCU43_CC41 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004200 - - 0x0 - 0x100 - registers - - - - CCU43_CC42 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004300 - - 0x0 - 0x100 - registers - - - - CCU43_CC43 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004400 - - 0x0 - 0x100 - registers - - - - CCU80 - Capture Compare Unit 8 - Unit 0 - CCU8 - CCU8 - 0x40020000 - - 0x0 - 0x4000 - registers - - - - GCTRL - Global Control Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRBC - Prescaler Clear Configuration - 0 - 2 - read-write - - - value1 - SW only - 0b000 - - - value2 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC80 is cleared. - 0b001 - - - value3 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC81 is cleared. - 0b010 - - - value4 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC82 is cleared. - 0b011 - - - value5 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC83 is cleared. - 0b100 - - - - - PCIS - Prescaler Input Clock Selection - 4 - 5 - read-write - - - value1 - Module clock - 0b00 - - - value2 - CCU8x.ECLKA - 0b01 - - - value3 - CCU8x.ECLKB - 0b10 - - - value4 - CCU8x.ECLKC - 0b11 - - - - - SUSCFG - Suspend Mode Configuration - 8 - 9 - read-write - - - value1 - Suspend request ignored. The module never enters in suspend - 0b00 - - - value2 - Stops all the running slices immediately. Safe stop is not applied. - 0b01 - - - value3 - Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. - 0b10 - - - value4 - Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. - 0b11 - - - - - MSE0 - Slice 0 Multi Channel shadow transfer enable - 10 - 10 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8x.MCSS input. - 0b1 - - - - - MSE1 - Slice 1 Multi Channel shadow transfer enable - 11 - 11 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8x.MCSS input. - 0b1 - - - - - MSE2 - Slice 2 Multi Channel shadow transfer enable - 12 - 12 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8xMCSS input. - 0b1 - - - - - MSE3 - Slice 3 Multi Channel shadow transfer enable - 13 - 13 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8x.MCSS input. - 0b1 - - - - - MSDE - Multi Channel shadow transfer request configuration - 14 - 15 - read-write - - - value1 - Only the shadow transfer for period and compare values is requested - 0b00 - - - value2 - Shadow transfer for the compare, period and prescaler compare values is requested - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Shadow transfer for the compare, period, prescaler and dither compare values is requested - 0b11 - - - - - - - GSTAT - Global Status Register - 0x0004 - 32 - 0x0000000F - 0xFFFFFFFF - - - S0I - CC80 IDLE status - 0 - 0 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S1I - CC81 IDLE status - 1 - 1 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S2I - CC82 IDLE status - 2 - 2 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S3I - CC83 IDLE status - 3 - 3 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - PRB - Prescaler Run Bit - 8 - 8 - read-only - - - value1 - Prescaler is stopped - 0b0 - - - value2 - Prescaler is running - 0b1 - - - - - PCRB - Parity Checker Run Bit - 10 - 10 - read-only - - - value1 - Parity Checker is stopped - 0b0 - - - value2 - Parity Checker is running - 0b1 - - - - - - - GIDLS - Global Idle Set - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SS0I - CC80 IDLE mode set - 0 - 0 - write-only - - - SS1I - CC81 IDLE mode set - 1 - 1 - write-only - - - SS2I - CC82 IDLE mode set - 2 - 2 - write-only - - - SS3I - CC83 IDLE mode set - 3 - 3 - write-only - - - CPRB - Prescaler# Run Bit Clear - 8 - 8 - write-only - - - PSIC - Prescaler clear - 9 - 9 - write-only - - - CPCH - Parity Checker Run bit clear - 10 - 10 - write-only - - - - - GIDLC - Global Idle Clear - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - CS0I - CC80 IDLE mode clear - 0 - 0 - write-only - - - CS1I - CC81 IDLE mode clear - 1 - 1 - write-only - - - CS2I - CC82 IDLE mode clear - 2 - 2 - write-only - - - CS3I - CC83 IDLE mode clear - 3 - 3 - write-only - - - SPRB - Prescaler Run Bit Set - 8 - 8 - write-only - - - SPCH - Parity Checker run bit set - 10 - 10 - write-only - - - - - GCSS - Global Channel Set - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SE - Slice 0 shadow transfer set enable - 0 - 0 - write-only - - - S0DSE - Slice 0 Dither shadow transfer set enable - 1 - 1 - write-only - - - S0PSE - Slice 0 Prescaler shadow transfer set enable - 2 - 2 - write-only - - - S1SE - Slice 1 shadow transfer set enable - 4 - 4 - write-only - - - S1DSE - Slice 1 Dither shadow transfer set enable - 5 - 5 - write-only - - - S1PSE - Slice 1 Prescaler shadow transfer set enable - 6 - 6 - write-only - - - S2SE - Slice 2 shadow transfer set enable - 8 - 8 - write-only - - - S2DSE - Slice 2 Dither shadow transfer set enable - 9 - 9 - write-only - - - S2PSE - Slice 2 Prescaler shadow transfer set enable - 10 - 10 - write-only - - - S3SE - Slice 3 shadow transfer set enable - 12 - 12 - write-only - - - S3DSE - Slice 3 Dither shadow transfer set enable - 13 - 13 - write-only - - - S3PSE - Slice 3 Prescaler shadow transfer set enable - 14 - 14 - write-only - - - S0ST1S - Slice 0 status bit 1 set - 16 - 16 - write-only - - - S1ST1S - Slice 1 status bit 1 set - 17 - 17 - write-only - - - S2ST1S - Slice 2 status bit 1 set - 18 - 18 - write-only - - - S3ST1S - Slice 3 status bit 1 set - 19 - 19 - write-only - - - S0ST2S - Slice 0 status bit 2 set - 20 - 20 - write-only - - - S1ST2S - Slice 1 status bit 2 set - 21 - 21 - write-only - - - S2ST2S - Slice 2 status bit 2 set - 22 - 22 - write-only - - - S3ST2S - Slice 3 status bit 2 set - 23 - 23 - write-only - - - - - GCSC - Global Channel Clear - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SC - Slice 0 shadow transfer request clear - 0 - 0 - write-only - - - S0DSC - Slice 0 Dither shadow transfer clear - 1 - 1 - write-only - - - S0PSC - Slice 0 Prescaler shadow transfer clear - 2 - 2 - write-only - - - S1SC - Slice 1 shadow transfer clear - 4 - 4 - write-only - - - S1DSC - Slice 1 Dither shadow transfer clear - 5 - 5 - write-only - - - S1PSC - Slice 1 Prescaler shadow transfer clear - 6 - 6 - write-only - - - S2SC - Slice 2 shadow transfer clear - 8 - 8 - write-only - - - S2DSC - Slice 2 Dither shadow transfer clear - 9 - 9 - write-only - - - S2PSC - Slice 2 Prescaler shadow transfer clear - 10 - 10 - write-only - - - S3SC - Slice 3 shadow transfer clear - 12 - 12 - write-only - - - S3DSC - Slice 3 Dither shadow transfer clear - 13 - 13 - write-only - - - S3PSC - Slice 3 Prescaler shadow transfer clear - 14 - 14 - write-only - - - S0ST1C - Slice 0 status bit 1 clear - 16 - 16 - write-only - - - S1ST1C - Slice 1 status bit 1 clear - 17 - 17 - write-only - - - S2ST1C - Slice 2 status bit 1 clear - 18 - 18 - write-only - - - S3ST1C - Slice 3 status bit 1 clear - 19 - 19 - write-only - - - S0ST2C - Slice 0 status bit 2 clear - 20 - 20 - write-only - - - S1ST2C - Slice 1 status bit 2 clear - 21 - 21 - write-only - - - S2ST2C - Slice 2 status bit 2 clear - 22 - 22 - write-only - - - S3ST2C - Slice 3 status bit 2 clear - 23 - 23 - write-only - - - - - GCST - Global Channel status - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SS - Slice 0 shadow transfer status - 0 - 0 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S0DSS - Slice 0 Dither shadow transfer status - 1 - 1 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S0PSS - Slice 0 Prescaler shadow transfer status - 2 - 2 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S1SS - Slice 1 shadow transfer status - 4 - 4 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S1DSS - Slice 1 Dither shadow transfer status - 5 - 5 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S1PSS - Slice 1 Prescaler shadow transfer status - 6 - 6 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S2SS - Slice 2 shadow transfer status - 8 - 8 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S2DSS - Slice 2 Dither shadow transfer status - 9 - 9 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S2PSS - Slice 2 Prescaler shadow transfer status - 10 - 10 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S3SS - Slice 3 shadow transfer status - 12 - 12 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S3DSS - Slice 3 Dither shadow transfer status - 13 - 13 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S3PSS - Slice 3 Prescaler shadow transfer status - 14 - 14 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - CC80ST1 - Slice 0 compare channel 1 status bit - 16 - 16 - read-only - - - CC81ST1 - Slice 1 compare channel 1 status bit - 17 - 17 - read-only - - - CC82ST1 - Slice 2 compare channel 1 status bit - 18 - 18 - read-only - - - CC83ST1 - Slice 3 compare channel 1 status bit - 19 - 19 - read-only - - - CC80ST2 - Slice 0 compare channel 2 status bit - 20 - 20 - read-only - - - CC81ST2 - Slice 1 compare channel 2 status bit - 21 - 21 - read-only - - - CC82ST2 - Slice 2 compare channel 2 status bit - 22 - 22 - read-only - - - CC83ST2 - Slice 3 compare channel 2 status bit - 23 - 23 - read-only - - - - - GPCHK - Parity Checker Configuration - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - PASE - Parity Checker Automatic start/stop - 0 - 0 - read-write - - - PACS - Parity Checker Automatic start/stop selector - 1 - 2 - read-write - - - value1 - CC80 - 0b00 - - - value2 - CC81 - 0b01 - - - value3 - CC82 - 0b10 - - - value4 - CC83 - 0b11 - - - - - PISEL - Driver Input signal selector - 3 - 4 - read-write - - - value1 - CC8x.GP01 - driver output is connected to event 1 of slice 0 - 0b00 - - - value2 - CC8x.GP11 - drive output is connected to event 1 of slice 1 - 0b01 - - - value3 - CC8x.GP21 - driver output is connected to event 1 of slice 2 - 0b10 - - - value4 - CC8x.GP31 - driver output is connected to event 1 of slice 3 - 0b11 - - - - - PCDS - Parity Checker Delay Input Selector - 5 - 6 - read-write - - - value1 - CCU8x.IGBTA - 0b00 - - - value2 - CCU8x.IGBTB - 0b01 - - - value3 - CCU8x.IGBTC - 0b10 - - - value4 - CCU8x.IGBTD - 0b11 - - - - - PCTS - Parity Checker type selector - 7 - 7 - read-write - - - value1 - Even parity enabled - 0b0 - - - value2 - Odd parity enabled - 0b1 - - - - - PCST - Parity Checker XOR status - 15 - 15 - read-only - - - PCSEL0 - Parity Checker Slice 0 output selection - 16 - 19 - read-write - - - PCSEL1 - Parity Checker Slice 1 output selection - 20 - 23 - read-write - - - PCSEL2 - Parity Checker Slice 2 output selection - 24 - 27 - read-write - - - PCSEL3 - Parity Checker Slice 3 output selection - 28 - 31 - read-write - - - - - ECRD - Extended Capture Mode Read - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPV - Timer Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Capture value - 16 - 19 - read-only - - - SPTR - Slice pointer - 20 - 21 - read-only - - - value1 - CC80 - 0b00 - - - value2 - CC81 - 0b01 - - - value3 - CC82 - 0b10 - - - value4 - CC83 - 0b11 - - - - - VPTR - Capture register pointer - 22 - 23 - read-only - - - value1 - Capture register 0 - 0b00 - - - value2 - Capture register 1 - 0b01 - - - value3 - Capture register 2 - 0b10 - - - value4 - Capture register 3 - 0b11 - - - - - FFL - Full Flag - 24 - 24 - read-only - - - value1 - No new value was captured into this register - 0b0 - - - value2 - A new value has been captured into this register - 0b1 - - - - - - - MIDR - Module Identification - 0x0080 - 32 - 0x00A7C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - - - CCU81 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024000 - - 0x0 - 0x4000 - registers - - - - CCU80_CC80 - Capture Compare Unit 8 - Unit 0 - CCU8 - CCU8_CC8 - 0x40020100 - - 0x0 - 0x100 - registers - - - - INS - Input Selector Configuration - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - EV0IS - Event 0 signal selection - 0 - 3 - read-write - - - value1 - CCU8x.INyA - 0b0000 - - - value2 - CCU8x.INyB - 0b0001 - - - value3 - CCU8x.INyC - 0b0010 - - - value4 - CCU8x.INyD - 0b0011 - - - value5 - CCU8x.INyE - 0b0100 - - - value6 - CCU8x.INyF - 0b0101 - - - value7 - CCU8x.INyG - 0b0110 - - - value8 - CCU8x.INyH - 0b0111 - - - value9 - CCU8x.INyI - 0b1000 - - - value10 - CCU8x.INyJ - 0b1001 - - - value11 - CCU8x.INyK - 0b1010 - - - value12 - CCU8x.INyL - 0b1011 - - - value13 - CCU8x.INyM - 0b1100 - - - value14 - CCU8x.INyN - 0b1101 - - - value15 - CCU8x.INyO - 0b1110 - - - value16 - CCU8x.INyP - 0b1111 - - - - - EV1IS - Event 1 signal selection - 4 - 7 - read-write - - - EV2IS - Event 2 signal selection - 8 - 11 - read-write - - - EV0EM - Event 0 Edge Selection - 16 - 17 - read-write - - - value1 - No action - 0b00 - - - value2 - Signal active on rising edge - 0b01 - - - value3 - Signal active on falling edge - 0b10 - - - value4 - Signal active on both edges - 0b11 - - - - - EV1EM - Event 1 Edge Selection - 18 - 19 - read-write - - - EV2EM - Event 2 Edge Selection - 20 - 21 - read-write - - - EV0LM - Event 0 Level Selection - 22 - 22 - read-write - - - value1 - Active on HIGH level - 0b0 - - - value2 - Active on LOW level - 0b1 - - - - - EV1LM - Event 1 Level Selection - 23 - 23 - read-write - - - EV2LM - Event 2 Level Selection - 24 - 24 - read-write - - - LPF0M - Event 0 Low Pass Filter Configuration - 25 - 26 - read-write - - - value1 - LPF is disabled - 0b00 - - - value2 - 3 clock cycles of fCCU8 - 0b01 - - - value3 - 5 clock cycles of fCCU8 - 0b10 - - - value4 - 7 clock cycles of fCCU8 - 0b11 - - - - - LPF1M - Event 1 Low Pass Filter Configuration - 27 - 28 - read-write - - - LPF2M - Event 2 Low Pass Filter Configuration - 29 - 30 - read-write - - - - - CMC - Connection Matrix Control - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - STRTS - External Start Functionality Selector - 0 - 1 - read-write - - - value1 - External Start Function deactivated - 0b00 - - - value2 - External Start Function triggered by Event 0 - 0b01 - - - value3 - External Start Function triggered by Event 1 - 0b10 - - - value4 - External Start Function triggered by Event 2 - 0b11 - - - - - ENDS - External Stop Functionality Selector - 2 - 3 - read-write - - - value1 - External Stop Function deactivated - 0b00 - - - value2 - External Stop Function triggered by Event 0 - 0b01 - - - value3 - External Stop Function triggered by Event 1 - 0b10 - - - value4 - External Stop Function triggered by Event 2 - 0b11 - - - - - CAP0S - External Capture 0 Functionality Selector - 4 - 5 - read-write - - - value1 - External Capture 0 Function deactivated - 0b00 - - - value2 - External Capture 0 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 0 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 0 Function triggered by Event 2 - 0b11 - - - - - CAP1S - External Capture 1 Functionality Selector - 6 - 7 - read-write - - - value1 - External Capture 1 Function deactivated - 0b00 - - - value2 - External Capture 1 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 1 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 1 Function triggered by Event 2 - 0b11 - - - - - GATES - External Gate Functionality Selector - 8 - 9 - read-write - - - value1 - External Gating Function deactivated - 0b00 - - - value2 - External Gating Function triggered by Event 0 - 0b01 - - - value3 - External Gating Function triggered by Event 1 - 0b10 - - - value4 - External Gating Function triggered by Event 2 - 0b11 - - - - - UDS - External Up/Down Functionality Selector - 10 - 11 - read-write - - - value1 - External Up/Down Function deactivated - 0b00 - - - value2 - External Up/Down Function triggered by Event 0 - 0b01 - - - value3 - External Up/Down Function triggered by Event 1 - 0b10 - - - value4 - External Up/Down Function triggered by Event 2 - 0b11 - - - - - LDS - External Timer Load Functionality Selector - 12 - 13 - read-write - - - CNTS - External Count Selector - 14 - 15 - read-write - - - value1 - External Count Function deactivated - 0b00 - - - value2 - External Count Function triggered by Event 0 - 0b01 - - - value3 - External Count Function triggered by Event 1 - 0b10 - - - value4 - External Count Function triggered by Event 2 - 0b11 - - - - - OFS - Override Function Selector - 16 - 16 - read-write - - - value1 - Override functionality disabled - 0b0 - - - value2 - Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 - 0b1 - - - - - TS - Trap Function Selector - 17 - 17 - read-write - - - value1 - Trap function disabled - 0b0 - - - value2 - TRAP function connected to Event 2 - 0b1 - - - - - MOS - External Modulation Functionality Selector - 18 - 19 - read-write - - - TCE - Timer Concatenation Enable - 20 - 20 - read-write - - - value1 - Timer concatenation is disabled - 0b0 - - - value2 - Timer concatenation is enabled - 0b1 - - - - - - - TCST - Slice Timer Status - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRB - Timer Run Bit - 0 - 0 - read-only - - - value1 - Timer is stopped - 0b0 - - - value2 - Timer is running - 0b1 - - - - - CDIR - Timer Counting Direction - 1 - 1 - read-only - - - value1 - Timer is counting up - 0b0 - - - value2 - Timer is counting down - 0b1 - - - - - DTR1 - Dead Time Counter 1 Run bit - 3 - 3 - read-only - - - value1 - Dead Time counter is idle - 0b0 - - - value2 - Dead Time counter is running - 0b1 - - - - - DTR2 - Dead Time Counter 2 Run bit - 4 - 4 - read-only - - - value1 - Dead Time counter is idle - 0b0 - - - value2 - Dead Time counter is running - 0b1 - - - - - - - TCSET - Slice Timer Run Set - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBS - Timer Run Bit set - 0 - 0 - write-only - - - - - TCCLR - Slice Timer Clear - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBC - Timer Run Bit Clear - 0 - 0 - write-only - - - TCC - Timer Clear - 1 - 1 - write-only - - - DITC - Dither Counter Clear - 2 - 2 - write-only - - - DTC1C - Dead Time Counter 1 Clear - 3 - 3 - write-only - - - DTC2C - Dead Time Counter 2 Clear - 4 - 4 - write-only - - - - - TC - Slice Timer Control - 0x0014 - 32 - 0x18000000 - 0xFFFFFFFF - - - TCM - Timer Counting Mode - 0 - 0 - read-write - - - value1 - Edge aligned mode - 0b0 - - - value2 - Center aligned mode - 0b1 - - - - - TSSM - Timer Single Shot Mode - 1 - 1 - read-write - - - value1 - Single shot mode is disabled - 0b0 - - - value2 - Single shot mode is enabled - 0b1 - - - - - CLST - Shadow Transfer on Clear - 2 - 2 - read-write - - - CMOD - Capture Compare Mode - 3 - 3 - read-only - - - value1 - Compare Mode - 0b0 - - - value2 - Capture Mode - 0b1 - - - - - ECM - Extended Capture Mode - 4 - 4 - read-write - - - value1 - Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. - 0b0 - - - value2 - Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared - 0b1 - - - - - CAPC - Clear on Capture Control - 5 - 6 - read-write - - - value1 - Timer is never cleared on a capture event - 0b00 - - - value2 - Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) - 0b01 - - - value3 - Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) - 0b10 - - - value4 - Timer is always cleared in a capture event. - 0b11 - - - - - TLS - Timer Load selector - 7 - 7 - read-write - - - value1 - Timer is loaded with the value of CR1 - 0b0 - - - value2 - Timer is loaded with the value of CR2 - 0b1 - - - - - ENDM - Extended Stop Function Control - 8 - 9 - read-write - - - value1 - Clears the timer run bit only (default stop) - 0b00 - - - value2 - Clears the timer only (flush) - 0b01 - - - value3 - Clears the timer and run bit (flush/stop) - 0b10 - - - value4 - Reserved - 0b11 - - - - - STRM - Extended Start Function Control - 10 - 10 - read-write - - - value1 - Sets run bit only (default start) - 0b0 - - - value2 - Clears the timer and sets run bit, if not set (flush/start) - 0b1 - - - - - SCE - Equal Capture Event enable - 11 - 11 - read-write - - - value1 - Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b0 - - - value2 - Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b1 - - - - - CCS - Continuous Capture Enable - 12 - 12 - read-write - - - value1 - The capture into a specific capture register is done with the rules linked with the full flags, described at . - 0b0 - - - value2 - The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). - 0b1 - - - - - DITHE - Dither Enable - 13 - 14 - read-write - - - value1 - Dither is disabled - 0b00 - - - value2 - Dither is applied to the Period - 0b01 - - - value3 - Dither is applied to the Compare - 0b10 - - - value4 - Dither is applied to the Period and Compare - 0b11 - - - - - DIM - Dither input selector - 15 - 15 - read-write - - - value1 - Slice is using it own dither unit - 0b0 - - - value2 - Slice is connected to the dither unit of slice 0. - 0b1 - - - - - FPE - Floating Prescaler enable - 16 - 16 - read-write - - - value1 - Floating prescaler mode is disabled - 0b0 - - - value2 - Floating prescaler mode is enabled - 0b1 - - - - - TRAPE0 - TRAP enable for CCU8x.OUTy0 - 17 - 17 - read-write - - - value1 - TRAP functionality has no effect on the CCU8x.OUTy0 output - 0b0 - - - value2 - TRAP functionality affects the CCU8x.OUTy0 output - 0b1 - - - - - TRAPE1 - TRAP enable for CCU8x.OUTy1 - 18 - 18 - read-write - - - TRAPE2 - TRAP enable for CCU8x.OUTy2 - 19 - 19 - read-write - - - TRAPE3 - TRAP enable for CCU8x.OUTy3 - 20 - 20 - read-write - - - TRPSE - TRAP Synchronization Enable - 21 - 21 - read-write - - - value1 - Exiting from TRAP state isn't synchronized with the PWM signal - 0b0 - - - value2 - Exiting from TRAP state is synchronized with the PWM signal - 0b1 - - - - - TRPSW - TRAP State Clear Control - 22 - 22 - read-write - - - value1 - The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW) - 0b0 - - - value2 - The TRAP state can only be exited by a SW request. - 0b1 - - - - - EMS - External Modulation Synchronization - 23 - 23 - read-write - - - value1 - External Modulation functionality is not synchronized with the PWM signal - 0b0 - - - value2 - External Modulation functionality is synchronized with the PWM signal - 0b1 - - - - - EMT - External Modulation Type - 24 - 24 - read-write - - - value1 - External Modulation functionality is clearing the CC8ySTx bits. - 0b0 - - - value2 - External Modulation functionality is gating the outputs. - 0b1 - - - - - MCME1 - Multi Channel Mode Enable for Channel 1 - 25 - 25 - read-write - - - value1 - Multi Channel Mode in Channel 1 is disabled - 0b0 - - - value2 - Multi Channel Mode in Channel 1 is enabled - 0b1 - - - - - MCME2 - Multi Channel Mode Enable for Channel 2 - 26 - 26 - read-write - - - value1 - Multi Channel Mode in Channel 2 is disabled - 0b0 - - - value2 - Multi Channel Mode in Channel 2 is enabled - 0b1 - - - - - EME - External Modulation Channel enable - 27 - 28 - read-write - - - value1 - External Modulation functionality doesn't affect any channel - 0b00 - - - value2 - External Modulation only applied on channel 1 - 0b01 - - - value3 - External Modulation only applied on channel 2 - 0b10 - - - value4 - External Modulation applied on both channels - 0b11 - - - - - STOS - Status bit output selector - 29 - 30 - read-write - - - value1 - CC8yST1 forward to CCU8x.STy - 0b00 - - - value2 - CC8yST2 forward to CCU8x.STy - 0b01 - - - value3 - CC8yST1 AND CC8yST2 forward to CCU8x.STy - 0b10 - - - value4 - Reserved - 0b11 - - - - - - - PSL - Passive Level Config - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSL11 - Output Passive Level for CCU8x.OUTy0 - 0 - 0 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - PSL12 - Output Passive Level for CCU8x.OUTy1 - 1 - 1 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - PSL21 - Output Passive Level for CCU8x.OUTy2 - 2 - 2 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - PSL22 - Output Passive Level for CCU8x.OUTy3 - 3 - 3 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - - - DIT - Dither Config - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - DCV - Dither compare Value - 0 - 3 - read-only - - - DCNT - Dither counter actual value - 8 - 11 - read-only - - - - - DITS - Dither Shadow Register - 0x0020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCVS - Dither Shadow Compare Value - 0 - 3 - read-write - - - - - PSC - Prescaler Control - 0x0024 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSIV - Prescaler Initial Value - 0 - 3 - read-write - - - - - FPC - Floating Prescaler Control - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Compare Value - 0 - 3 - read-only - - - PVAL - Actual Prescaler Value - 8 - 11 - read-write - - - - - FPCS - Floating Prescaler Shadow - 0x002C - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Shadow Compare Value - 0 - 3 - read-write - - - - - PR - Timer Period Value - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - PR - Period Register - 0 - 15 - read-only - - - - - PRS - Timer Shadow Period Value - 0x0034 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRS - Period Register - 0 - 15 - read-write - - - - - CR1 - Channel 1 Compare Value - 0x0038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR1 - Compare Register for Channel 1 - 0 - 15 - read-only - - - - - CR1S - Channel 1 Compare Shadow Value - 0x003C - 32 - 0x00000000 - 0xFFFFFFFF - - - CR1S - Shadow Compare Register for Channel 1 - 0 - 15 - read-write - - - - - CR2 - Channel 2 Compare Value - 0x0040 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR2 - Compare Register for Channel 2 - 0 - 15 - read-only - - - - - CR2S - Channel 2 Compare Shadow Value - 0x0044 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR2S - Shadow Compare Register for Channel 2 - 0 - 15 - read-write - - - - - CHC - Channel Control - 0x0048 - 32 - 0x00000000 - 0xFFFFFFFF - - - ASE - Asymmetric PWM mode Enable - 0 - 0 - read-write - - - value1 - Asymmetric PWM is disabled - 0b0 - - - value2 - Asymmetric PWM is enabled - 0b1 - - - - - OCS1 - Output selector for CCU8x.OUTy0 - 1 - 1 - read-write - - - value1 - CC8yST1 signal path is connected to the CCU8x.OUTy0 - 0b0 - - - value2 - Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0 - 0b1 - - - - - OCS2 - Output selector for CCU8x.OUTy1 - 2 - 2 - read-write - - - value1 - Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1 - 0b0 - - - value2 - CC8yST1 signal path is connected to the CCU8x.OUTy1 - 0b1 - - - - - OCS3 - Output selector for CCU8x.OUTy2 - 3 - 3 - read-write - - - value1 - CC8yST2 signal path is connected to the CCU8x.OUTy2 - 0b0 - - - value2 - Inverted CCST2 signal path is connected to the CCU8x.OUTy2 - 0b1 - - - - - OCS4 - Output selector for CCU8x.OUTy3 - 4 - 4 - read-write - - - value1 - Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3 - 0b0 - - - value2 - CC8yST2 signal path is connected to the CCU8x.OUTy3 - 0b1 - - - - - - - DTC - Dead Time Control - 0x004C - 32 - 0x00000000 - 0xFFFFFFFF - - - DTE1 - Dead Time Enable for Channel 1 - 0 - 0 - read-write - - - value1 - Dead Time for channel 1 is disabled - 0b0 - - - value2 - Dead Time for channel 1 is enabled - 0b1 - - - - - DTE2 - Dead Time Enable for Channel 2 - 1 - 1 - read-write - - - value1 - Dead Time for channel 2 is disabled - 0b0 - - - value2 - Dead Time for channel 2 is enabled - 0b1 - - - - - DCEN1 - Dead Time Enable for CC8yST1 - 2 - 2 - read-write - - - value1 - Dead Time for CC8yST1 path is disabled - 0b0 - - - value2 - Dead Time for CC8yST1 path is enabled - 0b1 - - - - - DCEN2 - Dead Time Enable for inverted CC8yST1 - 3 - 3 - read-write - - - value1 - Dead Time for inverted CC8yST1 path is disabled - 0b0 - - - value2 - Dead Time for inverted CC8yST1 path is enabled - 0b1 - - - - - DCEN3 - Dead Time Enable for CC8yST2 - 4 - 4 - read-write - - - value1 - Dead Time for CC8yST2 path is disabled - 0b0 - - - value2 - Dead Time for CC8yST2 path is enabled - 0b1 - - - - - DCEN4 - Dead Time Enable for inverted CC8yST2 - 5 - 5 - read-write - - - value1 - Dead Time for inverted CC8yST2 path is disabled - 0b0 - - - value2 - Dead Time for inverted CC8yST2 path is enabled - 0b1 - - - - - DTCC - Dead Time clock control - 6 - 7 - read-write - - - value1 - ftclk - 0b00 - - - value2 - ftclk/2 - 0b01 - - - value3 - ftclk/4 - 0b10 - - - value4 - ftclk/8 - 0b11 - - - - - - - DC1R - Channel 1 Dead Time Values - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - DT1R - Rise Value for Dead Time of Channel 1 - 0 - 7 - read-write - - - DT1F - Fall Value for Dead Time of Channel 1 - 8 - 15 - read-write - - - - - DC2R - Channel 2 Dead Time Values - 0x0054 - 32 - 0x00000000 - 0xFFFFFFFF - - - DT2R - Rise Value for Dead Time of Channel 2 - 0 - 7 - read-write - - - DT2F - Fall Value for Dead Time of Channel 2 - 8 - 15 - read-write - - - - - TIMER - Timer Value - 0x0070 - 32 - 0x00000000 - 0xFFFFFFFF - - - TVAL - Timer Value - 0 - 15 - read-write - - - - - C0V - Capture Register 0 - 0x0074 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C1V - Capture Register 1 - 0x0078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C2V - Capture Register 2 - 0x007C - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C3V - Capture Register 3 - 0x0080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - INTS - Interrupt Status - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PMUS - Period Match while Counting Up - 0 - 0 - read-only - - - value1 - Period match while counting up not detected - 0b0 - - - value2 - Period match while counting up detected - 0b1 - - - - - OMDS - One Match while Counting Down - 1 - 1 - read-only - - - value1 - One match while counting down not detected - 0b0 - - - value2 - One match while counting down detected - 0b1 - - - - - CMU1S - Channel 1 Compare Match while Counting Up - 2 - 2 - read-only - - - value1 - Compare match while counting up not detected - 0b0 - - - value2 - Compare match while counting up detected - 0b1 - - - - - CMD1S - Channel 1 Compare Match while Counting Down - 3 - 3 - read-only - - - value1 - Compare match while counting down not detected - 0b0 - - - value2 - Compare match while counting down detected - 0b1 - - - - - CMU2S - Channel 2 Compare Match while Counting Up - 4 - 4 - read-only - - - value1 - Compare match while counting up not detected - 0b0 - - - value2 - Compare match while counting up detected - 0b1 - - - - - CMD2S - Channel 2 Compare Match while Counting Down - 5 - 5 - read-only - - - value1 - Compare match while counting down not detected - 0b0 - - - value2 - Compare match while counting down detected - 0b1 - - - - - E0AS - Event 0 Detection Status - 8 - 8 - read-only - - - value1 - Event 0 not detected - 0b0 - - - value2 - Event 0 detected - 0b1 - - - - - E1AS - Event 1 Detection Status - 9 - 9 - read-only - - - value1 - Event 1 not detected - 0b0 - - - value2 - Event 1 detected - 0b1 - - - - - E2AS - Event 2 Detection Status - 10 - 10 - read-only - - - value1 - Event 2 not detected - 0b0 - - - value2 - Event 2 detected - 0b1 - - - - - TRPF - Trap Flag Status - 11 - 11 - read-only - - - - - INTE - Interrupt Enable Control - 0x00A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - PME - Period match while counting up enable - 0 - 0 - read-write - - - value1 - Period Match interrupt is disabled - 0b0 - - - value2 - Period Match interrupt is enabled - 0b1 - - - - - OME - One match while counting down enable - 1 - 1 - read-write - - - value1 - One Match interrupt is disabled - 0b0 - - - value2 - One Match interrupt is enabled - 0b1 - - - - - CMU1E - Channel 1 Compare match while counting up enable - 2 - 2 - read-write - - - value1 - Compare Match while counting up interrupt is disabled - 0b0 - - - value2 - Compare Match while counting up interrupt is enabled - 0b1 - - - - - CMD1E - Channel 1 Compare match while counting down enable - 3 - 3 - read-write - - - value1 - Compare Match while counting down interrupt is disabled - 0b0 - - - value2 - Compare Match while counting down interrupt is enabled - 0b1 - - - - - CMU2E - Channel 2 Compare match while counting up enable - 4 - 4 - read-write - - - value1 - Compare Match while counting up interrupt is disabled - 0b0 - - - value2 - Compare Match while counting up interrupt is enabled - 0b1 - - - - - CMD2E - Channel 2 Compare match while counting down enable - 5 - 5 - read-write - - - value1 - Compare Match while counting down interrupt is disabled - 0b0 - - - value2 - Compare Match while counting down interrupt is enabled - 0b1 - - - - - E0AE - Event 0 interrupt enable - 8 - 8 - read-write - - - value1 - Event 0 detection interrupt is disabled - 0b0 - - - value2 - Event 0 detection interrupt is enabled - 0b1 - - - - - E1AE - Event 1 interrupt enable - 9 - 9 - read-write - - - value1 - Event 1 detection interrupt is disabled - 0b0 - - - value2 - Event 1 detection interrupt is enabled - 0b1 - - - - - E2AE - Event 2 interrupt enable - 10 - 10 - read-write - - - value1 - Event 2 detection interrupt is disabled - 0b0 - - - value2 - Event 2 detection interrupt is enabled - 0b1 - - - - - - - SRS - Service Request Selector - 0x00A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSR - Period/One match Service request selector - 0 - 1 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - CM1SR - Channel 1 Compare match Service request selector - 2 - 3 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - CM2SR - Channel 2 Compare match Service request selector - 4 - 5 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - E0SR - Event 0 Service request selector - 8 - 9 - read-write - - - value1 - Forward to CCvySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - E1SR - Event 1 Service request selector - 10 - 11 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - E2SR - Event 2 Service request selector - 12 - 13 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CCvySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - - - SWS - Interrupt Status Set - 0x00AC - 32 - 0x00000000 - 0xFFFFFFFF - - - SPM - Period match while counting up set - 0 - 0 - write-only - - - SOM - One match while counting down set - 1 - 1 - write-only - - - SCM1U - Channel 1 Compare match while counting up set - 2 - 2 - write-only - - - SCM1D - Channel 1 Compare match while counting down set - 3 - 3 - write-only - - - SCM2U - Compare match while counting up set - 4 - 4 - write-only - - - SCM2D - Compare match while counting down set - 5 - 5 - write-only - - - SE0A - Event 0 detection set - 8 - 8 - write-only - - - SE1A - Event 1 detection set - 9 - 9 - write-only - - - SE2A - Event 2 detection set - 10 - 10 - write-only - - - STRPF - Trap Flag status set - 11 - 11 - write-only - - - - - SWR - Interrupt Status Clear - 0x00B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPM - Period match while counting up clear - 0 - 0 - write-only - - - ROM - One match while counting down clear - 1 - 1 - write-only - - - RCM1U - Channel 1 Compare match while counting up clear - 2 - 2 - write-only - - - RCM1D - Channel 1 Compare match while counting down clear - 3 - 3 - write-only - - - RCM2U - Channel 2 Compare match while counting up clear - 4 - 4 - write-only - - - RCM2D - Channel 2 Compare match while counting down clear - 5 - 5 - write-only - - - RE0A - Event 0 detection clear - 8 - 8 - write-only - - - RE1A - Event 1 detection clear - 9 - 9 - write-only - - - RE2A - Event 2 detection clear - 10 - 10 - write-only - - - RTRPF - Trap Flag status clear - 11 - 11 - write-only - - - - - - - CCU80_CC81 - Capture Compare Unit 8 - Unit 0 - CCU8 - 0x40020200 - - 0x0 - 0x100 - registers - - - - CCU80_CC82 - Capture Compare Unit 8 - Unit 0 - CCU8 - 0x40020300 - - 0x0 - 0x100 - registers - - - - CCU80_CC83 - Capture Compare Unit 8 - Unit 0 - CCU8 - 0x40020400 - - 0x0 - 0x100 - registers - - - - CCU81_CC80 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024100 - - 0x0 - 0x100 - registers - - - - CCU81_CC81 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024200 - - 0x0 - 0x100 - registers - - - - CCU81_CC82 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024300 - - 0x0 - 0x100 - registers - - - - CCU81_CC83 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024400 - - 0x0 - 0x100 - registers - - - - POSIF0 - Position Interface 0 - POSIF - POSIF - 0x40028000 - - 0x0 - 0x4000 - registers - - - - PCONF - POSIF configuration - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - FSEL - Function Selector - 0 - 1 - read-write - - - value1 - Hall Sensor Mode enabled - 0b00 - - - value2 - Quadrature Decoder Mode enabled - 0b01 - - - value3 - stand-alone Multi-Channel Mode enabled - 0b10 - - - value4 - Quadrature Decoder and stand-alone Multi-Channel Mode enabled - 0b11 - - - - - QDCM - Position Decoder Mode selection - 2 - 2 - read-write - - - value1 - Position encoder is in Quadrature Mode - 0b0 - - - value2 - Position encoder is in Direction Count Mode. - 0b1 - - - - - HIDG - Idle generation enable - 4 - 4 - read-write - - - MCUE - Multi-Channel Pattern SW update enable - 5 - 5 - read-write - - - value1 - Multi-Channel pattern update is controlled via HW - 0b0 - - - value2 - Multi-Channel pattern update is controlled via SW - 0b1 - - - - - INSEL0 - PhaseA/Hal input 1 selector - 8 - 9 - read-write - - - value1 - POSIFx.IN0A - 0b00 - - - value2 - POSIFx.IN0B - 0b01 - - - value3 - POSIFx.IN0C - 0b10 - - - value4 - POSIFx.IN0D - 0b11 - - - - - INSEL1 - PhaseB/Hall input 2 selector - 10 - 11 - read-write - - - value1 - POSIFx.IN1A - 0b00 - - - value2 - POSIFx.IN1B - 0b01 - - - value3 - POSIFx.IN1C - 0b10 - - - value4 - POSIFx.IN1D - 0b11 - - - - - INSEL2 - Index/Hall input 3 selector - 12 - 13 - read-write - - - value1 - POSIFx.IN2A - 0b00 - - - value2 - POSIFx.IN2B - 0b01 - - - value3 - POSIFx.IN2C - 0b10 - - - value4 - POSIFx.IN2D - 0b11 - - - - - DSEL - Delay Pin selector - 16 - 16 - read-write - - - value1 - POSIFx.HSDA - 0b0 - - - value2 - POSIFx.HSDB - 0b1 - - - - - SPES - Edge selector for the sampling trigger - 17 - 17 - read-write - - - value1 - Rising edge - 0b0 - - - value2 - Falling edge - 0b1 - - - - - MSETS - Pattern update signal select - 18 - 20 - read-write - - - value1 - POSIFx.MSETA - 0b000 - - - value2 - POSIFx.MSETB - 0b001 - - - value3 - POSIFx.MSETC - 0b010 - - - value4 - POSIFx.MSETD - 0b011 - - - value5 - POSIFx.MSETE - 0b100 - - - value6 - POSIFx.MSETF - 0b101 - - - value7 - POSIFx.MSETG - 0b110 - - - value8 - POSIFx.MSETH - 0b111 - - - - - MSES - Multi-Channel pattern update trigger edge - 21 - 21 - read-write - - - value1 - The signal used to enable a pattern update is active on the rising edge - 0b0 - - - value2 - The signal used to enable a pattern update is active on the falling edge - 0b1 - - - - - MSYNS - PWM synchronization signal selector - 22 - 23 - read-write - - - value1 - POSIFx.MSYNCA - 0b00 - - - value2 - POSIFx.MSYNCB - 0b01 - - - value3 - POSIFx.MSYNCC - 0b10 - - - value4 - POSIFx.MSYNCD - 0b11 - - - - - EWIS - Wrong Hall Event selection - 24 - 25 - read-write - - - value1 - POSIFx.EWHEA - 0b00 - - - value2 - POSIFx.EWHEB - 0b01 - - - value3 - POSIFx.EWHEC - 0b10 - - - value4 - POSIFx.EWHED - 0b11 - - - - - EWIE - External Wrong Hall Event enable - 26 - 26 - read-write - - - value1 - External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled - 0b0 - - - value2 - External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled. - 0b1 - - - - - EWIL - External Wrong Hall Event active level - 27 - 27 - read-write - - - value1 - POSIFx.EWHE[D...A] signal is active HIGH - 0b0 - - - value2 - POSIFx.EWHE[D...A] signal is active LOW - 0b1 - - - - - LPC - Low Pass Filters Configuration - 28 - 30 - read-write - - - value1 - Low pass filter disabled - 0b000 - - - value2 - Low pass of 1 clock cycle - 0b001 - - - value3 - Low pass of 2 clock cycles - 0b010 - - - value4 - Low pass of 4 clock cycles - 0b011 - - - value5 - Low pass of 8 clock cycles - 0b100 - - - value6 - Low pass of 16 clock cycles - 0b101 - - - value7 - Low pass of 32 clock cycles - 0b110 - - - value8 - Low pass of 64 clock cycles - 0b111 - - - - - - - PSUS - POSIF Suspend Config - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - QSUS - Quadrature Mode Suspend Config - 0 - 1 - read-write - - - value1 - Suspend request ignored - 0b00 - - - value2 - Stop immediately - 0b01 - - - value3 - Suspend in the next index occurrence - 0b10 - - - value4 - Suspend in the next phase (PhaseA or PhaseB) occurrence - 0b11 - - - - - MSUS - Multi-Channel Mode Suspend Config - 2 - 3 - read-write - - - value1 - Suspend request ignored - 0b00 - - - value2 - Stop immediately. Multi-Channel pattern is not set to the reset value. - 0b01 - - - value3 - Stop immediately. Multi-Channel pattern is set to the reset value. - 0b10 - - - value4 - Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization. - 0b11 - - - - - - - PRUNS - POSIF Run Bit Set - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRB - Set Run bit - 0 - 0 - write-only - - - - - PRUNC - POSIF Run Bit Clear - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - CRB - Clear Run bit - 0 - 0 - write-only - - - CSM - Clear Current internal status - 1 - 1 - write-only - - - - - PRUN - POSIF Run Bit Status - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - RB - Run Bit - 0 - 0 - read-only - - - value1 - IDLE - 0b0 - - - value2 - Running - 0b1 - - - - - - - MIDR - Module Identification register - 0x0020 - 32 - 0x00A8C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - HALP - Hall Sensor Patterns - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - HCP - Hall Current Pattern - 0 - 2 - read-only - - - HEP - Hall Expected Pattern - 3 - 5 - read-only - - - - - HALPS - Hall Sensor Shadow Patterns - 0x0034 - 32 - 0x00000000 - 0xFFFFFFFF - - - HCPS - Shadow Hall Current Pattern - 0 - 2 - read-write - - - HEPS - Shadow Hall expected Pattern - 3 - 5 - read-write - - - - - MCM - Multi-Channel Pattern - 0x0040 - 32 - 0x00000000 - 0xFFFFFFFF - - - MCMP - Multi-Channel Pattern - 0 - 15 - read-only - - - - - MCSM - Multi-Channel Shadow Pattern - 0x0044 - 32 - 0x00000000 - 0xFFFFFFFF - - - MCMPS - Shadow Multi-Channel Pattern - 0 - 15 - read-write - - - - - MCMS - Multi-Channel Pattern Control set - 0x0048 - 32 - 0x00000000 - 0xFFFFFFFF - - - MNPS - Multi-Channel Pattern Update Enable Set - 0 - 0 - write-only - - - STHR - Hall Pattern Shadow Transfer Request - 1 - 1 - write-only - - - STMR - Multi-Channel Shadow Transfer Request - 2 - 2 - write-only - - - - - MCMC - Multi-Channel Pattern Control clear - 0x004C - 32 - 0x00000000 - 0xFFFFFFFF - - - MNPC - Multi-Channel Pattern Update Enable Clear - 0 - 0 - write-only - - - MPC - Multi-Channel Pattern clear - 1 - 1 - write-only - - - - - MCMF - Multi-Channel Pattern Control flag - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - MSS - Multi-Channel Pattern update status - 0 - 0 - read-only - - - value1 - Update of the Multi-Channel pattern is set - 0b0 - - - value2 - Update of the Multi-Channel pattern is not set - 0b1 - - - - - - - QDC - Quadrature Decoder Control - 0x0060 - 32 - 0x00000000 - 0xFFFFFFFF - - - PALS - Phase A Level selector - 0 - 0 - read-write - - - value1 - Phase A is active HIGH - 0b0 - - - value2 - Phase A is active LOW - 0b1 - - - - - PBLS - Phase B Level selector - 1 - 1 - read-write - - - value1 - Phase B is active HIGH - 0b0 - - - value2 - Phase B is active LOW - 0b1 - - - - - PHS - Phase signals swap - 2 - 2 - read-write - - - value1 - Phase A is the leading signal for clockwise rotation - 0b0 - - - value2 - Phase B is the leading signal for clockwise rotation - 0b1 - - - - - ICM - Index Marker generations control - 4 - 5 - read-write - - - value1 - No index marker generation on POSIFx.OUT3 - 0b00 - - - value2 - Only first index occurrence generated on POSIFx.OUT3 - 0b01 - - - value3 - All index occurrences generated on POSIFx.OUT3 - 0b10 - - - value4 - Reserved - 0b11 - - - - - DVAL - Current rotation direction - 8 - 8 - read-only - - - value1 - Counterclockwise rotation - 0b0 - - - value2 - Clockwise rotation - 0b1 - - - - - - - PFLG - POSIF Interrupt Flags - 0x0070 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHES - Correct Hall Event Status - 0 - 0 - read-only - - - value1 - Correct Hall Event not detected - 0b0 - - - value2 - Correct Hall Event detected - 0b1 - - - - - WHES - Wrong Hall Event Status - 1 - 1 - read-only - - - value1 - Wrong Hall Event not detected - 0b0 - - - value2 - Wrong Hall Event detected - 0b1 - - - - - HIES - Hall Inputs Update Status - 2 - 2 - read-only - - - value1 - Transition on the Hall Inputs not detected - 0b0 - - - value2 - Transition on the Hall Inputs detected - 0b1 - - - - - MSTS - Multi-Channel pattern shadow transfer status - 4 - 4 - read-only - - - value1 - Shadow transfer not done - 0b0 - - - value2 - Shadow transfer done - 0b1 - - - - - INDXS - Quadrature Index Status - 8 - 8 - read-only - - - value1 - Index event not detected - 0b0 - - - value2 - Index event detected - 0b1 - - - - - ERRS - Quadrature Phase Error Status - 9 - 9 - read-only - - - value1 - Phase Error event not detected - 0b0 - - - value2 - Phase Error event detected - 0b1 - - - - - CNTS - Quadrature CLK Status - 10 - 10 - read-only - - - value1 - Quadrature clock not generated - 0b0 - - - value2 - Quadrature clock generated - 0b1 - - - - - DIRS - Quadrature Direction Change - 11 - 11 - read-only - - - value1 - Change on direction not detected - 0b0 - - - value2 - Change on direction detected - 0b1 - - - - - PCLKS - Quadrature Period Clk Status - 12 - 12 - read-only - - - value1 - Period clock not generated - 0b0 - - - value2 - Period clock generated - 0b1 - - - - - - - PFLGE - POSIF Interrupt Enable - 0x0074 - 32 - 0x00000000 - 0xFFFFFFFF - - - ECHE - Correct Hall Event Enable - 0 - 0 - read-write - - - value1 - Correct Hall Event interrupt disabled - 0b0 - - - value2 - Correct Hall Event interrupt enabled - 0b1 - - - - - EWHE - Wrong Hall Event Enable - 1 - 1 - read-write - - - value1 - Wrong Hall Event interrupt disabled - 0b0 - - - value2 - Wrong Hall Event interrupt enabled - 0b1 - - - - - EHIE - Hall Input Update Enable - 2 - 2 - read-write - - - value1 - Update of the Hall Inputs interrupt is disabled - 0b0 - - - value2 - Update of the Hall Inputs interrupt is enabled - 0b1 - - - - - EMST - Multi-Channel pattern shadow transfer enable - 4 - 4 - read-write - - - value1 - Shadow transfer event interrupt disabled - 0b0 - - - value2 - Shadow transfer event interrupt enabled - 0b1 - - - - - EINDX - Quadrature Index Event Enable - 8 - 8 - read-write - - - value1 - Index event interrupt disabled - 0b0 - - - value2 - Index event interrupt enabled - 0b1 - - - - - EERR - Quadrature Phase Error Enable - 9 - 9 - read-write - - - value1 - Phase error event interrupt disabled - 0b0 - - - value2 - Phase error event interrupt enabled - 0b1 - - - - - ECNT - Quadrature CLK interrupt Enable - 10 - 10 - read-write - - - value1 - Quadrature CLK event interrupt disabled - 0b0 - - - value2 - Quadrature CLK event interrupt enabled - 0b1 - - - - - EDIR - Quadrature direction change interrupt Enable - 11 - 11 - read-write - - - value1 - Direction change event interrupt disabled - 0b0 - - - value2 - Direction change event interrupt enabled - 0b1 - - - - - EPCLK - Quadrature Period CLK interrupt Enable - 12 - 12 - read-write - - - value1 - Quadrature Period CLK event interrupt disabled - 0b0 - - - value2 - Quadrature Period CLK event interrupt enabled - 0b1 - - - - - CHESEL - Correct Hall Event Service Request Selector - 16 - 16 - read-write - - - value1 - Correct Hall Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Correct Hall Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - WHESEL - Wrong Hall Event Service Request Selector - 17 - 17 - read-write - - - value1 - Wrong Hall Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Wrong Hall Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - HIESEL - Hall Inputs Update Event Service Request Selector - 18 - 18 - read-write - - - value1 - Hall Inputs Update Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Hall Inputs Update Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - MSTSEL - Multi-Channel pattern Update Event Service Request Selector - 20 - 20 - read-write - - - value1 - Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - INDSEL - Quadrature Index Event Service Request Selector - 24 - 24 - read-write - - - value1 - Quadrature Index Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Index Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - ERRSEL - Quadrature Phase Error Event Service Request Selector - 25 - 25 - read-write - - - value1 - Quadrature Phase error Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Phase error Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - CNTSEL - Quadrature Clock Event Service Request Selector - 26 - 26 - read-write - - - value1 - Quadrature Clock Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Clock Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - DIRSEL - Quadrature Direction Update Event Service Request Selector - 27 - 27 - read-write - - - value1 - Quadrature Direction Update Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Direction Update Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - PCLSEL - Quadrature Period clock Event Service Request Selector - 28 - 28 - read-write - - - value1 - Quadrature Period clock Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Period clock Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - - - SPFLG - POSIF Interrupt Set - 0x0078 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCHE - Correct Hall Event flag set - 0 - 0 - write-only - - - SWHE - Wrong Hall Event flag set - 1 - 1 - write-only - - - SHIE - Hall Inputs Update Event flag set - 2 - 2 - write-only - - - SMST - Multi-Channel Pattern shadow transfer flag set - 4 - 4 - write-only - - - SINDX - Quadrature Index flag set - 8 - 8 - write-only - - - SERR - Quadrature Phase Error flag set - 9 - 9 - write-only - - - SCNT - Quadrature CLK flag set - 10 - 10 - write-only - - - SDIR - Quadrature Direction flag set - 11 - 11 - write-only - - - SPCLK - Quadrature period clock flag set - 12 - 12 - write-only - - - - - RPFLG - POSIF Interrupt Clear - 0x007C - 32 - 0x00000000 - 0xFFFFFFFF - - - RCHE - Correct Hall Event flag clear - 0 - 0 - write-only - - - RWHE - Wrong Hall Event flag clear - 1 - 1 - write-only - - - RHIE - Hall Inputs Update Event flag clear - 2 - 2 - write-only - - - RMST - Multi-Channel Pattern shadow transfer flag clear - 4 - 4 - write-only - - - RINDX - Quadrature Index flag clear - 8 - 8 - write-only - - - RERR - Quadrature Phase Error flag clear - 9 - 9 - write-only - - - RCNT - Quadrature CLK flag clear - 10 - 10 - write-only - - - RDIR - Quadrature Direction flag clear - 11 - 11 - write-only - - - RPCLK - Quadrature period clock flag clear - 12 - 12 - write-only - - - - - PDBG - POSIF Debug register - 0x0100 - 32 - 0x00000000 - 0xFFFFFFFF - - - QCSV - Quadrature Decoder Current state - 0 - 1 - read-only - - - QPSV - Quadrature Decoder Previous state - 2 - 3 - read-only - - - IVAL - Current Index Value - 4 - 4 - read-only - - - HSP - Hall Current Sampled Pattern - 5 - 7 - read-only - - - LPP0 - Actual count of the Low Pass Filter for POSI0 - 8 - 13 - read-only - - - LPP1 - Actual count of the Low Pass Filter for POSI1 - 16 - 21 - read-only - - - LPP2 - Actual count of the Low Pass Filter for POSI2 - 22 - 27 - read-only - - - - - - - POSIF1 - Position Interface 1 - POSIF - 0x4002C000 - - 0x0 - 0x4000 - registers - - - - PORT0 - Port 0 - PORTS - 0x48028000 - - 0x0 - 0x0100 - registers - - - - OUT - Port 0 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 0 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 0 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 0 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 0 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 0 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 0 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 0 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 0 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 0 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 0 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 0 Pin Hardware Select Register - 0x74 - 32 - 0x00014000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT1 - Port 1 - PORTS - 0x48028100 - - 0x0 - 0x0100 - registers - - - - OUT - Port 1 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 1 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 1 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 1 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 1 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 1 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 1 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 1 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 1 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 1 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 1 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 1 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT2 - Port 2 - PORTS - 0x48028200 - - 0x0 - 0x0100 - registers - - - - OUT - Port 2 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 2 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 2 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 2 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 2 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 2 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 2 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 2 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 2 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 2 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 2 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 2 Pin Hardware Select Register - 0x74 - 32 - 0x00000004 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT3 - Port 3 - PORTS - 0x48028300 - - 0x0 - 0x0100 - registers - - - - OUT - Port 3 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 3 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 3 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 3 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 3 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 3 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 3 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 3 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 3 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 3 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 3 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 3 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT4 - Port 4 - PORTS - 0x48028400 - - 0x0 - 0x0100 - registers - - - - OUT - Port 4 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 4 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 4 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 4 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IN - Port 4 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 4 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDISC - Port 4 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 4 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 4 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT5 - Port 5 - PORTS - 0x48028500 - - 0x0 - 0x0100 - registers - - - - OUT - Port 5 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 5 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 5 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 5 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 5 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IN - Port 5 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 5 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 5 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 5 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 5 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 5 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT6 - Port 6 - PORTS - 0x48028600 - - 0x0 - 0x0100 - registers - - - - OUT - Port 6 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 6 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 6 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 6 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IN - Port 6 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 6 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDISC - Port 6 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 6 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 6 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT14 - Port 14 - PORTS - 0x48028E00 - - 0x0 - 0x0100 - registers - - - - OUT - Port 14 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 14 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 14 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 14 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 14 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 14 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 14 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDISC - Port 14 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port 14 Pin 0 - 0 - 0 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 0 selected. - 0b1 - - - - - PDIS1 - Pad Disable for Port 14 Pin 1 - 1 - 1 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 1 selected. - 0b1 - - - - - PDIS2 - Pad Disable for Port 14 Pin 2 - 2 - 2 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 and ADC 1 analog input 2 selected. - 0b1 - - - - - PDIS3 - Pad Disable for Port 14 Pin 3 - 3 - 3 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 and ADC 1 analog input 3 selected. - 0b1 - - - - - PDIS4 - Pad Disable for Port 14 Pin 4 - 4 - 4 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 4 and ADC 2 analog input 0 and DAC Reference selected. - 0b1 - - - - - PDIS5 - Pad Disable for Port 14 Pin 5 - 5 - 5 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 5 and ADC 2 analog input 1 selected. - 0b1 - - - - - PDIS6 - Pad Disable for Port 14 Pin 6 - 6 - 6 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 6 selected. - 0b1 - - - - - PDIS7 - Pad Disable for Port 14 Pin 7 - 7 - 7 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC0 analog input 7 selected. - 0b1 - - - - - PDIS8 - Pad Disable for Port 14 Pin 8 - 8 - 8 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 0 and ADC 2 analog input 4 and DAC output 0 selected. - 0b1 - - - - - PDIS9 - Pad Disable for Port 14 Pin 9 - 9 - 9 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 1 and ADC 2 analog input 5 and DAC output 1 selected. - 0b1 - - - - - PDIS12 - Pad Disable for Port 14 Pin 12 - 12 - 12 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 4 selected. - 0b1 - - - - - PDIS13 - Pad Disable for Port 14 Pin 13 - 13 - 13 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 5 selected. - 0b1 - - - - - PDIS14 - Pad Disable for Port 14 Pin 14 - 14 - 14 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 6 selected. - 0b1 - - - - - PDIS15 - Pad Disable for Port 14 Pin 15 - 15 - 15 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 7 selected. - 0b1 - - - - - - - PPS - Port 14 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 14 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT15 - Port 15 - PORTS - 0x48028F00 - - 0x0 - 0x0100 - registers - - - - OUT - Port 15 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 15 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 15 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 15 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 15 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 15 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 15 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDISC - Port 15 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS2 - Pad Disable for Port 15 Pin 2 - 2 - 2 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 2. - 0b1 - - - - - PDIS3 - Pad Disable for Port 15 Pin 3 - 3 - 3 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 3. - 0b1 - - - - - PDIS4 - Pad Disable for Port 15 Pin 4 - 4 - 4 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 4. - 0b1 - - - - - PDIS5 - Pad Disable for Port 15 Pin 5 - 5 - 5 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 5. - 0b1 - - - - - PDIS6 - Pad Disable for Port 15 Pin 6 - 6 - 6 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 6. - 0b1 - - - - - PDIS7 - Pad Disable for Port 15 Pin 7 - 7 - 7 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 7. - 0b1 - - - - - PDIS8 - Pad Disable for Port 15 Pin 8 - 8 - 8 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 0. - 0b1 - - - - - PDIS9 - Pad Disable for Port 15 Pin 9 - 9 - 9 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 1. - 0b1 - - - - - PDIS12 - Pad Disable for Port 15 Pin 12 - 12 - 12 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 4. - 0b1 - - - - - PDIS13 - Pad Disable for Port 15 Pin 13 - 13 - 13 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 5. - 0b1 - - - - - PDIS14 - Pad Disable for Port 15 Pin 14 - 14 - 14 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 6. - 0b1 - - - - - PDIS15 - Pad Disable for Port 15 Pin 15 - 15 - 15 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 7. - 0b1 - - - - - - - PPS - Port 15 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 15 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - + + + + + + + + + + + + + + + + + Infineon + XMC4700 + 1.3.0 (Reference Manual v1.3) + SVD file + + CM4 + r2p0 + little + true + true + 6 + false + + 8 + 32 + + + PPB + Cortex-M4 Private Peripheral Block + 0xE000E000 + + 0x0 + 0x1000 + registers + + + + ACTLR + Auxiliary Control Register + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + DISMCYCINT + Disable load/store multiple + 0 + 0 + read-write + + + DISDEFWBUF + Disable write buffer + 1 + 1 + read-write + + + DISFOLD + Disable IT folding + 2 + 2 + read-write + + + DISFPCA + Disable FPCA update + 8 + 8 + read-write + + + DISOOFP + Disable out of order FP execution + 9 + 9 + read-write + + + + + SYST_CSR + SysTick Control and Status Register + 0x010 + 32 + 0x00000004 + 0xFFFFFFFF + + + ENABLE + Enable + 0 + 0 + read-write + + + value1 + counter disabled + #0 + + + value2 + counter enabled. + #1 + + + + + TICKINT + Tick Interrupt Enable + 1 + 1 + read-write + + + value1 + counting down to zero does not assert the SysTick exception request + #0 + + + value2 + counting down to zero to asserts the SysTick exception request. + #1 + + + + + CLKSOURCE + Indicates the clock source: + 2 + 2 + read-write + + + value1 + external clock + #0 + + + value2 + processor clock. + #1 + + + + + COUNTFLAG + Counter Flag + 16 + 16 + read-write + + + + + SYST_RVR + SysTick Reload Value Register + 0x014 + 32 + 0x00000000 + 0x00000000 + + + RELOAD + Reload Value + 0 + 23 + read-write + + + + + SYST_CVR + SysTick Current Value Register + 0x018 + 32 + 0x00000000 + 0x00000000 + + + CURRENT + Current Value + 0 + 23 + read-write + + + + + SYST_CALIB + SysTick Calibration Value Register r + 0x01C + 32 + 0xC0000000 + 0xFFFFFFFF + + + TENMS + Ten Milliseconds Reload Value + 0 + 23 + read-write + + + SKEW + Ten Milliseconds Skewed + 30 + 30 + read-write + + + value1 + TENMS value is exact + #0 + + + value2 + TENMS value is inexact, or not given. + #1 + + + + + NOREF + No Reference Clock + 31 + 31 + read-write + + + value1 + reference clock provided + #0 + + + value2 + no reference clock provided. + #1 + + + + + + + NVIC_ISER0 + Interrupt Set-enable Register 0 + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISER1 + Interrupt Set-enable Register 1 + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISER2 + Interrupt Set-enable Register 2 + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISER3 + Interrupt Set-enable Register 3 + 0x10C + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER0 + Interrupt Clear-enable Register 0 + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER1 + Interrupt Clear-enable Register 1 + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER2 + Interrupt Clear-enable Register 2 + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER3 + Interrupt Clear-enable Register 3 + 0x18C + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISPR0 + Interrupt Set-pending Register 0 + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ISPR1 + Interrupt Set-pending Register 1 + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ISPR2 + Interrupt Set-pending Register 2 + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ISPR3 + Interrupt Set-pending Register 3 + 0x20C + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR0 + Interrupt Clear-pending Register 0 + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR1 + Interrupt Clear-pending Register 1 + 0x284 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR2 + Interrupt Clear-pending Register 2 + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR3 + Interrupt Clear-pending Register 3 + 0x28C + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_IABR0 + Interrupt Active Bit Register 0 + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IABR1 + Interrupt Active Bit Register 1 + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IABR2 + Interrupt Active Bit Register 2 + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IABR3 + Interrupt Active Bit Register 3 + 0x30C + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IPR0 + Interrupt Priority Register 0 + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR1 + Interrupt Priority Register 1 + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR2 + Interrupt Priority Register 2 + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR3 + Interrupt Priority Register 3 + 0x40C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR4 + Interrupt Priority Register 4 + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR5 + Interrupt Priority Register 5 + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR6 + Interrupt Priority Register 6 + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR7 + Interrupt Priority Register 7 + 0x41C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR8 + Interrupt Priority Register 8 + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR9 + Interrupt Priority Register 9 + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR10 + Interrupt Priority Register 10 + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR11 + Interrupt Priority Register 11 + 0x42C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR12 + Interrupt Priority Register 12 + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR13 + Interrupt Priority Register 13 + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR14 + Interrupt Priority Register 14 + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR15 + Interrupt Priority Register 15 + 0x43C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR16 + Interrupt Priority Register 16 + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR17 + Interrupt Priority Register 17 + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR18 + Interrupt Priority Register 18 + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR19 + Interrupt Priority Register 19 + 0x44C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR20 + Interrupt Priority Register 20 + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR21 + Interrupt Priority Register 21 + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR22 + Interrupt Priority Register 22 + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR23 + Interrupt Priority Register 23 + 0x45C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR24 + Interrupt Priority Register 24 + 0x460 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR25 + Interrupt Priority Register 25 + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR26 + Interrupt Priority Register 26 + 0x468 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR27 + Interrupt Priority Register 27 + 0x46C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + 0x410FC241 + 0xFFFFFFFF + + + Revision + Revision number + 0 + 3 + read-only + + + value1 + Patch 1 + 0x1 + + + + + PartNo + Part number of the processor + 4 + 15 + read-only + + + value1 + Cortex-M4 + 0xC24 + + + + + Constant + Reads as 0xF + 16 + 19 + read-only + + + Variant + Variant number + 20 + 23 + read-only + + + value1 + Revision 0 + 0x0 + + + + + Implementer + Implementer code + 24 + 31 + read-only + + + value1 + ARM + 0x41 + + + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 8 + read-only + + + value1 + Thread mode + 0x00 + + + + + RETTOBASE + Return to Base + 11 + 11 + read-only + + + value1 + there are preempted active exceptions to execute + #0 + + + value2 + there are no active exceptions, or the currently-executing exception is the only active exception. + #1 + + + + + VECTPENDING + Vector Pending + 12 + 17 + read-only + + + value1 + no pending exceptions + 0x0 + + + + + ISRPENDING + Interrupt pending flag + 22 + 22 + read-only + + + value1 + interrupt not pending + #0 + + + value2 + interrupt pending. + #1 + + + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 25 + write-only + + + value1 + no effect + #0 + + + value2 + removes the pending state from the SysTick exception. + #1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 26 + read-write + + + value1 + no effect + #0 + + + value2 + changes SysTick exception state to pending. + #1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 27 + write-only + + + value1 + no effect + #0 + + + value2 + removes the pending state from the PendSV exception. + #1 + + + + + PENDSVSET + PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending., + 28 + 28 + read-write + + + NMIPENDSET + NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending., + 31 + 31 + read-write + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset field + 10 + 31 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + Reserved for Debug use. + 0 + 0 + write-only + + + VECTCLRACTIVE + Reserved for Debug use. + 1 + 1 + write-only + + + SYSRESETREQ + System reset request + 2 + 2 + write-only + + + value1 + no system reset request + #0 + + + value2 + asserts a signal to the outer system that requests a reset. + #1 + + + + + PRIGROUP + Interrupt priority grouping field + 8 + 10 + read-write + + + ENDIANNESS + Data endianness bit + 15 + 15 + read-only + + + value1 + Little-endian + #0 + + + value2 + Big-endian. + #1 + + + + + VECTKEY + Register key + 16 + 31 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLEEPONEXIT + Sleep on Exit + 1 + 1 + read-write + + + value1 + do not sleep when returning to Thread mode. + #0 + + + value2 + enter sleep, or deep sleep, on return from an ISR. + #1 + + + + + SLEEPDEEP + Sleep or Deep Sleep + 2 + 2 + read-write + + + value1 + sleep + #0 + + + value2 + deep sleep + #1 + + + + + SEVONPEND + Send Event on Pending bit: + 4 + 4 + read-write + + + value1 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + #0 + + + value2 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + #1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + 0x00000200 + 0xFFFFFFFF + + + NONBASETHRDENA + Non Base Thread Mode Enable + 0 + 0 + read-write + + + value1 + processor can enter Thread mode only when no exception is active. + #0 + + + value2 + processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. . + #1 + + + + + USERSETMPEND + User Set Pending Enable + 1 + 1 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + UNALIGN_TRP + Unaligned Access Trap Enable + 3 + 3 + read-write + + + value1 + do not trap unaligned halfword and word accesses + #0 + + + value2 + trap unaligned halfword and word accesses. + #1 + + + + + DIV_0_TRP + Divide by Zero Trap Enable + 4 + 4 + read-write + + + value1 + do not trap divide by 0 + #0 + + + value2 + trap divide by 0. + #1 + + + + + BFHFNMIGN + Bus Fault Hard Fault and NMI Ignore + 8 + 8 + read-write + + + value1 + data bus faults caused by load and store instructions cause a lock-up + #0 + + + value2 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. + #1 + + + + + STKALIGN + Stack Alignment + 9 + 9 + read-write + + + value1 + 4-byte aligned + #0 + + + value2 + 8-byte aligned. + #1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 7 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 15 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 23 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 31 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14 + 16 + 23 + read-write + + + PRI_15 + Priority of system handler 15 + 24 + 31 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active bit + 0 + 0 + read-write + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + read-write + + + USGFAULTACT + UsageFault exception active bit + 3 + 3 + read-write + + + SVCALLACT + SVCall active bit + 7 + 7 + read-write + + + MONITORACT + Debug monitor active bit + 8 + 8 + read-write + + + PENDSVACT + PendSV exception active bit + 10 + 10 + read-write + + + SYSTICKACT + SysTick exception active bit + 11 + 11 + read-write + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 12 + read-write + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 13 + read-write + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 14 + read-write + + + SVCALLPENDED + SVCall pending bit + 15 + 15 + read-write + + + MEMFAULTENA + MemManage enable bit + 16 + 16 + read-write + + + BUSFAULTENA + BusFault enable bit + 17 + 17 + read-write + + + USGFAULTENA + UsageFault enable bit + 18 + 18 + read-write + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + 0x00000000 + 0xFFFFFFFF + + + IACCVIOL + Instruction access violation flag + 0 + 0 + read-write + + + value1 + no instruction access violation fault + #0 + + + value2 + the processor attempted an instruction fetch from a location that does not permit execution. + #1 + + + + + DACCVIOL + Data access violation flag + 1 + 1 + read-write + + + value1 + no data access violation fault + #0 + + + value2 + the processor attempted a load or store at a location that does not permit the operation. + #1 + + + + + MUNSTKERR + MemManage fault on unstacking for a return from exception + 3 + 3 + read-write + + + value1 + no unstacking fault + #0 + + + value2 + unstack for an exception return has caused one or more access violations. + #1 + + + + + MSTKERR + MemManage fault on stacking for exception entry + 4 + 4 + read-write + + + value1 + no stacking fault + #0 + + + value2 + stacking for an exception entry has caused one or more access violations. + #1 + + + + + MLSPERR + MemManage fault during floating point lazy state preservation + 5 + 5 + read-write + + + value1 + No MemManage fault occurred during floating-point lazy state preservation + #0 + + + value2 + A MemManage fault occurred during floating-point lazy state preservation + #1 + + + + + MMARVALID + MemManage Fault Address Register (MMFAR) valid flag + 7 + 7 + read-write + + + value1 + value in MMAR is not a valid fault address + #0 + + + value2 + MMAR holds a valid fault address. + #1 + + + + + IBUSERR + Instruction bus error + 8 + 8 + read-write + + + value1 + no instruction bus error + #0 + + + value2 + instruction bus error. + #1 + + + + + PRECISERR + Precise data bus error + 9 + 9 + read-write + + + value1 + no precise data bus error + #0 + + + value2 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. + #1 + + + + + IMPRECISERR + Imprecise data bus error + 10 + 10 + read-write + + + value1 + no imprecise data bus error + #0 + + + value2 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. + #1 + + + + + UNSTKERR + BusFault on unstacking for a return from exception + 11 + 11 + read-write + + + value1 + no unstacking fault + #0 + + + value2 + stacking for an exception entry has caused one or more BusFaults. + #1 + + + + + STKERR + BusFault on stacking for exception entry + 12 + 12 + read-write + + + value1 + no stacking fault + #0 + + + value2 + stacking for an exception entry has caused one or more BusFaults. + #1 + + + + + LSPERR + BusFault during floating point lazy state preservation + 13 + 13 + read-write + + + value1 + No bus fault occurred during floating-point lazy state preservation. + #0 + + + value2 + A bus fault occurred during floating-point lazy state preservation + #1 + + + + + BFARVALID + BusFault Address Register (BFAR) valid flag + 15 + 15 + read-write + + + value1 + value in BFAR is not a valid fault address + #0 + + + value2 + BFAR holds a valid fault address. + #1 + + + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 16 + read-write + + + value1 + no undefined instruction UsageFault + #0 + + + value2 + the processor has attempted to execute an undefined instruction. + #1 + + + + + INVSTATE + Invalid state UsageFault + 17 + 17 + read-write + + + value1 + no invalid state UsageFault + #0 + + + value2 + the processor has attempted to execute an instruction that makes illegal use of the EPSR. + #1 + + + + + INVPC + Invalid PC load UsageFault + 18 + 18 + read-write + + + value1 + no invalid PC load UsageFault + #0 + + + value2 + the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. + #1 + + + + + NOCP + No coprocessor UsageFault + 19 + 19 + read-write + + + value1 + no UsageFault caused by attempting to access a coprocessor + #0 + + + value2 + the processor has attempted to access a coprocessor. + #1 + + + + + UNALIGNED + Unaligned access UsageFault + 24 + 24 + read-write + + + value1 + no unaligned access fault, or unaligned access trapping not enabled + #0 + + + value2 + the processor has made an unaligned memory access. + #1 + + + + + DIVBYZERO + Divide by zero UsageFault + 25 + 25 + read-write + + + value1 + no divide by zero fault, or divide by zero trapping not enabled + #0 + + + value2 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + #1 + + + + + + + HFSR + HardFault Status Register + 0xD2C + 32 + 0x00000000 + 0xFFFFFFFF + + + VECTTBL + BusFault on vector table read + 1 + 1 + read-write + + + value1 + no BusFault on vector table read + #0 + + + value2 + BusFault on vector table read + #1 + + + + + FORCED + Forced HardFault + 30 + 30 + read-write + + + value1 + no forced HardFault + #0 + + + value2 + forced HardFault. + #1 + + + + + DEBUGEVT + Reserved for Debug use + 31 + 31 + read-write + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + 0x00000000 + 0x00000000 + + + ADDRESS + Address causing the fault + 0 + 31 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + 0x00000000 + 0x00000000 + + + ADDRESS + Address causing the fault + 0 + 31 + read-write + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + Reserved + 0 + 31 + read-write + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + 0x00000000 + 0xFFFFFFFF + + + CP10 + Access privileges for coprocessor 10 + 20 + 21 + read-write + + + value1 + Access denied. Any attempted access generates a NOCP UsageFault. + #00 + + + value2 + Privileged access only. An unprivileged access generates a NOCP fault. + #01 + + + value4 + Full access. + #11 + + + + + CP11 + Access privileges for coprocessor 11 + 22 + 23 + read-write + + + value1 + Access denied. Any attempted access generates a NOCP UsageFault. + #00 + + + value2 + Privileged access only. An unprivileged access generates a NOCP fault. + #01 + + + value4 + Full access. + #11 + + + + + + + MPU_TYPE + MPU Type Register + 0xD90 + 32 + 0x00000800 + 0xFFFFFFFF + + + SEPARATE + Support for unified or separate instruction and date memory maps + 0 + 0 + read-only + + + DREGION + Number of supported MPU data regions + 8 + 15 + read-only + + + IREGION + Number of supported MPU instruction regions + 16 + 23 + read-only + + + + + MPU_CTRL + MPU Control Register + 0xD94 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Enable MPU + 0 + 0 + read-write + + + value1 + MPU disabled + #0 + + + value2 + MPU enabled. + #1 + + + + + HFNMIENA + Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers + 1 + 1 + read-write + + + value1 + MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit + #0 + + + value2 + the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. + #1 + + + + + PRIVDEFENA + Enables privileged software access to the default memory map + 2 + 2 + read-write + + + value1 + If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. + #0 + + + value2 + If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. + #1 + + + + + + + MPU_RNR + MPU Region Number Register + 0xD98 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + Region + 0 + 7 + read-write + + + + + MPU_RBAR + MPU Region Base Address Register + 0xD9C + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR + MPU Region Attribute and Size Register + 0xDA0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + MPU_RBAR_A1 + MPU Region Base Address Register A1 + 0xDA4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR_A1 + MPU Region Attribute and Size Register A1 + 0xDA8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + MPU_RBAR_A2 + MPU Region Base Address Register A2 + 0xDAC + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR_A2 + MPU Region Attribute and Size Register A2 + 0xDB0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + MPU_RBAR_A3 + MPU Region Base Address Register A3 + 0xDB4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR_A3 + MPU Region Attribute and Size Register A3 + 0xDB8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + STIR + Software Trigger Interrupt Register + 0xF00 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger + 0 + 8 + write-only + + + + + FPCCR + Floating-point Context Control Register + 0xF34 + 32 + 0x00000000 + 0xFFFFFFFF + + + LSPACT + Lazy State Preservation Active + 0 + 0 + read-write + + + value1 + Lazy state preservation is not active. + #0 + + + value2 + Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. + #1 + + + + + USER + User allocated Stack Frame + 1 + 1 + read-write + + + value1 + Privilege level was not user when the floating-point stack frame was allocated. + #0 + + + value2 + Privilege level was user when the floating-point stack frame was allocated. + #1 + + + + + THREAD + Thread Mode allocated Stack Frame + 3 + 3 + read-write + + + value1 + Mode was not Thread Mode when the floating-point stack frame was allocated. + #0 + + + value2 + Mode was Thread Mode when the floating-point stack frame was allocated. + #1 + + + + + HFRDY + HardFault Ready + 4 + 4 + read-write + + + value1 + Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. + #0 + + + value2 + Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. + #1 + + + + + MMRDY + MemManage Ready + 5 + 5 + read-write + + + value1 + MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. + #0 + + + value2 + MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. + #1 + + + + + BFRDY + BusFault Ready + 6 + 6 + read-write + + + value1 + BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. + #0 + + + value2 + BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. + #1 + + + + + MONRDY + Monitor Ready + 8 + 8 + read-write + + + value1 + Debug Monitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. + #0 + + + value2 + Debug Monitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. + #1 + + + + + LSPEN + Lazy State Preservation Enabled + 30 + 30 + read-write + + + value1 + Disable automatic lazy state preservation for floating-point context. + #0 + + + value2 + Enable automatic lazy state preservation for floating-point context. + #1 + + + + + ASPEN + Automatic State Preservation + 31 + 31 + read-write + + + value1 + Disable CONTROL setting on execution of a floating-point instruction. + #0 + + + value2 + Enable CONTROL setting on execution of a floating-point instruction. + #1 + + + + + + + FPCAR + Floating-point Context Address Register + 0xF38 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + Address + 3 + 31 + read-write + + + + + FPDSCR + Floating-point Default Status Control Register + 0xF3C + 32 + 0x00000000 + 0xFFFFFFFF + + + RMode + Default value for FPSCR.RMode + 22 + 23 + read-write + + + FZ + Default value for FPSCR.FZ + 24 + 24 + read-write + + + DN + Default value for FPSCR.DN + 25 + 25 + read-write + + + AHP + Default value for FPSCR.AHP + 26 + 26 + read-write + + + + + + + DLR + DMA Line Router + 0x50004900 + + 0x0 + 0x0100 + registers + + + + OVRSTAT + Overrun Status + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + LN0 + Line 0 Overrun Status + 0 + 0 + read-only + + + LN1 + Line 1 Overrun Status + 1 + 1 + read-only + + + LN2 + Line 2 Overrun Status + 2 + 2 + read-only + + + LN3 + Line 3 Overrun Status + 3 + 3 + read-only + + + LN4 + Line 4 Overrun Status + 4 + 4 + read-only + + + LN5 + Line 5 Overrun Status + 5 + 5 + read-only + + + LN6 + Line 6 Overrun Status + 6 + 6 + read-only + + + LN7 + Line 7 Overrun Status + 7 + 7 + read-only + + + LN8 + Line 8 Overrun Status + 8 + 8 + read-only + + + LN9 + Line 9 Overrun Status + 9 + 9 + read-only + + + LN10 + Line 10 Overrun Status + 10 + 10 + read-only + + + LN11 + Line 11 Overrun Status + 11 + 11 + read-only + + + + + OVRCLR + Overrun Clear + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + LN0 + Line 0 Overrun Status Clear + 0 + 0 + write-only + + + LN1 + Line 1 Overrun Status Clear + 1 + 1 + write-only + + + LN2 + Line 2 Overrun Status Clear + 2 + 2 + write-only + + + LN3 + Line 3 Overrun Status Clear + 3 + 3 + write-only + + + LN4 + Line 4 Overrun Status Clear + 4 + 4 + write-only + + + LN5 + Line 5 Overrun Status Clear + 5 + 5 + write-only + + + LN6 + Line 6 Overrun Status Clear + 6 + 6 + write-only + + + LN7 + Line 7 Overrun Status Clear + 7 + 7 + write-only + + + LN8 + Line 8 Overrun Status Clear + 8 + 8 + write-only + + + LN9 + Line 9 Overrun Status Clear + 9 + 9 + write-only + + + LN10 + Line 10 Overrun Status Clear + 10 + 10 + write-only + + + LN11 + Line 11 Overrun Status Clear + 11 + 11 + write-only + + + + + SRSEL0 + Service Request Selection 0 + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + RS0 + Request Source for Line 0 + 0 + 3 + read-write + + + RS1 + Request Source for Line 1 + 4 + 7 + read-write + + + RS2 + Request Source for Line 2 + 8 + 11 + read-write + + + RS3 + Request Source for Line 3 + 12 + 15 + read-write + + + RS4 + Request Source for Line 4 + 16 + 19 + read-write + + + RS5 + Request Source for Line 5 + 20 + 23 + read-write + + + RS6 + Request Source for Line 6 + 24 + 27 + read-write + + + RS7 + Request Source for Line 7 + 28 + 31 + read-write + + + + + SRSEL1 + Service Request Selection 1 + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + RS8 + Request Source for Line 8 + 0 + 3 + read-write + + + RS9 + Request Source for Line 9 + 4 + 7 + read-write + + + RS10 + Request Source for Line 10 + 8 + 11 + read-write + + + RS11 + Request Source for Line 11 + 12 + 15 + read-write + + + + + LNEN + Line Enable + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + LN0 + Line 0 Enable + 0 + 0 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN1 + Line 1 Enable + 1 + 1 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN2 + Line 2 Enable + 2 + 2 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN3 + Line 3 Enable + 3 + 3 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN4 + Line 4 Enable + 4 + 4 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN5 + Line 5 Enable + 5 + 5 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN6 + Line 6 Enable + 6 + 6 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN7 + Line 7 Enable + 7 + 7 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN8 + Line 8 Enable + 8 + 8 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN9 + Line 9 Enable + 9 + 9 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN10 + Line 10 Enable + 10 + 10 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN11 + Line 11 Enable + 11 + 11 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + + + + + ERU0 + Event Request Unit 0 + ERU + ERU + 0x50004800 + + 0x0 + 0x0100 + registers + + + ERU0_0 + External Request Unit 0 + 1 + + + ERU0_1 + External Request Unit 0 + 2 + + + ERU0_2 + External Request Unit 0 + 3 + + + ERU0_3 + External Request Unit 0 + 4 + + + + EXISEL + Event Input Select + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + EXS0A + Event Source Select for A0 (ERS0) + 0 + 1 + read-write + + + value1 + Input ERU_0A0 is selected + #00 + + + value2 + Input ERU_0A1 is selected + #01 + + + value3 + Input ERU_0A2 is selected + #10 + + + value4 + Input ERU_0A3 is selected + #11 + + + + + EXS0B + Event Source Select for B0 (ERS0) + 2 + 3 + read-write + + + value1 + Input ERU_0B0 is selected + #00 + + + value2 + Input ERU_0B1 is selected + #01 + + + value3 + Input ERU_0B2 is selected + #10 + + + value4 + Input ERU_0B3 is selected + #11 + + + + + EXS1A + Event Source Select for A1 (ERS1) + 4 + 5 + read-write + + + value1 + Input ERU_1A0 is selected + #00 + + + value2 + Input ERU_1A1 is selected + #01 + + + value3 + Input ERU_1A2 is selected + #10 + + + value4 + Input ERU_1A3 is selected + #11 + + + + + EXS1B + Event Source Select for B1 (ERS1) + 6 + 7 + read-write + + + value1 + Input ERU_1B0 is selected + #00 + + + value2 + Input ERU_1B1 is selected + #01 + + + value3 + Input ERU_1B2 is selected + #10 + + + value4 + Input ERU_1B3 is selected + #11 + + + + + EXS2A + Event Source Select for A2 (ERS2) + 8 + 9 + read-write + + + value1 + Input ERU_2A0 is selected + #00 + + + value2 + Input ERU_2A1 is selected + #01 + + + value3 + Input ERU_2A2 is selected + #10 + + + value4 + Input ERU_2A3 is selected + #11 + + + + + EXS2B + Event Source Select for B2 (ERS2) + 10 + 11 + read-write + + + value1 + Input ERU_2B0 is selected + #00 + + + value2 + Input ERU_2B1 is selected + #01 + + + value3 + Input ERU_2B2 is selected + #10 + + + value4 + Input ERU_2B3 is selected + #11 + + + + + EXS3A + Event Source Select for A3 (ERS3) + 12 + 13 + read-write + + + value1 + Input ERU_3A0 is selected + #00 + + + value2 + Input ERU_3A1 is selected + #01 + + + value3 + Input ERU_3A2 is selected + #10 + + + value4 + Input ERU_3A3 is selected + #11 + + + + + EXS3B + Event Source Select for B3 (ERS3) + 14 + 15 + read-write + + + value1 + Input ERU_3B0 is selected + #00 + + + value2 + Input ERU_3B1 is selected + #01 + + + value3 + Input ERU_3B2 is selected + #10 + + + value4 + Input ERU_3B3 is selected + #11 + + + + + + + 4 + 4 + EXICON[%s] + Event Input Control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PE + Output Trigger Pulse Enable for ETLx + 0 + 0 + read-write + + + value1 + The trigger pulse generation is disabled + #0 + + + value2 + The trigger pulse generation is enabled + #1 + + + + + LD + Rebuild Level Detection for Status Flag for ETLx + 1 + 1 + read-write + + + value1 + The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software. + #0 + + + value2 + The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0. + #1 + + + + + RE + Rising Edge Detection Enable ETLx + 2 + 2 + read-write + + + value1 + A rising edge is not considered as edge event + #0 + + + value2 + A rising edge is considered as edge event + #1 + + + + + FE + Falling Edge Detection Enable ETLx + 3 + 3 + read-write + + + value1 + A falling edge is not considered as edge event + #0 + + + value2 + A falling edge is considered as edge event + #1 + + + + + OCS + Output Channel Select for ETLx Output Trigger Pulse + 4 + 6 + read-write + + + value1 + Trigger pulses are sent to OGU0 + #000 + + + value2 + Trigger pulses are sent to OGU1 + #001 + + + value3 + Trigger pulses are sent to OGU2 + #010 + + + value4 + Trigger pulses are sent to OGU3 + #011 + + + + + FL + Status Flag for ETLx + 7 + 7 + read-write + + + value1 + The enabled edge event has not been detected + #0 + + + value2 + The enabled edge event has been detected + #1 + + + + + SS + Input Source Select for ERSx + 8 + 9 + read-write + + + value1 + Input A without additional combination + #00 + + + value2 + Input B without additional combination + #01 + + + value3 + Input A OR input B + #10 + + + value4 + Input A AND input B + #11 + + + + + NA + Input A Negation Select for ERSx + 10 + 10 + read-write + + + value1 + Input A is used directly + #0 + + + value2 + Input A is inverted + #1 + + + + + NB + Input B Negation Select for ERSx + 11 + 11 + read-write + + + value1 + Input B is used directly + #0 + + + value2 + Input B is inverted + #1 + + + + + + + 4 + 4 + EXOCON[%s] + Event Output Trigger Control + 0x20 + 32 + 0x00000008 + 0xFFFFFFFF + + + ISS + Internal Trigger Source Selection + 0 + 1 + read-write + + + value1 + The peripheral trigger function is disabled + #00 + + + value2 + Input ERU_OGUy1 is selected + #01 + + + value3 + Input ERU_OGUy2 is selected + #10 + + + value4 + Input ERU_OGUy3 is selected + #11 + + + + + GEEN + Gating Event Enable + 2 + 2 + read-write + + + value1 + The event detection is disabled + #0 + + + value2 + The event detection is enabled + #1 + + + + + PDR + Pattern Detection Result Flag + 3 + 3 + read-only + + + value1 + A pattern miss is detected + #0 + + + value2 + A pattern match is detected + #1 + + + + + GP + Gating Selection for Pattern Detection Result + 4 + 5 + read-write + + + value1 + ERU_GOUTy is always disabled and ERU_IOUTy can not be activated + #00 + + + value2 + ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy + #01 + + + value3 + ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1) + #10 + + + value4 + ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0) + #11 + + + + + IPEN0 + Pattern Detection Enable for ETL0 + 12 + 12 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + IPEN1 + Pattern Detection Enable for ETL1 + 13 + 13 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + IPEN2 + Pattern Detection Enable for ETL2 + 14 + 14 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + IPEN3 + Pattern Detection Enable for ETL3 + 15 + 15 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + + + + + ERU1 + Event Request Unit 1 + ERU + 0x40044000 + + 0x0 + 0x4000 + registers + + + ERU1_0 + External Request Unit 1 + 5 + + + ERU1_1 + External Request Unit 1 + 6 + + + ERU1_2 + External Request Unit 1 + 7 + + + ERU1_3 + External Request Unit 1 + 8 + + + + GPDMA0 + General Purpose DMA Unit 0 + GPDMA + 0x500142C0 + + 0x0 + 0x3D40 + registers + + + GPDMA0_0 + General Purpose DMA Unit 0 + 105 + + + + RAWTFR + Raw IntTfr Status + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWBLOCK + Raw IntBlock Status + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWSRCTRAN + Raw IntSrcTran Status + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWDSTTRAN + Raw IntBlock Status + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWERR + Raw IntErr Status + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + STATUSTFR + IntTfr Status + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSBLOCK + IntBlock Status + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSSRCTRAN + IntSrcTran Status + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSDSTTRAN + IntBlock Status + 0x040 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSERR + IntErr Status + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + MASKTFR + Mask for Raw IntTfr Status + 0x050 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKBLOCK + Mask for Raw IntBlock Status + 0x058 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKSRCTRAN + Mask for Raw IntSrcTran Status + 0x060 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKDSTTRAN + Mask for Raw IntBlock Status + 0x068 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKERR + Mask for Raw IntErr Status + 0x070 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + CLEARTFR + IntTfr Status + 0x078 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARBLOCK + IntBlock Status + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARSRCTRAN + IntSrcTran Status + 0x088 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARDSTTRAN + IntBlock Status + 0x090 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARERR + IntErr Status + 0x098 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + STATUSINT + Combined Interrupt Status Register + 0x0A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ERR + OR of the contents of STATUSERR register + 4 + 4 + read-only + + + DSTT + OR of the contents of STATUSDSTTRAN register + 3 + 3 + read-only + + + SRCT + OR of the contents of STATUSSRCTRAN register + 2 + 2 + read-only + + + BLOCK + OR of the contents of STATUSBLOCK register + 1 + 1 + read-only + + + TFR + OR of the contents of STATUSTFR register + 0 + 0 + read-only + + + + + REQSRCREG + Source Software Transaction Request Register + 0x0A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + REQDSTREG + Destination Software Transaction Request Register + 0x0B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + SGLREQSRCREG + Single Source Transaction Request Register + 0x0B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + SGLREQDSTREG + Single Destination Transaction Request Register + 0x0C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + LSTSRCREG + Last Source Transaction Request Register + 0x0C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source last transaction request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source last transaction request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source last transaction request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source last transaction request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Source last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Source last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Source last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH4 + Source last request for channel 4 + 4 + 4 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH5 + Source last request for channel 5 + 5 + 5 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH6 + Source last request for channel 6 + 6 + 6 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH7 + Source last request for channel 7 + 7 + 7 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + LSTDSTREG + Last Destination Transaction Request Register + 0x0D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Destination last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Destination last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Destination last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Destination last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Destination last transaction request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Destination last transaction request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Destination last transaction request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Destination last transaction request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Destination last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Destination last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Destination last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Destination last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH4 + Destination last request for channel 4 + 4 + 4 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH5 + Destination last request for channel 5 + 5 + 5 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH6 + Destination last request for channel 6 + 6 + 6 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH7 + Destination last request for channel 7 + 7 + 7 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + DMACFGREG + GPDMA Configuration Register + 0x0D8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DMA_EN + GPDMA Enable bit. + 0 + 0 + read-write + + + value1 + GPDMA Disabled + #0 + + + value2 + GPDMA Enabled. + #1 + + + + + + + CHENREG + GPDMA Channel Enable Register + 0x0E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH + Channel enable write enable + 8 + 15 + write-only + + + CH + Enables/Disables the channel + 0 + 7 + read-write + + + value1 + Disable the Channel + #0 + + + value2 + Enable the Channel + #1 + + + + + + + ID + GPDMA0 ID Register + 0x0E8 + 32 + 0x00AFC000 + 0xFFFFFF00 + + + VALUE + Hardcoded GPDMA Peripheral ID + 0 + 31 + read-only + + + + + TYPE + GPDMA Component Type + 0x138 + 32 + 0x44571110 + 0xFFFFFFFF + + + VALUE + Component Type + 0 + 31 + read-only + + + + + VERSION + DMA Component Version + 0x13C + 32 + 0x3231342A + 0xFFFFFFFF + + + VALUE + Version number of the component + 0 + 31 + read-only + + + + + + + GPDMA0_CH0 + General Purpose DMA Unit 0 + GPDMA + GPDMA0_CH0_1 + 0x50014000 + + 0x0 + 0x55 + registers + + + + SAR + Source Address Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + SAR + Current Source Address of DMA transfer + 0 + 31 + read-write + + + + + DAR + Destination Address Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAR + Current Destination address of DMA transfer + 0 + 31 + read-write + + + + + LLP + Linked List Pointer Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + Starting Address In Memory + 2 + 31 + read-write + + + + + CTLL + Control Register Low + 0x18 + 32 + 0x00304801 + 0xFFFFFFFF + + + LLP_SRC_EN + Linked List Pointer for Source Enable + 28 + 28 + read-write + + + LLP_DST_EN + Linked List Pointer for Destination Enable + 27 + 27 + read-write + + + TT_FC + Transfer Type and Flow Control + 20 + 22 + read-write + + + DST_SCATTER_EN + Destination scatter enable + 18 + 18 + read-write + + + value1 + Scatter disabled + #0 + + + value2 + Scatter enabled + #1 + + + + + SRC_GATHER_EN + Source gather enable + 17 + 17 + read-write + + + value1 + Gather disabled + #0 + + + value2 + Gather enabled + #1 + + + + + SRC_MSIZE + Source Burst Transaction Length + 14 + 16 + read-write + + + DEST_MSIZE + Destination Burst Transaction Length + 11 + 13 + read-write + + + SINC + Source Address Increment + 9 + 10 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + DINC + Destination Address Increment + 7 + 8 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + SRC_TR_WIDTH + Source Transfer Width + 4 + 6 + read-write + + + DST_TR_WIDTH + Destination Transfer Width + 1 + 3 + read-write + + + INT_EN + Interrupt Enable Bit + 0 + 0 + read-write + + + + + CTLH + Control Register High + 0x1C + 32 + 0x00000002 + 0xFFFFFFFF + + + DONE + Done bit + 12 + 12 + read-write + + + BLOCK_TS + Block Transfer Size + 0 + 11 + read-write + + + + + SSTAT + Source Status Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SSTAT + Source Status + 0 + 31 + read-write + + + + + DSTAT + Destination Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTAT + Destination Status + 0 + 31 + read-write + + + + + SSTATAR + Source Status Address Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + SSTATAR + Source Status Address + 0 + 31 + read-write + + + + + DSTATAR + Destination Status Address Register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTATAR + Destination Status Address + 0 + 31 + read-write + + + + + CFGL + Configuration Register Low + 0x40 + 32 + 0x00000E00 + 0xFFFFFF0F + + + RELOAD_DST + Automatic Destination Reload + 31 + 31 + read-write + + + RELOAD_SRC + Automatic Source Reload + 30 + 30 + read-write + + + MAX_ABRST + Maximum AMBA Burst Length + 20 + 29 + read-write + + + SRC_HS_POL + Source Handshaking Interface Polarity + 19 + 19 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + DST_HS_POL + Destination Handshaking Interface Polarity + 18 + 18 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + LOCK_B + Bus Lock Bit + 17 + 17 + read-write + + + LOCK_CH + Channel Lock Bit + 16 + 16 + read-write + + + LOCK_B_L + Bus Lock Level + 14 + 15 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + LOCK_CH_L + Channel Lock Level + 12 + 13 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + HS_SEL_SRC + Source Software or Hardware Handshaking Select + 11 + 11 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware-initiated transaction requests are ignored. + #1 + + + + + HS_SEL_DST + Destination Software or Hardware Handshaking Select + 10 + 10 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware- initiated transaction requests are ignored. + #1 + + + + + FIFO_EMPTY + Indicates if there is data left in the channel FIFO + 9 + 9 + read-only + + + value1 + Channel FIFO empty + #1 + + + value2 + Channel FIFO not empty + #0 + + + + + CH_SUSP + Channel Suspend + 8 + 8 + read-write + + + value1 + Not suspended. + #0 + + + value2 + Suspend DMA transfer from the source. + #1 + + + + + CH_PRIOR + Channel priority + 5 + 7 + read-write + + + + + CFGH + Configuration Register High + 0x44 + 32 + 0x00000004 + 0xFFFFFFFF + + + DEST_PER + Destination Peripheral + 11 + 14 + read-write + + + SRC_PER + Source Peripheral + 7 + 10 + read-write + + + SS_UPD_EN + Source Status Update Enable + 6 + 6 + read-write + + + DS_UPD_EN + Destination Status Update Enable + 5 + 5 + read-write + + + PROTCTL + Protection Control + 2 + 4 + read-write + + + FIFO_MODE + FIFO Mode Select + 1 + 1 + read-write + + + value1 + Space/data available for single AHB transfer of the specified transfer width. + #0 + + + value2 + Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. + #1 + + + + + FCMODE + Flow Control Mode + 0 + 0 + read-write + + + value1 + Source transaction requests are serviced when they occur. Data pre-fetching is enabled. + #0 + + + value2 + Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. + #1 + + + + + + + SGR + Source Gather Register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + SGC + Source gather count + 20 + 31 + read-write + + + SGI + Source gather interval + 0 + 19 + read-write + + + + + DSR + Destination Scatter Register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSC + Destination scatter count + 20 + 31 + read-write + + + DSI + Destination scatter interval + 0 + 19 + read-write + + + + + + + GPDMA0_CH1 + General Purpose DMA Unit 0 + GPDMA + 0x50014058 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH2 + General Purpose DMA Unit 0 + GPDMA + GPDMA0_CH2_7 + 0x500140B0 + + 0x0 + 0x55 + registers + + + + SAR + Source Address Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + SAR + Current Source Address of DMA transfer + 0 + 31 + read-write + + + + + DAR + Destination Address Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAR + Current Destination address of DMA transfer + 0 + 31 + read-write + + + + + CTLL + Control Register Low + 0x18 + 32 + 0x00304801 + 0xFFFFFFFF + + + TT_FC + Transfer Type and Flow Control + 20 + 22 + read-write + + + SRC_MSIZE + Source Burst Transaction Length + 14 + 16 + read-write + + + DEST_MSIZE + Destination Burst Transaction Length + 11 + 13 + read-write + + + SINC + Source Address Increment + 9 + 10 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + DINC + Destination Address Increment + 7 + 8 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + SRC_TR_WIDTH + Source Transfer Width + 4 + 6 + read-write + + + DST_TR_WIDTH + Destination Transfer Width + 1 + 3 + read-write + + + INT_EN + Interrupt Enable Bit + 0 + 0 + read-write + + + + + CTLH + Control Register High + 0x1C + 32 + 0x00000002 + 0xFFFFFFFF + + + DONE + Done bit + 12 + 12 + read-write + + + BLOCK_TS + Block Transfer Size + 0 + 11 + read-write + + + + + CFGL + Configuration Register Low + 0x40 + 32 + 0x00000E00 + 0xFFFFFF0F + + + MAX_ABRST + Maximum AMBA Burst Length + 20 + 29 + read-write + + + SRC_HS_POL + Source Handshaking Interface Polarity + 19 + 19 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + DST_HS_POL + Destination Handshaking Interface Polarity + 18 + 18 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + LOCK_B + Bus Lock Bit + 17 + 17 + read-write + + + LOCK_CH + Channel Lock Bit + 16 + 16 + read-write + + + LOCK_B_L + Bus Lock Level + 14 + 15 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + LOCK_CH_L + Channel Lock Level + 12 + 13 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + HS_SEL_SRC + Source Software or Hardware Handshaking Select + 11 + 11 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware-initiated transaction requests are ignored. + #1 + + + + + HS_SEL_DST + Destination Software or Hardware Handshaking Select + 10 + 10 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware- initiated transaction requests are ignored. + #1 + + + + + FIFO_EMPTY + Indicates if there is data left in the channel FIFO + 9 + 9 + read-only + + + value1 + Channel FIFO empty + #1 + + + value2 + Channel FIFO not empty + #0 + + + + + CH_SUSP + Channel Suspend + 8 + 8 + read-write + + + value1 + Not suspended. + #0 + + + value2 + Suspend DMA transfer from the source. + #1 + + + + + CH_PRIOR + Channel priority + 5 + 7 + read-write + + + + + CFGH + Configuration Register High + 0x44 + 32 + 0x00000004 + 0xFFFFFFFF + + + DEST_PER + Destination Peripheral + 11 + 14 + read-write + + + SRC_PER + Source Peripheral + 7 + 10 + read-write + + + PROTCTL + Protection Control + 2 + 4 + read-write + + + FIFO_MODE + FIFO Mode Select + 1 + 1 + read-write + + + value1 + Space/data available for single AHB transfer of the specified transfer width. + #0 + + + value2 + Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. + #1 + + + + + FCMODE + Flow Control Mode + 0 + 0 + read-write + + + value1 + Source transaction requests are serviced when they occur. Data pre-fetching is enabled. + #0 + + + value2 + Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. + #1 + + + + + + + + + GPDMA0_CH3 + General Purpose DMA Unit 0 + GPDMA + 0x50014108 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH4 + General Purpose DMA Unit 0 + GPDMA + 0x50014160 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH5 + General Purpose DMA Unit 0 + GPDMA + 0x500141B8 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH6 + General Purpose DMA Unit 0 + GPDMA + 0x50014210 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH7 + General Purpose DMA Unit 0 + GPDMA + 0x50014268 + + 0x0 + 0x55 + registers + + + + GPDMA1 + General Purpose DMA Unit 1 + GPDMA + 0x500182C0 + + 0x0 + 0x7D40 + registers + + + GPDMA1_0 + General Purpose DMA Unit 1 + 110 + + + + RAWTFR + Raw IntTfr Status + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWBLOCK + Raw IntBlock Status + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWSRCTRAN + Raw IntSrcTran Status + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWDSTTRAN + Raw IntBlock Status + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWERR + Raw IntErr Status + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + STATUSTFR + IntTfr Status + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSBLOCK + IntBlock Status + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSSRCTRAN + IntSrcTran Status + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSDSTTRAN + IntBlock Status + 0x040 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSERR + IntErr Status + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + MASKTFR + Mask for Raw IntTfr Status + 0x050 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKBLOCK + Mask for Raw IntBlock Status + 0x058 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKSRCTRAN + Mask for Raw IntSrcTran Status + 0x060 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKDSTTRAN + Mask for Raw IntBlock Status + 0x068 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKERR + Mask for Raw IntErr Status + 0x070 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + CLEARTFR + IntTfr Status + 0x078 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARBLOCK + IntBlock Status + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARSRCTRAN + IntSrcTran Status + 0x088 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARDSTTRAN + IntBlock Status + 0x090 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARERR + IntErr Status + 0x098 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + STATUSINT + Combined Interrupt Status Register + 0x0A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ERR + OR of the contents of STATUSERR register + 4 + 4 + read-only + + + DSTT + OR of the contents of STATUSDSTTRAN register + 3 + 3 + read-only + + + SRCT + OR of the contents of STATUSSRCTRAN register + 2 + 2 + read-only + + + BLOCK + OR of the contents of STATUSBLOCK register + 1 + 1 + read-only + + + TFR + OR of the contents of STATUSTFR register + 0 + 0 + read-only + + + + + REQSRCREG + Source Software Transaction Request Register + 0x0A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + REQDSTREG + Destination Software Transaction Request Register + 0x0B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + SGLREQSRCREG + Single Source Transaction Request Register + 0x0B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + SGLREQDSTREG + Single Destination Transaction Request Register + 0x0C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + LSTSRCREG + Last Source Transaction Request Register + 0x0C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Source last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Source last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Source last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + LSTDSTREG + Last Destination Transaction Request Register + 0x0D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Destination last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Destination last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Destination last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Destination last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Destination last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Destination last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Destination last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Destination last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + DMACFGREG + GPDMA Configuration Register + 0x0D8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DMA_EN + GPDMA Enable bit. + 0 + 0 + read-write + + + value1 + GPDMA Disabled + #0 + + + value2 + GPDMA Enabled. + #1 + + + + + + + CHENREG + GPDMA Channel Enable Register + 0x0E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH + Channel enable write enable + 8 + 11 + write-only + + + CH + Enables/Disables the channel + 0 + 3 + read-write + + + value1 + Disable the Channel + #0 + + + value2 + Enable the Channel + #1 + + + + + + + ID + GPDMA1 ID Register + 0x0E8 + 32 + 0x00B0C000 + 0xFFFFFF00 + + + VALUE + Hardcoded GPDMA Peripheral ID + 0 + 31 + read-only + + + + + TYPE + GPDMA Component Type + 0x138 + 32 + 0x44571110 + 0xFFFFFFFF + + + VALUE + Component Type + 0 + 31 + read-only + + + + + VERSION + DMA Component Version + 0x13C + 32 + 0x3231342A + 0xFFFFFFFF + + + VALUE + Version number of the component + 0 + 31 + read-only + + + + + + + GPDMA1_CH0 + General Purpose DMA Unit 1 + GPDMA + GPDMA1_CH + 0x50018000 + + 0x0 + 0x55 + registers + + + + SAR + Source Address Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + SAR + Current Source Address of DMA transfer + 0 + 31 + read-write + + + + + DAR + Destination Address Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAR + Current Destination address of DMA transfer + 0 + 31 + read-write + + + + + CTLL + Control Register Low + 0x18 + 32 + 0x00304801 + 0xFFFFFFFF + + + TT_FC + Transfer Type and Flow Control + 20 + 22 + read-write + + + SRC_MSIZE + Source Burst Transaction Length + 14 + 16 + read-write + + + DEST_MSIZE + Destination Burst Transaction Length + 11 + 13 + read-write + + + SINC + Source Address Increment + 9 + 10 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + DINC + Destination Address Increment + 7 + 8 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + SRC_TR_WIDTH + Source Transfer Width + 4 + 6 + read-write + + + DST_TR_WIDTH + Destination Transfer Width + 1 + 3 + read-write + + + INT_EN + Interrupt Enable Bit + 0 + 0 + read-write + + + + + CTLH + Control Register High + 0x1C + 32 + 0x00000002 + 0xFFFFFFFF + + + DONE + Done bit + 12 + 12 + read-write + + + BLOCK_TS + Block Transfer Size + 0 + 11 + read-write + + + + + CFGL + Configuration Register Low + 0x40 + 32 + 0x00000E00 + 0xFFFFFF0F + + + MAX_ABRST + Maximum AMBA Burst Length + 20 + 29 + read-write + + + SRC_HS_POL + Source Handshaking Interface Polarity + 19 + 19 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + DST_HS_POL + Destination Handshaking Interface Polarity + 18 + 18 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + LOCK_B + Bus Lock Bit + 17 + 17 + read-write + + + LOCK_CH + Channel Lock Bit + 16 + 16 + read-write + + + LOCK_B_L + Bus Lock Level + 14 + 15 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + LOCK_CH_L + Channel Lock Level + 12 + 13 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + HS_SEL_SRC + Source Software or Hardware Handshaking Select + 11 + 11 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware-initiated transaction requests are ignored. + #1 + + + + + HS_SEL_DST + Destination Software or Hardware Handshaking Select + 10 + 10 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware- initiated transaction requests are ignored. + #1 + + + + + FIFO_EMPTY + Indicates if there is data left in the channel FIFO + 9 + 9 + read-only + + + value1 + Channel FIFO empty + #1 + + + value2 + Channel FIFO not empty + #0 + + + + + CH_SUSP + Channel Suspend + 8 + 8 + read-write + + + value1 + Not suspended. + #0 + + + value2 + Suspend DMA transfer from the source. + #1 + + + + + CH_PRIOR + Channel priority + 5 + 7 + read-write + + + + + CFGH + Configuration Register High + 0x44 + 32 + 0x00000004 + 0xFFFFFFFF + + + DEST_PER + Destination Peripheral + 11 + 14 + read-write + + + SRC_PER + Source Peripheral + 7 + 10 + read-write + + + PROTCTL + Protection Control + 2 + 4 + read-write + + + FIFO_MODE + FIFO Mode Select + 1 + 1 + read-write + + + value1 + Space/data available for single AHB transfer of the specified transfer width. + #0 + + + value2 + Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. + #1 + + + + + FCMODE + Flow Control Mode + 0 + 0 + read-write + + + value1 + Source transaction requests are serviced when they occur. Data pre-fetching is enabled. + #0 + + + value2 + Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. + #1 + + + + + + + + + GPDMA1_CH1 + General Purpose DMA Unit 1 + GPDMA + 0x50018058 + + 0x0 + 0x55 + registers + + + + GPDMA1_CH2 + General Purpose DMA Unit 1 + GPDMA + 0x500180B0 + + 0x0 + 0x55 + registers + + + + GPDMA1_CH3 + General Purpose DMA Unit 1 + GPDMA + 0x50018108 + + 0x0 + 0x55 + registers + + + + FCE + Flexible CRC Engine + FCE + 0x50020000 + + 0x0 + 0x20 + registers + + + FCE0_0 + Flexible CRC Engine + 104 + + + + CLC + Clock Control Register + 0x00 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + + + ID + Module Identification Register + 0x08 + 32 + 0x00CAC001 + 0xFFFFFFFF + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + + + FCE_KE0 + Flexible CRC Engine + FCE + FCE_KE + 0x50020020 + + 0x0 + 0x20 + registers + + + + IR + Input Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + IR + Input Register + 0 + 31 + read-write + + + + + RES + CRC Result Register + 0x04 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RES + Result Register + 0 + 31 + read-only + + + + + CFG + CRC Configuration Register + 0x08 + 32 + 0x00000700 + 0xFFFFFFFF + + + CMI + CRC Mismatch Interrupt + 0 + 0 + read-write + + + value1 + CRC Mismatch Interrupt is disabled + #0 + + + value2 + CRC Mismatch Interrupt is enabled + #1 + + + + + CEI + Configuration Error Interrupt + 1 + 1 + read-write + + + value1 + Configuration Error Interrupt is disabled + #0 + + + value2 + Configuration Error Interrupt is enabled + #1 + + + + + LEI + Length Error Interrupt + 2 + 2 + read-write + + + value1 + Length Error Interrupt is disabled + #0 + + + value2 + Length Error Interrupt is enabled + #1 + + + + + BEI + Bus Error Interrupt + 3 + 3 + read-write + + + value1 + Bus Error Interrupt is disabled + #0 + + + value2 + Bus Error Interrupt is enabled + #1 + + + + + CCE + CRC Check Comparison + 4 + 4 + read-write + + + value1 + CRC check comparison at the end of a message is disabled + #0 + + + value2 + CRC check comparison at the end of a message is enabled + #1 + + + + + ALR + Automatic Length Reload + 5 + 5 + read-write + + + value1 + Disables automatic reload of the LENGTH field. + #0 + + + value2 + Enables automatic reload of the LENGTH field at the end of a message. + #1 + + + + + REFIN + IR Byte Wise Reflection + 8 + 8 + read-write + + + value1 + IR Byte Wise Reflection is disabled + #0 + + + value2 + IR Byte Wise Reflection is enabled + #1 + + + + + REFOUT + CRC 32-Bit Wise Reflection + 9 + 9 + read-write + + + value1 + CRC 32-bit wise is disabled + #0 + + + value2 + CRC 32-bit wise is enabled + #1 + + + + + XSEL + Selects the value to be xored with the final CRC + 10 + 10 + read-write + + + value1 + 0x00000000 + #0 + + + value2 + 0xFFFFFFFF + #1 + + + + + + + STS + CRC Status Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + CMF + CRC Mismatch Flag + 0 + 0 + read-write + + + CEF + Configuration Error Flag + 1 + 1 + read-write + + + LEF + Length Error Flag + 2 + 2 + read-write + + + BEF + Bus Error Flag + 3 + 3 + read-write + + + + + LENGTH + CRC Length Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + LENGTH + Message Length Register + 0 + 15 + read-write + + + + + CHECK + CRC Check Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHECK + CHECK Register + 0 + 31 + read-write + + + + + CRC + CRC Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC + CRC Register + 0 + 31 + read-write + + + + + CTR + CRC Test Register + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + FCM + Force CRC Mismatch + 0 + 0 + read-write + + + FRM_CFG + Force CFG Register Mismatch + 1 + 1 + read-write + + + FRM_CHECK + Force Check Register Mismatch + 2 + 2 + read-write + + + + + + + FCE_KE1 + Flexible CRC Engine + FCE + 0x50020040 + + 0x0 + 0x20 + registers + + + + FCE_KE2 + Flexible CRC Engine + FCE + 0x50020060 + + 0x0 + 0x20 + registers + + + + FCE_KE3 + Flexible CRC Engine + FCE + 0x50020080 + + 0x0 + 0x20 + registers + + + + PBA0 + Peripheral Bridge AHB 0 + PBA + PBA + 0x40000000 + + 0x0 + 0x4000 + registers + + + + STS + Peripheral Bridge Status Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + WERR + Bufferable Write Access Error + 0 + 0 + read-write + + + value1 + no write error occurred. + #0 + + + value2 + write error occurred, interrupt request is pending. + #1 + + + + + + + WADDR + PBA Write Error Address Register + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + WADDR + Write Error Address + 0 + 31 + read-only + + + + + + + PBA1 + Peripheral Bridge AHB 1 + PBA + 0x48000000 + + 0x0 + 0x4000 + registers + + + + FLASH0 + Flash Memory Controller + FLASH + 0x58001000 + + 0x0 + 0x1400 + registers + + + + ID + Flash Module Identification Register + 0x1008 + 32 + 0x0092C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + FSR + Flash Status Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + PBUSY + Program Flash Busy + 0 + 0 + read-only + + + value1 + PFLASH ready, not busy; PFLASH in read mode. + #0 + + + value2 + PFLASH busy; PFLASH not in read mode. + #1 + + + + + FABUSY + Flash Array Busy + 1 + 1 + read-only + + + PROG + Programming State + 4 + 4 + read-only + + + value1 + There is no program operation requested or in progress or just finished. + #0 + + + value2 + Programming operation (write page) requested (from FIM) or in action or finished. + #1 + + + + + ERASE + Erase State + 5 + 5 + read-only + + + value1 + There is no erase operation requested or in progress or just finished + #0 + + + value2 + Erase operation requested (from FIM) or in action or finished. + #1 + + + + + PFPAGE + Program Flash in Page Mode + 6 + 6 + read-only + + + value1 + Program Flash not in page mode + #0 + + + value2 + Program Flash in page mode; assembly buffer of PFLASH (256 byte) is in use (being filled up) + #1 + + + + + PFOPER + Program Flash Operation Error + 8 + 8 + read-only + + + value1 + No operation error reported by Program Flash + #0 + + + value2 + Flash array operation aborted, because of a Flash array failure, e.g. an ECC error in microcode. + #1 + + + + + SQER + Command Sequence Error + 10 + 10 + read-only + + + value1 + No sequence error + #0 + + + value2 + Command state machine operation unsuccessful because of improper address or command sequence. + #1 + + + + + PROER + Protection Error + 11 + 11 + read-only + + + value1 + No protection error + #0 + + + value2 + Protection error. + #1 + + + + + PFSBER + PFLASH Single-Bit Error and Correction + 12 + 12 + read-only + + + value1 + No Single-Bit Error detected during read access to PFLASH + #0 + + + value2 + Single-Bit Error detected and corrected + #1 + + + + + PFDBER + PFLASH Double-Bit Error + 14 + 14 + read-only + + + value1 + No Double-Bit Error detected during read access to PFLASH + #0 + + + value2 + Double-Bit Error detected in PFLASH + #1 + + + + + PROIN + Protection Installed + 16 + 16 + read-only + + + value1 + No protection is installed + #0 + + + value2 + Read or/and write protection for one or more users is configured and correctly confirmed in the User Configuration Block(s). + #1 + + + + + RPROIN + Read Protection Installed + 18 + 18 + read-only + + + value1 + No read protection installed + #0 + + + value2 + Read protection and global write protection is configured and correctly confirmed in the User Configuration Block 0. + #1 + + + + + RPRODIS + Read Protection Disable State + 19 + 19 + read-only + + + value1 + Read protection (if installed) is not disabled + #0 + + + value2 + Read and global write protection is temporarily disabled. + #1 + + + + + WPROIN0 + Sector Write Protection Installed for User 0 + 21 + 21 + read-only + + + value1 + No write protection installed for user 0 + #0 + + + value2 + Sector write protection for user 0 is configured and correctly confirmed in the User Configuration Block 0. + #1 + + + + + WPROIN1 + Sector Write Protection Installed for User 1 + 22 + 22 + read-only + + + value1 + No write protection installed for user 1 + #0 + + + value2 + Sector write protection for user 1 is configured and correctly confirmed in the User Configuration Block 1. + #1 + + + + + WPROIN2 + Sector OTP Protection Installed for User 2 + 23 + 23 + read-only + + + value1 + No OTP write protection installed for user 2 + #0 + + + value2 + Sector OTP write protection with ROM functionality is configured and correctly confirmed in the UCB2. The protection is locked for ever. + #1 + + + + + WPRODIS0 + Sector Write Protection Disabled for User 0 + 25 + 25 + read-only + + + value1 + All protected sectors of user 0 are locked if write protection is installed + #0 + + + value2 + All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection. + #1 + + + + + WPRODIS1 + Sector Write Protection Disabled for User 1 + 26 + 26 + read-only + + + value1 + All protected sectors of user 1 are locked if write protection is installed + #0 + + + value2 + All write-protected sectors of user 1 are temporarily unlocked, if not coincidently locked by user 0 or user 2 or via read protection. + #1 + + + + + SLM + Flash Sleep Mode + 28 + 28 + read-only + + + value1 + Flash not in sleep mode + #0 + + + value2 + Flash is in sleep or shut down mode + #1 + + + + + VER + Verify Error + 31 + 31 + read-only + + + value1 + The page is correctly programmed or the sector correctly erased. All programmed or erased bits have full expected quality. + #0 + + + value2 + A program verify error or an erase verify error has been detected. Full quality (retention time) of all programmed ("1") or erased ("0") bits cannot be guaranteed. + #1 + + + + + + + FCON + Flash Configuration Register + 0x1014 + 32 + 0x00000006 + 0xFFF0FFFF + + + WSPFLASH + Wait States for read access to PFLASH + 0 + 3 + read-write + + + value1 + PFLASH access in one clock cycle + #0000 + + + value2 + PFLASH access in one clock cycle + #0001 + + + value3 + PFLASH access in two clock cycles + #0010 + + + value4 + PFLASH access in three clock cycles + #0011 + + + value5 + PFLASH access in fifteen clock cycles. + #1111 + + + + + WSECPF + Wait State for Error Correction of PFLASH + 4 + 4 + read-write + + + value1 + No additional wait state for error correction + #0 + + + value2 + One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer. + #1 + + + + + IDLE + Dynamic Flash Idle + 13 + 13 + read-write + + + value1 + Normal/standard Flash read operation + #0 + + + value2 + Dynamic idle of Program Flash enabled for power saving; static prefetching disabled + #1 + + + + + ESLDIS + External Sleep Request Disable + 14 + 14 + read-write + + + value1 + External sleep request signal input is enabled + #0 + + + value2 + Externally requested Flash sleep is disabled + #1 + + + + + SLEEP + Flash SLEEP + 15 + 15 + read-write + + + value1 + Normal state or wake-up + #0 + + + value2 + Flash sleep mode is requested + #1 + + + + + RPA + Read Protection Activated + 16 + 16 + read-only + + + value1 + The Flash-internal read protection is not activated. Bits DCF, DDF are not taken into account. Bits DCF, DDFx can be cleared + #0 + + + value2 + The Flash-internal read protection is activated. Bits DCF, DDF are enabled and evaluated. + #1 + + + + + DCF + Disable Code Fetch from Flash Memory + 17 + 17 + read-write + + + value1 + Code fetching from the Flash memory area is allowed. + #0 + + + value2 + Code fetching from the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. + #1 + + + + + DDF + Disable Any Data Fetch from Flash + 18 + 18 + read-write + + + value1 + Data read access to the Flash memory area is allowed. + #0 + + + value2 + Data read access to the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. + #1 + + + + + VOPERM + Verify and Operation Error Interrupt Mask + 24 + 24 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + Flash interrupt because of Verify Error or Operation Error in Flash array (FSI) is enabled + #1 + + + + + SQERM + Command Sequence Error Interrupt Mask + 25 + 25 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + Flash interrupt because of Sequence Error is enabled + #1 + + + + + PROERM + Protection Error Interrupt Mask + 26 + 26 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + Flash interrupt because of Protection Error is enabled + #1 + + + + + PFSBERM + PFLASH Single-Bit Error Interrupt Mask + 27 + 27 + read-write + + + value1 + No Single-Bit Error interrupt enabled + #0 + + + value2 + Single-Bit Error interrupt enabled for PFLASH + #1 + + + + + PFDBERM + PFLASH Double-Bit Error Interrupt Mask + 29 + 29 + read-write + + + value1 + Double-Bit Error interrupt for PFLASH not enabled + #0 + + + value2 + Double-Bit Error interrupt for PFLASH enabled. Especially intended for margin check + #1 + + + + + EOBM + End of Busy Interrupt Mask + 31 + 31 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + EOB interrupt is enabled + #1 + + + + + + + MARP + Margin Control Register PFLASH + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + MARGIN + PFLASH Margin Selection + 0 + 3 + read-write + + + value1 + Standard (default) margin. + #0000 + + + value2 + Tight margin for 0 (low) level. Suboptimal 0-bits are read as 1s. + #0001 + + + value3 + Tight margin for 1 (high) level. Suboptimal 1-bits are read as 0s. + #0100 + + + + + TRAPDIS + PFLASH Double-Bit Error Trap Disable + 15 + 15 + read-write + + + value1 + If a double-bit error occurs in PFLASH, a bus error trap is generated. + #0 + + + value2 + The double-bit error trap is disabled. Shall be used only during margin check + #1 + + + + + + + PROCON0 + Flash Protection Configuration Register User 0 + 0x1020 + 32 + 0x00000000 + 0xFFFF0000 + + + S0L + Sector 0 Locked for Write Protection by User 0 + 0 + 0 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S1L + Sector 1 Locked for Write Protection by User 0 + 1 + 1 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S2L + Sector 2 Locked for Write Protection by User 0 + 2 + 2 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S3L + Sector 3 Locked for Write Protection by User 0 + 3 + 3 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S4L + Sector 4 Locked for Write Protection by User 0 + 4 + 4 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S5L + Sector 5 Locked for Write Protection by User 0 + 5 + 5 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S6L + Sector 6 Locked for Write Protection by User 0 + 6 + 6 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S7L + Sector 7 Locked for Write Protection by User 0 + 7 + 7 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S8L + Sector 8 Locked for Write Protection by User 0 + 8 + 8 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S9L + Sector 9 Locked for Write Protection by User 0 + 9 + 9 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S10_S11L + Sectors 10 and 11 Locked for Write Protection by User 0 + 10 + 10 + read-only + + + value1 + No write protection is configured for sectors 10+11. + #0 + + + value2 + Write protection is configured for sectors 10+11. + #1 + + + + + S12_S13L + Sectors 12 and 13 Locked for Write Protection by User 0 + 11 + 11 + read-only + + + value1 + No write protection is configured for sectors 12+13. + #0 + + + value2 + Write protection is configured for sectors 12+13. + #1 + + + + + S14_S15L + Sectors 14 and 15 Locked for Write Protection by User 0 + 12 + 12 + read-only + + + value1 + No write protection is configured for sectors 14+15. + #0 + + + value2 + Write protection is configured for sectors 14+15. + #1 + + + + + RPRO + Read Protection Configuration + 15 + 15 + read-only + + + value1 + No read protection configured + #0 + + + value2 + Read protection and global write protection is configured by user 0 (master user) + #1 + + + + + + + PROCON1 + Flash Protection Configuration Register User 1 + 0x1024 + 32 + 0x00000000 + 0xFFFF0000 + + + S0L + Sector 0 Locked for Write Protection by User 1 + 0 + 0 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S1L + Sector 1 Locked for Write Protection by User 1 + 1 + 1 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S2L + Sector 2 Locked for Write Protection by User 1 + 2 + 2 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S3L + Sector 3 Locked for Write Protection by User 1 + 3 + 3 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S4L + Sector 4 Locked for Write Protection by User 1 + 4 + 4 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S5L + Sector 5 Locked for Write Protection by User 1 + 5 + 5 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S6L + Sector 6 Locked for Write Protection by User 1 + 6 + 6 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S7L + Sector 7 Locked for Write Protection by User 1 + 7 + 7 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S8L + Sector 8 Locked for Write Protection by User 1 + 8 + 8 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S9L + Sector 9 Locked for Write Protection by User 1 + 9 + 9 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S10_S11L + Sectors 10 and 11 Locked for Write Protection by User 1 + 10 + 10 + read-only + + + value1 + No write protection is configured for sectors 10+11. + #0 + + + value2 + Write protection is configured for sectors 10+11. + #1 + + + + + S12_S13L + Sectors 12 and 13 Locked for Write Protection by User 1 + 11 + 11 + read-only + + + value1 + No write protection is configured for sectors 12+13. + #0 + + + value2 + Write protection is configured for sectors 12+13. + #1 + + + + + S14_S15L + Sectors 14 and 15 Locked for Write Protection by User 1 + 12 + 12 + read-only + + + value1 + No write protection is configured for sectors 14+15. + #0 + + + value2 + Write protection is configured for sectors 14+15. + #1 + + + + + PSR + Physical Sector Repair + 16 + 16 + read-only + + + value1 + Physical Sector Repair command disabled; Erase Physical Sector command sequence available. + #0 + + + value2 + Physical Sector Repair command sequence enabled; Erase Physical Sector command sequence disabled. + #1 + + + + + + + PROCON2 + Flash Protection Configuration Register User 2 + 0x1028 + 32 + 0x00000000 + 0xFFFF0000 + + + S0ROM + Sector 0 Locked Forever by User 2 + 0 + 0 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S1ROM + Sector 1 Locked Forever by User 2 + 1 + 1 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S2ROM + Sector 2 Locked Forever by User 2 + 2 + 2 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S3ROM + Sector 3 Locked Forever by User 2 + 3 + 3 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S4ROM + Sector 4 Locked Forever by User 2 + 4 + 4 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S5ROM + Sector 5 Locked Forever by User 2 + 5 + 5 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S6ROM + Sector 6 Locked Forever by User 2 + 6 + 6 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S7ROM + Sector 7 Locked Forever by User 2 + 7 + 7 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S8ROM + Sector 8 Locked Forever by User 2 + 8 + 8 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S9ROM + Sector 9 Locked Forever by User 2 + 9 + 9 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S10_S11ROM + Sectors 10 and 11 Locked Forever by User 2 + 10 + 10 + read-only + + + value1 + No ROM functionality is configured for sectors 10+11. + #0 + + + value2 + ROM functionality is configured for sectors 10+11. + #1 + + + + + S12_S13ROM + Sectors 12 and 13 Locked Forever by User 2 + 11 + 11 + read-only + + + value1 + No ROM functionality is configured for sectors 12+13. + #0 + + + value2 + ROM functionality is configured for sectors 12+13. + #1 + + + + + S14_S15ROM + Sectors 14 and 15 Locked Forever by User 2 + 12 + 12 + read-only + + + value1 + No ROM functionality is configured for sectors 14+15. + #0 + + + value2 + ROM functionality is configured for sectors 14+15. + #1 + + + + + + + + + PREF + Prefetch Unit + 0x58004000 + + 0 + 4 + registers + + + + PCON + Prefetch Configuration Register + 0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IBYP + Instruction Prefetch Buffer Bypass + 0 + 0 + read-write + + + value1 + Instruction prefetch buffer not bypassed. + #0 + + + value2 + Instruction prefetch buffer bypassed. + #1 + + + + + IINV + Instruction Prefetch Buffer Invalidate + 1 + 1 + write-only + + + value1 + No effect. + #0 + + + value2 + Initiate invalidation of entire instruction cache. + #1 + + + + + DBYP + Data Buffer Bypass + 4 + 4 + read-write + + + value1 + Prefetch Data buffer not bypassed. + #0 + + + value2 + Prefetch Data buffer bypassed. + #1 + + + + + + + + + PMU0 + Program Management Unit + PMU + 0x58000508 + + 0 + 4 + registers + + + PMU0_0 + Program Management Unit + 12 + + + + ID + PMU0 Identification Register + 0 + 32 + 0x0091C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + + + WDT + Watch Dog Timer + 0x50008000 + + 0x0 + 0x4000 + registers + + + + ID + WDT ID Register + 0x00 + 32 + 0x00ADC000 + 0xFFFFFF00 + + + MOD_REV + Module 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0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43 + CCU43 Gating Set + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + LEDTSCU0 + LEDTS Gating Set + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + MCAN0 + MultiCAN Gating Set + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + DAC + DAC Gating Set + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + MMCI + MMC Interface Gating Set + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + USIC1 + USIC1 Gating Set + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + USIC2 + USIC2 Gating Set + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + PPORTS + PORTS Gating Set + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + + + CGATCLR1 + Peripheral 1 Clock Gating Clear + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43 + CCU43 Gating Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + LEDTSCU0 + LEDTS Gating Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + MCAN0 + MultiCAN Gating Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + DAC + DAC Gating Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + MMCI + MMC Interface Gating Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + USIC1 + USIC1 Gating Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + USIC2 + USIC2 Gating Clear + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + PPORTS + PORTS Gating Clear + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + + + CGATSTAT2 + Peripheral 2 Clock Gating Status + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT + WDT Gating Status + 1 + 1 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + ETH0 + ETH0 Gating Status + 2 + 2 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + DMA0 + DMA0 Gating Status + 4 + 4 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + DMA1 + DMA1 Gating Status + 5 + 5 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + FCE + FCE Gating Status + 6 + 6 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + USB + USB Gating Status + 7 + 7 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + + + CGATSET2 + Peripheral 2 Clock Gating Set + 0x5C + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT + WDT Gating Set + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + ETH0 + ETH0 Gating Set + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + DMA0 + DMA0 Gating Set + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + DMA1 + DMA1 Gating Set + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + FCE + FCE Gating Set + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + USB + USB Gating Set + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + + + CGATCLR2 + Peripheral 2 Clock Gating Clear + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT + WDT Gating Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + ETH0 + ETH0 Gating Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + DMA0 + DMA0 Gating Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + DMA1 + DMA1 Gating Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + FCE + FCE Gating Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + USB + USB Gating Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + + + CGATSTAT3 + Peripheral 3 Clock Gating Status + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBU + EBU Gating Status + 2 + 2 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + + + CGATSET3 + Peripheral 3 Clock Gating Set + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBU + EBU Gating Set + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + + + CGATCLR3 + Peripheral 3 Clock Gating Clear + 0x6C + 32 + 0x00000000 + 0xFFFFFFFF + + + EBU + EBU Gating Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + + + + + SCU_OSC + System Control Unit + SCU + 0x50004700 + + 0x0 + 0x10 + registers + + + + OSCHPSTAT + OSC_HP Status Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + X1D + XTAL1 Data Value + 0 + 0 + read-only + + + + + OSCHPCTRL + OSC_HP Control Register + 0x04 + 32 + 0x0000003C + 0xFFFFFFFF + + + X1DEN + XTAL1 Data Enable + 0 + 0 + read-write + + + value1 + Bit X1D is not updated + #0 + + + value2 + Bit X1D can be updated + #1 + + + + + SHBY + Shaper Bypass + 1 + 1 + read-write + + + value1 + The shaper is not bypassed + #0 + + + value2 + The shaper is bypassed + #1 + + + + + GAINSEL + Oscillator Gain Selection + 2 + 3 + read-write + + + value1 + The gain control is configured for frequencies from 4 MHz to 8 MHz + #00 + + + value2 + The gain control is configured for frequencies from 4 MHz to 16 MHz + #01 + + + value3 + The gain control is configured for frequencies from 4 MHz to 20 MHz + #10 + + + value4 + The gain control is configured for frequencies from 4 MHz to 25 MHz + #11 + + + + + MODE + Oscillator Mode + 4 + 5 + read-write + + + value1 + External Crystal Mode and External Input Clock Mode. The oscillator Power-Saving Mode is not entered. + #00 + + + value2 + OSC is disabled. The oscillator Power-Saving Mode is not entered. + #01 + + + value3 + External Input Clock Mode and the oscillator Power-Saving Mode is entered + #10 + + + value4 + OSC is disabled. The oscillator Power-Saving Mode is entered. + #11 + + + + + OSCVAL + OSC Frequency Value + 16 + 19 + read-write + + + + + CLKCALCONST + Clock Calibration Constant Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + CALIBCONST + Clock Calibration Constant Value + 0 + 3 + read-write + + + + + + + SCU_PLL + System Control Unit + SCU + 0x50004710 + + 0x0 + 0x38 + registers + + + + PLLSTAT + PLL Status Register + 0x00 + 32 + 0x00000002 + 0xFFFFFFFF + + + VCOBYST + VCO Bypass Status + 0 + 0 + read-only + + + value1 + Free-running / Normal Mode is entered + #0 + + + value2 + Prescaler Mode is entered + #1 + + + + + PWDSTAT + PLL Power-saving Mode Status + 1 + 1 + read-only + + + value1 + PLL Power-saving Mode was not entered + #0 + + + value2 + PLL Power-saving Mode was entered + #1 + + + + + VCOLOCK + PLL LOCK Status + 2 + 2 + read-only + + + value1 + PLL not locked + #0 + + + value2 + PLL locked + #1 + + + + + K1RDY + K1 Divider Ready Status + 4 + 4 + read-only + + + value1 + K1-Divider does not operate with the new value + #0 + + + value2 + K1-Divider operate with the new value + #1 + + + + + K2RDY + K2 Divider Ready Status + 5 + 5 + read-only + + + value1 + K2-Divider does not operate with the new value + #0 + + + value2 + K2-Divider operate with the new value + #1 + + + + + BY + Bypass Mode Status + 6 + 6 + read-only + + + value1 + Bypass Mode is not entered + #0 + + + value2 + Bypass Mode is entered. Input fOSC is selected as output fPLL. + #1 + + + + + PLLLV + Oscillator for PLL Valid Low Status Bit + 7 + 7 + read-only + + + value1 + The OSC frequency is not usable. Frequency fREF is too low. + #0 + + + value2 + The OSC frequency is usable + #1 + + + + + PLLHV + Oscillator for PLL Valid High Status Bit + 8 + 8 + read-only + + + value1 + The OSC frequency is not usable. Frequency fOSC is too high. + #0 + + + value2 + The OSC frequency is usable + #1 + + + + + PLLSP + Oscillator for PLL Valid Spike Status Bit + 9 + 9 + read-only + + + value1 + The OSC frequency is not usable. Spikes are detected that disturb a locked operation + #0 + + + value2 + The OSC frequency is usable + #1 + + + + + + + PLLCON0 + PLL Configuration 0 Register + 0x04 + 32 + 0x00030003 + 0xFFFFFFFF + + + VCOBYP + VCO Bypass + 0 + 0 + read-write + + + value1 + Normal operation, VCO is not bypassed + #0 + + + value2 + Prescaler Mode, VCO is bypassed + #1 + + + + + VCOPWD + VCO Power Saving Mode + 1 + 1 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The VCO is put into a Power Saving Mode and can no longer be used. Only the Bypass and Prescaler Mode are active if previously selected. + #1 + + + + + VCOTR + VCO Trim Control + 2 + 2 + read-write + + + value1 + VCO bandwidth is operation in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #0 + + + value2 + VCO bandwidth is operation in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #1 + + + + + FINDIS + Disconnect Oscillator from VCO + 4 + 4 + read-write + + + value1 + connect oscillator to the VCO part + #0 + + + value2 + disconnect oscillator from the VCO part. + #1 + + + + + OSCDISCDIS + Oscillator Disconnect Disable + 6 + 6 + read-write + + + value1 + In case of a PLL loss-of-lock bit FINDIS is set + #0 + + + value2 + In case of a PLL loss-of-lock bit FINDIS is cleared + #1 + + + + + PLLPWD + PLL Power Saving Mode + 16 + 16 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The complete PLL block is put into a Power Saving Mode and can no longer be used. Only the Bypass Mode is active if previously selected. + #1 + + + + + OSCRES + Oscillator Watchdog Reset + 17 + 17 + read-write + + + value1 + The Oscillator Watchdog of the PLL is not cleared and remains active + #0 + + + value2 + The Oscillator Watchdog of the PLL is cleared and restarted + #1 + + + + + RESLD + Restart VCO Lock Detection + 18 + 18 + write-only + + + AOTREN + Automatic Oscillator Calibration Enable + 19 + 19 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + FOTR + Factory Oscillator Calibration + 20 + 20 + read-write + + + value1 + No effect + #0 + + + value2 + Force fixed-value trimming + #1 + + + + + + + PLLCON1 + PLL Configuration 1 Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + K1DIV + K1-Divider Value + 0 + 6 + read-write + + + NDIV + N-Divider Value + 8 + 14 + read-write + + + K2DIV + K2-Divider Value + 16 + 22 + read-write + + + PDIV + P-Divider Value + 24 + 27 + read-write + + + + + PLLCON2 + PLL Configuration 2 Register + 0x0C + 32 + 0x00000001 + 0xFFFFFFFF + + + PINSEL + P-Divider Input Selection + 0 + 0 + read-write + + + value1 + PLL external oscillator selected + #0 + + + value2 + Backup clock fofi selected + #1 + + + + + K1INSEL + K1-Divider Input Selection + 8 + 8 + read-write + + + value1 + PLL external oscillator selected + #0 + + + value2 + Backup clock fofi selected + #1 + + + + + + + USBPLLSTAT + USB PLL Status Register + 0x10 + 32 + 0x00000002 + 0xFFFFFFFF + + + VCOBYST + VCO Bypass Status + 0 + 0 + read-only + + + value1 + Normal Mode is entered + #0 + + + value2 + Prescaler Mode is entered + #1 + + + + + PWDSTAT + PLL Power-saving Mode Status + 1 + 1 + read-only + + + value1 + PLL Power-saving Mode was not entered + #0 + + + value2 + PLL Power-saving Mode was entered + #1 + + + + + VCOLOCK + PLL VCO Lock Status + 2 + 2 + read-only + + + value1 + The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency. + #0 + + + value2 + The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation + #1 + + + + + BY + Bypass Mode Status + 6 + 6 + read-only + + + value1 + Bypass Mode is not entered + #0 + + + value2 + Bypass Mode is entered. Input fOSC is selected as output fPLL. + #1 + + + + + VCOLOCKED + PLL LOCK Status + 7 + 7 + read-only + + + value1 + PLL not locked + #0 + + + value2 + PLL locked + #1 + + + + + + + USBPLLCON + USB PLL Configuration Register + 0x14 + 32 + 0x00010003 + 0xFFFFFFFF + + + VCOBYP + VCO Bypass + 0 + 0 + read-write + + + value1 + Normal operation, VCO is not bypassed + #0 + + + value2 + Prescaler Mode, VCO is bypassed + #1 + + + + + VCOPWD + VCO Power Saving Mode + 1 + 1 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The VCO is put into a Power Saving Mode + #1 + + + + + VCOTR + VCO Trim Control + 2 + 2 + read-write + + + value1 + VCO bandwidth is operating in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #0 + + + value2 + VCO bandwidth is operating in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #1 + + + + + FINDIS + Disconnect Oscillator from VCO + 4 + 4 + read-write + + + value1 + Connect oscillator to the VCO part + #0 + + + value2 + Disconnect oscillator from the VCO part. + #1 + + + + + OSCDISCDIS + Oscillator Disconnect Disable + 6 + 6 + read-write + + + value1 + In case of a PLL loss-of-lock bit FINDIS is set + #0 + + + value2 + In case of a PLL loss-of-lock bit FINDIS is cleared + #1 + + + + + NDIV + N-Divider Value + 8 + 14 + read-write + + + PLLPWD + PLL Power Saving Mode + 16 + 16 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The complete PLL block is put into a Power Saving Mode. Only the Bypass Mode is active if previously selected. + #1 + + + + + RESLD + Restart VCO Lock Detection + 18 + 18 + write-only + + + PDIV + P-Divider Value + 24 + 27 + read-write + + + + + CLKMXSTAT + Clock Multiplexing Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SYSCLKMUX + Status of System Clock Multiplexing Upon Source Switching + 0 + 1 + read-only + + + value1 + fOFI clock active + #01 + + + value2 + fPLL clock active + #10 + + + + + + + + + SCU_GENERAL + System Control Unit + SCU + 0x50004000 + + 0x0 + 0x100 + registers + + + + ID + SCU Module ID Register + 0x0000 + 32 + 0x0090C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + IDCHIP + Chip ID Register + 0x0004 + 32 + 0x00000000 + 0x00000000 + + + IDCHIP + Chip ID + 0 + 31 + read-only + + + + + IDMANUF + Manufactory ID Register + 0x0008 + 32 + 0x00001820 + 0xFFFFFFFF + + + DEPT + Department Identification Number + 0 + 4 + read-only + + + MANUF + Manufacturer Identification Number + 5 + 15 + read-only + + + + + STCON + Startup Configuration Register + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + HWCON + HW Configuration + 0 + 1 + read-only + + + value1 + Normal mode, JTAG + #00 + + + value2 + ASC BSL enabled + #01 + + + value3 + BMI customized boot enabled + #10 + + + value4 + CAN BSL enabled + #11 + + + + + SWCON + SW Configuration + 8 + 11 + read-write + + + value1 + Normal mode, boot from Boot ROM + #0000 + + + value2 + ASC BSL enabled + #0001 + + + value3 + BMI customized boot enabled + #0010 + + + value4 + CAN BSL enabled + #0011 + + + value5 + Boot from Code SRAM + #0100 + + + value6 + Boot from alternate Flash Address 0 + #1000 + + + value7 + Boot from alternate Flash Address 1 + #1100 + + + value8 + Enable fallback Alternate Boot Mode (ABM) + #1110 + + + + + + + GPR0 + General Purpose Register 0 + 0x002C + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + User Data + 0 + 31 + read-write + + + + + GPR1 + General Purpose Register 1 + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + User Data + 0 + 31 + read-write + + + + + CCUCON + CCU Control Register + 0x004C + 32 + 0x00000000 + 0xFFFFFFFF + + + GSC40 + Global Start Control CCU40 + 0 + 0 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC41 + Global Start Control CCU41 + 1 + 1 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC42 + Global Start Control CCU42 + 2 + 2 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC43 + Global Start Control CCU43 + 3 + 3 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC80 + Global Start Control CCU80 + 8 + 8 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC81 + Global Start Control CCU81 + 9 + 9 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + + + DTSCON + Die Temperature Sensor Control Register + 0x008C + 32 + 0x00000001 + 0xFFFFFFFF + + + PWD + Sensor Power Down + 0 + 0 + read-write + + + value1 + The DTS is powered + #0 + + + value2 + The DTS is not powered + #1 + + + + + START + Sensor Measurement Start + 1 + 1 + write-only + + + value1 + No DTS measurement is started + #0 + + + value2 + A DTS measurement is started + #1 + + + + + OFFSET + Offset Calibration Value + 4 + 10 + read-write + + + GAIN + Gain Calibration Value + 11 + 16 + read-write + + + REFTRIM + Reference Trim Calibration Value + 17 + 19 + read-write + + + BGTRIM + Bandgap Trim Calibration Value + 20 + 23 + read-write + + + + + DTSSTAT + Die Temperature Sensor Status Register + 0x0090 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of the DTS Measurement + 0 + 9 + read-only + + + RDY + Sensor Ready Status + 14 + 14 + read-only + + + value1 + The DTS is not ready + #0 + + + value2 + The DTS is ready + #1 + + + + + BUSY + Sensor Busy Status + 15 + 15 + read-only + + + value1 + not busy + #0 + + + value2 + busy + #1 + + + + + + + SDMMCDEL + SD-MMC Delay Control Register + 0x009C + 32 + 0x00000000 + 0xFFFFFFFF + + + TAPEN + Enable delay on the CMD/DAT out lines + 0 + 0 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + TAPDEL + Number of Delay Elements Select + 4 + 7 + read-write + + + + + G0ORCEN + Out of Range Comparator Enable Register 0 + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENORC6 + Enable Out of Range Comparator, Channel 6 + 6 + 6 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + ENORC7 + Enable Out of Range Comparator, Channel 7 + 7 + 7 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + + + G1ORCEN + Out of Range Comparator Enable Register 1 + 0x00A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENORC6 + Enable Out of Range Comparator, Channel 6 + 6 + 6 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + ENORC7 + Enable Out of Range Comparator, Channel 7 + 7 + 7 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + + + MIRRSTS + Mirror Write Status Register + 0x00C4 + 32 + 0x00000000 + 0xFFFFFFFF + + + HDCLR + HDCLR Mirror Register Write Status + 1 + 1 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + HDSET + HDSET Mirror Register Write Status + 2 + 2 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + HDCR + HDCR Mirror Register Write Status + 3 + 3 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + OSCSICTRL + OSCSICTRL Mirror Register Write Status + 5 + 5 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + OSCULCTRL + OSCULCTRL Mirror Register Write Status + 7 + 7 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_CTR + RTC CTR Mirror Register Write Status + 8 + 8 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_ATIM0 + RTC ATIM0 Mirror Register Write Status + 9 + 9 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_ATIM1 + RTC ATIM1 Mirror Register Write Status + 10 + 10 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_TIM0 + RTC TIM0 Mirror Register Write Status + 11 + 11 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_TIM1 + RTC TIM1 Mirror Register Write Status + 12 + 12 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RMX + Retention Memory Access Register Update Status + 13 + 13 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_MSKSR + RTC MSKSSR Mirror Register Write Status + 14 + 14 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_CLRSR + RTC CLRSR Mirror Register Write Status + 15 + 15 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + + + RMACR + Retention Memory Access Control Register + 0x00C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDWR + Hibernate Retention Memory Register Update Control + 0 + 0 + read-write + + + value1 + transfer data from Retention Memory in Hibernate domain to RMDATA register + #0 + + + value2 + transfer data from RMDATA into Retention Memory in Hibernate domain + #1 + + + + + ADDR + Hibernate Retention Memory Register Address Select + 16 + 19 + read-write + + + + + RMDATA + Retention Memory Access Data Register + 0x00CC + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Hibernate Retention Memory Data + 0 + 31 + read-write + + + + + + + SCU_INTERRUPT + System Control Unit + SCU + 0x50004074 + + 0x0 + 0x18 + registers + + + SCU_0 + System Control + 0 + + + + SRSTAT + SCU Service Request Status + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRWARN + WDT pre-warning Interrupt Status + 0 + 0 + read-only + + + value1 + Inactive + #0 + + + value2 + Active + #1 + + + + + PI + RTC Periodic Interrupt Status + 1 + 1 + read-only + + + AI + Alarm Interrupt Status + 2 + 2 + read-only + + + DLROVR + DLR Request Overrun Interrupt Status + 3 + 3 + read-only + + + HDCLR + HDCLR Mirror Register Update Status + 17 + 17 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + HDSET + HDSET Mirror Register Update Status + 18 + 18 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + HDCR + HDCR Mirror Register Update Status + 19 + 19 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + OSCSICTRL + OSCSICTRL Mirror Register Update Status + 21 + 21 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + OSCULCTRL + OSCULCTRL Mirror Register Update Status + 23 + 23 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_CTR + RTC CTR Mirror Register Update Status + 24 + 24 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_ATIM0 + RTC ATIM0 Mirror Register Update Status + 25 + 25 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_ATIM1 + RTC ATIM1 Mirror Register Update Status + 26 + 26 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_TIM0 + RTC TIM0 Mirror Register Update Status + 27 + 27 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_TIM1 + RTC TIM1 Mirror Register Update Status + 28 + 28 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RMX + Retention Memory Mirror Register Update Status + 29 + 29 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + + + SRRAW + SCU Raw Service Request Status + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRWARN + WDT pre-warning Interrupt Status Before Masking + 0 + 0 + read-only + + + value1 + Inactive + #0 + + + value2 + Active + #1 + + + + + PI + RTC Raw Periodic Interrupt Status Before Masking + 1 + 1 + read-only + + + AI + RTC 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Memory + 17 + 17 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + PETEETH0RX + Parity Error Trap Enable for ETH0 RX Memory + 18 + 18 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + PETESD0 + Parity Error Trap Enable for SDMMC SRAM 0 Memory + 19 + 19 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + PETESD1 + Parity Error Trap Enable for SDMMC SRAM 1 Memory + 20 + 20 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + + + PERSTEN + Parity Error Reset Enable Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + RSEN + System Reset Enable upon Parity Error Trap + 0 + 0 + read-write + + + value1 + Reset request disabled + #0 + + + value2 + Reset request enabled + #1 + + + + + + + PEFLAG + Parity Error Flag Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PEFPS + Parity Error Flag for PSRAM + 0 + 0 + read-write + + + value1 + No parity error detected + #0 + + + value2 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read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTEU2 + Test Enable Control for USIC2 Memory + 10 + 10 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTEMC + Test Enable Control for MultiCAN Memory + 12 + 12 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTEPPRF + Test Enable Control for PMU Prefetch Memory + 13 + 13 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTUSB + Test Enable Control for USB Memory + 16 + 16 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTETH0TX + Test Enable Control for ETH TX Memory + 17 + 17 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTETH0RX + Test Enable Control for ETH RX Memory + 18 + 18 + read-write + + + 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pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + SVCOLCKT + System VCO Lock Trap Raw Status + 2 + 2 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + UVCOLCKT + USB VCO Lock Trap Raw Status + 3 + 3 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + PET + Parity Error Trap Raw Status + 4 + 4 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + BRWNT + Brown Out Trap Raw Status + 5 + 5 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + ULPWDGT + OSC_ULP Oscillator Watchdog Trap Raw Status + 6 + 6 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + BWERR0T + Peripheral Bridge 0 Trap Raw Status + 7 + 7 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap 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+ 0x00000000 + 0xFFFFFFFF + + + EPEV + Wake-up Pin Event Positive Edge + 0 + 0 + read-only + + + value1 + Wake-up on positive edge pin event inactive + #0 + + + value2 + Wake-up on positive edge pin event active + #1 + + + + + ENEV + Wake-up Pin Event Negative Edge + 1 + 1 + read-only + + + value1 + Wake-up on negative edge pin event inactive + #0 + + + value2 + Wake-up on negative edge pin event active + #1 + + + + + RTCEV + RTC Event + 2 + 2 + read-only + + + value1 + Wake-up on RTC event inactive + #0 + + + value2 + Wake-up on RTC event active + #1 + + + + + ULPWDG + ULP WDG Alarm Status + 3 + 3 + read-only + + + value1 + Watchdog alarm did not occur + #0 + + + value2 + Watchdog alarm occurred + #1 + + + + + HIBNOUT + Hibernate Control Status + 4 + 4 + read-only + + + value1 + Hibernate not driven active to pads + #0 + + + value2 + Hibernate driven active to pads + #1 + + + + + + + HDCLR + Hibernate Domain Status Clear Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPEV + Wake-up Pin Event Positive Edge Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Clear wake-up event + #1 + + + + + ENEV + Wake-up Pin Event Negative Edge Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Clear wake-up event + #1 + + + + + RTCEV + RTC Event Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Clear wake-up event + #1 + + + + + ULPWDG + ULP WDG Alarm Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Clear watchdog alarm + #1 + + + + + + + HDSET + Hibernate Domain Status Set Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPEV + Wake-up Pin Event Positive Edge Set + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Set wake-up event + #1 + + + + + ENEV + Wake-up Pin Event Negative Edge Set + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Set wake-up event + #1 + + + + + RTCEV + RTC Event Set + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Set wake-up event + #1 + + + + + ULPWDG + ULP WDG Alarm Set + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Set watchdog alarm + #1 + + + + + + + HDCR + Hibernate Domain Control Register + 0x0C + 32 + 0x000C2000 + 0xFFFFFFFF + + + WKPEP + Wake-Up on Pin Event Positive Edge Enable + 0 + 0 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + WKPEN + Wake-up on Pin Event Negative Edge Enable + 1 + 1 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + RTCE + Wake-up on RTC Event Enable + 2 + 2 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + ULPWDGEN + ULP WDG Alarm Enable + 3 + 3 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + HIB + Hibernate Request Value Set + 4 + 4 + read-write + + + value1 + External hibernate request inactive + #0 + + + value2 + External hibernate request active + #1 + + + + + RCS + fRTC Clock Selection + 6 + 6 + read-write + + + value1 + fOSI selected + #0 + + + value2 + fULP selected + #1 + + + + + STDBYSEL + fSTDBY Clock Selection + 7 + 7 + read-write + + + value1 + fOSI selected + #0 + + + value2 + fULP selected + #1 + + + + + WKUPSEL + Wake-Up from Hibernate Trigger Input Selection + 8 + 8 + read-write + + + value1 + HIB_IO_1 pin selected + #0 + + + value2 + HIB_IO_0 pin selected + #1 + + + + + GPI0SEL + General Purpose Input 0 Selection + 10 + 10 + read-write + + + value1 + HIB_IO_1 pin selected + #0 + + + value2 + HIB_IO_0 pin selected + #1 + + + + + HIBIO0POL + HIBIO0 Polarity Set + 12 + 12 + read-write + + + value1 + Direct value + #0 + + + value2 + Inverted value + #1 + + + + + HIBIO1POL + HIBIO1 Polarity Set + 13 + 13 + read-write + + + value1 + Direct value + #0 + + + value2 + Inverted value + #1 + + + + + HIBIO0SEL + HIB_IO_0 Pin I/O Control (default HIBOUT) + 16 + 19 + read-write + + + value1 + Direct input, No input pull device connected + #0000 + + + value2 + Direct input, Input pull-down device connected + #0001 + + + value3 + Direct input, Input pull-up device connected + #0010 + + + value4 + Push-pull HIB Control output + #1000 + + + value5 + Push-pull WDT service output + #1001 + + + value6 + Push-pull GPIO output + #1010 + + + value7 + Open-drain HIB Control output + #1100 + + + value8 + Open-drain WDT service output + #1101 + + + value9 + Open-drain GPIO output + #1110 + + + value10 + Analog input + #1111 + + + + + HIBIO1SEL + HIB_IO_1 Pin I/O Control (Default WKUP) + 20 + 23 + read-write + + + value1 + Direct input, No input pull device connected + #0000 + + + value2 + Direct input, Input pull-down device connected + #0001 + + + value3 + Direct input, Input pull-up device connected + #0010 + + + value4 + Push-pull HIB Control output + #1000 + + + value5 + Push-pull WDT service output + #1001 + + + value6 + Push-pull GPIO output + #1010 + + + value7 + Open-drain HIB Control output + #1100 + + + value8 + Open-drain WDT service output + #1101 + + + value9 + Open-drain GPIO output + #1110 + + + value10 + Analog input + #1111 + + + + + + + OSCSICTRL + fOSI Control Register + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + PWD + Turn OFF the fOSI Clock Source + 0 + 0 + read-write + + + value1 + Enabled + #0 + + + value2 + Disabled + #1 + + + + + + + OSCULSTAT + OSC_ULP Status Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + X1D + XTAL1 Data Value + 0 + 0 + read-only + + + + + OSCULCTRL + OSC_ULP Control Register + 0x1C + 32 + 0x00000020 + 0xFFFFFFFF + + + X1DEN + XTAL1 Data General Purpose Input Enable + 0 + 0 + read-write + + + value1 + Data input inactivated, power down + #0 + + + value2 + Data input active + #1 + + + + + MODE + Oscillator Mode + 4 + 5 + read-write + + + value1 + Oscillator is enabled, in operation + #00 + + + value2 + Oscillator is enabled, in bypass mode + #01 + + + value3 + Oscillator in power down + #10 + + + value4 + Oscillator in power down, can be used as GPI + #11 + + + + + + + + + SCU_POWER + System Control Unit + SCU + 0x50004200 + + 0x0 + 0x100 + registers + + + + PWRSTAT + PCU Status Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIBEN + Hibernate Domain Enable Status + 0 + 0 + read-only + + + value1 + Inactive + #0 + + + value2 + Active + #1 + + + + + USBPHYPDQ + USB PHY Transceiver State + 16 + 16 + read-only + + + value1 + Power-down + #0 + + + value2 + Active + #1 + + + + + USBOTGEN + USB On-The-Go Comparators State + 17 + 17 + read-only + + + value1 + Power-down + #0 + + + value2 + Active + #1 + + + + + USBPUWQ + USB Weak Pull-Up at PADN State + 18 + 18 + read-only + + + value1 + Pull-up active + #0 + + + value2 + Pull-up not active + #1 + + + + + + + PWRSET + PCU Set Control Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIB + Set Hibernate Domain Enable + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Enable Hibernate domain + #1 + + + + + USBPHYPDQ + Set USB PHY Transceiver Disable + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + Active + #1 + + + + + USBOTGEN + Set USB On-The-Go Comparators Enable + 17 + 17 + write-only + + + value1 + No effect + #0 + + + value2 + Active + #1 + + + + + USBPUWQ + Set USB Weak Pull-Up at PADN Enable + 18 + 18 + write-only + + + value1 + No effect + #0 + + + value2 + Pull-up not active + #1 + + + + + + + PWRCLR + PCU Clear Control Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIB + Clear Disable Hibernate Domain + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Disable Hibernate domain + #1 + + + + + USBPHYPDQ + Clear USB PHY Transceiver Disable + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + Power-down + #1 + + + + + USBOTGEN + Clear USB On-The-Go Comparators Enable + 17 + 17 + write-only + + + value1 + No effect + #0 + + + value2 + Power-down + #1 + + + + + USBPUWQ + Clear USB Weak Pull-Up at PADN Enable + 18 + 18 + write-only + + + value1 + No effect + #0 + + + value2 + Pull-up active + #1 + + + + + + + EVRSTAT + EVR Status Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + OV13 + Regulator Overvoltage for 1.3 V + 1 + 1 + read-only + + + value1 + No overvoltage condition + #0 + + + value2 + Regulator is in overvoltage + #1 + + + + + + + EVRVADCSTAT + EVR VADC Status Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VADC13V + VADC 1.3 V Conversion Result + 0 + 7 + read-only + + + VADC33V + VADC 3.3 V Conversion Result + 8 + 15 + read-only + + + + + PWRMON + Power Monitor Control + 0x2C + 32 + 0x00000000 + 0xFFFFFFFF + + + THRS + Threshold + 0 + 7 + read-write + + + INTV + Interval + 8 + 15 + read-write + + + ENB + Enable + 16 + 16 + read-write + + + + + + + SCU_RESET + System Control Unit + SCU + 0x50004400 + + 0x0 + 0x100 + registers + + + + RSTSTAT + RCU Reset Status + 0x00 + 32 + 0x00000000 + 0xFFFF0000 + + + RSTSTAT + Reset Status Information + 0 + 7 + read-only + + + value1 + PORST reset + #00000001 + + + value2 + SWD reset + #00000010 + + + value3 + PV reset + #00000100 + + + value4 + CPU system reset + #00001000 + + + value5 + CPU lockup reset + #00010000 + + + value6 + WDT reset + #00100000 + + + value8 + Parity Error reset + #10000000 + + + + + HIBWK + Hibernate Wake-up Status + 8 + 8 + read-only + + + value1 + No Wake-up + #0 + + + value2 + Wake-up event + #1 + + + + + HIBRS + Hibernate Reset Status + 9 + 9 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + LCKEN + Enable Lockup Status + 10 + 10 + read-only + + + value1 + Reset by Lockup disabled + #0 + + + value2 + Reset by Lockup enabled + #1 + + + + + + + RSTSET + RCU Reset Set Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIBWK + Set Hibernate Wake-up Reset Status + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset status bit + #1 + + + + + HIBRS + Set Hibernate Reset + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + LCKEN + Enable Lockup Reset + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + Enable reset when Lockup gets asserted + #1 + + + + + + + RSTCLR + RCU Reset Clear Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSCLR + Clear Reset Status + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Clears field RSTSTAT.RSTSTAT + #1 + + + + + HIBWK + Clear Hibernate Wake-up Reset Status + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset status bit + #1 + + + + + HIBRS + Clear Hibernate Reset + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + LCKEN + Enable Lockup Reset + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + Disable reset when Lockup gets asserted + #1 + + + + + + + PRSTAT0 + RCU Peripheral 0 Reset Status + 0x0C + 32 + 0x00010F9F + 0xFFFFFFFF + + + VADCRS + VADC Reset Status + 0 + 0 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DSDRS + DSD Reset Status + 1 + 1 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU40RS + CCU40 Reset Status + 2 + 2 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU41RS + CCU41 Reset Status + 3 + 3 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU42RS + CCU42 Reset Status + 4 + 4 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU80RS + CCU80 Reset Status + 7 + 7 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU81RS + CCU81 Reset Status + 8 + 8 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + POSIF0RS + POSIF0 Reset Status + 9 + 9 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + POSIF1RS + POSIF1 Reset Status + 10 + 10 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USIC0RS + USIC0 Reset Status + 11 + 11 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + ERU1RS + ERU1 Reset Status + 16 + 16 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET0 + RCU Peripheral 0 Reset Set + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VADCRS + VADC Reset Assert + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DSDRS + DSD Reset Assert + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU40RS + CCU40 Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU41RS + CCU41 Reset Assert + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU42RS + CCU42 Reset Assert + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU80RS + CCU80 Reset Assert + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU81RS + CCU81 Reset Assert + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + POSIF0RS + POSIF0 Reset Assert + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + POSIF1RS + POSIF1 Reset Assert + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USIC0RS + USIC0 Reset Assert + 11 + 11 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + ERU1RS + ERU1 Reset Assert + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR0 + RCU Peripheral 0 Reset Clear + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VADCRS + VADC Reset Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DSDRS + DSD Reset Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU40RS + CCU40 Reset Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU41RS + CCU41 Reset Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU42RS + CCU42 Reset Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU80RS + CCU80 Reset Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU81RS + CCU81 Reset Clear + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + POSIF0RS + POSIF0 Reset Clear + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + POSIF1RS + POSIF1 Reset Clear + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USIC0RS + USIC0 Reset Clear + 11 + 11 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + ERU1RS + ERU1 Reset Clear + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + PRSTAT1 + RCU Peripheral 1 Reset Status + 0x18 + 32 + 0x000001F9 + 0xFFFFFFFF + + + CCU43RS + CCU43 Reset Status + 0 + 0 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + LEDTSCU0RS + LEDTS Reset Status + 3 + 3 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + MCAN0RS + MultiCAN Reset Status + 4 + 4 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DACRS + DAC Reset Status + 5 + 5 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + MMCIRS + MMC Interface Reset Status + 6 + 6 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USIC1RS + USIC1 Reset Status + 7 + 7 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USIC2RS + USIC2 Reset Status + 8 + 8 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + PPORTSRS + PORTS Reset Status + 9 + 9 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET1 + RCU Peripheral 1 Reset Set + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43RS + CCU43 Reset Assert + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + LEDTSCU0RS + LEDTS Reset Assert + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + MCAN0RS + MultiCAN Reset Assert + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DACRS + DAC Reset Assert + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + MMCIRS + MMC Interface Reset Assert + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USIC1RS + USIC1 Reset Assert + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USIC2RS + USIC2 Reset Assert + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + PPORTSRS + PORTS Reset Assert + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR1 + RCU Peripheral 1 Reset Clear + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43RS + CCU43 Reset Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + LEDTSCU0RS + LEDTS Reset Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + MCAN0RS + MultiCAN Reset Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DACRS + DAC Reset Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + MMCIRS + MMC Interface Reset Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USIC1RS + USIC1 Reset Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USIC2RS + USIC2 Reset Clear + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + PPORTSRS + PORTS Reset Clear + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + PRSTAT2 + RCU Peripheral 2 Reset Status + 0x24 + 32 + 0x000004F6 + 0xFFFFFFFF + + + WDTRS + WDT Reset Status + 1 + 1 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + ETH0RS + ETH0 Reset Status + 2 + 2 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DMA0RS + DMA0 Reset Status + 4 + 4 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DMA1RS + DMA1 Reset Status + 5 + 5 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + FCERS + FCE Reset Status + 6 + 6 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USBRS + USB Reset Status + 7 + 7 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET2 + RCU Peripheral 2 Reset Set + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDTRS + WDT Reset Assert + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + ETH0RS + ETH0 Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DMA0RS + DMA0 Reset Assert + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DMA1RS + DMA1 Reset Assert + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + FCERS + FCE Reset Assert + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USBRS + USB Reset Assert + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR2 + RCU Peripheral 2 Reset Clear + 0x2C + 32 + 0x00000000 + 0xFFFFFFFF + + + WDTRS + WDT Reset Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + ETH0RS + ETH0 Reset Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DMA0RS + DMA0 Reset Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DMA1RS + DMA1 Reset Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + FCERS + FCE Reset Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USBRS + USB Reset Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + PRSTAT3 + RCU Peripheral 3 Reset Status + 0x30 + 32 + 0x00000004 + 0xFFFFFFFF + + + EBURS + EBU Reset Status + 2 + 2 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET3 + RCU Peripheral 3 Reset Set + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBURS + EBU Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR3 + RCU Peripheral 3 Reset Clear + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBURS + EBU Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + + + LEDTS0 + LED and Touch Sense Unit 0 + LEDTS + 0x48010000 + + 0x0 + 0x0100 + registers + + + LEDTS0_0 + LED and Touch Sense Control Unit (Module 0) + 102 + + + + ID + Module Identification Register + 0x0000 + 32 + 0x00ABC000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + GLOBCTL + Global Control Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS_EN + Touch-Sense Function Enable + 0 + 0 + read-write + + + LD_EN + LED Function Enable + 1 + 1 + read-write + + + CMTR + Clock Master Disable + 2 + 2 + read-write + + + value1 + Kernel generates its own clock for LEDTS-counter based on SFR setting + #0 + + + value2 + LEDTS-counter takes its clock from another master kernel + #1 + + + + + ENSYNC + Enable Autoscan Time Period Synchronization + 3 + 3 + read-write + + + value1 + No synchronization + #0 + + + value2 + Synchronization enabled on Kernel0 autoscan time period + #1 + + + + + SUSCFG + Suspend Request Configuration + 8 + 8 + read-write + + + value1 + Ignore suspend request + #0 + + + value2 + Enable suspend according to request + #1 + + + + + MASKVAL + Mask Number of LSB Bits for Event Validation + 9 + 11 + read-write + + + value1 + Mask LSB bit + 0 + + + value2 + Mask 2 LSB bits + 1 + + + value3 + Mask 8 LSB bits + 7 + + + + + FENVAL + Enable (Extended) Time Frame Validation + 12 + 12 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + ITS_EN + Enable Time Slice Interrupt + 13 + 13 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + ITF_EN + Enable (Extended) Time Frame Interrupt + 14 + 14 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + ITP_EN + Enable Autoscan Time Period Interrupt + 15 + 15 + read-write + + + value1 + Disable + #0 + + + value2 + Enable (valid only for case of hardware-enabled pad turn control) + #1 + + + + + CLK_PS + LEDTS-Counter Clock Pre-Scale Factor + 16 + 31 + read-write + + + + + FNCTL + Function Control Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + PADT + Touch-Sense TSIN Pad Turn + 0 + 2 + read-write + + + value1 + TSIN0 + 0 + + + value2 + TSIN7 + 7 + + + + + PADTSW + Software Control for Touch-Sense Pad Turn + 3 + 3 + read-write + + + value1 + The hardware automatically enables the touch-sense inputs in sequence round-robin, starting from TSIN0. + #0 + + + value2 + Disable hardware control for software control only. The touch-sense input is configured in bit PADT. + #1 + + + + + EPULL + Enable External Pull-up Configuration on Pin COLA + 4 + 4 + read-write + + + value1 + HW over-rule to enable internal pull-up is active on TSIN[x] for set duration in touch-sense time slice. With this setting, it is not specified to assign the COLA to any pin. + #0 + + + value2 + Enable external pull-up: Output 1 on pin COLA for whole duration of touch-sense time slice. + #1 + + + + + FNCOL + Previous Active Function/LED Column Status + 5 + 7 + read-only + + + ACCCNT + Accumulate Count on Touch-Sense Input + 16 + 19 + read-write + + + value1 + 1 time + 0 + + + value2 + 2 times + 1 + + + value3 + 16 times + 15 + + + + + TSCCMP + Common Compare Enable for Touch-Sense + 20 + 20 + read-write + + + value1 + Disable common compare for touch-sense + #0 + + + value2 + Enable common compare for touch-sense + #1 + + + + + TSOEXT + Extension for Touch-Sense Output for Pin-Low-Level + 21 + 22 + read-write + + + value1 + Extend by 1 ledts_clk + #00 + + + value2 + Extend by 4 ledts_clk + #01 + + + value3 + Extend by 8 ledts_clk + #10 + + + value4 + Extend by 16 ledts_clk + #11 + + + + + TSCTRR + TS-Counter Auto Reset + 23 + 23 + read-write + + + value1 + Disable TS-counter automatic reset + #0 + + + value2 + Enable TS-counter automatic reset to 00H on the first pad turn of a new TSIN[x]. Triggered on compare match in time slice. + #1 + + + + + TSCTRSAT + Saturation of TS-Counter + 24 + 24 + read-write + + + value1 + Disable + #0 + + + value2 + Enable. TS-counter stops counting in the touch-sense time slice(s) of the same (extended) frame when it reaches FFH. Counter starts to count again on the first pad turn of a new TSIN[x], triggered on compare match. + #1 + + + + + NR_TSIN + Number of Touch-Sense Input + 25 + 27 + read-write + + + value1 + 1 + 0 + + + value2 + 8 + 7 + + + + + COLLEV + Active Level of LED Column + 28 + 28 + read-write + + + value1 + Active low + #0 + + + value2 + Active high + #1 + + + + + NR_LEDCOL + Number of LED Columns + 29 + 31 + read-write + + + value1 + 1 LED column + #000 + + + value2 + 2 LED columns + #001 + + + value3 + 3 LED columns + #010 + + + value4 + 4 LED columns + #011 + + + value5 + 5 LED columns + #100 + + + value6 + 6 LED columns + #101 + + + value7 + 7 LED columns + #110 + + + value8 + 8 LED columns (max. LED columns = 7 if bit TS_EN = 1) + #111 + + + + + + + EVFR + Event Flag Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + TSF + Time Slice Interrupt Flag + 0 + 0 + read-only + + + TFF + (Extended) Time Frame Interrupt Flag + 1 + 1 + read-only + + + TPF + Autoscan Time Period Interrupt Flag + 2 + 2 + read-only + + + TSCTROVF + TS-Counter Overflow Indication + 3 + 3 + read-only + + + value1 + No overflow has occurred. + #0 + + + value2 + The TS-counter has overflowed at least once. + #1 + + + + + CTSF + Clear Time Slice Interrupt Flag + 16 + 16 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TSF is cleared. + #1 + + + + + CTFF + Clear (Extended) Time Frame Interrupt Flag + 17 + 17 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TFF is cleared. + #1 + + + + + CTPF + Clear Autoscan Time Period Interrupt Flag + 18 + 18 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TPF is cleared. + #1 + + + + + + + TSVAL + Touch-sense TS-Counter Value + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSCTRVALR + Shadow TS-Counter (Read) + 0 + 15 + read-only + + + TSCTRVAL + TS-Counter Value + 16 + 31 + read-write + + + + + LINE0 + Line Pattern Register 0 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINE_0 + Output on LINE[x] + 0 + 7 + read-write + + + LINE_1 + Output on LINE[x] + 8 + 15 + read-write + + + LINE_2 + Output on LINE[x] + 16 + 23 + read-write + + + LINE_3 + Output on LINE[x] + 24 + 31 + read-write + + + + + LINE1 + Line Pattern Register 1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINE_4 + Output on LINE[x] + 0 + 7 + read-write + + + LINE_5 + Output on LINE[x] + 8 + 15 + read-write + + + LINE_6 + Output on LINE[x] + 16 + 23 + read-write + + + LINE_A + Output on LINE[x] + 24 + 31 + read-write + + + + + LDCMP0 + LED Compare Register 0 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_LD0 + Compare Value for LED COL[x] + 0 + 7 + read-write + + + CMP_LD1 + Compare Value for LED COL[x] + 8 + 15 + read-write + + + CMP_LD2 + Compare Value for LED COL[x] + 16 + 23 + read-write + + + CMP_LD3 + Compare Value for LED COL[x] + 24 + 31 + read-write + + + + + LDCMP1 + LED Compare Register 1 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_LD4 + Compare Value for LED COL[x] + 0 + 7 + read-write + + + CMP_LD5 + Compare Value for LED COL[x] + 8 + 15 + read-write + + + CMP_LD6 + Compare Value for LED COL[x] + 16 + 23 + read-write + + + CMP_LDA_TSCOM + Compare Value for LED COLA / Common Compare Value for Touch-sense Pad Turns + 24 + 31 + read-write + + + + + TSCMP0 + Touch-sense Compare Register 0 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_TS0 + Compare Value for Touch-Sense TSIN[x] + 0 + 7 + read-write + + + CMP_TS1 + Compare Value for Touch-Sense TSIN[x] + 8 + 15 + read-write + + + CMP_TS2 + Compare Value for Touch-Sense TSIN[x] + 16 + 23 + read-write + + + CMP_TS3 + Compare Value for Touch-Sense TSIN[x] + 24 + 31 + read-write + + + + + TSCMP1 + Touch-sense Compare Register 1 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_TS4 + Compare Value for Touch-Sense TSIN[x] + 0 + 7 + read-write + + + CMP_TS5 + Compare Value for Touch-Sense TSIN[x] + 8 + 15 + read-write + + + CMP_TS6 + Compare Value for Touch-Sense TSIN[x] + 16 + 23 + read-write + + + CMP_TS7 + Compare Value for Touch-Sense TSIN[x] + 24 + 31 + read-write + + + + + + + SDMMC_CON + SD and Multimediacard Control Register + 0x500040B4 + + 0 + 4 + registers + + + + SDMMC_CON + SDMMC Configuration + 0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WPSEL + SDMMC Write Protection Input Multiplexer Control + 0 + 0 + read-write + + + value1 + P1.1 input pin selected + #0 + + + value2 + Software bit WPVAL is selected + #1 + + + + + WPSVAL + SDMMC Write Protect Software Control + 4 + 4 + read-write + + + value1 + No write protection + #0 + + + value2 + Write protection active + #1 + + + + + CDSEL + SDMMC Card Detection Control + 16 + 16 + read-write + + + value1 + P1.10 input pin selected + #0 + + + value2 + Software bit CDSVAL is selected + #1 + + + + + CDSVAL + SDMMC Write Protect Software Control + 20 + 20 + read-write + + + value1 + No card detected + #0 + + + value2 + Card detected + #1 + + + + + + + + + SDMMC + SD and Multimediacard Interface + 0x4801C000 + + 0x0 + 0x4000 + registers + + + SDMMC0_0 + Multi Media Card Interface + 106 + + + + BLOCK_SIZE + Block Size Register + 0x0004 + 16 + 0x0000 + 0xFFFF + + + TX_BLOCK_SIZE_12 + Transfer Block Size 12th bit. + 15 + 15 + read-write + + + TX_BLOCK_SIZE + Transfer Block Size + 0 + 11 + read-write + + + + + BLOCK_COUNT + Block Count Register + 0x0006 + 16 + 0x0000 + 0xFFFF + + + BLOCK_COUNT + Blocks Count for Current Transfer + 0 + 15 + read-write + + + + + ARGUMENT1 + Argument1 Register + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMENT1 + Command Argument + 0 + 31 + read-write + + + + + TRANSFER_MODE + Transfer Mode Register + 0x000C + 16 + 0x0000 + 0xFFFF + + + CMD_COMP_ATA + Command Completion Signal Enable for CE-ATA Device + 6 + 6 + read-write + + + value1 + Device will send command completion Signal + #1 + + + value2 + Device will not send command completion Signal + #0 + + + + + MULTI_BLOCK_SELECT + Multi / Single Block Select + 5 + 5 + read-write + + + value1 + Single Block + #0 + + + value2 + Multiple Block + #1 + + + + + TX_DIR_SELECT + Data Transfer Direction Select + 4 + 4 + read-write + + + value1 + Write (Host to Card) + #0 + + + value2 + Read (Card to Host) + #1 + + + + + ACMD_EN + Auto CMD Enable + 2 + 3 + read-write + + + value1 + Auto Command Disabled + #00 + + + value2 + Auto CMD12 Enable + #01 + + + + + BLOCK_COUNT_EN + Block Count Enable + 1 + 1 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + + + COMMAND + Command Register + 0x000E + 16 + 0x0000 + 0xFFFF + + + CMD_IND + Command Index + 8 + 13 + read-write + + + CMD_TYPE + Command Type + 6 + 7 + read-write + + + value1 + Normal + #00 + + + value2 + Suspend + #01 + + + value3 + Resume + #10 + + + value4 + Abort + #11 + + + + + DATA_PRESENT_SELECT + Data Present Select + 5 + 5 + read-write + + + value1 + No Data Present + #0 + + + value2 + Data Present + #1 + + + + + CMD_IND_CHECK_EN + Command Index Check Enable + 4 + 4 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + CMD_CRC_CHECK_EN + Command CRC Check Enable + 3 + 3 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + RESP_TYPE_SELECT + Response Type Select + 0 + 1 + read-write + + + value1 + No Response + #00 + + + value2 + Response length 136 + #01 + + + value3 + Response length 48 + #10 + + + value4 + Response length 48 check Busy after response + #11 + + + + + + + RESPONSE0 + Response 0 Register + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE1 + Response1 + 16 + 31 + read-only + + + RESPONSE0 + Response0 + 0 + 15 + read-only + + + + + RESPONSE2 + Response 2 Register + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE3 + Response3 + 16 + 31 + read-only + + + RESPONSE2 + Response2 + 0 + 15 + read-only + + + + + RESPONSE4 + Response 4 Register + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE5 + Response5 + 16 + 31 + read-only + + + RESPONSE4 + Response4 + 0 + 15 + read-only + + + + + RESPONSE6 + Response 6 Register + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE7 + Response7 + 16 + 31 + read-only + + + RESPONSE6 + Response6 + 0 + 15 + read-only + + + + + DATA_BUFFER + Data Buffer Register + 0x0020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_BUFFER + Data Buffer + 0 + 31 + read-write + + + + + PRESENT_STATE + Present State Register + 0x0024 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT_7_4_PIN_LEVEL + Line Signal Level + 25 + 28 + read-only + + + CMD_LINE_LEVEL + CMD Line Signal Level + 24 + 24 + read-only + + + DAT_3_0_PIN_LEVEL + Line Signal Level + 20 + 23 + read-only + + + WRITE_PROTECT_PIN_LEVEL + Write Protect Switch Pin Level + 19 + 19 + read-only + + + value1 + Write protected (SDWP = 1) + #0 + + + value2 + Write enabled (SDWP = 0) + #1 + + + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level + 18 + 18 + read-only + + + value1 + No Card present (SDCD = 1) + #0 + + + value2 + Card present (SDCD = 0) + #1 + + + + + CARD_STATE_STABLE + Card State Stable + 17 + 17 + read-only + + + value1 + Reset of Debouncing + #0 + + + value2 + No Card or Inserted + #1 + + + + + CARD_INSERTED + Card Inserted + 16 + 16 + read-only + + + value1 + Reset or Debouncing or No Card + #0 + + + value2 + Card Inserted + #1 + + + + + BUFFER_READ_ENABLE + Buffer Read Enable + 11 + 11 + read-only + + + value1 + Read Disable + #0 + + + value2 + Read Enable. + #1 + + + + + BUFFER_WRITE_ENABLE + Buffer Write Enable + 10 + 10 + read-only + + + value1 + Write Disable + #0 + + + value2 + Write Enable. + #1 + + + + + READ_TRANSFER_ACTIVE + Read Transfer Active + 9 + 9 + read-only + + + value1 + No valid data + #0 + + + value2 + Transferring data + #1 + + + + + WRITE_TRANSFER_ACTIVE + Write Transfer Active + 8 + 8 + read-only + + + value1 + No valid data + #0 + + + value2 + Transferring data + #1 + + + + + DAT_LINE_ACTIVE + DAT Line Active + 2 + 2 + read-only + + + value1 + DAT line inactive + #0 + + + value2 + DAT line active + #1 + + + + + COMMAND_INHIBIT_DAT + Command Inhibit (DAT) + 1 + 1 + read-only + + + value1 + Can issue command which uses the DAT line + #0 + + + value2 + Cannot issue command which uses the DAT line + #1 + + + + + COMMAND_INHIBIT_CMD + Command Inhibit (CMD) + 0 + 0 + read-only + + + + + HOST_CTRL + Host Control Register + 0x0028 + 8 + 0x00 + 0xFF + + + CARD_DET_SIGNAL_DETECT + Card detect signal detetction + 7 + 7 + read-write + + + value1 + SDCD is selected (for normal use) + #0 + + + value2 + The card detect test level is selected + #1 + + + + + CARD_DETECT_TEST_LEVEL + Card Detect Test Level + 6 + 6 + read-write + + + value1 + No Card + #0 + + + value2 + Card Inserted + #1 + + + + + SD_8BIT_MODE + Extended Data Transfer Width + 5 + 5 + read-write + + + value1 + Bus Width is selected by Data Transfer Width + #0 + + + value2 + 8-bit Bus Width + #1 + + + + + HIGH_SPEED_EN + High Speed Enable + 2 + 2 + read-write + + + value1 + Normal Speed Mode + #0 + + + value2 + High Speed Mode + #1 + + + + + DATA_TX_WIDTH + Data Transfer Width (SD1 or SD4) + 1 + 1 + read-write + + + value1 + 1 bit mode + #0 + + + value2 + 4-bit mode + #1 + + + + + LED_CTRL + LED Control + 0 + 0 + read-write + + + value1 + LED off + #0 + + + value2 + LED on + #1 + + + + + + + POWER_CTRL + Power Control Register + 0x0029 + 8 + 0x00 + 0xFF + + + HARDWARE_RESET + Hardware reset + 4 + 4 + read-write + + + SD_BUS_VOLTAGE_SEL + SD Bus Voltage Select + 1 + 3 + read-write + + + value1 + 3.3V (Flattop.) + #111 + + + + + SD_BUS_POWER + SD Bus Power + 0 + 0 + read-write + + + value1 + Power off + #0 + + + value2 + Power on + #1 + + + + + + + BLOCK_GAP_CTRL + Block Gap Control Register + 0x002A + 8 + 0x00 + 0xFF + + + INT_AT_BLOCK_GAP + Interrupt At Block Gap + 3 + 3 + read-write + + + READ_WAIT_CTRL + Read Wait Control + 2 + 2 + read-write + + + value1 + Disable Read Wait Control + #0 + + + value2 + Enable Read Wait Control + #1 + + + + + CONTINUE_REQ + Continue Request + 1 + 1 + read-write + + + value1 + Ignored + #0 + + + value2 + Restart + #1 + + + + + STOP_AT_BLOCK_GAP + Stop At Block Gap Request + 0 + 0 + read-write + + + value1 + Transfer + #0 + + + value2 + Stop + #1 + + + + + + + WAKEUP_CTRL + Wake-up Control Register + 0x002B + 8 + 0x00 + 0xFF + + + WAKEUP_EVENT_EN_REM + Wakeup Event Enable On SD Card Removal + 2 + 2 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + WAKEUP_EVENT_EN_INS + Wakeup Event Enable On SD Card Insertion + 1 + 1 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + WAKEUP_EVENT_EN_INT + Wakeup Event Enable On Card Interrupt + 0 + 0 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + + + CLOCK_CTRL + Clock Control Register + 0x002C + 16 + 0x0000 + 0xFFFF + + + SDCLK_FREQ_SEL + SDCLK Frequency Select + 8 + 15 + read-write + + + value1 + base clock(10MHz-63MHz) + 0x00 + + + value2 + base clock divided by 2 + 0x01 + + + value3 + base clock divided by 32 + 0x10 + + + value4 + base clock divided by 4 + 0x02 + + + value5 + base clock divided by 8 + 0x04 + + + value6 + base clock divided by 16 + 0x08 + + + value7 + base clock divided by 64 + 0x20 + + + value8 + base clock divided by 128 + 0x40 + + + value9 + base clock divided by 256 + 0x80 + + + + + SDCLOCK_EN + SD Clock Enable + 2 + 2 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + INTERNAL_CLOCK_STABLE + Internal Clock Stable + 1 + 1 + read-only + + + value1 + Not Ready + #0 + + + value2 + Ready + #1 + + + + + INTERNAL_CLOCK_EN + Internal Clock Enable + 0 + 0 + read-write + + + value1 + Stop + #0 + + + value2 + Oscillate + #1 + + + + + + + TIMEOUT_CTRL + Timeout Control Register + 0x002E + 8 + 0x00 + 0xFF + + + DAT_TIMEOUT_CNT_VAL + Data Timeout Counter Value + 0 + 3 + read-write + + + value1 + TMCLK * 2^13 + #0000 + + + value2 + TMCLK * 2^14 + #0001 + + + value3 + TMCLK * 2^27 + #1110 + + + + + + + SW_RESET + Software Reset Register + 0x002F + 8 + 0x00 + 0xFF + + + SW_RST_DAT_LINE + Software Reset for DAT Line + 2 + 2 + read-write + + + value1 + Work + #0 + + + value2 + Reset + #1 + + + + + SW_RST_CMD_LINE + Software Reset for CMD Line + 1 + 1 + read-write + + + value1 + Work + #0 + + + value2 + Reset + #1 + + + + + SW_RST_ALL + Software Reset for All + 0 + 0 + read-write + + + + + INT_STATUS_NORM + Normal Interrupt Status Register + 0x0030 + 16 + 0x0000 + 0xFFFF + + + ERR_INT + Error Interrupt + 15 + 15 + read-only + + + value1 + No Error. + #0 + + + value2 + Error. + #1 + + + + + CARD_INT + Card Interrupt + 8 + 8 + read-only + + + value1 + No Card Interrupt + #0 + + + value2 + Generate Card Interrupt + #1 + + + + + CARD_REMOVAL + Card Removal + 7 + 7 + read-write + + + value1 + Card State Stable or Debouncing + #0 + + + value2 + Card Removed + #1 + + + + + CARD_INS + Card Insertion + 6 + 6 + read-write + + + value1 + Card State Stable or Debouncing + #0 + + + value2 + Card Inserted + #1 + + + + + BUFF_READ_READY + Buffer Read Ready + 5 + 5 + read-write + + + value1 + Not Ready to read Buffer. + #0 + + + value2 + Ready to read Buffer. + #1 + + + + + BUFF_WRITE_READY + Buffer Write Ready + 4 + 4 + read-write + + + value1 + Not Ready to Write Buffer. + #0 + + + value2 + Ready to Write Buffer. + #1 + + + + + BLOCK_GAP_EVENT + Block Gap Event + 2 + 2 + read-write + + + value1 + No Block Gap Event + #0 + + + value2 + Transaction stopped at Block Gap + #1 + + + + + TX_COMPLETE + Transfer Complete + 1 + 1 + read-write + + + value1 + No Data Transfer Complete + #0 + + + value2 + Data Transfer Complete + #1 + + + + + CMD_COMPLETE + Command Complete + 0 + 0 + read-write + + + value1 + No Command Complete + #0 + + + value2 + Command Complete + #1 + + + + + + + INT_STATUS_ERR + Error Interrupt Status Register + 0x0032 + 16 + 0x0000 + 0xFFFF + + + CEATA_ERR + Ceata Error Status + 13 + 13 + read-write + + + value1 + no error + #0 + + + value2 + error + #1 + + + + + ACMD_ERR + Auto CMD Error + 8 + 8 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + CURRENT_LIMIT_ERR + Current Limit Error + 7 + 7 + read-write + + + value1 + No Error + #0 + + + value2 + Power Fail + #1 + + + + + DATA_END_BIT_ERR + Data End Bit Error + 6 + 6 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + DATA_CRC_ERR + Data CRC Error + 5 + 5 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + DATA_TIMEOUT_ERR + Data Timeout Error + 4 + 4 + read-write + + + value1 + No Error + #0 + + + value2 + Timeout + #1 + + + + + CMD_IND_ERR + Command Index Error + 3 + 3 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + CMD_END_BIT_ERR + Command End Bit Error + 2 + 2 + read-write + + + value1 + No Error + #0 + + + value2 + End Bit Error Generated + #1 + + + + + CMD_CRC_ERR + Command CRC Error + 1 + 1 + read-write + + + value1 + No Error + #0 + + + value2 + CRC Error Generated + #1 + + + + + CMD_TIMEOUT_ERR + Command Timeout Error + 0 + 0 + read-write + + + value1 + No Error + #0 + + + value2 + Timeout + #1 + + + + + + + EN_INT_STATUS_NORM + Normal Interrupt Status Enable Register + 0x0034 + 16 + 0x0000 + 0xFFFF + + + FIXED_TO_0 + Fixed to 0 + 15 + 15 + read-only + + + CARD_INT_EN + Card Interrupt Status Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_REMOVAL_EN + Card Removal Status Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_INS_EN + Card Insertion Status Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_READ_READY_EN + Buffer Read Ready Status Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_WRITE_READY_EN + Buffer Write Ready Status Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BLOCK_GAP_EVENT_EN + Block Gap Event Status Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TX_COMPLETE_EN + Transfer Complete Status Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_COMPLETE_EN + Command Complete Status Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + EN_INT_STATUS_ERR + Error Interrupt Status Enable Register + 0x0036 + 16 + 0x0000 + 0xFFFF + + + CEATA_ERR_EN + Ceata Error Status Enable + 13 + 13 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TARGET_RESP_ERR_EN + Target Response Error Status Enable + 12 + 12 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + ACMD_ERR_EN + Auto CMD12 Error Status Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CURRENT_LIMIT_ERR_EN + Current Limit Error Status Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_END_BIT_ERR_EN + Data End Bit Error Status Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_CRC_ERR_EN + Data CRC Error Status Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_TIMEOUT_ERR_EN + Data Timeout Error Status Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_IND_ERR_EN + Command Index Error Status Enable + 3 + 3 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_END_BIT_ERR_EN + Command End Bit Error Status Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_CRC_ERR_EN + Command CRC Error Status Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_TIMEOUT_ERR_EN + Command Timeout Error Status Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + EN_INT_SIGNAL_NORM + Normal Interrupt Signal Enable Register + 0x0038 + 16 + 0x0000 + 0xFFFF + + + FIXED_TO_0 + Fixed to 0 + 15 + 15 + read-only + + + CARD_INT_EN + Card Interrupt Signal Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_REMOVAL_EN + Card Removal Signal Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_INS_EN + Card Insertion Signal Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_READ_READY_EN + Buffer Read Ready Signal Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_WRITE_READY_EN + Buffer Write Ready Signal Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BLOCK_GAP_EVENT_EN + Block Gap Event Signal Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TX_COMPLETE_EN + Transfer Complete Signal Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_COMPLETE_EN + Command Complete Signal Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + EN_INT_SIGNAL_ERR + Error Interrupt Signal Enable Register + 0x003A + 16 + 0x0000 + 0xFFFF + + + CEATA_ERR_EN + Ceata Error Signal Enable + 13 + 13 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TARGET_RESP_ERR_EN + Target Response Error Signal Enable + 12 + 12 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + ACMD_ERR_EN + Auto CMD12 Error Signal Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CURRENT_LIMIT_ERR_EN + Current Limit Error Signal Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_END_BIT_ERR_EN + Data End Bit Error Signal Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_CRC_ERR_EN + Data CRC Error Signal Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_TIMEOUT_ERR_EN + Data Timeout Error Signal Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_IND_ERR_EN + Command Index Error Signal Enable + 3 + 3 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_END_BIT_ERR_EN + Command End Bit Error Signal Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_CRC_ERR_EN + Command CRC Error Signal Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_TIMEOUT_ERR_EN + Command Timeout Error Signal Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + ACMD_ERR_STATUS + Auto CMD Error Status Register + 0x003C + 16 + 0x0000 + 0xFFFF + + + CMD_NOT_ISSUED_BY_ACMD12_ERR + Command Not Issued By Auto CMD12 Error + 7 + 7 + read-only + + + value1 + No Error + #0 + + + value2 + Not Issued + #1 + + + + + ACMD_IND_ERR + Auto CMD Index Error + 4 + 4 + read-only + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + ACMD_END_BIT_ERR + Auto CMD End Bit Error + 3 + 3 + read-only + + + value1 + No Error + #0 + + + value2 + End Bit Error Generated + #1 + + + + + ACMD_CRC_ERR + Auto CMD CRC Error + 2 + 2 + read-only + + + value1 + No Error + #0 + + + value2 + CRC Error Generated + #1 + + + + + ACMD_TIMEOUT_ERR + Auto CMD Timeout Error + 1 + 1 + read-only + + + value1 + No Error + #0 + + + value2 + Timeout + #1 + + + + + ACMD12_NOT_EXEC_ERR + Auto CMD12 Not Executed + 0 + 0 + read-only + + + value1 + Executed + #0 + + + value2 + Not Executed + #1 + + + + + + + CAPABILITIES + Capabilities Register + 0x0040 + 32 + 0x01A030B0 + 0xFFFFFFFF + + + TIMEOUT_CLOCK_FREQ + Timeout Clock Frequency + 0 + 5 + read-only + + + value1 + 48 MHz + #110000 + + + + + TIMEOUT_CLOCK_UNIT + Timeout Clock Unit + 7 + 7 + read-only + + + value1 + MHz + #1 + + + + + BASE_SD_CLOCK_FREQ + Base Clock Frequency for SD Clock + 8 + 15 + read-only + + + value1 + 48 MHz + 0x30 + + + + + MAX_BLOCK_LENGTH + Max Block Length + 16 + 17 + read-only + + + value1 + 512 byte + #00 + + + + + EXT_MEDIA_BUS_SUPPORT + Extended Media Bus Support + 18 + 18 + read-only + + + value1 + Extended Media Bus not supported + #0 + + + + + ADMA2_SUPPORT + ADMA2 Support + 19 + 19 + read-only + + + value1 + ADMA not supported + #0 + + + + + HIGH_SPEED_SUPPORT + High Speed Support + 21 + 21 + read-only + + + value1 + High Speed supported + #1 + + + + + SDMA_SUPPORT + SDMA Support + 22 + 22 + read-only + + + value1 + SDMA not supported + #0 + + + + + SUSPEND_RESUME_SUPPORT + Suspend / Resume Support + 23 + 23 + read-only + + + value1 + Supported + #1 + + + + + VOLTAGE_SUPPORT_3_3V + Voltage Support 3.3V + 24 + 24 + read-only + + + value1 + 3.3V supported + #1 + + + + + VOLTAGE_SUPPORT_3V + Voltage Support 3.0V + 25 + 25 + read-only + + + value1 + 3.0V not supported + #0 + + + + + VOLTAGE_SUPPORT_1_8V + Voltage Support 1.8V + 26 + 26 + read-only + + + value1 + 1.8V not supported + #0 + + + + + SYSBUS_64_SUPPORT + 64-bit System Bus Support + 28 + 28 + read-only + + + value1 + Does not support 64-bit system address + #0 + + + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support + 29 + 29 + read-only + + + value1 + Asynchronous Interrupt not supported + #0 + + + + + SLOT_TYPE + Slot Type + 30 + 31 + read-only + + + value1 + Removable Card Slot + #00 + + + + + + + CAPABILITIES_HI + Capabilities Register High + 0x0044 + 32 + 0x03000000 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 Support + 0 + 0 + read-only + + + value1 + SDR50 is not supported + #0 + + + + + SDR104_SUPPORT + SDR104 Support + 1 + 1 + read-only + + + value1 + SDR104 is not supported + #0 + + + + + DDR50_SUPPORT + DDR50 Support + 2 + 2 + read-only + + + value1 + DDR50 is not supported + #0 + + + + + DRV_A_SUPPORT + Driver Type A Support + 4 + 4 + read-only + + + value1 + Driver Type A is not supported + #0 + + + + + DRV_C_SUPPORT + Driver Type C Support + 5 + 5 + read-only + + + value1 + Driver Type C is not supported + #0 + + + + + DRV_D_SUPPORT + Driver Type D Support + 6 + 6 + read-only + + + value1 + Driver Type D is not supported + #0 + + + + + TIM_CNT_RETUNE + Timer count for Re-Tuning + 8 + 11 + read-only + + + value1 + Get information via other source + 0x0 + + + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 13 + 13 + read-only + + + value1 + SDR50 does not require tuning + #0 + + + + + RE_TUNING_MODES + Re-tuning modes + 14 + 15 + read-only + + + value1 + Mode 1 + #00 + + + + + CLK_MULT + Clock Multiplier + 16 + 23 + read-only + + + value1 + Clock Multiplier not supported + 0x00 + + + + + + + MAX_CURRENT_CAP + Maximum Current Capabilities Register + 0x0048 + 32 + 0x00000001 + 0xFFFFFFFF + + + MAX_CURRENT_FOR_3_3V + Maximum Current for 3.3V + 0 + 7 + read-only + + + + + FORCE_EVENT_ACMD_ERR_STATUS + Force Event Register for Auto CMD Error Status + 0x0050 + 16 + 0x0000 + 0xFFFF + + + FE_CMD_NOT_ISSUED_ACMD12_ERR + Force Event for CMD not issued by Auto CMD12 Error + 7 + 7 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_IND_ERR + Force Event for Auto CMD Index Error + 4 + 4 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_END_BIT_ERR + Force Event for Auto CMD End bit Error + 3 + 3 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_CRC_ERR + Force Event for Auto CMD CRC Error + 2 + 2 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_TIMEOUT_ERR + Force Event for Auto CMD timeout Error + 1 + 1 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_NOT_EXEC + Force Event for Auto CMD12 NOT Executed + 0 + 0 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + + + FORCE_EVENT_ERR_STATUS + Force Event Register for Error Interrupt Status + 0x0052 + 16 + 0x0000 + 0xFFFF + + + FE_CEATA_ERR + Force Event for Ceata Error + 13 + 13 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_TARGET_RESPONSE_ERR + Force event for Target Response Error + 12 + 12 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD12_ERR + Force Event for Auto CMD Error + 8 + 8 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CURRENT_LIMIT_ERR + Force Event for Current Limit Error + 7 + 7 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_DATA_END_BIT_ERR + Force Event for Data End Bit Error + 6 + 6 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_DATA_CRC_ERR + Force Event for Data CRC Error + 5 + 5 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_DATA_TIMEOUT_ERR + Force Event for Data Timeout Error + 4 + 4 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_IND_ERR + Force Event for Command Index Error + 3 + 3 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_END_BIT_ERR + Force Event for Command End Bit Error + 2 + 2 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_CRC_ERR + Force Event for Command CRC Error + 1 + 1 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_TIMEOUT_ERR + Force Event for Command Timeout Error + 0 + 0 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + + + DEBUG_SEL + Debug Selection Register + 0x0074 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_SEL + Debug_sel + 0 + 0 + write-only + + + value1 + receiver module and fifo_ctrl module signals are probed out + #0 + + + value2 + cmd register, Interrupt status, transmitter module and clk sdcard signals are probed out. + #1 + + + + + + + SLOT_INT_STATUS + Slot Interrupt Status Register + 0x00FC + 16 + 0x0000 + 0xFFFF + + + SLOT_INT_STATUS + Interrupt Signal for Card Slot + 0 + 7 + read-only + + + value1 + Slot 1 + 0x00 + + + + + + + + + EBU + External Bus Unit + 0x58008000 + + 0x0 + 0x4000 + registers + + + + CLC + EBU Clock Control Register + 0x00 + 32 + 0x00110000 + 0xFFFFFFFF + + + DISR + EBU Disable Request Bit + 0 + 0 + read-write + + + value1 + EBU disable is not requested + #0 + + + value2 + EBU disable is requested + #1 + + + + + DISS + EBU Disable Status Bit + 1 + 1 + read-only + + + value1 + EBU is enabled (default after reset) + #0 + + + value2 + EBU is disabled + #1 + + + + + SYNC + EBU Clocking Mode + 16 + 16 + read-write + + + value1 + request EBU to run asynchronously to AHB bus clock and use separate clock source + #0 + + + value2 + request EBU to run synchronously to ARM processor (default after reset) + #1 + + + + + DIV2 + DIV2 Clocking Mode + 17 + 17 + read-write + + + value1 + standard clocking mode. clock input selected by SYNC bitfield (default after reset). + #0 + + + value2 + request EBU to run off AHB bus clock divided by 2. + #1 + + + + + EBUDIV + EBU Clock Divide Ratio + 18 + 19 + read-write + + + value1 + request EBU to run off input clock (default after reset) + #00 + + + value2 + request EBU to run off input clock divided by 2 + #01 + + + value3 + request EBU to run off input clock divided by 3 + #10 + + + value4 + request EBU to run off input clock divided by 4 + #11 + + + + + SYNCACK + EBU Clocking Mode Status + 20 + 20 + read-only + + + value1 + the EBU is asynchronous to the AHB bus clock and is using a separate clock source + #0 + + + value2 + EBU is synchronous to the AHB bus clock (default after reset) + #1 + + + + + DIV2ACK + DIV2 Clocking Mode Status + 21 + 21 + read-only + + + value1 + EBU is using standard clocking mode. clock input selected by SYNC bitfield (default after reset). + #0 + + + value2 + EBU is running off AHB bus clock divided by 2. + #1 + + + + + EBUDIVACK + EBU Clock Divide Ratio Status + 22 + 23 + read-only + + + value1 + EBU is running off input clock (default after reset) + #00 + + + value2 + EBU is running off input clock divided by 2 + #01 + + + value3 + EBU is running off input clock divided by 3 + #10 + + + value4 + EBU is running off input clock divided by 4 + #11 + + + + + + + MODCON + EBU Configuration Register + 0x04 + 32 + 0x00000020 + 0xFFFFFFFF + + + STS + Memory Status Bit + 0 + 0 + read-only + + + LCKABRT + Lock Abort + 1 + 1 + read-only + + + SDTRI + SDRAM Tristate + 2 + 2 + read-write + + + value1 + SDRAM control signals are driven by the EBU when the EBU does not own the external bus. SDRAM cannot be shared. + #0 + + + value2 + SDRAM control signals are tri-stated by the EBU when the EBU does not own the external bus. The SDRAM can be shared. + #1 + + + + + EXTLOCK + External Bus Lock Control + 4 + 4 + read-write + + + value1 + External bus is not locked after the EBU gains ownership + #0 + + + value2 + External bus is locked after the EBU gains ownership + #1 + + + + + ARBSYNC + Arbitration Signal Synchronization Control + 5 + 5 + read-write + + + value1 + Arbitration inputs are synchronous + #0 + + + value2 + Arbitration inputs are asynchronous + #1 + + + + + ARBMODE + Arbitration Mode Selection + 6 + 7 + read-write + + + value1 + No Bus arbitration mode selected + #00 + + + value2 + Arbiter Mode arbitration mode selected + #01 + + + value3 + Participant arbitration mode selected + #10 + + + value4 + Sole Master arbitration mode selected + #11 + + + + + TIMEOUTC + Bus Time-out Control + 8 + 15 + read-write + + + value1 + Time-out is disabled. + 0x00 + + + value2 + Time-out is generated after 1 8 clock cycles. + 0x01 + + + value3 + Time-out is generated after 255 8 clock cycles. + 0xFF + + + + + LOCKTIMEOUT + Lock Timeout Counter Preload + 16 + 23 + read-write + + + GLOBALCS + Global Chip Select Enable + 24 + 27 + read-write + + + ACCSINH + Access Inhibit request + 28 + 28 + read-write + + + ACCSINHACK + Access inhibit acknowledge + 29 + 29 + read-only + + + ALE + ALE Mode + 31 + 31 + read-write + + + value1 + Output is ADV + #0 + + + value2 + Output is ALE + #1 + + + + + + + ID + EBU Module Identification Register + 0x08 + 32 + 0x0014C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + USERCON + EBU Test/Control Configuration Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + DIP + Disable Internal Pipelining + 0 + 0 + read-write + + + ADDIO + Address Pins to GPIO Mode + 16 + 24 + read-write + + + value1 + Address Bit is required for addressing memory + #0 + + + value2 + Address Bit is available for GPIO function + #1 + + + + + ADVIO + ADV Pin to GPIO Mode + 25 + 25 + read-write + + + value1 + ADV pin is required for controlling memory + #0 + + + value2 + ADV pin is available for GPIO function + #1 + + + + + + + ADDRSEL0 + EBU Address Select Register 0 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + ADDRSEL1 + EBU Address Select Register 1 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + ADDRSEL2 + EBU Address Select Register 2 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + ADDRSEL3 + EBU Address Select Register 3 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + BUSRCON0 + EBU Bus Configuration Register + 0x28 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP0 + EBU Bus Read Access Parameter Register + 0x2C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON0 + EBU Bus Write Configuration Register + 0x30 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP0 + EBU Bus Write Access Parameter Register + 0x34 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSRCON1 + EBU Bus Configuration Register + 0x38 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP1 + EBU Bus Read Access Parameter Register + 0x3C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON1 + EBU Bus Write Configuration Register + 0x40 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP1 + EBU Bus Write Access Parameter Register + 0x44 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSRCON2 + EBU Bus Configuration Register + 0x48 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP2 + EBU Bus Read Access Parameter Register + 0x4C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON2 + EBU Bus Write Configuration Register + 0x50 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP2 + EBU Bus Write Access Parameter Register + 0x54 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSRCON3 + EBU Bus Configuration Register + 0x58 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP3 + EBU Bus Read Access Parameter Register + 0x5C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON3 + EBU Bus Write Configuration Register + 0x60 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP3 + EBU Bus Write Access Parameter Register + 0x64 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + SDRMCON + EBU SDRAM Control Register + 0x68 + 32 + 0x80000000 + 0xFFFFFFFF + + + SDCMSEL + SDRAM clock mode select + 31 + 31 + read-write + + + value1 + clock disabled between accesses + #1 + + + value2 + clock continuously runs + #0 + + + + + PWR_MODE + Power Save Mode used for gated clock mode + 29 + 30 + read-write + + + value1 + precharge before clock stop (default after reset) + 0x0 + + + value2 + auto-precharge before clock stop + 0x1 + + + value3 + active power down (stop clock without precharge) + 0x2 + + + value4 + clock stop power down + 0x3 + + + + + CLKDIS + Disable SDRAM clock output + 28 + 28 + read-write + + + value1 + clock enabled + #0 + + + value2 + clock disabled + #1 + + + + + CRCE + Row cycle time counter extension + 25 + 27 + read-write + + + BANKM + Mask for bank tag + 22 + 24 + read-write + + + value2 + Address bit 21 to 20 + 0x1 + + + value3 + Address bit 22 to 21 + 0x2 + + + value4 + Address bit 23 to 22 + 0x3 + + + value5 + Address bit 24 to 23 + 0x4 + + + value6 + Address bit 25 to 24 + 0x5 + + + value7 + Address bit 26 to 25 + 0x6 + + + value8 + Address bit 26 + 0x7 + + + + + ROWM + Mask for row tag + 19 + 21 + read-write + + + value2 + Address bit 26 to 9 + 0x1 + + + value3 + Address bit 26 to 10 + 0x2 + + + value4 + Address bit 26 to 11 + 0x3 + + + value5 + Address bit 26 to 12 + 0x4 + + + value6 + Address bit 26 to 13 + 0x5 + + + + + CRC + Row cycle time counter + 16 + 18 + read-write + + + CRCD + Row to column delay counter + 14 + 15 + read-write + + + AWIDTH + Width of column address + 12 + 13 + read-write + + + value1 + do not use + 0x0 + + + value2 + Address(8:0) + 0x1 + + + value3 + Address(9:0) + 0x2 + + + value4 + Address(10:0) + 0x3 + + + + + CRP + Row precharge time counter + 10 + 11 + read-write + + + CRSC + Mode register set-up time + 8 + 9 + read-write + + + CRFSH + Initialization refresh commands counter + 4 + 7 + read-write + + + CRAS + Row to precharge delay counter + 0 + 3 + read-write + + + + + SDRMOD + EBU SDRAM Mode Register + 0x6C + 32 + 0x00000020 + 0xFFFFFFFF + + + XBA + Extended Operation Bank Select + 28 + 31 + read-write + + + XOPM + Extended Operation Mode + 16 + 27 + read-write + + + COLDSTART + SDRAM coldstart + 15 + 15 + write-only + + + OPMODE + Operation Mode + 7 + 13 + read-write + + + value1 + Only this value must be written (default after reset) + #000000 + + + + + CASLAT + CAS latency + 4 + 6 + read-write + + + value1 + Two clocks (default after reset) + 2 + + + value2 + Three clocks + 3 + + + + + BTYP + Burst type + 3 + 3 + read-write + + + value1 + Only this value should be written (default after reset) + #0 + + + + + BURSTL + Burst length + 0 + 2 + read-write + + + value1 + 1 (default after reset) + 0 + + + value2 + 2 + 1 + + + value3 + 4 + 2 + + + value4 + 8 + 3 + + + value5 + 16 + 4 + + + + + + + SDRMREF + EBU SDRAM Refresh Control Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + RES_DLY + Delay on Power Down Exit + 25 + 27 + read-write + + + ARFSH + Auto Refresh on Self refresh Exit + 24 + 24 + read-write + + + SELFREX_DLY + Self Refresh Exit Delay + 16 + 23 + read-write + + + ERFSHC + Extended Refresh Counter Period + 14 + 15 + read-write + + + AUTOSELFR + Automatic Self Refresh + 13 + 13 + read-write + + + SELFREN + Self Refresh Entry + 12 + 12 + read-write + + + SELFRENST + Self Refresh Entry Status. + 11 + 11 + read-only + + + SELFREX + Self Refresh Exit (Power Up). + 10 + 10 + read-write + + + SELFREXST + Self Refresh Exit Status. + 9 + 9 + read-only + + + REFRESHR + Number of refresh commands + 6 + 8 + read-write + + + REFRESHC + Refresh counter period + 0 + 5 + read-write + + + + + SDRSTAT + EBU SDRAM Status Register + 0x74 + 32 + 0x00010000 + 0xFFFFFFFF + + + SDERR + SDRAM read error + 2 + 2 + read-only + + + value1 + Reads running successfully + #0 + + + value2 + Read error condition has been detected + #1 + + + + + SDRMBUSY + SDRAM Busy + 1 + 1 + read-only + + + value1 + Power-up initialization sequence is not running + #0 + + + value2 + Power-up initialization sequence is running + #1 + + + + + REFERR + SDRAM Refresh Error + 0 + 0 + read-only + + + value1 + No refresh error. + #0 + + + value2 + Refresh error occurred. + #1 + + + + + + + + + ETH0_CON + Ethernet Control Register + ETH + 0x50004040 + + 0 + 4 + registers + + + + ETH0_CON + Ethernet 0 Port Control Register + 0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXD0 + MAC Receive Input 0 + 0 + 1 + read-write + + + value1 + Data input RXD0A is selected + #00 + + + value2 + Data input RXD0B is selected + #01 + + + value3 + Data input RXD0C is selected + #10 + + + value4 + Data input RXD0D is selected + #11 + + + + + RXD1 + MAC Receive Input 1 + 2 + 3 + read-write + + + value1 + Data input RXD1A is selected + #00 + + + value2 + Data input RXD1B is selected + #01 + + + value3 + Data input RXD1C is selected + #10 + + + value4 + Data input RXD1D is selected + #11 + + + + + RXD2 + MAC Receive Input 2 + 4 + 5 + read-write + + + value1 + Data input RXD2A is selected + #00 + + + value2 + Data input RXD2B is selected + #01 + + + value3 + Data input RXD2C is selected + #10 + + + value4 + Data input RXD2D is selected + #11 + + + + + RXD3 + MAC Receive Input 3 + 6 + 7 + read-write + + + value1 + Data input RXD3A is selected + #00 + + + value2 + Data input RXD3B is selected + #01 + + + value3 + Data input RXD3C is selected + #10 + + + value4 + Data input RXD3D is selected + #11 + + + + + CLK_RMII + RMII clock input + 8 + 9 + read-write + + + value1 + Data input RMIIA is selected + #00 + + + value2 + Data input RMIIB is selected + #01 + + + value3 + Data input RMIIC is selected + #10 + + + value4 + Data input RMIID is selected + #11 + + + + + CRS_DV + CRS_DV input + 10 + 11 + read-write + + + value1 + Data input CRS_DVA is selected + #00 + + + value2 + Data input CRS_DVB is selected + #01 + + + value3 + Data input CRS_DVC is selected + #10 + + + value4 + Data input CRS_DVD is selected + #11 + + + + + CRS + CRS input + 12 + 13 + read-write + + + value1 + Data input CRSA + #00 + + + value2 + Data input CRSB + #01 + + + value3 + Data input CRSC + #10 + + + value4 + Data input CRSD + #11 + + + + + RXER + RXER Input + 14 + 15 + read-write + + + value1 + Data input RXERA is selected + #00 + + + value2 + Data input RXERB is selected + #01 + + + value3 + Data input RXERC is selected + #10 + + + value4 + Data input RXERD is selected + #11 + + + + + COL + COL input + 16 + 17 + read-write + + + value1 + Data input COLA is selected + #00 + + + value2 + Data input COLB is selected + #01 + + + value3 + Data input COLC is selected + #10 + + + value4 + Data input COLD is selected + #11 + + + + + CLK_TX + CLK_TX input + 18 + 19 + read-write + + + value1 + Data input CLK_TXA is selected + #00 + + + value2 + Data input CLK_TXB is selected + #01 + + + value3 + Data input CLK_TXC is selected + #10 + + + value4 + Data input CLK_TXD is selected + #11 + + + + + MDIO + MDIO Input Select + 22 + 23 + read-write + + + value1 + Data input MDIA is selected + #00 + + + value2 + Data input MDIB is selected + #01 + + + value3 + Data input MDIC is selected + #10 + + + value4 + Data input MDID is selected + #11 + + + + + INFSEL + Ethernet MAC Interface Selection + 26 + 26 + read-write + + + value1 + MII + #0 + + + value2 + RMII + #1 + + + + + + + + + ETH0 + Ethernet Unit 0 + ETH + ETH + 0x5000C000 + + 0x0 + 0x4000 + registers + + + ETH0_0 + Ethernet (Module 0) + 108 + + + + MAC_CONFIGURATION + MAC Configuration Register + 0x0000 + 32 + 0x00008000 + 0xFFFFFFFF + + + PRELEN + Preamble Length for Transmit Frames + 0 + 1 + read-write + + + RE + Receiver Enable + 2 + 2 + read-write + + + TE + Transmitter Enable + 3 + 3 + read-write + + + DC + Deferral Check + 4 + 4 + read-write + + + BL + Back-Off Limit + 5 + 6 + read-write + + + ACS + Automatic Pad or CRC Stripping + 7 + 7 + read-write + + + DR + Disable Retry + 9 + 9 + read-write + + + IPC + Checksum Offload + 10 + 10 + read-write + + + DM + Duplex Mode + 11 + 11 + read-write + + + LM + Loopback Mode + 12 + 12 + read-write + + + DO + Disable Receive Own + 13 + 13 + read-write + + + FES + Speed + 14 + 14 + read-write + + + DCRS + Disable Carrier Sense During Transmission + 16 + 16 + read-write + + + IFG + Inter-Frame Gap + 17 + 19 + read-write + + + JE + Jumbo Frame Enable + 20 + 20 + read-write + + + BE + Frame Burst Enable + 21 + 21 + read-only + + + JD + Jabber Disable + 22 + 22 + read-write + + + WD + Watchdog Disable + 23 + 23 + read-write + + + TC + Transmit Configuration in RMII + 24 + 24 + read-only + + + CST + CRC Stripping of Type Frames + 25 + 25 + read-write + + + TWOKPE + IEEE 802.3as support for 2K packets Enable + 27 + 27 + read-write + + + SARC + Source Address Insertion or Replacement Control + 28 + 30 + read-only + + + + + MAC_FRAME_FILTER + MAC Frame Filter + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + PR + Promiscuous Mode + 0 + 0 + read-write + + + HUC + Hash Unicast + 1 + 1 + read-write + + + HMC + Hash Multicast + 2 + 2 + read-write + + + DAIF + DA Inverse Filtering + 3 + 3 + read-write + + + PM + Pass All Multicast + 4 + 4 + read-write + + + DBF + Disable Broadcast Frames + 5 + 5 + read-write + + + PCF + Pass Control Frames + 6 + 7 + read-write + + + SAIF + SA Inverse Filtering + 8 + 8 + read-write + + + SAF + Source Address Filter Enable + 9 + 9 + read-write + + + HPF + Hash or Perfect Filter + 10 + 10 + read-write + + + VTFE + VLAN Tag Filter Enable + 16 + 16 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + 20 + 20 + read-only + + + DNTU + Drop non-TCP/UDP over IP Frames + 21 + 21 + read-only + + + RA + Receive All + 31 + 31 + read-write + + + + + HASH_TABLE_HIGH + Hash Table High Register + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + 0 + 31 + read-write + + + + + HASH_TABLE_LOW + Hash Table Low Register + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + 0 + 31 + read-write + + + + + GMII_ADDRESS + MII Address Register + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + MB + MII Busy + 0 + 0 + read-write + + + MW + MII Write + 1 + 1 + read-write + + + CR + CSR Clock Range + 2 + 5 + read-write + + + MR + MII Register + 6 + 10 + read-write + + + PA + Physical Layer Address + 11 + 15 + read-write + + + + + GMII_DATA + MII Data Register + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + MD + MII Data + 0 + 15 + read-write + + + + + FLOW_CONTROL + Flow Control Register + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + FCA_BPA + Flow Control Busy or Backpressure Activate + 0 + 0 + read-write + + + TFE + Transmit Flow Control Enable + 1 + 1 + read-write + + + RFE + Receive Flow Control Enable + 2 + 2 + read-write + + + UP + Unicast Pause Frame Detect + 3 + 3 + read-write + + + PLT + Pause Low Threshold + 4 + 5 + read-write + + + DZPQ + Disable Zero-Quanta Pause + 7 + 7 + read-write + + + PT + Pause Time + 16 + 31 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + VL + VLAN Tag Identifier for Receive Frames + 0 + 15 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + 16 + 16 + read-write + + + VTIM + VLAN Tag Inverse Match Enable + 17 + 17 + read-write + + + ESVL + Enable S-VLAN + 18 + 18 + read-write + + + VTHM + VLAN Tag Hash Table Match Enable + 19 + 19 + read-only + + + + + VERSION + Version Register + 0x0020 + 32 + 0x00001037 + 0xFFFFFFFF + + + SNPSVER + Synopsys-defined Version (3.7) + 0 + 7 + read-only + + + USERVER + User-defined Version (Configured with the coreConsultant) + 8 + 15 + read-only + + + + + DEBUG + Debug Register + 0x0024 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPESTS + MAC MII Receive Protocol Engine Status + 0 + 0 + read-only + + + RFCFCSTS + MAC Receive Frame Controller FIFO Status + 1 + 2 + read-only + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + 4 + 4 + read-only + + + RRCSTS + MTL Rx FIFO Read Controller State + 5 + 6 + read-only + + + RXFSTS + MTL Rx FIFO Fill-level Status + 8 + 9 + read-only + + + TPESTS + MAC MII Transmit Protocol Engine Status + 16 + 16 + read-only + + + TFCSTS + MAC Transmit Frame Controller Status + 17 + 18 + read-only + + + TXPAUSED + MAC transmitter in PAUSE + 19 + 19 + read-only + + + TRCSTS + MTL Tx FIFO Read Controller Status + 20 + 21 + read-only + + + TWCSTS + MTL Tx FIFO Write Controller Active Status + 22 + 22 + read-only + + + TXFSTS + MTL Tx FIFO Not Empty Status + 24 + 24 + read-only + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + 25 + 25 + read-only + + + + + REMOTE_WAKE_UP_FRAME_FILTER + Remote Wake Up Frame Filter Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFTR + Remote Wake-Up Frame Filter + 0 + 31 + read-write + + + + + PMT_CONTROL_STATUS + PMT Control and Status Register + 0x002C + 32 + 0x00000000 + 0xFFFFFFFF + + + PWRDWN + Power Down + 0 + 0 + read-write + + + MGKPKTEN + Magic Packet Enable + 1 + 1 + read-write + + + RWKPKTEN + Wake-Up Frame Enable + 2 + 2 + read-write + + + MGKPRCVD + Magic Packet Received + 5 + 5 + read-only + + + RWKPRCVD + Wake-Up Frame Received + 6 + 6 + read-only + + + GLBLUCAST + Global Unicast + 9 + 9 + read-write + + + RWKFILTRST + Wake-Up Frame Filter Register Pointer Reset + 31 + 31 + read-write + + + + + INTERRUPT_STATUS + Interrupt Register + 0x0038 + 32 + 0x00000000 + 0xFFFFFFFF + + + PMTIS + PMT Interrupt Status + 3 + 3 + read-only + + + MMCIS + MMC Interrupt Status + 4 + 4 + read-only + + + MMCRXIS + MMC Receive Interrupt Status + 5 + 5 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status + 6 + 6 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status + 7 + 7 + read-only + + + TSIS + Timestamp Interrupt Status + 9 + 9 + read-only + + + + + INTERRUPT_MASK + Interrupt Mask Register + 0x003C + 32 + 0x00000000 + 0xFFFFFFFF + + + PMTIM + PMT Interrupt Mask + 3 + 3 + read-write + + + TSIM + Timestamp Interrupt Mask + 9 + 9 + read-write + + + + + MAC_ADDRESS0_HIGH + MAC Address0 High Register + 0x0040 + 32 + 0x8000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address0 [47:32] + 0 + 15 + read-write + + + AE + Address Enable + 31 + 31 + read-only + + + + + MAC_ADDRESS0_LOW + MAC Address0 Low Register + 0x0044 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + 0 + 31 + read-write + + + + + MAC_ADDRESS1_HIGH + MAC Address1 High Register + 0x0048 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address1 [47:32] + 0 + 15 + read-write + + + MBC + Mask Byte Control + 24 + 29 + read-write + + + SA + Source Address + 30 + 30 + read-write + + + AE + Address Enable + 31 + 31 + read-write + + + + + MAC_ADDRESS1_LOW + MAC Address1 Low Register + 0x004C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] + 0 + 31 + read-write + + + + + MAC_ADDRESS2_HIGH + MAC Address2 High Register + 0x0050 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address2 [47:32] + 0 + 15 + read-write + + + MBC + Mask Byte Control + 24 + 29 + read-write + + + SA + Source Address + 30 + 30 + read-write + + + AE + Address Enable + 31 + 31 + read-write + + + + + MAC_ADDRESS2_LOW + MAC Address2 Low Register + 0x0054 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address2 [31:0] + 0 + 31 + read-write + + + + + MAC_ADDRESS3_HIGH + MAC Address3 High Register + 0x0058 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address3 [47:32] + 0 + 15 + read-write + + + MBC + Mask Byte Control + 24 + 29 + read-write + + + SA + Source Address + 30 + 30 + read-write + + + AE + Address Enable + 31 + 31 + read-write + + + + + MAC_ADDRESS3_LOW + MAC Address3 Low Register + 0x005C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address3 [31:0] + 0 + 31 + read-write + + + + + MMC_CONTROL + MMC Control Register + 0x0100 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTRST + Counters Reset + 0 + 0 + read-write + + + CNTSTOPRO + Counters Stop Rollover + 1 + 1 + read-write + + + RSTONRD + Reset on Read + 2 + 2 + read-write + + + CNTFREEZ + MMC Counter Freeze + 3 + 3 + read-write + + + CNTPRST + Counters Preset + 4 + 4 + read-write + + + CNTPRSTLVL + Full-Half Preset + 5 + 5 + read-write + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames + 8 + 8 + read-write + + + + + MMC_RECEIVE_INTERRUPT + MMC Receive Interrupt Register + 0x0104 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status + 0 + 0 + read-only + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status + 1 + 1 + read-only + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status. + 2 + 2 + read-only + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status. + 3 + 3 + read-only + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status + 4 + 4 + read-only + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status + 5 + 5 + read-only + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status + 6 + 6 + read-only + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status + 7 + 7 + read-only + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status + 8 + 8 + read-only + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status + 9 + 9 + read-only + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status + 10 + 10 + read-only + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + 11 + 11 + read-only + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + 12 + 12 + read-only + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + 13 + 13 + read-only + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + 14 + 14 + read-only + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + 15 + 15 + read-only + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + 16 + 16 + read-only + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status + 17 + 17 + read-only + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status + 18 + 18 + read-only + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status + 19 + 19 + read-only + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status + 20 + 20 + read-only + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status + 21 + 21 + read-only + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status + 22 + 22 + read-only + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status + 23 + 23 + read-only + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status + 24 + 24 + read-only + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status + 25 + 25 + read-only + + + + + MMC_TRANSMIT_INTERRUPT + MMC Transmit Interrupt Register + 0x0108 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status + 0 + 0 + read-only + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status + 1 + 1 + read-only + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status + 2 + 2 + read-only + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status + 3 + 3 + read-only + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. + 4 + 4 + read-only + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + 5 + 5 + read-only + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + 6 + 6 + read-only + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + 7 + 7 + read-only + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + 8 + 8 + read-only + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + 9 + 9 + read-only + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + 10 + 10 + read-only + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + 11 + 11 + read-only + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + 12 + 12 + read-only + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status + 13 + 13 + read-only + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status + 14 + 14 + read-only + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + 15 + 15 + read-only + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status + 16 + 16 + read-only + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status + 17 + 17 + read-only + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status + 18 + 18 + read-only + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status + 19 + 19 + read-only + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status + 20 + 20 + read-only + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status + 21 + 21 + read-only + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status + 22 + 22 + read-only + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status + 23 + 23 + read-only + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status + 24 + 24 + read-only + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status + 25 + 25 + read-only + + + + + MMC_RECEIVE_INTERRUPT_MASK + MMC Reveive Interrupt Mask Register + 0x010C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXGBFRMIM + MMC Receive Good Bad Frame Counter Interrupt Mask + 0 + 0 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask + 1 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask + 2 + 2 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask + 3 + 3 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask + 4 + 4 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask + 5 + 5 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask + 6 + 6 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask + 7 + 7 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask + 8 + 8 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask + 9 + 9 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask + 10 + 10 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + 11 + 11 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + 12 + 12 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + 13 + 13 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + 14 + 14 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + 15 + 15 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + 16 + 16 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask + 17 + 17 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask + 18 + 18 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask + 19 + 19 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask + 20 + 20 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask + 21 + 21 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + 22 + 22 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask + 23 + 23 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask + 24 + 24 + read-write + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask + 25 + 25 + read-write + + + + + MMC_TRANSMIT_INTERRUPT_MASK + MMC Transmit Interrupt Mask Register + 0x0110 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask + 0 + 0 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask + 1 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask + 2 + 2 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask + 3 + 3 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + 4 + 4 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + 5 + 5 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + 6 + 6 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + 7 + 7 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + 8 + 8 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + 9 + 9 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + 10 + 10 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + 11 + 11 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + 12 + 12 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask + 13 + 13 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask + 14 + 14 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + 15 + 15 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask + 16 + 16 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask + 17 + 17 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask + 18 + 18 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask + 19 + 19 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask + 20 + 20 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask + 21 + 21 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + 22 + 22 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask + 23 + 23 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask + 24 + 24 + read-write + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask + 25 + 25 + read-write + + + + + TX_OCTET_COUNT_GOOD_BAD + Transmit Octet Count for Good and Bad Frames Register + 0x0114 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXOCTGB + This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes. + 0 + 31 + read-only + + + + + TX_FRAME_COUNT_GOOD_BAD + Transmit Frame Count for Goodand Bad Frames Register + 0x0118 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFRMGB + This field indicates the number of good and bad frames transmitted, exclusive of retried frames + 0 + 31 + read-only + + + + + TX_BROADCAST_FRAMES_GOOD + Transmit Frame Count for Good Broadcast Frames + 0x011C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXBCASTG + This field indicates the number of transmitted good broadcast frames. + 0 + 31 + read-only + + + + + TX_MULTICAST_FRAMES_GOOD + Transmit Frame Count for Good Multicast Frames + 0x0120 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXMCASTG + This field indicates the number of transmitted good multicast frames. + 0 + 31 + read-only + + + + + TX_64OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 64 Byte Frames + 0x0124 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX64OCTGB + This field indicates the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_65TO127OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames + 0x0128 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX65_127OCTGB + This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_128TO255OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames + 0x012C + 32 + 0x00000000 + 0xFFFFFFFF + + + TX128_255OCTGB + This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_256TO511OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames + 0x0130 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX256_511OCTGB + This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_512TO1023OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames + 0x0134 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX512_1023OCTGB + This field indicates the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames + 0x0138 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX1024_MAXOCTGB + This field indicates the number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_UNICAST_FRAMES_GOOD_BAD + Transmit Frame Count for Good and Bad Unicast Frames + 0x013C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXUCASTGB + This field indicates the number of transmitted good and bad unicast frames. + 0 + 31 + read-only + + + + + TX_MULTICAST_FRAMES_GOOD_BAD + Transmit Frame Count for Good and Bad Multicast Frames + 0x0140 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXMCASTGB + This field indicates the number of transmitted good and bad multicast frames. + 0 + 31 + read-only + + + + + TX_BROADCAST_FRAMES_GOOD_BAD + Transmit Frame Count for Good and Bad Broadcast Frames + 0x0144 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXBCASTGB + This field indicates the number of transmitted good and bad broadcast frames. + 0 + 31 + read-only + + + + + TX_UNDERFLOW_ERROR_FRAMES + Transmit Frame Count for Underflow Error Frames + 0x0148 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXUNDRFLW + This field indicates the number of frames aborted because of frame underflow error. + 0 + 31 + read-only + + + + + TX_SINGLE_COLLISION_GOOD_FRAMES + Transmit Frame Count for Frames Transmitted after Single Collision + 0x014C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXSNGLCOLG + This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode. + 0 + 31 + read-only + + + + + TX_MULTIPLE_COLLISION_GOOD_FRAMES + Transmit Frame Count for Frames Transmitted after Multiple Collision + 0x0150 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXMULTCOLG + This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode. + 0 + 31 + read-only + + + + + TX_DEFERRED_FRAMES + Tx Deferred Frames Register + 0x0154 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXDEFRD + This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode. + 0 + 31 + read-only + + + + + TX_LATE_COLLISION_FRAMES + Transmit Frame Count for Late Collision Error Frames + 0x0158 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXLATECOL + This field indicates the number of frames aborted because of late collision error. + 0 + 31 + read-only + + + + + TX_EXCESSIVE_COLLISION_FRAMES + Transmit Frame Count for Excessive Collision Error Frames + 0x015C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXEXSCOL + This field indicates the number of frames aborted because of excessive (16) collision error. + 0 + 31 + read-only + + + + + TX_CARRIER_ERROR_FRAMES + Transmit Frame Count for Carrier Sense Error Frames + 0x0160 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXCARR + This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier). + 0 + 31 + read-only + + + + + TX_OCTET_COUNT_GOOD + Tx Octet Count Good Register + 0x0164 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXOCTG + This field indicates the number of bytes transmitted, exclusive of preamble, in good frames. + 0 + 31 + read-only + + + + + TX_FRAME_COUNT_GOOD + Tx Frame Count Good Register + 0x0168 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFRMG + This field indicates the number of transmitted good frames, exclusive of preamble. + 0 + 31 + read-only + + + + + TX_EXCESSIVE_DEFERRAL_ERROR + Transmit Frame Count for Excessive Deferral Error Frames + 0x016C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXEXSDEF + This field indicates the number of frames aborted because of excessive deferral error, that is, frames deferred for more than two max-sized frame times. + 0 + 31 + read-only + + + + + TX_PAUSE_FRAMES + Transmit Frame Count for Good PAUSE Frames + 0x0170 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXPAUSE + This field indicates the number of transmitted good PAUSE frames. + 0 + 31 + read-only + + + + + TX_VLAN_FRAMES_GOOD + Transmit Frame Count for Good VLAN Frames + 0x0174 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXVLANG + This register maintains the number of transmitted good VLAN frames, exclusive of retried frames. + 0 + 31 + read-only + + + + + TX_OSIZE_FRAMES_GOOD + Transmit Frame Count for Good Oversize Frames + 0x0178 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXOSIZG + This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled by setting MAC Configuration.2KPE). + 0 + 31 + read-only + + + + + RX_FRAMES_COUNT_GOOD_BAD + Receive Frame Count for Good and Bad Frames + 0x0180 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFRMGB + This field indicates the number of received good and bad frames. + 0 + 31 + read-only + + + + + RX_OCTET_COUNT_GOOD_BAD + Receive Octet Count for Good and Bad Frames + 0x0184 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOCTGB + This field indicates the number of bytes received, exclusive of preamble, in good and bad frames. + 0 + 31 + read-only + + + + + RX_OCTET_COUNT_GOOD + Rx Octet Count Good Register + 0x0188 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOCTG + This field indicates the number of bytes received, exclusive of preamble, only in good frames. + 0 + 31 + read-only + + + + + RX_BROADCAST_FRAMES_GOOD + Receive Frame Count for Good Broadcast Frames + 0x018C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXBCASTG + This field indicates the number of received good broadcast frames. + 0 + 31 + read-only + + + + + RX_MULTICAST_FRAMES_GOOD + Receive Frame Count for Good Multicast Frames + 0x0190 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXMCASTG + This field indicates the number of received good multicast frames. + 0 + 31 + read-only + + + + + RX_CRC_ERROR_FRAMES + Receive Frame Count for CRC Error Frames + 0x0194 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXCRCERR + This field indicates the number of frames received with CRC error. + 0 + 31 + read-only + + + + + RX_ALIGNMENT_ERROR_FRAMES + Receive Frame Count for Alignment Error Frames + 0x0198 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXALGNERR + This field indicates the number of frames received with alignment (dribble) error. + 0 + 31 + read-only + + + + + RX_RUNT_ERROR_FRAMES + Receive Frame Count for Runt Error Frames + 0x019C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXRUNTERR + This field indicates the number of frames received with runt error(<64 bytes and CRC error). + 0 + 31 + read-only + + + + + RX_JABBER_ERROR_FRAMES + Receive Frame Count for Jabber Error Frames + 0x01A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXJABERR + This field indicates the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. + 0 + 31 + read-only + + + + + RX_UNDERSIZE_FRAMES_GOOD + Receive Frame Count for Undersize Frames + 0x01A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUNDERSZG + This field indicates the number of frames received with length less than 64 bytes and without errors. + 0 + 31 + read-only + + + + + RX_OVERSIZE_FRAMES_GOOD + Rx Oversize Frames Good Register + 0x01A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOVERSZG + This field indicates the number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled by setting MAC Configuration.2KPE). + 0 + 31 + read-only + + + + + RX_64OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 64 Byte Frames + 0x01AC + 32 + 0x00000000 + 0xFFFFFFFF + + + RX64OCTGB + This field indicates the number of received good and bad frames with length 64 bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_65TO127OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 65 to 127 Bytes Frames + 0x01B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX65_127OCTGB + This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_128TO255OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 128 to 255 Bytes Frames + 0x01B4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX128_255OCTGB + This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_256TO511OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 256 to 511 Bytes Frames + 0x01B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX256_511OCTGB + This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_512TO1023OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames + 0x01BC + 32 + 0x00000000 + 0xFFFFFFFF + + + RX512_1023OCTGB + This field indicates the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX1024_MAXOCTGB + This field indicates the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + RX_UNICAST_FRAMES_GOOD + Receive Frame Count for Good Unicast Frames + 0x01C4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUCASTG + This field indicates the number of received good unicast frames. + 0 + 31 + read-only + + + + + RX_LENGTH_ERROR_FRAMES + Receive Frame Count for Length Error Frames + 0x01C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXLENERR + This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field. + 0 + 31 + read-only + + + + + RX_OUT_OF_RANGE_TYPE_FRAMES + Receive Frame Count for Out of Range Frames + 0x01CC + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOUTOFRNG + This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). + 0 + 31 + read-only + + + + + RX_PAUSE_FRAMES + Receive Frame Count for PAUSE Frames + 0x01D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXPAUSEFRM + This field indicates the number of received good and valid PAUSE frames. + 0 + 31 + read-only + + + + + RX_FIFO_OVERFLOW_FRAMES + Receive Frame Count for FIFO Overflow Frames + 0x01D4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFOOVFL + This field indicates the number of received frames missed because of FIFO overflow. + 0 + 31 + read-only + + + + + RX_VLAN_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad VLAN Frames + 0x01D8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXVLANFRGB + This field indicates the number of received good and bad VLAN frames. + 0 + 31 + read-only + + + + + RX_WATCHDOG_ERROR_FRAMES + Receive Frame Count for Watchdog Error Frames + 0x01DC + 32 + 0x00000000 + 0xFFFFFFFF + + + RXWDGERR + This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). + 0 + 31 + read-only + + + + + RX_RECEIVE_ERROR_FRAMES + Receive Frame Count for Receive Error Frames + 0x01E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXRCVERR + This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). + 0 + 31 + read-only + + + + + RX_CONTROL_FRAMES_GOOD + Receive Frame Count for Good Control Frames Frames + 0x01E4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXCTRLG + This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). + 0 + 31 + read-only + + + + + MMC_IPC_RECEIVE_INTERRUPT_MASK + MMC Receive Checksum Offload Interrupt Mask Register + 0x0200 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask + 0 + 0 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask + 1 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask + 2 + 2 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask + 3 + 3 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask + 4 + 4 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask + 5 + 5 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask + 6 + 6 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask + 7 + 7 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask + 8 + 8 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask + 9 + 9 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask + 10 + 10 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask + 11 + 11 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask + 12 + 12 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask + 13 + 13 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask + 16 + 16 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask + 17 + 17 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask + 18 + 18 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask + 19 + 19 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask + 20 + 20 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask + 21 + 21 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask + 22 + 22 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask + 23 + 23 + read-write + + + RXUDPGOIM + MMC Receive UDP Good Octet Counter Interrupt Mask + 24 + 24 + read-write + + + RXUDPEROIM + MMC Receive UDP Error Octet Counter Interrupt Mask + 25 + 25 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask + 26 + 26 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask + 27 + 27 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask + 28 + 28 + read-write + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask + 29 + 29 + read-write + + + + + MMC_IPC_RECEIVE_INTERRUPT + MMC Receive Checksum Offload Interrupt Register + 0x0208 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status + 0 + 0 + read-only + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status + 1 + 1 + read-only + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status + 2 + 2 + read-only + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status + 3 + 3 + read-only + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status + 4 + 4 + read-only + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status + 5 + 5 + read-only + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status + 6 + 6 + read-only + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status + 7 + 7 + read-only + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status + 8 + 8 + read-only + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status + 9 + 9 + read-only + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status + 10 + 10 + read-only + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status + 11 + 11 + read-only + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status + 12 + 12 + read-only + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status + 13 + 13 + read-only + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status + 16 + 16 + read-only + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status + 17 + 17 + read-only + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status + 18 + 18 + read-only + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status + 19 + 19 + read-only + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status + 20 + 20 + read-only + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status + 21 + 21 + read-only + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status + 22 + 22 + read-only + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status + 23 + 23 + read-only + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status + 24 + 24 + read-only + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status + 25 + 25 + read-only + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status + 26 + 26 + read-only + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status + 27 + 27 + read-only + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status + 28 + 28 + read-only + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status + 29 + 29 + read-only + + + + + RXIPV4_GOOD_FRAMES + RxIPv4 Good Frames Register + 0x0210 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GDFRM + This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. + 0 + 31 + read-only + + + + + RXIPV4_HEADER_ERROR_FRAMES + Receive IPV4 Header Error Frame Counter Register + 0x0214 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4HDRERRFRM + This field indicates the number of IPv4 datagrams received with header errors (checksum, length, or version mismatch). + 0 + 31 + read-only + + + + + RXIPV4_NO_PAYLOAD_FRAMES + Receive IPV4 No Payload Frame Counter Register + 0x0218 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4NOPAYFRM + This field indicates the number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine. + 0 + 31 + read-only + + + + + RXIPV4_FRAGMENTED_FRAMES + Receive IPV4 Fragmented Frame Counter Register + 0x021C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4FRAGFRM + This field indicates the number of good IPv4 datagrams received with fragmentation. + 0 + 31 + read-only + + + + + RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES + Receive IPV4 UDP Checksum Disabled Frame Counter Register + 0x0220 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4UDSBLFRM + This field indicates the number of received good IPv4 datagrams which have the UDP payload with checksum disabled. + 0 + 31 + read-only + + + + + RXIPV6_GOOD_FRAMES + RxIPv6 Good Frames Register + 0x0224 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6GDFRM + This field indicates the number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads. + 0 + 31 + read-only + + + + + RXIPV6_HEADER_ERROR_FRAMES + Receive IPV6 Header Error Frame Counter Register + 0x0228 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6HDRERRFRM + This field indicates the number of IPv6 datagrams received with header errors (length or version mismatch). + 0 + 31 + read-only + + + + + RXIPV6_NO_PAYLOAD_FRAMES + Receive IPV6 No Payload Frame Counter Register + 0x022C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6NOPAYFRM + This field indicates the number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers. + 0 + 31 + read-only + + + + + RXUDP_GOOD_FRAMES + RxUDP Good Frames Register + 0x0230 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPGDFRM + This field indicates the number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented. + 0 + 31 + read-only + + + + + RXUDP_ERROR_FRAMES + RxUDP Error Frames Register + 0x0234 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPERRFRM + This field indicates the number of good IP datagrams whose UDP payload has a checksum error. + 0 + 31 + read-only + + + + + RXTCP_GOOD_FRAMES + RxTCP Good Frames Register + 0x0238 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPGDFRM + This field indicates the number of good IP datagrams with a good TCP payload. + 0 + 31 + read-only + + + + + RXTCP_ERROR_FRAMES + RxTCP Error Frames Register + 0x023C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPERRFRM + This field indicates the number of good IP datagrams whose TCP payload has a checksum error. + 0 + 31 + read-only + + + + + RXICMP_GOOD_FRAMES + RxICMP Good Frames Register + 0x0240 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPGDFRM + This field indicates the number of good IP datagrams with a good ICMP payload. + 0 + 31 + read-only + + + + + RXICMP_ERROR_FRAMES + RxICMP Error Frames Register + 0x0244 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPERRFRM + This field indicates the number of good IP datagrams whose ICMP payload has a checksum error. + 0 + 31 + read-only + + + + + RXIPV4_GOOD_OCTETS + RxIPv4 Good Octets Register + 0x0250 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GDOCT + This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. The Ethernet header, FCS, pad, or IP pad + 0 + 31 + read-only + + + + + RXIPV4_HEADER_ERROR_OCTETS + Receive IPV4 Header Error Octet Counter Register + 0x0254 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4HDRERROCT + This field indicates the number of bytes received in the IPv4 datagrams with header errors (checksum, length, or version mismatch). The value in the Length field of IPv4 header is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV4_NO_PAYLOAD_OCTETS + Receive IPV4 No Payload Octet Counter Register + 0x0258 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4NOPAYOCT + This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV4_FRAGMENTED_OCTETS + Receive IPV4 Fragmented Octet Counter Register + 0x025C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4FRAGOCT + This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS + Receive IPV4 Fragmented Octet Counter Register + 0x0260 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4UDSBLOCT + This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXIPV6_GOOD_OCTETS + RxIPv6 Good Octets Register + 0x0264 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6GDOCT + Thsi field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data. + 0 + 31 + read-only + + + + + RXIPV6_HEADER_ERROR_OCTETS + Receive IPV6 Header Error Octet Counter Register + 0x0268 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6HDRERROCT + This field indicates the number of bytes received in IPv6 datagrams with header errors (length or version mismatch). The value in the IPv6 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV6_NO_PAYLOAD_OCTETS + Receive IPV6 No Payload Octet Counter Register + 0x026C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6NOPAYOCT + This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXUDP_GOOD_OCTETS + Receive UDP Good Octets Register + 0x0270 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPGDOCT + This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXUDP_ERROR_OCTETS + Receive UDP Error Octets Register + 0x0274 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPERROCT + This field indicates the number of bytes received in a UDP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXTCP_GOOD_OCTETS + Receive TCP Good Octets Register + 0x0278 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPGDOCT + This field indicates the number of bytes received in a good TCP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXTCP_ERROR_OCTETS + Receive TCP Error Octets Register + 0x027C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPERROCT + Thsi field indicates the number of bytes received in a TCP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXICMP_GOOD_OCTETS + Receive ICMP Good Octets Register + 0x0280 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPGDOCT + This field indicates the number of bytes received in a good ICMP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXICMP_ERROR_OCTETS + Receive ICMP Error Octets Register + 0x0284 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPERROCT + Number of bytes received in an ICMP segment with checksum errors + 0 + 31 + read-only + + + + + TIMESTAMP_CONTROL + Timestamp Control Register + 0x0700 + 32 + 0x00002000 + 0xFFFFFFFF + + + TSENA + Timestamp Enable + 0 + 0 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update + 1 + 1 + read-write + + + TSINIT + Timestamp Initialize + 2 + 2 + read-write + + + TSUPDT + Timestamp Update + 3 + 3 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable + 4 + 4 + read-write + + + TSADDREG + Addend Reg Update + 5 + 5 + read-write + + + TSENALL + Enable Timestamp for All Frames + 8 + 8 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control + 9 + 9 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format + 10 + 10 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames + 11 + 11 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent Over IPv6-UDP + 12 + 12 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + 13 + 13 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages + 14 + 14 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master + 15 + 15 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + 16 + 17 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering + 18 + 18 + read-write + + + + + SUB_SECOND_INCREMENT + Sub-Second Increment Register + 0x0704 + 32 + 0x00000000 + 0xFFFFFFFF + + + SSINC + Sub-second Increment Value + 0 + 7 + read-write + + + + + SYSTEM_TIME_SECONDS + System Time - Seconds Register + 0x0708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + 0 + 31 + read-only + + + + + SYSTEM_TIME_NANOSECONDS + System Time Nanoseconds Register + 0x070C + 32 + 0x00000000 + 0xFFFFFFFF + + + TSSS + Timestamp Sub Seconds + 0 + 30 + read-only + + + + + SYSTEM_TIME_SECONDS_UPDATE + System Time - Seconds Update Register + 0x0710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + 0 + 31 + read-write + + + + + SYSTEM_TIME_NANOSECONDS_UPDATE + System Time Nanoseconds Update Register + 0x0714 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSSS + Timestamp Sub Second + 0 + 30 + read-write + + + ADDSUB + Add or subtract time + 31 + 31 + read-write + + + + + TIMESTAMP_ADDEND + Timestamp Addend Register + 0x0718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register + 0 + 31 + read-write + + + + + TARGET_TIME_SECONDS + Target Time Seconds Register + 0x071C + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + 0 + 31 + read-write + + + + + TARGET_TIME_NANOSECONDS + Target Time Nanoseconds Register + 0x0720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TTSLO + Target Timestamp Low Register + 0 + 30 + read-write + + + TRGTBUSY + Target Time Register Busy + 31 + 31 + read-only + + + + + SYSTEM_TIME_HIGHER_WORD_SECONDS + System Time - Higher Word Seconds Register + 0x0724 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSHWR + Timestamp Higher Word Register + 0 + 15 + read-write + + + + + TIMESTAMP_STATUS + Timestamp Status Register + 0x0728 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSSOVF + Timestamp Seconds Overflow + 0 + 0 + read-only + + + TSTARGT + Timestamp Target Time Reached + 1 + 1 + read-only + + + TSTRGTERR + Timestamp Target Time Error + 3 + 3 + read-only + + + TSTARGT1 + Timestamp Target Time Reached for Target Time PPS1 + 4 + 4 + read-only + + + TSTRGTERR1 + Timestamp Target Time Error + 5 + 5 + read-only + + + TSTARGT2 + Timestamp Target Time Reached for Target Time PPS2 + 6 + 6 + read-only + + + TSTRGTERR2 + Timestamp Target Time Error + 7 + 7 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 + 8 + 8 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error + 9 + 9 + read-only + + + + + BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00020101 + 0xFFFFFFFF + + + SWR + Software Reset + 0 + 0 + read-write + + + DA + DMA Arbitration Scheme + 1 + 1 + read-write + + + DSL + Descriptor Skip Length + 2 + 6 + read-write + + + ATDS + Alternate Descriptor Size + 7 + 7 + read-write + + + PBL + Programmable Burst Length + 8 + 13 + read-write + + + PR + Priority Ratio + 14 + 15 + read-write + + + FB + Fixed Burst + 16 + 16 + read-write + + + RPBL + Rx DMA PBL + 17 + 22 + read-write + + + USP + Use Seperate PBL + 23 + 23 + read-write + + + PBLX8 + 8xPBL Mode + 24 + 24 + read-write + + + AAL + Address Aligned Beats + 25 + 25 + read-write + + + MB + Mixed Burst + 26 + 26 + read-write + + + TXPR + Transmit Priority + 27 + 27 + read-write + + + PRWG + Channel Priority Weights + 28 + 29 + read-only + + + + + TRANSMIT_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand + 0 + 31 + read-write + + + + + RECEIVE_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand + 0 + 31 + read-write + + + + + RECEIVE_DESCRIPTOR_LIST_ADDRESS + Receive Descriptor Address Register + 0x100C + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA_32bit + Start of Receive List + 2 + 31 + read-write + + + + + TRANSMIT_DESCRIPTOR_LIST_ADDRESS + Transmit descripter Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA_32bit + Start of Transmit List + 2 + 31 + read-write + + + + + STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0xFFFFFFFF + + + TI + Transmit Interrupt + 0 + 0 + read-write + + + TPS + Transmit Process Stopped + 1 + 1 + read-write + + + TU + Transmit Buffer Unavailable + 2 + 2 + read-write + + + TJT + Transmit Jabber Timeout + 3 + 3 + read-write + + + OVF + Receive Overflow + 4 + 4 + read-write + + + UNF + Transmit Underflow + 5 + 5 + read-write + + + RI + Receive Interrupt + 6 + 6 + read-write + + + RU + Receive Buffer Unavailable + 7 + 7 + read-write + + + RPS + Receive Process Stopped + 8 + 8 + read-write + + + RWT + Receive Watchdog Timeout + 9 + 9 + read-write + + + ETI + Early Transmit Interrupt + 10 + 10 + read-write + + + FBI + Fatal Bus Error Interrupt + 13 + 13 + read-write + + + ERI + Early Receive Interrupt + 14 + 14 + read-write + + + AIS + Abnormal Interrupt Summary + 15 + 15 + read-write + + + NIS + Normal Interrupt Summary + 16 + 16 + read-write + + + RS + Received Process State + 17 + 19 + read-only + + + TS + Transmit Process State + 20 + 22 + read-only + + + EB + Error Bits + 23 + 25 + read-only + + + EMI + ETH MMC Interrupt + 27 + 27 + read-only + + + EPI + ETH PMT Interrupt + 28 + 28 + read-only + + + TTI + Timestamp Trigger Interrupt + 29 + 29 + read-only + + + + + OPERATION_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + SR + Start or Stop Receive + 1 + 1 + read-write + + + OSF + Operate on Second Frame + 2 + 2 + read-write + + + RTC + Receive Threshold Control + 3 + 4 + read-write + + + FUF + Forward Undersized Good Frames + 6 + 6 + read-write + + + FEF + Forward Error Frames + 7 + 7 + read-write + + + ST + Start or Stop Transmission Command + 13 + 13 + read-write + + + TTC + Transmit Threshold Control + 14 + 16 + read-write + + + FTF + Flush Transmit FIFO + 20 + 20 + read-write + + + TSF + Transmit Store and Forward + 21 + 21 + read-write + + + DFF + Disable Flushing of Received Frames + 24 + 24 + read-write + + + RSF + Receive Store and Forward + 25 + 25 + read-write + + + DT + Disable Dropping of TCP/IP Checksum Error Frames + 26 + 26 + read-write + + + + + INTERRUPT_ENABLE + Interrupt Enable Register + 0x101C + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmit Interrupt Enable + 0 + 0 + read-write + + + TSE + Transmit Stopped Enable + 1 + 1 + read-write + + + TUE + Transmit Buffer Unvailable Enable + 2 + 2 + read-write + + + TJE + Transmit Jabber Timeout Enable + 3 + 3 + read-write + + + OVE + Overflow Interrupt Enable + 4 + 4 + read-write + + + UNE + Underflow Interrupt Enable + 5 + 5 + read-write + + + RIE + Receive Interrupt Enable + 6 + 6 + read-write + + + RUE + Receive Buffer Unavailable Enable + 7 + 7 + read-write + + + RSE + Receive Stopped Enable + 8 + 8 + read-write + + + RWE + Receive Watchdog Timeout Enable + 9 + 9 + read-write + + + ETE + Early Transmit Interrupt Enable + 10 + 10 + read-write + + + FBE + Fatal Bus Error Enable + 13 + 13 + read-write + + + ERE + Early Receive Interrupt Enable + 14 + 14 + read-write + + + AIE + Abnormal Interrupt Summary Enable + 15 + 15 + read-write + + + NIE + Normal Interrupt Summary Enable + 16 + 16 + read-write + + + + + MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER + Missed Frame and Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0xFFFFFFFF + + + MISFRMCNT + This field indicates the number of frames missed by the controller because of the RAM Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read. + 0 + 15 + read-only + + + MISCNTOVF + Overflow bit for Missed Frame Counter + 16 + 16 + read-only + + + OVFFRMCNT + This field indicates the number of frames missed by the application. The counter is cleared when this register is read. + 17 + 27 + read-only + + + OVFCNTOVF + Overflow bit for FIFO Overflow Counter + 28 + 28 + read-only + + + + + RECEIVE_INTERRUPT_WATCHDOG_TIMER + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0xFFFFFFFF + + + RIWT + RI Watchdog Timer Count + 0 + 7 + read-write + + + + + AHB_STATUS + AHB Status Register + 0x102C + 32 + 0x00000000 + 0xFFFFFFFF + + + AHBMS + AHB Master Status + 0 + 0 + read-only + + + + + CURRENT_HOST_TRANSMIT_DESCRIPTOR + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer + 0 + 31 + read-only + + + + + CURRENT_HOST_RECEIVE_DESCRIPTOR + Current Host Receive Descriptor Register + 0x104C + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer + 0 + 31 + read-only + + + + + CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer + 0 + 31 + read-only + + + + + CURRENT_HOST_RECEIVE_BUFFER_ADDRESS + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer + 0 + 31 + read-only + + + + + HW_FEATURE + HW Feature Register + 0x1058 + 32 + 0x03052F35 + 0xFFFFFFFF + + + MIISEL + 10 or 100 Mbps support + 0 + 0 + read-only + + + GMIISEL + 1000 Mbps support + 1 + 1 + read-only + + + HDSEL + Half-Duplex support + 2 + 2 + read-only + + + EXTHASHEN + Expanded DA Hash Filter + 3 + 3 + read-only + + + HASHSEL + HASH Filter + 4 + 4 + read-only + + + ADDMACADRSEL + Multiple MAC Address Registers + 5 + 5 + read-only + + + PCSSEL + PCS registers (TBI, SGMII, or RTBI PHY interface) + 6 + 6 + read-only + + + L3L4FLTREN + Layer 3 and Layer 4 Filter Feature + 7 + 7 + read-only + + + SMASEL + SMA (MDIO) Interface + 8 + 8 + read-only + + + RWKSEL + PMT Remote Wakeup + 9 + 9 + read-only + + + MGKSEL + PMT Magic Packet + 10 + 10 + read-only + + + MMCSEL + RMON Module + 11 + 11 + read-only + + + TSVER1SEL + Only IEEE 1588-2002 Timestamp + 12 + 12 + read-only + + + TSVER2SEL + IEEE 1588-2008 Advanced Timestamp + 13 + 13 + read-only + + + EEESEL + Energy Efficient Ethernet + 14 + 14 + read-only + + + AVSEL + AV Feature + 15 + 15 + read-only + + + TXCOESEL + Checksum Offload in Tx + 16 + 16 + read-only + + + RXTYP1COE + IP Checksum Offload (Type 1) in Rx + 17 + 17 + read-only + + + RXTYP2COE + IP Checksum Offload (Type 2) in Rx + 18 + 18 + read-only + + + RXFIFOSIZE + Rx FIFO > 2,048 Bytes + 19 + 19 + read-write + + + RXCHCNT + Number of additional Rx channels + 20 + 21 + read-only + + + TXCHCNT + Number of additional Tx channels + 22 + 23 + read-only + + + ENHDESSEL + Alternate (Enhanced Descriptor) + 24 + 24 + read-only + + + INTTSEN + Timestamping with Internal System Time + 25 + 25 + read-only + + + FLEXIPPSEN + Flexible Pulse-Per-Second Output + 26 + 26 + read-only + + + SAVLANINS + Source Address or VLAN Insertion + 27 + 27 + read-only + + + ACTPHYIF + Active or Selected PHY interface + 28 + 30 + read-only + + + + + + + USB0 + Universal Serial Bus + USB + USB + 0x50040000 + + 0x0 + 0x040000 + registers + + + USB0_0 + Universal Serial Bus (Module 0) + 107 + + + + GOTGCTL + Control and Status Register + 0x000 + 32 + 0x00010000 + 0xFFFFFFFF + + + SesReqScs + Session Request Success + 0 + 0 + read-only + + + value1 + Session request failure + #0 + + + value2 + Session request success + #1 + + + + + SesReq + Session Request + 1 + 1 + read-write + + + value1 + No session request + #0 + + + value2 + Session request + #1 + + + + + VbvalidOvEn + VBUS Valid Override Enable + 2 + 2 + read-write + + + value1 + Override is disabled and vbus valid signal from the PHY is used internally by the core. + #0 + + + value2 + Internally vbus valid received from the PHY is overridden with GOTGCTL.VbvalidOvVal. + #1 + + + + + VbvalidOvVal + VBUS Valid Override Value + 3 + 3 + read-write + + + value1 + vbusvalid value is 0# when GOTGCTL.VbvalidOvEn = 1 + #0 + + + value2 + vbusvalid value is 1# when GOTGCTL.VbvalidOvEn = 1 + #1 + + + + + AvalidOvEn + A-Peripheral Session Valid Override Enable + 4 + 4 + read-write + + + value1 + Override is disabled and Avalid signal from the PHY is used internally by the core. + #0 + + + value2 + Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal. + #1 + + + + + AvalidOvVal + A-Peripheral Session Valid Override Value + 5 + 5 + read-write + + + value1 + Avalid value is 0# when GOTGCTL.AvalidOvEn = 1 + #0 + + + value2 + Avalid value is 1# when GOTGCTL.AvalidOvEn = 1 + #1 + + + + + BvalidOvEn + B-Peripheral Session Valid Override Enable + 6 + 6 + read-write + + + value1 + Override is disabled and Bvalid signal from the PHY is used internally by the core. + #0 + + + value2 + Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal. + #1 + + + + + BvalidOvVal + B-Peripheral Session Valid Override Value + 7 + 7 + read-write + + + value1 + Bvalid value is 0# when GOTGCTL.BvalidOvEn = 1 + #0 + + + value2 + Bvalid value is 1# when GOTGCTL.BvalidOvEn = 1 + #1 + + + + + HstNegScs + Host Negotiation Success + 8 + 8 + read-only + + + value1 + Host negotiation failure + #0 + + + value2 + Host negotiation success + #1 + + + + + HNPReq + HNP Request + 9 + 9 + read-write + + + value1 + No HNP request + #0 + + + value2 + HNP request + #1 + + + + + HstSetHNPEn + Host Set HNP Enable + 10 + 10 + read-write + + + value1 + Host Set HNP is not enabled + #0 + + + value2 + Host Set HNP is enabled + #1 + + + + + DevHNPEn + Device HNP Enabled + 11 + 11 + read-write + + + value1 + HNP is not enabled in the application + #0 + + + value2 + HNP is enabled in the application + #1 + + + + + ConlDSts + Connector ID Status + 16 + 16 + read-only + + + value1 + The USB core is in A-Device mode + #0 + + + value2 + The USB core is in B-Device mode + #1 + + + + + DbncTime + Long/Short Debounce Time + 17 + 17 + read-only + + + value1 + Long debounce time, used for physical connections (100 ms + 2.5 us) + #0 + + + value2 + Short debounce time, used for soft connections (2.5 us) + #1 + + + + + ASesVId + A-Session Valid + 18 + 18 + read-only + + + value1 + A-session is not valid + #0 + + + value2 + A-session is valid + #1 + + + + + BSesVld + B-Session Valid + 19 + 19 + read-only + + + value1 + B-session is not valid. + #0 + + + value2 + B-session is valid. + #1 + + + + + OTGVer + OTG Version + 20 + 20 + read-write + + + value1 + OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP. + #0 + + + value2 + OTG Version 2.0. In this version the core supports only Data line pulsing for SRP. + #1 + + + + + + + GOTGINT + OTG Interrupt Register + 0x004 + 32 + 0x00000000 + 0xFFFFFFFF + + + SesEndDet + Session End Detected + 2 + 2 + read-write + + + SesReqSucStsChng + Session Request Success Status Change + 8 + 8 + read-write + + + HstNegSucStsChng + Host Negotiation Success Status Change + 9 + 9 + read-write + + + HstNegDet + Host Negotiation Detected + 17 + 17 + read-write + + + ADevTOUTChg + A-Device Timeout Change + 18 + 18 + read-write + + + DbnceDone + Debounce Done + 19 + 19 + read-write + + + + + GAHBCFG + AHB Configuration Register + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + GlblIntrMsk + Global Interrupt Mask + 0 + 0 + read-write + + + value1 + Mask the interrupt assertion to the application. + #0 + + + value2 + Unmask the interrupt assertion to the application. + #1 + + + + + HBstLen + Burst Length/Type + 1 + 4 + read-write + + + value1 + Single + #0000 + + + value2 + INCR + #0001 + + + value3 + INCR4 + #0011 + + + value4 + INCR8 + #0101 + + + value5 + INCR16 + #0111 + + + + + DMAEn + DMA Enable + 5 + 5 + read-write + + + value1 + Core operates in Slave mode + #0 + + + value2 + Core operates in a DMA mode + #1 + + + + + NPTxFEmpLvl + Non-Periodic TxFIFO Empty Level + 7 + 7 + read-write + + + value1 + DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty + #0 + + + value2 + DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty + #1 + + + + + PTxFEmpLvl + Periodic TxFIFO Empty Level + 8 + 8 + read-write + + + value1 + GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty + #0 + + + value2 + GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty + #1 + + + + + AHBSingle + AHB Single Support + 23 + 23 + read-write + + + value1 + The remaining data in a transfer is sent using INCR burst size. This is the default mode. + #0 + + + value2 + The remaining data in a transfer is sent using single burst size. + #1 + + + + + + + GUSBCFG + USB Configuration Register + 0x00C + 32 + 0x00001440 + 0xFFFFFFFF + + + TOutCal + FS Timeout Calibration + 0 + 2 + read-write + + + PHYSel + USB 1.1 Full-Speed Serial Transceiver Select + 6 + 6 + read-only + + + value2 + USB 1.1 full-speed serial transceiver + #1 + + + + + SRPCap + SRP-Capable + 8 + 8 + read-write + + + value1 + SRP capability is not enabled. + #0 + + + value2 + SRP capability is enabled. + #1 + + + + + HNPCap + HNP-Capable + 9 + 9 + read-write + + + value1 + HNP capability is not enabled. + #0 + + + value2 + HNP capability is enabled. + #1 + + + + + USBTrdTim + USB Turnaround Time + 10 + 13 + read-write + + + OtgI2CSel + UTMIFS Interface Select + 16 + 16 + read-write + + + value1 + UTMI USB 1.1 Full-Speed interface for OTG signals + #0 + + + + + TxEndDelay + Tx End Delay + 28 + 28 + read-write + + + value1 + Normal mode + #0 + + + value2 + Introduce Tx end delay timers + #1 + + + + + ForceHstMode + Force Host Mode + 29 + 29 + read-write + + + value1 + Normal Mode + #0 + + + value2 + Force Host Mode + #1 + + + + + ForceDevMode + Force Device Mode + 30 + 30 + read-write + + + value1 + Normal Mode + #0 + + + value2 + Force Device Mode + #1 + + + + + CTP + Corrupt Tx packet + 31 + 31 + read-write + + + + + GRSTCTL + Reset Register + 0x010 + 32 + 0x10000000 + 0xFFFFFFFF + + + CSftRst + Core Soft Reset + 0 + 0 + read-write + + + FrmCntrRst + Host Frame Counter Reset + 2 + 2 + read-write + + + RxFFlsh + RxFIFO Flush + 4 + 4 + read-write + + + TxFFlsh + TxFIFO Flush + 5 + 5 + read-write + + + TxFNum + TxFIFO Number + 6 + 10 + read-write + + + value1 + Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode + 0x00 + + + value2 + Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode + 0x01 + + + value3 + Tx FIFO 2 flush in device mode + 0x02 + + + value4 + Tx FIFO 15 flush in device mode + 0x0F + + + value5 + Flush all the transmit FIFOs in device or host mode. + 0x10 + + + + + DMAReq + DMA Request Signal + 30 + 30 + read-only + + + AHBIdle + AHB Master Idle + 31 + 31 + read-only + + + + + GINTSTS_HOSTMODE + Interrupt Register [HOSTMODE] + 0x014 + 32 + 0x14000020 + 0xFFFFFFFF + + + CurMod + Current Mode of Operation + 0 + 0 + read-only + + + value1 + Device mode + #0 + + + value2 + Host mode + #1 + + + + + ModeMis + Mode Mismatch Interrupt + 1 + 1 + read-write + + + OTGInt + OTG Interrupt + 2 + 2 + read-only + + + Sof + Start of Frame + 3 + 3 + read-write + + + RxFLvl + RxFIFO Non-Empty + 4 + 4 + read-only + + + incomplP + Incomplete Periodic Transfer + 21 + 21 + read-write + + + PrtInt + Host Port Interrupt + 24 + 24 + read-only + + + HChInt + Host Channels Interrupt + 25 + 25 + read-only + + + PTxFEmp + Periodic TxFIFO Empty + 26 + 26 + read-only + + + ConIDStsChng + Connector ID Status Change + 28 + 28 + read-write + + + DisconnInt + Disconnect Detected Interrupt + 29 + 29 + read-write + + + SessReqInt + Session Request/New Session Detected Interrupt + 30 + 30 + read-write + + + WkUpInt + Resume/Remote Wakeup Detected Interrupt + 31 + 31 + read-write + + + + + GINTSTS_DEVICEMODE + Interrupt Register [DEVICEMODE] + GINTSTS_HOSTMODE + 0x014 + 32 + 0x14000020 + 0xFFFFFFFF + + + CurMod + Current Mode of Operation + 0 + 0 + read-only + + + value1 + Device mode + #0 + + + value2 + Host mode + #1 + + + + + ModeMis + Mode Mismatch Interrupt + 1 + 1 + read-write + + + OTGInt + OTG Interrupt + 2 + 2 + read-only + + + Sof + Start of Frame + 3 + 3 + read-write + + + RxFLvl + RxFIFO Non-Empty + 4 + 4 + read-only + + + GINNakEff + Global IN Non-Periodic NAK Effective + 6 + 6 + read-only + + + GOUTNakEff + Global OUT NAK Effective + 7 + 7 + read-only + + + ErlySusp + Early Suspend + 10 + 10 + read-write + + + USBSusp + USB Suspend + 11 + 11 + read-write + + + USBRst + USB Reset + 12 + 12 + read-write + + + EnumDone + Enumeration Done + 13 + 13 + read-write + + + ISOOutDrop + Isochronous OUT Packet Dropped Interrupt + 14 + 14 + read-write + + + EOPF + End of Periodic Frame Interrupt + 15 + 15 + read-write + + + IEPInt + IN Endpoints Interrupt + 18 + 18 + read-only + + + OEPInt + OUT Endpoints Interrupt + 19 + 19 + read-only + + + incompISOIN + Incomplete Isochronous IN Transfer + 20 + 20 + read-write + + + incomplSOOUT + Incomplete Isochronous OUT Transfer + 21 + 21 + read-write + + + ConIDStsChng + Connector ID Status Change + 28 + 28 + read-write + + + SessReqInt + Session Request/New Session Detected Interrupt + 30 + 30 + read-write + + + WkUpInt + Resume/Remote Wakeup Detected Interrupt + 31 + 31 + read-write + + + + + GINTMSK_HOSTMODE + Interrupt Mask Register [HOSTMODE] + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ModeMisMsk + Mode Mismatch Interrupt Mask + 1 + 1 + read-write + + + OTGIntMsk + OTG Interrupt Mask + 2 + 2 + read-write + + + SofMsk + Start of Frame Mask + 3 + 3 + read-write + + + RxFLvlMsk + Receive FIFO Non-Empty Mask + 4 + 4 + read-write + + + incomplPMsk + Incomplete Periodic Transfer Mask + 21 + 21 + read-write + + + PrtIntMsk + Host Port Interrupt Mask + 24 + 24 + read-write + + + HChIntMsk + Host Channels Interrupt Mask + 25 + 25 + read-write + + + PTxFEmpMsk + Periodic TxFIFO Empty Mask + 26 + 26 + read-write + + + ConIDStsChngMsk + Connector ID Status Change Mask + 28 + 28 + read-write + + + DisconnIntMsk + Disconnect Detected Interrupt Mask + 29 + 29 + read-write + + + SessReqIntMsk + Session Request/New Session Detected Interrupt Mask + 30 + 30 + read-write + + + WkUpIntMsk + Resume/Remote Wakeup Detected Interrupt Mask + 31 + 31 + read-write + + + + + GINTMSK_DEVICEMODE + Interrupt Mask Register [DEVICEMODE] + GINTMSK_HOSTMODE + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ModeMisMsk + Mode Mismatch Interrupt Mask + 1 + 1 + read-write + + + OTGIntMsk + OTG Interrupt Mask + 2 + 2 + read-write + + + SofMsk + Start of Frame Mask + 3 + 3 + read-write + + + RxFLvlMsk + Receive FIFO Non-Empty Mask + 4 + 4 + read-write + + + GINNakEffMsk + Global Non-periodic IN NAK Effective Mask + 6 + 6 + read-write + + + GOUTNakEffMsk + Global OUT NAK Effective Mask + 7 + 7 + read-write + + + ErlySuspMsk + Early Suspend Mask + 10 + 10 + read-write + + + USBSuspMsk + USB Suspend Mask + 11 + 11 + read-write + + + USBRstMsk + USB Reset Mask + 12 + 12 + read-write + + + EnumDoneMsk + Enumeration Done Mask + 13 + 13 + read-write + + + ISOOutDropMsk + Isochronous OUT Packet Dropped Interrupt Mask + 14 + 14 + read-write + + + EOPFMsk + End of Periodic Frame Interrupt Mask + 15 + 15 + read-write + + + IEPIntMsk + IN Endpoints Interrupt Mask + 18 + 18 + read-write + + + OEPIntMsk + OUT Endpoints Interrupt Mask + 19 + 19 + read-write + + + incompISOINMsk + Incomplete Isochronous IN Transfer Mask + 20 + 20 + read-write + + + incomplSOOUTMsk + Incomplete Isochronous OUT Transfer Mask + 21 + 21 + read-write + + + ConIDStsChngMsk + Connector ID Status Change Mask + 28 + 28 + read-write + + + DisconnIntMsk + Disconnect Detected Interrupt Mask + 29 + 29 + read-write + + + SessReqIntMsk + Session Request/New Session Detected Interrupt Mask + 30 + 30 + read-write + + + WkUpIntMsk + Resume/Remote Wakeup Detected Interrupt Mask + 31 + 31 + read-write + + + + + GRXSTSR_HOSTMODE + Receive Status Debug Read Register [HOSTMODE] + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + ChNum + Channel Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + IN data packet received + #0010 + + + value2 + IN transfer completed (triggers an interrupt) + #0011 + + + value3 + Data toggle error (triggers an interrupt) + #0101 + + + value4 + Channel halted (triggers an interrupt) + #0111 + + + + + + + GRXSTSR_DEVICEMODE + Receive Status Debug Read Register [DEVICEMODE] + GRXSTSR_HOSTMODE + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + EPNum + Endpoint Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + Global OUT NAK (triggers an interrupt) + #0001 + + + value2 + OUT data packet received + #0010 + + + value3 + OUT transfer completed (triggers an interrupt) + #0011 + + + value4 + SETUP transaction completed (triggers an interrupt) + #0100 + + + value5 + SETUP data packet received + #0110 + + + + + FN + Frame Number + 21 + 24 + read-only + + + + + GRXSTSP_DEVICEMODE + Receive Status Read and Pop Register [DEVICEMODE] + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + EPNum + Endpoint Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + Global OUT NAK (triggers an interrupt) + #0001 + + + value2 + OUT data packet received + #0010 + + + value3 + OUT transfer completed (triggers an interrupt) + #0011 + + + value4 + SETUP transaction completed (triggers an interrupt) + #0100 + + + value5 + SETUP data packet received + #0110 + + + + + FN + Frame Number + 21 + 24 + read-only + + + + + GRXSTSP_HOSTMODE + Receive Status Read and Pop Register [HOSTMODE] + GRXSTSP_DEVICEMODE + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + ChNum + Channel Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + IN data packet received + #0010 + + + value2 + IN transfer completed (triggers an interrupt) + #0011 + + + value3 + Data toggle error (triggers an interrupt) + #0101 + + + value4 + Channel halted (triggers an interrupt) + #0111 + + + + + + + GRXFSIZ + Receive FIFO Size Register + 0x024 + 32 + 0x0000011A + 0xFFFFFFFF + + + RxFDep + RxFIFO Depth + 0 + 15 + read-write + + + + + GNPTXFSIZ_HOSTMODE + Non-Periodic Transmit FIFO Size Register [HOSTMODE] + 0x028 + 32 + 0x0010011A + 0xFFFFFFFF + + + NPTxFStAddr + Non-periodic Transmit RAM Start Address + 0 + 15 + read-write + + + NPTxFDep + Non-periodic TxFIFO Depth + 16 + 31 + read-write + + + + + GNPTXFSIZ_DEVICEMODE + Non-Periodic Transmit FIFO Size Register [DEVICEMODE] + GNPTXFSIZ_HOSTMODE + 0x028 + 32 + 0x00100000 + 0xFFFFFFFF + + + INEPTxF0StAddr + IN Endpoint FIFO0 Transmit RAM Start Address + 0 + 15 + read-write + + + INEPTxF0Dep + IN Endpoint TxFIFO 0 Depth + 16 + 31 + read-write + + + + + GNPTXSTS + Non-Periodic Transmit FIFO/Queue Status Register + 0x02C + 32 + 0x00080010 + 0xFFFFFFFF + + + NPTxFSpcAvail + Non-periodic TxFIFO Space Avail + 0 + 15 + read-only + + + value1 + Non-periodic TxFIFO is full + 0x0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + NPTxQSpcAvail + Non-periodic Transmit Request Queue Space Available + 16 + 23 + read-only + + + value1 + Non-periodic Transmit Request Queue is full + 0x0 + + + value2 + 1 location available + 0x1 + + + value3 + 2 locations available + 0x2 + + + + + NPTxQTop + Top of the Non-periodic Transmit Request Queue + 24 + 30 + read-only + + + value1 + IN/OUT token + #00 + + + value2 + Zero-length transmit packet (device IN/host OUT) + #01 + + + value4 + Channel halt command + #11 + + + + + + + GUID + USB Module Identification Register + 0x03C + 32 + 0x00AEC000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-write + + + MOD_TYPE + Module Type + 8 + 15 + read-write + + + MOD_NUMBER + Module Number + 16 + 31 + read-write + + + + + GDFIFOCFG + Global DFIFO Software Config Register + 0x05C + 32 + 0x027A02B2 + 0xFFFFFFFF + + + GDFIFOCfg + GDFIFOCfg + 0 + 15 + read-write + + + EPInfoBaseAddr + EPInfoBaseAddr + 16 + 31 + read-write + + + + + HPTXFSIZ + Host Periodic Transmit FIFO Size Register + 0x100 + 32 + 0x0100012A + 0xFFFFFFFF + + + PTxFStAddr + Host Periodic TxFIFO Start Address + 0 + 15 + read-write + + + PTxFSize + Host Periodic TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF1 + Device IN Endpoint Transmit FIFO Size Register + 0x104 + 32 + 0x0100012A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF2 + Device IN Endpoint Transmit FIFO Size Register + 0x108 + 32 + 0x0100022A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF3 + Device IN Endpoint Transmit FIFO Size Register + 0x10C + 32 + 0x0100032A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF4 + Device IN Endpoint Transmit FIFO Size Register + 0x110 + 32 + 0x0100042A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF5 + Device IN Endpoint Transmit FIFO Size Register + 0x114 + 32 + 0x0100052A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF6 + Device IN Endpoint Transmit FIFO Size Register + 0x118 + 32 + 0x0100062A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + HCFG + Host Configuration Register + 0x400 + 32 + 0x00000200 + 0xFFFFFFFF + + + FSLSPclkSel + FS PHY Clock Select + 0 + 1 + read-write + + + value1 + PHY clock is running at 48 MHz + #01 + + + + + FSLSSupp + FS-Only Support + 2 + 2 + read-write + + + value1 + FS-only, connected device can supports also only FS. + #0 + + + value2 + FS-only, even if the connected device can support HS + #1 + + + + + DescDMA + Enable Scatter/gather DMA in Host mode + 23 + 23 + read-write + + + FrListEn + Frame List Entries + 24 + 25 + read-write + + + value1 + 8 Entries + #00 + + + value2 + 16 Entries + #01 + + + value3 + 32 Entries + #10 + + + value4 + 64 Entries + #11 + + + + + PerSchedEna + Enable Periodic Scheduling + 26 + 26 + read-write + + + + + HFIR + Host Frame Interval Register + 0x404 + 32 + 0x0000EA60 + 0xFFFFFFFF + + + FrInt + Frame Interval + 0 + 15 + read-write + + + HFIRRldCtrl + Reload Control + 16 + 16 + read-write + + + value1 + HFIR cannot be reloaded dynamically + #0 + + + value2 + HFIR can be dynamically reloaded during runtime + #1 + + + + + + + HFNUM + Host Frame Number/Frame Time Remaining Register + 0x408 + 32 + 0x00003FFF + 0xFFFFFFFF + + + FrNum + Frame Number + 0 + 15 + read-write + + + FrRem + Frame Time Remaining + 16 + 31 + read-only + + + + + HPTXSTS + Host Periodic Transmit FIFO/ Queue Status Register + 0x410 + 32 + 0x00080100 + 0xFFFFFFFF + + + PTxFSpcAvail + Periodic Transmit Data FIFO Space Available + 0 + 15 + read-write + + + value1 + Periodic TxFIFO is full + #0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + PTxQSpcAvail + Periodic Transmit Request Queue Space Available + 16 + 23 + read-only + + + value1 + Periodic Transmit Request Queue is full + 0x0 + + + value2 + 1 location available + 0x1 + + + value3 + 2 locations available + 0x2 + + + + + PTxQTop + Top of the Periodic Transmit Request Queue + 24 + 31 + read-only + + + + + HAINT + Host All Channels Interrupt Register + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + HAINT + Channel Interrupts + 0 + 13 + read-only + + + + + HAINTMSK + Host All Channels Interrupt Mask Register + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + HAINTMsk + Channel Interrupt Mask + 0 + 13 + read-write + + + + + HFLBADDR + Host Frame List Base Address Register + 0x41C + 32 + 0x00000000 + 0xFFFFFFFF + + + Starting_Address + Starting Address + 0 + 31 + read-write + + + + + HPRT + Host Port Control and Status Register + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + PrtConnSts + Port Connect Status + 0 + 0 + read-only + + + value1 + No device is attached to the port. + #0 + + + value2 + A device is attached to the port. + #1 + + + + + PrtConnDet + Port Connect Detected + 1 + 1 + read-write + + + PrtEna + Port Enable + 2 + 2 + read-write + + + value1 + Port disabled + #0 + + + value2 + Port enabled + #1 + + + + + PrtEnChng + Port Enable/Disable Change + 3 + 3 + read-write + + + PrtOvrCurrAct + Port Overcurrent Active + 4 + 4 + read-only + + + value1 + No overcurrent condition + #0 + + + value2 + Overcurrent condition + #1 + + + + + PrtOvrCurrChng + Port Overcurrent Change + 5 + 5 + read-write + + + PrtRes + Port Resume + 6 + 6 + read-write + + + value1 + No resume driven + #0 + + + value2 + Resume driven + #1 + + + + + PrtSusp + Port Suspend + 7 + 7 + read-write + + + value1 + Port not in Suspend mode + #0 + + + value2 + Port in Suspend mode + #1 + + + + + PrtRst + Port Reset + 8 + 8 + read-write + + + value1 + Port not in reset + #0 + + + value2 + Port in reset + #1 + + + + + PrtLnSts + Port Line Status + 10 + 11 + read-only + + + PrtPwr + Port Power + 12 + 12 + read-write + + + value1 + Power off + #0 + + + value2 + Power on + #1 + + + + + PrtSpd + Port Speed + 17 + 18 + read-only + + + value1 + Full speed + #01 + + + + + + + DCFG + Device Configuration Register + 0x800 + 32 + 0x08200000 + 0xFFFFFFFF + + + DevSpd + Device Speed + 0 + 1 + read-write + + + value4 + Full speed (USB 1.1 transceiver clock is 48 MHz) + #11 + + + + + NZStsOUTHShk + Non-Zero-Length Status OUT Handshake + 2 + 2 + read-write + + + value1 + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. + #1 + + + value2 + Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register. + #0 + + + + + DevAddr + Device Address + 4 + 10 + read-write + + + PerFrInt + Periodic Frame Interval + 11 + 12 + read-write + + + value1 + 80% of the frame interval + #00 + + + value2 + 85% + #01 + + + value3 + 90% + #10 + + + value4 + 95% + #11 + + + + + DescDMA + Enable Scatter/Gather DMA in Device mode. + 23 + 23 + read-write + + + PerSchIntvl + Periodic Scheduling Interval + 24 + 25 + read-write + + + value1 + 25% of frame. + #00 + + + value2 + 50% of frame. + #01 + + + value3 + 75% of frame. + #10 + + + + + + + DCTL + Device Control Register + 0x804 + 32 + 0x00000002 + 0xFFFFFFFF + + + RmtWkUpSig + Remote Wakeup Signaling + 0 + 0 + read-write + + + SftDiscon + Soft Disconnect + 1 + 1 + read-write + + + value1 + Normal operation. When this bit is cleared after a soft disconnect, the core drives a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. + #0 + + + value2 + The core drives a device disconnect event to the USB host. + #1 + + + + + GNPINNakSts + Global Non-periodic IN NAK Status + 2 + 2 + read-only + + + value1 + A handshake is sent out based on the data availability in the transmit FIFO. + #0 + + + value2 + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + #1 + + + + + GOUTNakSts + Global OUT NAK Status + 3 + 3 + read-only + + + value1 + A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + #0 + + + value2 + No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + #1 + + + + + SGNPInNak + Set Global Non-periodic IN NAK + 7 + 7 + write-only + + + CGNPInNak + Clear Global Non-periodic IN NAK + 8 + 8 + write-only + + + SGOUTNak + Set Global OUT NAK + 9 + 9 + write-only + + + CGOUTNak + Clear Global OUT NAK + 10 + 10 + write-only + + + GMC + Global Multi Count + 13 + 14 + read-write + + + value1 + Invalid. + #00 + + + value2 + 1 packet. + #01 + + + value3 + 2 packets. + #10 + + + value4 + 3 packets. + #11 + + + + + IgnrFrmNum + Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA + 15 + 15 + read-write + + + value1 + Scatter/Gather enabled: The core transmits the packets only in the frame number in which they are intended to be transmitted. Scatter/Gather disabled: Periodic transfer interrupt feature is disabled; the application must program transfers for periodic endpoints every frame + #0 + + + value2 + Scatter/Gather enabled: The core ignores the frame number, sending packets immediately as the packets are ready. Scatter/Gather disabled: Periodic transfer interrupt feature is enabled; the application can program transfers for multiple frames for periodic endpoints. + #1 + + + + + NakOnBble + Set NAK automatically on babble + 16 + 16 + read-write + + + EnContOnBNA + Enable continue on BNA + 17 + 17 + read-write + + + value1 + After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor. + #0 + + + value2 + After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt. + #1 + + + + + + + DSTS + Device Status Register + 0x808 + 32 + 0x00000002 + 0xFFFFFFFF + + + SuspSts + Suspend Status + 0 + 0 + read-only + + + EnumSpd + Enumerated Speed + 1 + 2 + read-only + + + value4 + Full speed (PHY clock is running at 48 MHz) + #11 + + + + + ErrticErr + Erratic Error + 3 + 3 + read-only + + + SOFFN + Frame Number of the Received SOF + 8 + 21 + read-only + + + + + DIEPMSK + Device IN Endpoint Common Interrupt Mask Register + 0x810 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferComplMsk + Transfer Completed Interrupt Mask + 0 + 0 + read-write + + + EPDisbldMsk + Endpoint Disabled Interrupt Mask + 1 + 1 + read-write + + + AHBErrMsk + AHB Error Mask + 2 + 2 + read-write + + + TimeOUTMsk + Timeout Condition Mask + 3 + 3 + read-write + + + INTknTXFEmpMsk + IN Token Received When TxFIFO Empty Mask + 4 + 4 + read-write + + + INEPNakEffMsk + IN Endpoint NAK Effective Mask + 6 + 6 + read-write + + + TxfifoUndrnMsk + Fifo Underrun Mask + 8 + 8 + read-write + + + BNAInIntrMsk + BNA Interrupt Mask + 9 + 9 + read-write + + + NAKMsk + NAK interrupt Mask + 13 + 13 + read-write + + + + + DOEPMSK + Device OUT Endpoint Common Interrupt Mask Register + 0x814 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferComplMsk + Transfer Completed Interrupt Mask + 0 + 0 + read-write + + + EPDisbldMsk + Endpoint Disabled Interrupt Mask + 1 + 1 + read-write + + + AHBErrMsk + AHB Error + 2 + 2 + read-write + + + SetUPMsk + SETUP Phase Done Mask + 3 + 3 + read-write + + + OUTTknEPdisMsk + OUT Token Received when Endpoint Disabled Mask + 4 + 4 + read-write + + + Back2BackSETup + Back-to-Back SETUP Packets Received Mask + 6 + 6 + read-write + + + OutPktErrMsk + OUT Packet Error Mask + 8 + 8 + read-write + + + BnaOutIntrMsk + BNA interrupt Mask + 9 + 9 + read-write + + + BbleErrMsk + Babble Interrupt Mask + 12 + 12 + read-write + + + NAKMsk + NAK Interrupt Mask + 13 + 13 + read-write + + + NYETMsk + NYET Interrupt Mask + 14 + 14 + read-write + + + + + DAINT + Device All Endpoints Interrupt Register + 0x818 + 32 + 0x00000000 + 0xFFFFFFFF + + + InEpInt + IN Endpoint Interrupt Bits + 0 + 15 + read-only + + + OutEPInt + OUT Endpoint Interrupt Bits + 16 + 31 + read-only + + + + + DAINTMSK + Device All Endpoints Interrupt Mask Register + 0x81C + 32 + 0x00000000 + 0xFFFFFFFF + + + InEpMsk + IN EP Interrupt Mask Bits + 0 + 15 + read-write + + + OutEpMsk + OUT EP Interrupt Mask Bits + 16 + 31 + read-write + + + + + DVBUSDIS + Device VBUS Discharge Time Register + 0x828 + 32 + 0x000017D7 + 0xFFFFFFFF + + + DVBUSDis + Device Vbus Discharge Time + 0 + 15 + read-write + + + + + DVBUSPULSE + Device VBUS Pulsing Time Register + 0x82C + 32 + 0x000005B8 + 0xFFFFFFFF + + + DVBUSPulse + Device Vbus Pulsing Time + 0 + 11 + read-write + + + + + DIEPEMPMSK + Device IN Endpoint FIFO Empty Interrupt Mask Register + 0x834 + 32 + 0x00000000 + 0xFFFFFFFF + + + InEpTxfEmpMsk + IN EP Tx FIFO Empty Interrupt Mask Bits + 0 + 15 + read-write + + + + + PCGCCTL + Power and Clock Gating Control Register + 0xE00 + 32 + 0x00000100 + 0xFFFFFFFF + + + StopPclk + Stop Pclk + 0 + 0 + read-write + + + GateHclk + Gate Hclk + 1 + 1 + read-write + + + + + + + USB0_EP0 + Universal Serial Bus + USB + 0x50040900 + + 0x0 + 0x0400 + registers + + + + DIEPCTL0 + Device Control IN Endpoint Control Register + 0x000 + 32 + 0x00008000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 1 + read-write + + + value1 + 64 bytes + #00 + + + value2 + 32 bytes + #01 + + + value3 + 16 bytes + #10 + + + value4 + 8 bytes + #11 + + + + + USBActEP + USB Active Endpoint + 15 + 15 + read-only + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-only + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DIEPINT0 + Device Endpoint Interrupt Register + 0x008 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + TimeOUT + Timeout Condition + 3 + 3 + read-write + + + INTknTXFEmp + IN Token Received When TxFIFO is Empty + 4 + 4 + read-write + + + INEPNakEff + IN Endpoint NAK Effective + 6 + 6 + read-write + + + TxFEmp + Transmit FIFO Empty + 7 + 7 + read-only + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + + + DIEPTSIZ0 + Device IN Endpoint Transfer Size Register + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 6 + read-write + + + PktCnt + Packet Count + 19 + 20 + read-write + + + + + DIEPDMA0 + Device Endpoint DMA Address Register + 0x014 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DTXFSTS0 + Device IN Endpoint Transmit FIFO Status Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + INEPTxFSpcAvail + IN Endpoint TxFIFO Space Avail + 0 + 15 + read-only + + + value1 + Endpoint TxFIFO is full + 0x0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + + + DIEPDMAB0 + Device Endpoint DMA Buffer Address Register + 0x01C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + DOEPCTL0 + Device Control OUT Endpoint Control Register + 0x200 + 32 + 0x00008000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 1 + read-only + + + value1 + 64 bytes + #00 + + + value2 + 32 bytes + #01 + + + value3 + 16 bytes + #10 + + + value4 + 8 bytes + #11 + + + + + USBActEP + USB Active Endpoint + 15 + 15 + read-only + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-only + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-only + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DOEPINT0 + Device Endpoint Interrupt Register + 0x208 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + SetUp + SETUP Phase Done + 3 + 3 + read-write + + + OUTTknEPdis + OUT Token Received When Endpoint Disabled + 4 + 4 + read-write + + + StsPhseRcvd + Status Phase Received For Control Write + 5 + 5 + read-write + + + Back2BackSETup + Back-to-Back SETUP Packets Received + 6 + 6 + read-write + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + PktDrpSts + Packet Dropped Status + 11 + 11 + read-write + + + BbleErrIntrpt + BbleErr (Babble Error) interrupt + 12 + 12 + read-write + + + NAKIntrpt + NAK interrupt + 13 + 13 + read-write + + + NYETIntrpt + NYET interrupt + 14 + 14 + read-write + + + + + DOEPTSIZ0 + Device OUT Endpoint Transfer Size Register + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 6 + read-write + + + PktCnt + Packet Count + 19 + 20 + read-write + + + SUPCnt + SETUP Packet Count + 29 + 30 + read-write + + + value1 + 1 packet + #01 + + + value2 + 2 packets + #10 + + + value3 + 3 packets + #11 + + + + + + + DOEPDMA0 + Device Endpoint DMA Address Register + 0x214 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DOEPDMAB0 + Device Endpoint DMA Buffer Address Register + 0x21C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + + + USB0_EP1 + Universal Serial Bus + USB + USB_EP + 0x50040920 + + 0x0 + 0x0400 + registers + + + + DIEPCTL_ISOCONT + Device Endpoint Control Register [ISOCONT] + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + EO_FrNum + Even/Odd Frame + 16 + 16 + read-only + + + value1 + Even frame + #0 + + + value2 + Odd rame + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetEvenFr + In non-Scatter/Gather DMA mode: Set Even frame + 28 + 28 + write-only + + + SetOddFr + Set Odd frame + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DIEPCTL_INTBULK + Device Endpoint Control Register [INTBULK] + DIEPCTL_ISOCONT + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + DPID + Endpoint Data PID + 16 + 16 + read-only + + + value1 + DATA0 + #0 + + + value2 + DATA1 + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetD0PID + Set DATA0 PID + 28 + 28 + write-only + + + SetD1PID + 29 Set DATA1 PID + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DIEPINT + Device Endpoint Interrupt Register + 0x008 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + TimeOUT + Timeout Condition + 3 + 3 + read-write + + + INTknTXFEmp + IN Token Received When TxFIFO is Empty + 4 + 4 + read-write + + + INEPNakEff + IN Endpoint NAK Effective + 6 + 6 + read-write + + + TxFEmp + Transmit FIFO Empty + 7 + 7 + read-only + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + + + DIEPTSIZ + Device Endpoint Transfer Size Register + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + + + DIEPDMA + Device Endpoint DMA Address Register + 0x014 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DTXFSTS + Device IN Endpoint Transmit FIFO Status Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + INEPTxFSpcAvail + IN Endpoint TxFIFO Space Avail + 0 + 15 + read-only + + + value1 + Endpoint TxFIFO is full + 0x0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + + + DIEPDMAB + Device Endpoint DMA Buffer Address Register + 0x01C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + DOEPCTL_ISOCONT + Device Endpoint Control Register [ISOCONT] + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + EO_FrNum + Even/Odd Frame + 16 + 16 + read-only + + + value1 + Even frame + #0 + + + value2 + Odd rame + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetEvenFr + In non-Scatter/Gather DMA mode: Set Even frame + 28 + 28 + write-only + + + SetOddFr + Set Odd frame + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DOEPCTL_INTBULK + Device Endpoint Control Register [INTBULK] + DOEPCTL_ISOCONT + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + DPID + Endpoint Data PID + 16 + 16 + read-only + + + value1 + DATA0 + #0 + + + value2 + DATA1 + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetD0PID + Set DATA0 PID + 28 + 28 + write-only + + + SetD1PID + 29 Set DATA1 PID + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DOEPINT + Device Endpoint Interrupt Register + 0x208 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + SetUp + SETUP Phase Done + 3 + 3 + read-write + + + OUTTknEPdis + OUT Token Received When Endpoint Disabled + 4 + 4 + read-write + + + StsPhseRcvd + Status Phase Received For Control Write + 5 + 5 + read-write + + + Back2BackSETup + Back-to-Back SETUP Packets Received + 6 + 6 + read-write + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + PktDrpSts + Packet Dropped Status + 11 + 11 + read-write + + + BbleErrIntrpt + BbleErr (Babble Error) interrupt + 12 + 12 + read-write + + + NAKIntrpt + NAK interrupt + 13 + 13 + read-write + + + NYETIntrpt + NYET interrupt + 14 + 14 + read-write + + + + + DOEPTSIZ_ISO + Device Endpoint Transfer Size Register [ISO] + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + RxDPID + Received Data PID + 29 + 30 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA2 + #01 + + + value3 + DATA1 + #10 + + + value4 + MDATA + #11 + + + + + + + DOEPTSIZ_CONTROL + Device Endpoint Transfer Size Register [CONT] + DOEPTSIZ_ISO + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + SUPCnt + SETUP Packet Count: 0b00=1 packet, 0b00=2 packets, 0b00=3 packets, + 29 + 30 + read-write + + + + + DOEPDMA + Device Endpoint DMA Address Register + 0x214 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DOEPDMAB + Device Endpoint DMA Buffer Address Register + 0x21C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + + + USB0_EP2 + Universal Serial Bus + USB + 0x50040940 + + 0x0 + 0x0400 + registers + + + + USB0_EP3 + Universal Serial Bus + USB + 0x50040960 + + 0x0 + 0x0400 + registers + + + + USB0_EP4 + Universal Serial Bus + USB + 0x50040980 + + 0x0 + 0x0400 + registers + + + + USB0_EP5 + Universal Serial Bus + USB + 0x500409A0 + + 0x0 + 0x0400 + registers + + + + USB0_EP6 + Universal Serial Bus + USB + 0x500409C0 + + 0x0 + 0x0400 + registers + + + + USB0_CH0 + Universal Serial Bus + USB + USB_CH + 0x50040500 + + 0x0 + 0x20 + registers + + + + HCCHAR + Host Channel Characteristics Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + EPNum + Endpoint Number + 11 + 14 + read-write + + + EPDir + Endpoint Direction + 15 + 15 + read-write + + + value1 + OUT + #0 + + + value2 + IN + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + MC_EC + Multi Count / Error Count + 20 + 21 + read-write + + + value2 + 1 transaction + #01 + + + value3 + 2 transactions to be issued for this endpoint per frame + #10 + + + value4 + 3 transactions to be issued for this endpoint per frame + #11 + + + + + DevAddr + Device Address + 22 + 28 + read-write + + + OddFrm + Odd Frame + 29 + 29 + read-write + + + value1 + Even frame + #0 + + + value2 + Odd frame + #1 + + + + + ChDis + Channel Disable + 30 + 30 + read-write + + + ChEna + Channel Enable + 31 + 31 + read-write + + + value1 + Scatter/Gather mode enabled: Indicates that the descriptor structure is not yet ready. Scatter/Gather mode disabled: Channel disabled + #0 + + + value2 + Scatter/Gather mode enabled: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor. Scatter/Gather mode disabled: Channel enabled + #1 + + + + + + + HCINT + Host Channel Interrupt Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferCompl + Transfer Completed + 0 + 0 + read-write + + + ChHltd + Channel Halted + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + STALL + STALL Response Received Interrupt + 3 + 3 + read-write + + + NAK + NAK Response Received Interrupt + 4 + 4 + read-write + + + ACK + ACK Response Received/Transmitted Interrupt + 5 + 5 + read-write + + + NYET + NYET Response Received Interrupt + 6 + 6 + read-write + + + XactErr + Transaction Error + 7 + 7 + read-write + + + BblErr + Babble Error + 8 + 8 + read-write + + + FrmOvrun + Frame Overrun + 9 + 9 + read-write + + + DataTglErr + Data Toggle Error + 10 + 10 + read-write + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 11 + 11 + read-write + + + XCS_XACT_ERR + Excessive Transaction Error + 12 + 12 + read-write + + + DESC_LST_ROLLIntr + Descriptor rollover interrupt + 13 + 13 + read-write + + + + + HCINTMSK + Host Channel Interrupt Mask Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + XferComplMsk + Transfer Completed Mask + 0 + 0 + read-write + + + ChHltdMsk + Channel Halted Mask + 1 + 1 + read-write + + + AHBErrMsk + AHB Error Mask + 2 + 2 + read-write + + + StallMsk + STALL Response Received Interrupt Mask + 3 + 3 + read-write + + + NakMsk + NAK Response Received Interrupt Mask + 4 + 4 + read-write + + + AckMsk + ACK Response Received/Transmitted Interrupt Mask + 5 + 5 + read-write + + + NyetMsk + NYET Response Received Interrupt Mask + 6 + 6 + read-write + + + XactErrMsk + Transaction Error Mask + 7 + 7 + read-write + + + BblErrMsk + Babble Error Mask + 8 + 8 + read-write + + + FrmOvrunMsk + Frame Overrun Mask + 9 + 9 + read-write + + + DataTglErrMsk + Data Toggle Error Mask + 10 + 10 + read-write + + + BNAIntrMsk + BNA (Buffer Not Available) Interrupt mask register + 11 + 11 + read-write + + + DESC_LST_ROLLIntrMsk + Descriptor rollover interrupt Mask register + 13 + 13 + read-write + + + + + HCTSIZ_BUFFERMODE + Host Channel Transfer Size Register [BUFFERMODE] + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + Pid + PID + 29 + 30 + read-write + + + value1 + DATA0 + #00 + + + value2 + DATA2 + #01 + + + value3 + DATA1 + #10 + + + value4 + MDATA (non-control)/SETUP (control) + #11 + + + + + + + HCTSIZ_SCATGATHER + Host Channel Transfer Size Register [SCATGATHER] + HCTSIZ_BUFFERMODE + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCHED_INFO + Schedule information + 0 + 7 + read-write + + + NTD + Number of Transfer Descriptors: 0=1 descriptor, 63=64 descriptors, 1=2 descriptors, 3=4 descriptors, 7=8 descriptors, 15=16 descriptors, 31=32 descriptors, 63=64 descriptors, + 8 + 15 + read-write + + + Pid + PID + 29 + 30 + read-write + + + value1 + DATA0 + #00 + + + value2 + DATA2 + #01 + + + value3 + DATA1 + #10 + + + value4 + MDATA (non-control) + #11 + + + + + + + HCDMA_BUFFERMODE + Host Channel DMA Address Register [BUFFERMODE] + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + HCDMA_SCATGATHER + Host Channel DMA Address Register [SCATGATHER] + HCDMA_BUFFERMODE + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CTD + Current Transfer Desc: + 3 + 8 + read-write + + + value1 + 1 descriptor + 0 + + + value2 + 64 descriptors + 63 + + + + + DMAAddr + DMA Address + 9 + 31 + read-write + + + + + HCDMAB + Host Channel DMA Buffer Address Register + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + Buffer_Address + Buffer Address + 0 + 31 + read-only + + + + + + + USB0_CH1 + Universal Serial Bus + USB + 0x50040520 + + 0x0 + 0x20 + registers + + + + USB0_CH2 + Universal Serial Bus + USB + 0x50040540 + + 0x0 + 0x20 + registers + + + + USB0_CH3 + Universal Serial Bus + USB + 0x50040560 + + 0x0 + 0x20 + registers + + + + USB0_CH4 + Universal Serial Bus + USB + 0x50040580 + + 0x0 + 0x20 + registers + + + + USB0_CH5 + Universal Serial Bus + USB + 0x500405A0 + + 0x0 + 0x20 + registers + + + + USB0_CH6 + Universal Serial Bus + USB + 0x500405C0 + + 0x0 + 0x20 + registers + + + + USB0_CH7 + Universal Serial Bus + USB + 0x500405E0 + + 0x0 + 0x20 + registers + + + + USB0_CH8 + Universal Serial Bus + USB + 0x50040600 + + 0x0 + 0x20 + registers + + + + USB0_CH9 + Universal Serial Bus + USB + 0x50040620 + + 0x0 + 0x20 + registers + + + + USB0_CH10 + Universal Serial Bus + USB + 0x50040640 + + 0x0 + 0x20 + registers + + + + USB0_CH11 + Universal Serial Bus + USB + 0x50040660 + + 0x0 + 0x20 + registers + + + + USB0_CH12 + Universal Serial Bus + USB + 0x50040680 + + 0x0 + 0x20 + registers + + + + USB0_CH13 + Universal Serial Bus + USB + 0x500406A0 + + 0x0 + 0x20 + registers + + + + USIC0 + Universal Serial Interface Controller 0 + USIC + USIC + 0x40030008 + + 0 + 4 + registers + + + USIC0_0 + Universal Serial Interface Channel (Module 0) + 84 + + + USIC0_1 + Universal Serial Interface Channel (Module 0) + 85 + + + USIC0_2 + Universal Serial Interface Channel (Module 0) + 86 + + + USIC0_3 + Universal Serial Interface Channel (Module 0) + 87 + + + USIC0_4 + Universal Serial Interface Channel (Module 0) + 88 + + + USIC0_5 + Universal Serial Interface Channel (Module 0) + 89 + + + + ID + Module Identification Register + 0 + 32 + 0x00AAC000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + + + USIC1 + Universal Serial Interface Controller 1 + USIC + 0x48020008 + + 0 + 4 + registers + + + USIC1_0 + Universal Serial Interface Channel (Module 1) + 90 + + + USIC1_1 + Universal Serial Interface Channel (Module 1) + 91 + + + USIC1_2 + Universal Serial Interface Channel (Module 1) + 92 + + + USIC1_3 + Universal Serial Interface Channel (Module 1) + 93 + + + USIC1_4 + Universal Serial Interface Channel (Module 1) + 94 + + + USIC1_5 + Universal Serial Interface Channel (Module 1) + 95 + + + + USIC2 + Universal Serial Interface Controller 2 + USIC + 0x48024008 + + 0 + 4 + registers + + + USIC2_0 + Universal Serial Interface Channel (Module 2) + 96 + + + USIC2_1 + Universal Serial Interface Channel (Module 2) + 97 + + + USIC2_2 + Universal Serial Interface Channel (Module 2) + 98 + + + USIC2_3 + Universal Serial Interface Channel (Module 2) + 99 + + + USIC2_4 + Universal Serial Interface Channel (Module 2) + 100 + + + USIC2_5 + Universal Serial Interface Channel (Module 2) + 101 + + + + USIC0_CH0 + Universal Serial Interface Controller 0 + USIC + USIC_CH + 0x40030000 + + 0x0 + 0x0200 + registers + + + + CCFG + Channel Configuration Register + 0x004 + 32 + 0x000000CF + 0xFFFFFFFF + + + SSC + SSC Protocol Available + 0 + 0 + read-only + + + value1 + The SSC protocol is not available. + #0 + + + value2 + The SSC protocol is available. + #1 + + + + + ASC + ASC Protocol Available + 1 + 1 + read-only + + + value1 + The ASC protocol is not available. + #0 + + + value2 + The ASC protocol is available. + #1 + + + + + IIC + IIC Protocol Available + 2 + 2 + read-only + + + value1 + The IIC protocol is not available. + #0 + + + value2 + The IIC protocol is available. + #1 + + + + + IIS + IIS Protocol Available + 3 + 3 + read-only + + + value1 + The IIS protocol is not available. + #0 + + + value2 + The IIS protocol is available. + #1 + + + + + RB + Receive FIFO Buffer Available + 6 + 6 + read-only + + + value1 + A receive FIFO buffer is not available. + #0 + + + value2 + A receive FIFO buffer is available. + #1 + + + + + TB + Transmit FIFO Buffer Available + 7 + 7 + read-only + + + value1 + A transmit FIFO buffer is not available. + #0 + + + value2 + A transmit FIFO buffer is available. + #1 + + + + + + + KSCFG + Kernel State Configuration Register + 0x00C + 32 + 0x00000000 + 0xFFFFFFFF + + + MODEN + Module Enable + 0 + 0 + read-write + + + value1 + The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). + #0 + + + value2 + The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other Service Request Processing registers. + #1 + + + + + BPMODEN + Bit Protection for MODEN + 1 + 1 + write-only + + + value1 + MODEN is not changed. + #0 + + + value2 + MODEN is updated with the written value. + #1 + + + + + NOMCFG + Normal Operation Mode Configuration + 4 + 5 + read-write + + + value1 + Run mode 0 is selected. + #00 + + + value2 + Run mode 1 is selected. + #01 + + + value3 + Stop mode 0 is selected. + #10 + + + value4 + Stop mode 1 is selected. + #11 + + + + + BPNOM + Bit Protection for NOMCFG + 7 + 7 + write-only + + + value1 + NOMCFG is not changed. + #0 + + + value2 + NOMCFG is updated with the written value. + #1 + + + + + SUMCFG + Suspend Mode Configuration + 8 + 9 + read-write + + + BPSUM + Bit Protection for SUMCFG + 11 + 11 + write-only + + + value1 + SUMCFG is not changed. + #0 + + + value2 + SUMCFG is updated with the written value. + #1 + + + + + + + FDR + Fractional Divider Register + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + STEP + Step Value + 0 + 9 + read-write + + + DM + Divider Mode + 14 + 15 + read-write + + + value1 + The divider is switched off, fFD = 0. + #00 + + + value2 + Normal divider mode selected. + #01 + + + value3 + Fractional divider mode selected. + #10 + + + value4 + The divider is switched off, fFD = 0. + #11 + + + + + RESULT + Result Value + 16 + 25 + read-only + + + + + BRG + Baud Rate Generator Register + 0x014 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLKSEL + Clock Selection + 0 + 1 + read-write + + + value1 + The fractional divider frequency fFD is selected. + #00 + + + value3 + The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. + #10 + + + value4 + Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. + #11 + + + + + TMEN + Timing Measurement Enable + 3 + 3 + read-write + + + value1 + Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored. + #0 + + + value2 + Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. + #1 + + + + + PPPEN + Enable 2:1 Divider for fPPP + 4 + 4 + read-write + + + value1 + The 2:1 divider for fPPP is disabled. fPPP = fPIN + #0 + + + value2 + The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. + #1 + + + + + CTQSEL + Input Selection for CTQ + 6 + 7 + read-write + + + value1 + fCTQIN = fPDIV + #00 + + + value2 + fCTQIN = fPPP + #01 + + + value3 + fCTQIN = fSCLK + #10 + + + value4 + fCTQIN = fMCLK + #11 + + + + + PCTQ + Pre-Divider for Time Quanta Counter + 8 + 9 + read-write + + + DCTQ + Denominator for Time Quanta Counter + 10 + 14 + read-write + + + PDIV + Divider Mode: Divider Factor to Generate fPDIV + 16 + 25 + read-write + + + SCLKOSEL + Shift Clock Output Select + 28 + 28 + read-write + + + value1 + SCLK from the baud rate generator is selected as the SCLKOUT input source. + #0 + + + value2 + The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. + #1 + + + + + MCLKCFG + Master Clock Configuration + 29 + 29 + read-write + + + value1 + The passive level is 0. + #0 + + + value2 + The passive level is 1. + #1 + + + + + SCLKCFG + Shift Clock Output Configuration + 30 + 31 + read-write + + + value1 + The passive level is 0 and the delay is disabled. + #00 + + + value2 + The passive level is 1 and the delay is disabled. + #01 + + + value3 + The passive level is 0 and the delay is enabled. + #10 + + + value4 + The passive level is 1 and the delay is enabled. + #11 + + + + + + + INPR + Interrupt Node Pointer Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSINP + Transmit Shift Interrupt Node Pointer + 0 + 2 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + TBINP + Transmit Buffer Interrupt Node Pointer + 4 + 6 + read-write + + + RINP + Receive Interrupt Node Pointer + 8 + 10 + read-write + + + AINP + Alternative Receive Interrupt Node Pointer + 12 + 14 + read-write + + + PINP + Transmit Shift Interrupt Node Pointer + 16 + 18 + read-write + + + + + DX0CR + Input Control Register 0 + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX1CR + Input Control Register 1 + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DX1A is selected. + #000 + + + value2 + The data input DX1B is selected. + #001 + + + value3 + The data input DX1C is selected. + #010 + + + value4 + The data input DX1D is selected. + #011 + + + value5 + The data input DX1E is selected. + #100 + + + value6 + The data input DX1F is selected. + #101 + + + value7 + The data input DX1G is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + DCEN + Delay Compensation Enable + 3 + 3 + read-write + + + value1 + The receive shift clock is dependent on INSW selection. + #0 + + + value2 + The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. + #1 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DX1T. + #01 + + + value3 + A falling edge activates DX1T. + #10 + + + value4 + Both edges activate DX1T. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DX1S is 0. + #0 + + + value2 + The current value of DX1S is 1. + #1 + + + + + + + DX2CR + Input Control Register 2 + 0x024 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX3CR + Input Control Register 3 + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX4CR + Input Control Register 4 + 0x02C + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX5CR + Input Control Register 5 + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + SCTR + Shift Control Register + 0x034 + 32 + 0x00000000 + 0xFFFFFFFF + + + SDIR + Shift Direction + 0 + 0 + read-write + + + value1 + Shift LSB first. The first data bit of a data word is located at bit position 0. + #0 + + + value2 + Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE. + #1 + + + + + PDL + Passive Data Level + 1 + 1 + read-write + + + value1 + The passive data level is 0. + #0 + + + value2 + The passive data level is 1. + #1 + + + + + DSM + Data Shift Mode + 2 + 3 + read-write + + + value1 + Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0. + #00 + + + value3 + Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively. + #10 + + + value4 + Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively. + #11 + + + + + HPCDIR + Port Control Direction + 4 + 4 + read-write + + + value1 + The pin(s) with hardware pin control enabled are selected to be in input mode. + #0 + + + value2 + The pin(s) with hardware pin control enabled are selected to be in output mode. + #1 + + + + + DOCFG + Data Output Configuration + 6 + 7 + read-write + + + value1 + DOUTx = shift data value + #00 + + + value2 + DOUTx = inverted shift data value + #01 + + + + + TRM + Transmission Mode + 8 + 9 + read-write + + + value1 + The shift control signal is considered as inactive and data frame transfers are not possible. + #00 + + + value2 + The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. + #01 + + + value3 + The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. + #10 + + + value4 + The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. + #11 + + + + + FLE + Frame Length + 16 + 21 + read-write + + + WLE + Word Length + 24 + 27 + read-write + + + value1 + The data word contains 1 data bit located at bit position 0. + 0x0 + + + value2 + The data word contains 2 data bits located at bit positions [1:0]. + 0x1 + + + value3 + The data word contains 15 data bits located at bit positions [14:0]. + 0xE + + + value4 + The data word contains 16 data bits located at bit positions [15:0]. + 0xF + + + + + + + TCSR + Transmit Control/Status Register + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLEMD + WLE Mode + 0 + 0 + read-write + + + value1 + The automatic update of SCTR.WLE and TCSR.EOF is disabled. + #0 + + + value2 + The automatic update of SCTR.WLE and TCSR.EOF is enabled. + #1 + + + + + SELMD + Select Mode + 1 + 1 + read-write + + + value1 + The automatic update of PCR.CTR[23:16] is disabled. + #0 + + + value2 + The automatic update of PCR.CTR[23:16] is disabled. + #1 + + + + + FLEMD + FLE Mode + 2 + 2 + read-write + + + value1 + The automatic update of FLE is disabled. + #0 + + + value2 + The automatic update of FLE is enabled. + #1 + + + + + WAMD + WA Mode + 3 + 3 + read-write + + + value1 + The automatic update of bit WA is disabled. + #0 + + + value2 + The automatic update of bit WA is enabled. + #1 + + + + + HPCMD + Hardware Port Control Mode + 4 + 4 + read-write + + + value1 + The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled. + #0 + + + value2 + The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled. + #1 + + + + + SOF + Start Of Frame + 5 + 5 + read-write + + + value1 + The data word in TBUF is not considered as first word of a frame. + #0 + + + value2 + The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). + #1 + + + + + EOF + End Of Frame + 6 + 6 + read-write + + + value1 + The data word in TBUF is not considered as last word of an SSC frame. + #0 + + + value2 + The data word in TBUF is considered as last word of an SSC frame. + #1 + + + + + TDV + Transmit Data Valid + 7 + 7 + read-only + + + value1 + The data word in TBUF is not valid for transmission. + #0 + + + value2 + The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. + #1 + + + + + TDSSM + TBUF Data Single Shot Mode + 8 + 8 + read-write + + + value1 + The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. + #0 + + + value2 + The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. + #1 + + + + + TDEN + TBUF Data Enable + 10 + 11 + read-write + + + value1 + A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. + #00 + + + value2 + A transmission of the data word in TBUF can be started if TDV = 1. + #01 + + + value3 + A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. + #10 + + + value4 + A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. + #11 + + + + + TDVTR + TBUF Data Valid Trigger + 12 + 12 + read-write + + + value1 + Bit TCSR.TE is permanently set. + #0 + + + value2 + Bit TCSR.TE is set if DX2T becomes active while TDV = 1. + #1 + + + + + WA + Word Address + 13 + 13 + read-write + + + value1 + The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA). + #0 + + + value2 + The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA). + #1 + + + + + TSOF + Transmitted Start Of Frame + 24 + 24 + read-only + + + value1 + The latest data word transmission has not been started for the first word of a data frame. + #0 + + + value2 + The latest data word transmission has been started for the first word of a data frame. + #1 + + + + + TV + Transmission Valid + 26 + 26 + read-only + + + value1 + The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started. + #0 + + + value2 + The latest start of a data word transmission has taken place with valid data from TBUF. + #1 + + + + + TVC + Transmission Valid Cumulated + 27 + 27 + read-only + + + value1 + Since TVC has been set, at least one data buffer underflow condition has occurred. + #0 + + + value2 + Since TVC has been set, no data buffer underflow condition has occurred. + #1 + + + + + TE + Trigger Event + 28 + 28 + read-only + + + value1 + The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started. + #0 + + + value2 + The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can not be started. + #1 + + + + + + + PCR + Protocol Control Register + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + CTR0 + Protocol Control Bit 0 + 0 + 0 + read-write + + + CTR1 + Protocol Control Bit 1 + 1 + 1 + read-write + + + CTR2 + Protocol Control Bit 2 + 2 + 2 + read-write + + + CTR3 + Protocol Control Bit 3 + 3 + 3 + read-write + + + CTR4 + Protocol Control Bit 4 + 4 + 4 + read-write + + + CTR5 + Protocol Control Bit 5 + 5 + 5 + read-write + + + CTR6 + Protocol Control Bit 6 + 6 + 6 + read-write + + + CTR7 + Protocol Control Bit 7 + 7 + 7 + read-write + + + CTR8 + Protocol Control Bit 8 + 8 + 8 + read-write + + + CTR9 + Protocol Control Bit 9 + 9 + 9 + read-write + + + CTR10 + Protocol Control Bit 10 + 10 + 10 + read-write + + + CTR11 + Protocol Control Bit 11 + 11 + 11 + read-write + + + CTR12 + Protocol Control Bit 12 + 12 + 12 + read-write + + + CTR13 + Protocol Control Bit 13 + 13 + 13 + read-write + + + CTR14 + Protocol Control Bit 14 + 14 + 14 + read-write + + + CTR15 + Protocol Control Bit 15 + 15 + 15 + read-write + + + CTR16 + Protocol Control Bit 16 + 16 + 16 + read-write + + + CTR17 + Protocol Control Bit 17 + 17 + 17 + read-write + + + CTR18 + Protocol Control Bit 18 + 18 + 18 + read-write + + + CTR19 + Protocol Control Bit 19 + 19 + 19 + read-write + + + CTR20 + Protocol Control Bit 20 + 20 + 20 + read-write + + + CTR21 + Protocol Control Bit 21 + 21 + 21 + read-write + + + CTR22 + Protocol Control Bit 22 + 22 + 22 + read-write + + + CTR23 + Protocol Control Bit 23 + 23 + 23 + read-write + + + CTR24 + Protocol Control Bit 24 + 24 + 24 + read-write + + + CTR25 + Protocol Control Bit 25 + 25 + 25 + read-write + + + CTR26 + Protocol Control Bit 26 + 26 + 26 + read-write + + + CTR27 + Protocol Control Bit 27 + 27 + 27 + read-write + + + CTR28 + Protocol Control Bit 28 + 28 + 28 + read-write + + + CTR29 + Protocol Control Bit 29 + 29 + 29 + read-write + + + CTR30 + Protocol Control Bit 30 + 30 + 30 + read-write + + + CTR31 + Protocol Control Bit 31 + 31 + 31 + read-write + + + + + PCR_ASCMode + Protocol Control Register [ASC Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + SMD + Sample Mode + 0 + 0 + read-write + + + value1 + Only one sample is taken per bit time. The current input value is sampled. + #0 + + + value2 + Three samples are taken per bit time and a majority decision is made. + #1 + + + + + STPB + Stop Bits + 1 + 1 + read-write + + + value1 + The number of stop bits is 1. + #0 + + + value2 + The number of stop bits is 2. + #1 + + + + + IDM + Idle Detection Mode + 2 + 2 + read-write + + + value1 + The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. + #0 + + + value2 + The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). + #1 + + + + + SBIEN + Synchronization Break Interrupt Enable + 3 + 3 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + CDEN + Collision Detection Enable + 4 + 4 + read-write + + + value1 + The collision detection is disabled. + #0 + + + value2 + If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software. + #1 + + + + + RNIEN + Receiver Noise Detection Interrupt Enable + 5 + 5 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + FEIEN + Format Error Interrupt Enable + 6 + 6 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + FFIEN + Frame Finished Interrupt Enable + 7 + 7 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + SP + Sample Point + 8 + 12 + read-write + + + PL + Pulse Length + 13 + 15 + read-write + + + value1 + The pulse length is equal to the bit length (no shortened 0). + #000 + + + value2 + The pulse length of a 0 bit is 2 time quanta. + #001 + + + value3 + The pulse length of a 0 bit is 3 time quanta. + #010 + + + value4 + The pulse length of a 0 bit is 8 time quanta. + #111 + + + + + RSTEN + Receiver Status Enable + 16 + 16 + read-write + + + value1 + Flag PSR[9] is not modified depending on the receiver status. + #0 + + + value2 + Flag PSR[9] is set during the complete reception of a frame. + #1 + + + + + TSTEN + Transmitter Status Enable + 17 + 17 + read-write + + + value1 + Flag PSR[9] is not modified depending on the transmitter status. + #0 + + + value2 + Flag PSR[9] is set during the complete transmission of a frame. + #1 + + + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and the MCLK signal is 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + PCR_SSCMode + Protocol Control Register [SSC Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + MSLSEN + MSLS Enable + 0 + 0 + read-write + + + value1 + The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. + #0 + + + value2 + The MSLS generation is enabled. This is the setting for SSC master mode. + #1 + + + + + SELCTR + Select Control + 1 + 1 + read-write + + + value1 + The coded select mode is enabled. + #0 + + + value2 + The direct select mode is enabled. + #1 + + + + + SELINV + Select Inversion + 2 + 2 + read-write + + + value1 + The SELO outputs have the same polarity as the MSLS signal (active high). + #0 + + + value2 + The SELO outputs have the inverted polarity to the MSLS signal (active low). + #1 + + + + + FEM + Frame End Mode + 3 + 3 + read-write + + + value1 + The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). + #0 + + + value2 + The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. + #1 + + + + + CTQSEL1 + Input Frequency Selection + 4 + 5 + read-write + + + value1 + fCTQIN = fPDIV + #00 + + + value2 + fCTQIN = fPPP + #01 + + + value3 + fCTQIN = fSCLK + #10 + + + value4 + fCTQIN = fMCLK + #11 + + + + + PCTQ1 + Divider Factor PCTQ1 for Tiw and Tnf + 6 + 7 + read-write + + + DCTQ1 + Divider Factor DCTQ1 for Tiw and Tnf + 8 + 12 + read-write + + + PARIEN + Parity Error Interrupt Enable + 13 + 13 + read-write + + + value1 + A protocol interrupt is not generated with the detection of a parity error. + #0 + + + value2 + A protocol interrupt is generated with the detection of a parity error. + #1 + + + + + MSLSIEN + MSLS Interrupt Enable + 14 + 14 + read-write + + + value1 + A protocol interrupt is not generated if a change of signal MSLS is detected. + #0 + + + value2 + A protocol interrupt is generated if a change of signal MSLS is detected. + #1 + + + + + DX2TIEN + DX2T Interrupt Enable + 15 + 15 + read-write + + + value1 + A protocol interrupt is not generated if DX2T is activated. + #0 + + + value2 + A protocol interrupt is generated if DX2T is activated. + #1 + + + + + SELO + Select Output + 16 + 23 + read-write + + + value1 + The corresponding SELOx line cannot be activated. + #0 + + + value2 + The corresponding SELOx line can be activated (according to the mode selected by SELCTR). + #1 + + + + + TIWEN + Enable Inter-Word Delay Tiw + 24 + 24 + read-write + + + value1 + No delay between data words of the same frame. + #0 + + + value2 + The inter-word delay Tiw is enabled and introduced between data words of the same frame. + #1 + + + + + SLPHSEL + Slave Mode Clock Phase Select + 25 + 25 + read-write + + + value1 + Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge. + 0b0 + + + value2 + The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge. + 0b1 + + + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and output MCLK = 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + PCR_IICMode + Protocol Control Register [IIC Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + SLAD + Slave Address + 0 + 15 + read-write + + + ACK00 + Acknowledge 00H + 16 + 16 + read-write + + + value1 + The slave device is not sensitive to this address. + #0 + + + value2 + The slave device is sensitive to this address. + #1 + + + + + STIM + Symbol Timing + 17 + 17 + read-write + + + value1 + A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud). + #0 + + + value2 + A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud). + #1 + + + + + SCRIEN + Start Condition Received Interrupt Enable + 18 + 18 + read-write + + + value1 + The start condition interrupt is disabled. + #0 + + + value2 + The start condition interrupt is enabled. + #1 + + + + + RSCRIEN + Repeated Start Condition Received Interrupt Enable + 19 + 19 + read-write + + + value1 + The repeated start condition interrupt is disabled. + #0 + + + value2 + The repeated start condition interrupt is enabled. + #1 + + + + + PCRIEN + Stop Condition Received Interrupt Enable + 20 + 20 + read-write + + + value1 + The stop condition interrupt is disabled. + #0 + + + value2 + The stop condition interrupt is enabled. + #1 + + + + + NACKIEN + Non-Acknowledge Interrupt Enable + 21 + 21 + read-write + + + value1 + The non-acknowledge interrupt is disabled. + #0 + + + value2 + The non-acknowledge interrupt is enabled. + #1 + + + + + ARLIEN + Arbitration Lost Interrupt Enable + 22 + 22 + read-write + + + value1 + The arbitration lost interrupt is disabled. + #0 + + + value2 + The arbitration lost interrupt is enabled. + #1 + + + + + SRRIEN + Slave Read Request Interrupt Enable + 23 + 23 + read-write + + + value1 + The slave read request interrupt is disabled. + #0 + + + value2 + The slave read request interrupt is enabled. + #1 + + + + + ERRIEN + Error Interrupt Enable + 24 + 24 + read-write + + + value1 + The error interrupt is disabled. + #0 + + + value2 + The error interrupt is enabled. + #1 + + + + + SACKDIS + Slave Acknowledge Disable + 25 + 25 + read-write + + + value1 + The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received). + #0 + + + value2 + The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped). + #1 + + + + + HDEL + Hardware Delay + 26 + 29 + read-write + + + ACKIEN + Acknowledge Interrupt Enable + 30 + 30 + read-write + + + value1 + The acknowledge interrupt is disabled. + #0 + + + value2 + The acknowledge interrupt is enabled. + #1 + + + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and MCLK is 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + PCR_IISMode + Protocol Control Register [IIS Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + WAGEN + WA Generation Enable + 0 + 0 + read-write + + + value1 + The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. + #0 + + + value2 + The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. + #1 + + + + + DTEN + Data Transfers Enable + 1 + 1 + read-write + + + value1 + The changes of the WA input signal are ignored and no transfers take place. + #0 + + + value2 + Transfers are enabled. + #1 + + + + + SELINV + Select Inversion + 2 + 2 + read-write + + + value1 + The SELOx outputs have the same polarity as the WA signal. + #0 + + + value2 + The SELOx outputs have the inverted polarity to the WA signal. + #1 + + + + + WAFEIEN + WA Falling Edge Interrupt Enable + 4 + 4 + read-write + + + value1 + A protocol interrupt is not activated if a falling edge of WA is generated. + #0 + + + value2 + A protocol interrupt is activated if a falling edge of WA is generated. + #1 + + + + + WAREIEN + WA Rising Edge Interrupt Enable + 5 + 5 + read-write + + + value1 + A protocol interrupt is not activated if a rising edge of WA is generated. + #0 + + + value2 + A protocol interrupt is activated if a rising edge of WA is generated. + #1 + + + + + ENDIEN + END Interrupt Enable + 6 + 6 + read-write + + + value1 + A protocol interrupt is not activated. + #0 + + + value2 + A protocol interrupt is activated. + #1 + + + + + DX2TIEN + DX2T Interrupt Enable + 15 + 15 + read-write + + + value1 + A protocol interrupt is not generated if DX2T is active. + #0 + + + value2 + A protocol interrupt is generated if DX2T is active. + #1 + + + + + TDEL + Transfer Delay + 16 + 21 + read-write + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and MCLK is 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + CCR + Channel Control Register + 0x040 + 32 + 0x00000000 + 0xFFFFFFFF + + + MODE + Operating Mode + 0 + 3 + read-write + + + value1 + The USIC channel is disabled. All protocol-related state machines are set to an idle state. + 0x0 + + + value2 + The SSC (SPI) protocol is selected. + 0x1 + + + value3 + The ASC (SCI, UART) protocol is selected. + 0x2 + + + value4 + The IIS protocol is selected. + 0x3 + + + value5 + The IIC protocol is selected. + 0x4 + + + + + HPCEN + Hardware Port Control Enable + 6 + 7 + read-write + + + value1 + The hardware port control is disabled. + #00 + + + value2 + The hardware port control is enabled for DX0 and DOUT0. + #01 + + + value3 + The hardware port control is enabled for DX3, DX0 and DOUT[1:0]. + #10 + + + value4 + The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0]. + #11 + + + + + PM + Parity Mode + 8 + 9 + read-write + + + value1 + The parity generation is disabled. + #00 + + + value3 + Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). + #10 + + + value4 + Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). + #11 + + + + + RSIEN + Receiver Start Interrupt Enable + 10 + 10 + read-write + + + value1 + The receiver start interrupt is disabled. + #0 + + + value2 + The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated. + #1 + + + + + DLIEN + Data Lost Interrupt Enable + 11 + 11 + read-write + + + value1 + The data lost interrupt is disabled. + #0 + + + value2 + The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated. + #1 + + + + + TSIEN + Transmit Shift Interrupt Enable + 12 + 12 + read-write + + + value1 + The transmit shift interrupt is disabled. + #0 + + + value2 + The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated. + #1 + + + + + TBIEN + Transmit Buffer Interrupt Enable + 13 + 13 + read-write + + + value1 + The transmit buffer interrupt is disabled. + #0 + + + value2 + The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated. + #1 + + + + + RIEN + Receive Interrupt Enable + 14 + 14 + read-write + + + value1 + The receive interrupt is disabled. + #0 + + + value2 + The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated. + #1 + + + + + AIEN + Alternative Receive Interrupt Enable + 15 + 15 + read-write + + + value1 + The alternative receive interrupt is disabled. + #0 + + + value2 + The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated. + #1 + + + + + BRGIEN + Baud Rate Generator Interrupt Enable + 16 + 16 + read-write + + + value1 + The baud rate generator interrupt is disabled. + #0 + + + value2 + The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated. + #1 + + + + + + + CMTR + Capture Mode Timer Register + 0x044 + 32 + 0x00000000 + 0xFFFFFFFF + + + CTV + Captured Timer Value + 0 + 9 + read-write + + + + + PSR + Protocol Status Register + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + ST0 + Protocol Status Flag 0 + 0 + 0 + read-write + + + ST1 + Protocol Status Flag 1 + 1 + 1 + read-write + + + ST2 + Protocol Status Flag 2 + 2 + 2 + read-write + + + ST3 + Protocol Status Flag 3 + 3 + 3 + read-write + + + ST4 + Protocol Status Flag 4 + 4 + 4 + read-write + + + ST5 + Protocol Status Flag 5 + 5 + 5 + read-write + + + ST6 + Protocol Status Flag 6 + 6 + 6 + read-write + + + ST7 + Protocol Status Flag 7 + 7 + 7 + read-write + + + ST8 + Protocol Status Flag 8 + 8 + 8 + read-write + + + ST9 + Protocol Status Flag 9 + 9 + 9 + read-write + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_ASCMode + Protocol Status Register [ASC Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXIDLE + Transmission Idle + 0 + 0 + read-write + + + value1 + The transmitter line has not yet been idle. + #0 + + + value2 + The transmitter line has been idle and frame transmission is possible. + #1 + + + + + RXIDLE + Reception Idle + 1 + 1 + read-write + + + value1 + The receiver line has not yet been idle. + #0 + + + value2 + The receiver line has been idle and frame reception is possible. + #1 + + + + + SBD + Synchronization Break Detected + 2 + 2 + read-write + + + value1 + A synchronization break has not yet been detected. + #0 + + + value2 + A synchronization break has been detected. + #1 + + + + + COL + Collision Detected + 3 + 3 + read-write + + + value1 + A collision has not yet been detected and frame transmission is possible. + #0 + + + value2 + A collision has been detected and frame transmission is not possible. + #1 + + + + + RNS + Receiver Noise Detected + 4 + 4 + read-write + + + value1 + Receiver noise has not been detected. + #0 + + + value2 + Receiver noise has been detected. + #1 + + + + + FER0 + Format Error in Stop Bit 0 + 5 + 5 + read-write + + + value1 + A format error 0 has not been detected. + #0 + + + value2 + A format error 0 has been detected. + #1 + + + + + FER1 + Format Error in Stop Bit 1 + 6 + 6 + read-write + + + value1 + A format error 1 has not been detected. + #0 + + + value2 + A format error 1 has been detected. + #1 + + + + + RFF + Receive Frame Finished + 7 + 7 + read-write + + + value1 + The received frame is not yet finished. + #0 + + + value2 + The received frame is finished. + #1 + + + + + TFF + Transmitter Frame Finished + 8 + 8 + read-write + + + value1 + The transmitter frame is not yet finished. + #0 + + + value2 + The transmitter frame is finished. + #1 + + + + + BUSY + Transfer Status BUSY + 9 + 9 + read-only + + + value1 + A data transfer does not take place. + #0 + + + value2 + A data transfer currently takes place. + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_SSCMode + Protocol Status Register [SSC Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + MSLS + MSLS Status + 0 + 0 + read-write + + + value1 + The internal signal MSLS is inactive (0). + #0 + + + value2 + The internal signal MSLS is active (1). + #1 + + + + + DX2S + DX2S Status + 1 + 1 + read-write + + + value1 + DX2S is 0. + #0 + + + value2 + DX2S is 1. + #1 + + + + + MSLSEV + MSLS Event Detected + 2 + 2 + read-write + + + value1 + The MSLS signal has not changed its state. + #0 + + + value2 + The MSLS signal has changed its state. + #1 + + + + + DX2TEV + DX2T Event Detected + 3 + 3 + read-write + + + value1 + The DX2T signal has not been activated. + #0 + + + value2 + The DX2T signal has been activated. + #1 + + + + + PARERR + Parity Error Event Detected + 4 + 4 + read-write + + + value1 + A parity error event has not been activated. + #0 + + + value2 + A parity error event has been activated. + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_IICMode + Protocol Status Register [IIC Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLSEL + Slave Select + 0 + 0 + read-write + + + value1 + The device is not selected as slave. + #0 + + + value2 + The device is selected as slave. + #1 + + + + + WTDF + Wrong TDF Code Found + 1 + 1 + read-write + + + value1 + A wrong TDF code has not been found. + #0 + + + value2 + A wrong TDF code has been found. + #1 + + + + + SCR + Start Condition Received + 2 + 2 + read-write + + + value1 + A start condition has not yet been detected. + #0 + + + value2 + A start condition has been detected. + #1 + + + + + RSCR + Repeated Start Condition Received + 3 + 3 + read-write + + + value1 + A repeated start condition has not yet been detected. + #0 + + + value2 + A repeated start condition has been detected. + #1 + + + + + PCR + Stop Condition Received + 4 + 4 + read-write + + + value1 + A stop condition has not yet been detected. + #0 + + + value2 + A stop condition has been detected. + #1 + + + + + NACK + Non-Acknowledge Received + 5 + 5 + read-write + + + value1 + A non-acknowledge has not been received. + #0 + + + value2 + A non-acknowledge has been received. + #1 + + + + + ARL + Arbitration Lost + 6 + 6 + read-write + + + value1 + An arbitration has not been lost. + #0 + + + value2 + An arbitration has been lost. + #1 + + + + + SRR + Slave Read Request + 7 + 7 + read-write + + + value1 + A slave read request has not been detected. + #0 + + + value2 + A slave read request has been detected. + #1 + + + + + ERR + Error + 8 + 8 + read-write + + + value1 + An IIC error has not been detected. + #0 + + + value2 + An IIC error has been detected. + #1 + + + + + ACK + Acknowledge Received + 9 + 9 + read-write + + + value1 + An acknowledge has not been received. + #0 + + + value2 + An acknowledge has been received. + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_IISMode + Protocol Status Register [IIS Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + WA + Word Address + 0 + 0 + read-write + + + value1 + WA has been sampled 0. + #0 + + + value2 + WA has been sampled 1. + #1 + + + + + DX2S + DX2S Status + 1 + 1 + read-write + + + value1 + DX2S is 0. + #0 + + + value2 + DX2S is 1. + #1 + + + + + DX2TEV + DX2T Event Detected + 3 + 3 + read-write + + + value1 + The DX2T signal has not been activated. + #0 + + + value2 + The DX2T signal has been activated. + #1 + + + + + WAFE + WA Falling Edge Event + 4 + 4 + read-write + + + value1 + A WA falling edge has not been generated. + #0 + + + value2 + A WA falling edge has been generated. + #1 + + + + + WARE + WA Rising Edge Event + 5 + 5 + read-write + + + value1 + A WA rising edge has not been generated. + #0 + + + value2 + A WA rising edge has been generated. + #1 + + + + + END + WA Generation End + 6 + 6 + read-write + + + value1 + The WA generation has not yet ended (if it is running and WAGEN has been cleared). + #0 + + + value2 + The WA generation has ended (if it has been running). + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSCR + Protocol Status Clear Register + 0x04C + 32 + 0x00000000 + 0xFFFFFFFF + + + CST0 + Clear Status Flag 0 in PSR + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST1 + Clear Status Flag 1 in PSR + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST2 + Clear Status Flag 2 in PSR + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST3 + Clear Status Flag 3 in PSR + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST4 + Clear Status Flag 4 in PSR + 4 + 4 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST5 + Clear Status Flag 5 in PSR + 5 + 5 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST6 + Clear Status Flag 6 in PSR + 6 + 6 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST7 + Clear Status Flag 7 in PSR + 7 + 7 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST8 + Clear Status Flag 8 in PSR + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST9 + Clear Status Flag 9 in PSR + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CRSIF + Clear Receiver Start Indication Flag + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.RSIF is cleared. + #1 + + + + + CDLIF + Clear Data Lost Indication Flag + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.DLIF is cleared. + #1 + + + + + CTSIF + Clear Transmit Shift Indication Flag + 12 + 12 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.TSIF is cleared. + #1 + + + + + CTBIF + Clear Transmit Buffer Indication Flag + 13 + 13 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.TBIF is cleared. + #1 + + + + + CRIF + Clear Receive Indication Flag + 14 + 14 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.RIF is cleared. + #1 + + + + + CAIF + Clear Alternative Receive Indication Flag + 15 + 15 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.AIF is cleared. + #1 + + + + + CBRGIF + Clear Baud Rate Generator Indication Flag + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.BRGIF is cleared. + #1 + + + + + + + RBUFSR + Receiver Buffer Status Register + 0x050 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLEN + Received Data Word Length in RBUF or RBUFD + 0 + 3 + read-only + + + SOF + Start of Frame in RBUF or RBUFD + 6 + 6 + read-only + + + PAR + Protocol-Related Argument in RBUF or RBUFD + 8 + 8 + read-only + + + PERR + Protocol-related Error in RBUF or RBUFD + 9 + 9 + read-only + + + RDV0 + Receive Data Valid in RBUF or RBUFD + 13 + 13 + read-only + + + RDV1 + Receive Data Valid in RBUF or RBUFD + 14 + 14 + read-only + + + DS + Data Source of RBUF or RBUFD + 15 + 15 + read-only + + + + + RBUF + Receiver Buffer Register + 0x054 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + DSR + Received Data + 0 + 15 + read-only + + + + + RBUFD + Receiver Buffer Register for Debugger + 0x058 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR + Data from Shift Register + 0 + 15 + read-only + + + + + RBUF0 + Receiver Buffer Register 0 + 0x05C + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR0 + Data of Shift Registers 0[3:0] + 0 + 15 + read-only + + + + + RBUF1 + Receiver Buffer Register 1 + 0x060 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR1 + Data of Shift Registers 1[3:0] + 0 + 15 + read-only + + + + + RBUF01SR + Receiver Buffer 01 Status Register + 0x064 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLEN0 + Received Data Word Length in RBUF0 + 0 + 3 + read-only + + + SOF0 + Start of Frame in RBUF0 + 6 + 6 + read-only + + + value1 + The data in RBUF0 has not been the first data word of a data frame. + #0 + + + value2 + The data in RBUF0 has been the first data word of a data frame. + #1 + + + + + PAR0 + Protocol-Related Argument in RBUF0 + 8 + 8 + read-only + + + PERR0 + Protocol-related Error in RBUF0 + 9 + 9 + read-only + + + value1 + The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. + #0 + + + value2 + The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. + #1 + + + + + RDV00 + Receive Data Valid in RBUF0 + 13 + 13 + read-only + + + value1 + Register RBUF0 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF0 contains data that has not yet been read out. + #1 + + + + + RDV01 + Receive Data Valid in RBUF1 + 14 + 14 + read-only + + + value1 + Register RBUF1 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF1 contains data that has not yet been read out. + #1 + + + + + DS0 + Data Source + 15 + 15 + read-only + + + value1 + The register RBUF contains the data of RBUF0 (same for associated status information). + #0 + + + value2 + The register RBUF contains the data of RBUF1 (same for associated status information). + #1 + + + + + WLEN1 + Received Data Word Length in RBUF1 + 16 + 19 + read-only + + + value1 + One bit has been received. + 0x0 + + + value2 + Sixteen bits have been received. + 0xF + + + + + SOF1 + Start of Frame in RBUF1 + 22 + 22 + read-only + + + value1 + The data in RBUF1 has not been the first data word of a data frame. + #0 + + + value2 + The data in RBUF1 has been the first data word of a data frame. + #1 + + + + + PAR1 + Protocol-Related Argument in RBUF1 + 24 + 24 + read-only + + + PERR1 + Protocol-related Error in RBUF1 + 25 + 25 + read-only + + + value1 + The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. + #0 + + + value2 + The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. + #1 + + + + + RDV10 + Receive Data Valid in RBUF0 + 29 + 29 + read-only + + + value1 + Register RBUF0 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF0 contains data that has not yet been read out. + #1 + + + + + RDV11 + Receive Data Valid in RBUF1 + 30 + 30 + read-only + + + value1 + Register RBUF1 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF1 contains data that has not yet been read out. + #1 + + + + + DS1 + Data Source + 31 + 31 + read-only + + + value1 + The register RBUF contains the data of RBUF0 (same for associated status information). + #0 + + + value2 + The register RBUF contains the data of RBUF1 (same for associated status information). + #1 + + + + + + + FMR + Flag Modification Register + 0x068 + 32 + 0x00000000 + 0xFFFFFFFF + + + MTDV + Modify Transmit Data Valid + 0 + 1 + write-only + + + value1 + No action. + #00 + + + value2 + Bit TDV is set, TE is unchanged. + #01 + + + value3 + Bits TDV and TE are cleared. + #10 + + + + + ATVC + Activate Bit TVC + 4 + 4 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TCSR.TVC is set. + #1 + + + + + CRDV0 + Clear Bits RDV for RBUF0 + 14 + 14 + write-only + + + value1 + No action. + #0 + + + value2 + Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared. + #1 + + + + + CRDV1 + Clear Bit RDV for RBUF1 + 15 + 15 + write-only + + + value1 + No action. + #0 + + + value2 + Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared. + #1 + + + + + SIO0 + Set Interrupt Output SRx + 16 + 16 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO1 + Set Interrupt Output SRx + 17 + 17 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO2 + Set Interrupt Output SRx + 18 + 18 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO3 + Set Interrupt Output SRx + 19 + 19 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO4 + Set Interrupt Output SRx + 20 + 20 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO5 + Set Interrupt Output SRx + 21 + 21 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + + + 32 + 4 + TBUF[%s] + Transmit Buffer + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDATA + Transmit Data + 0 + 15 + read-write + + + + + BYP + Bypass Data Register + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + BDATA + Bypass Data + 0 + 15 + read-write + + + + + BYPCR + Bypass Control Register + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + BWLE + Bypass Word Length + 0 + 3 + read-write + + + BDSSM + Bypass Data Single Shot Mode + 8 + 8 + read-write + + + value1 + The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. + #0 + + + value2 + The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV. + #1 + + + + + BDEN + Bypass Data Enable + 10 + 11 + read-write + + + value1 + The transfer of bypass data is disabled. + #00 + + + value2 + The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. + #01 + + + value3 + Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. + #10 + + + value4 + Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. + #11 + + + + + BDVTR + Bypass Data Valid Trigger + 12 + 12 + read-write + + + value1 + Bit BDV is not influenced by DX2T. + #0 + + + value2 + Bit BDV is set if DX2T is active. + #1 + + + + + BPRIO + Bypass Priority + 13 + 13 + read-write + + + value1 + The transmit FIFO data has a higher priority than the bypass data. + #0 + + + value2 + The bypass data has a higher priority than the transmit FIFO data. + #1 + + + + + BDV + Bypass Data Valid + 15 + 15 + read-only + + + value1 + The bypass data is not valid. + #0 + + + value2 + The bypass data is valid. + #1 + + + + + BSELO + Bypass Select Outputs + 16 + 20 + read-write + + + BHPC + Bypass Hardware Port Control + 21 + 23 + read-write + + + + + TBCTR + Transmitter Buffer Control Register + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPTR + Data Pointer + 0 + 5 + write-only + + + LIMIT + Limit For Interrupt Generation + 8 + 13 + read-write + + + STBTM + Standard Transmit Buffer Trigger Mode + 14 + 14 + read-write + + + value1 + Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT. + #0 + + + value2 + Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE. + #1 + + + + + STBTEN + Standard Transmit Buffer Trigger Enable + 15 + 15 + read-write + + + value1 + The standard transmit buffer event trigger through bit TRBSR.STBT is disabled. + #0 + + + value2 + The standard transmit buffer event trigger through bit TRBSR.STBT is enabled. + #1 + + + + + STBINP + Standard Transmit Buffer Interrupt Node Pointer + 16 + 18 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + ATBINP + Alternative Transmit Buffer Interrupt Node Pointer + 19 + 21 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + SIZE + Buffer Size + 24 + 26 + read-write + + + value1 + The FIFO mechanism is disabled. The buffer does not accept any request for data. + #000 + + + value2 + The FIFO buffer contains 2 entries. + #001 + + + value3 + The FIFO buffer contains 4 entries. + #010 + + + value4 + The FIFO buffer contains 8 entries. + #011 + + + value5 + The FIFO buffer contains 16 entries. + #100 + + + value6 + The FIFO buffer contains 32 entries. + #101 + + + value7 + The FIFO buffer contains 64 entries. + #110 + + + + + LOF + Buffer Event on Limit Overflow + 28 + 28 + read-write + + + value1 + A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word. + #0 + + + value2 + A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. + #1 + + + + + STBIEN + Standard Transmit Buffer Interrupt Enable + 30 + 30 + read-write + + + value1 + The standard transmit buffer interrupt generation is disabled. + #0 + + + value2 + The standard transmit buffer interrupt generation is enabled. + #1 + + + + + TBERIEN + Transmit Buffer Error Interrupt Enable + 31 + 31 + read-write + + + value1 + The transmit buffer error interrupt generation is disabled. + #0 + + + value2 + The transmit buffer error interrupt generation is enabled. + #1 + + + + + + + RBCTR + Receiver Buffer Control Register + 0x10C + 32 + 0x00000000 + 0xFFFFFFFF + + + DPTR + Data Pointer + 0 + 5 + write-only + + + LIMIT + Limit For Interrupt Generation + 8 + 13 + read-write + + + SRBTM + Standard Receive Buffer Trigger Mode + 14 + 14 + read-write + + + value1 + Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. + #0 + + + value2 + Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. + #1 + + + + + SRBTEN + Standard Receive Buffer Trigger Enable + 15 + 15 + read-write + + + value1 + The standard receive buffer event trigger through bit TRBSR.SRBT is disabled. + #0 + + + value2 + The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. + #1 + + + + + SRBINP + Standard Receive Buffer Interrupt Node Pointer + 16 + 18 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + ARBINP + Alternative Receive Buffer Interrupt Node Pointer + 19 + 21 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + RCIM + Receiver Control Information Mode + 22 + 23 + read-write + + + value1 + RCI[4] = PERR, RCI[3:0] = WLEN + #00 + + + value2 + RCI[4] = SOF, RCI[3:0] = WLEN + #01 + + + value3 + RCI[4] = 0, RCI[3:0] = WLEN + #10 + + + value4 + RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF + #11 + + + + + SIZE + Buffer Size + 24 + 26 + read-write + + + value1 + The FIFO mechanism is disabled. The buffer does not accept any request for data. + #000 + + + value2 + The FIFO buffer contains 2 entries. + #001 + + + value3 + The FIFO buffer contains 4 entries. + #010 + + + value4 + The FIFO buffer contains 8 entries. + #011 + + + value5 + The FIFO buffer contains 16 entries. + #100 + + + value6 + The FIFO buffer contains 32 entries. + #101 + + + value7 + The FIFO buffer contains 64 entries. + #110 + + + + + RNM + Receiver Notification Mode + 27 + 27 + read-write + + + value1 + Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). + #0 + + + value2 + RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. + #1 + + + + + LOF + Buffer Event on Limit Overflow + 28 + 28 + read-write + + + value1 + A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR. + #0 + + + value2 + A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. + #1 + + + + + ARBIEN + Alternative Receive Buffer Interrupt Enable + 29 + 29 + read-write + + + value1 + The alternative receive buffer interrupt generation is disabled. + #0 + + + value2 + The alternative receive buffer interrupt generation is enabled. + #1 + + + + + SRBIEN + Standard Receive Buffer Interrupt Enable + 30 + 30 + read-write + + + value1 + The standard receive buffer interrupt generation is disabled. + #0 + + + value2 + The standard receive buffer interrupt generation is enabled. + #1 + + + + + RBERIEN + Receive Buffer Error Interrupt Enable + 31 + 31 + read-write + + + value1 + The receive buffer error interrupt generation is disabled. + #0 + + + value2 + The receive buffer error interrupt generation is enabled. + #1 + + + + + + + TRBPTR + Transmit/Receive Buffer Pointer Register + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDIPTR + Transmitter Data Input Pointer + 0 + 5 + read-only + + + TDOPTR + Transmitter Data Output Pointer + 8 + 13 + read-only + + + RDIPTR + Receiver Data Input Pointer + 16 + 21 + read-only + + + RDOPTR + Receiver Data Output Pointer + 24 + 29 + read-only + + + + + TRBSR + Transmit/Receive Buffer Status Register + 0x114 + 32 + 0x00000808 + 0xFFFFFFFF + + + SRBI + Standard Receive Buffer Event + 0 + 0 + read-write + + + value1 + A standard receive buffer event has not been detected. + #0 + + + value2 + A standard receive buffer event has been detected. + #1 + + + + + RBERI + Receive Buffer Error Event + 1 + 1 + read-write + + + value1 + A receive buffer error event has not been detected. + #0 + + + value2 + A receive buffer error event has been detected. + #1 + + + + + ARBI + Alternative Receive Buffer Event + 2 + 2 + read-write + + + value1 + An alternative receive buffer event has not been detected. + #0 + + + value2 + An alternative receive buffer event has been detected. + #1 + + + + + REMPTY + Receive Buffer Empty + 3 + 3 + read-only + + + value1 + The receive buffer is not empty. + #0 + + + value2 + The receive buffer is empty. + #1 + + + + + RFULL + Receive Buffer Full + 4 + 4 + read-only + + + value1 + The receive buffer is not full. + #0 + + + value2 + The receive buffer is full. + #1 + + + + + RBUS + Receive Buffer Busy + 5 + 5 + read-only + + + value1 + The receive buffer information has been completely updated. + #0 + + + value2 + The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. + #1 + + + + + SRBT + Standard Receive Buffer Event Trigger + 6 + 6 + read-only + + + value1 + A standard receive buffer event is not triggered using this bit. + #0 + + + value2 + A standard receive buffer event is triggered using this bit. + #1 + + + + + STBI + Standard Transmit Buffer Event + 8 + 8 + read-write + + + value1 + A standard transmit buffer event has not been detected. + #0 + + + value2 + A standard transmit buffer event has been detected. + #1 + + + + + TBERI + Transmit Buffer Error Event + 9 + 9 + read-write + + + value1 + A transmit buffer error event has not been detected. + #0 + + + value2 + A transmit buffer error event has been detected. + #1 + + + + + TEMPTY + Transmit Buffer Empty + 11 + 11 + read-only + + + value1 + The transmit buffer is not empty. + #0 + + + value2 + The transmit buffer is empty. + #1 + + + + + TFULL + Transmit Buffer Full + 12 + 12 + read-only + + + value1 + The transmit buffer is not full. + #0 + + + value2 + The transmit buffer is full. + #1 + + + + + TBUS + Transmit Buffer Busy + 13 + 13 + read-only + + + value1 + The transmit buffer information has been completely updated. + #0 + + + value2 + The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. + #1 + + + + + STBT + Standard Transmit Buffer Event Trigger + 14 + 14 + read-only + + + value1 + A standard transmit buffer event is not triggered using this bit. + #0 + + + value2 + A standard transmit buffer event is triggered using this bit. + #1 + + + + + RBFLVL + Receive Buffer Filling Level + 16 + 22 + read-only + + + TBFLVL + Transmit Buffer Filling Level + 24 + 30 + read-only + + + + + TRBSCR + Transmit/Receive Buffer Status Clear Register + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + CSRBI + Clear Standard Receive Buffer Event + 0 + 0 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.SRBI. + #1 + + + + + CRBERI + Clear Receive Buffer Error Event + 1 + 1 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.RBERI. + #1 + + + + + CARBI + Clear Alternative Receive Buffer Event + 2 + 2 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.ARBI. + #1 + + + + + CSTBI + Clear Standard Transmit Buffer Event + 8 + 8 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.STBI. + #1 + + + + + CTBERI + Clear Transmit Buffer Error Event + 9 + 9 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.TBERI. + #1 + + + + + CBDV + Clear Bypass Data Valid + 10 + 10 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear BYPCR.BDV. + #1 + + + + + FLUSHRB + Flush Receive Buffer + 14 + 14 + write-only + + + value1 + No effect. + #0 + + + value2 + The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. + #1 + + + + + FLUSHTB + Flush Transmit Buffer + 15 + 15 + write-only + + + value1 + No effect. + #0 + + + value2 + The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. + #1 + + + + + + + OUTR + Receiver Buffer Output Register + 0x11C + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + DSR + Received Data + 0 + 15 + read-only + + + RCI + Receiver Control Information + 16 + 20 + read-only + + + + + OUTDR + Receiver Buffer Output Register L for Debugger + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR + Data from Shift Register + 0 + 15 + read-only + + + RCI + Receive Control Information from Shift Register + 16 + 20 + read-only + + + + + 32 + 4 + IN[%s] + Transmit FIFO Buffer + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDATA + Transmit Data + 0 + 15 + write-only + + + + + + + USIC0_CH1 + Universal Serial Interface Controller 0 + USIC + 0x40030200 + + 0x0 + 0x0200 + registers + + + + USIC1_CH0 + Universal Serial Interface Controller 0 + USIC + 0x48020000 + + 0x0 + 0x0200 + registers + + + + USIC1_CH1 + Universal Serial Interface Controller 0 + USIC + 0x48020200 + + 0x0 + 0x0200 + registers + + + + USIC2_CH0 + Universal Serial Interface Controller 0 + USIC + 0x48024000 + + 0x0 + 0x0200 + registers + + + + USIC2_CH1 + Universal Serial Interface Controller 0 + USIC + 0x48024200 + + 0x0 + 0x0200 + registers + + + + CAN + Controller Area Networks + CAN + 0x48014000 + + 0x0 + 0x200 + registers + + + CAN0_0 + MultiCAN + 76 + + + CAN0_1 + MultiCAN + 77 + + + CAN0_2 + MultiCAN + 78 + + + CAN0_3 + MultiCAN + 79 + + + CAN0_4 + MultiCAN + 80 + + + CAN0_5 + MultiCAN + 81 + + + CAN0_6 + MultiCAN + 82 + + + CAN0_7 + MultiCAN + 83 + + + + CLC + CAN Clock Control Register + 0x0000 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + EDIS + Sleep Mode Enable Control + 3 + 3 + read-write + + + + + ID + Module Identification Register + 0x0008 + 32 + 0x00B5C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + value1 + Define the module as a 32-bit module. + 0xC0 + + + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + FDR + CAN Fractional Divider Register + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + STEP + Step Value + 0 + 9 + read-write + + + DM + Divider Mode + 14 + 15 + read-write + + + + + 16 + 4 + LIST[%s] + List Register + 0x0100 + 32 + 0x00000000 + 0x00000000 + + + BEGIN + List Begin + 0 + 7 + read-only + + + END + List End + 8 + 15 + read-only + + + SIZE + List Size + 16 + 23 + read-only + + + EMPTY + List Empty Indication + 24 + 24 + read-only + + + value1 + At least one message object is allocated to list i. + #0 + + + value2 + No message object is allocated to the list i. List i is empty. + #1 + + + + + + + 8 + 4 + MSPND[%s] + Message Pending Register + 0x0140 + 32 + 0x00000000 + 0xFFFFFFFF + + + PND + Message Pending + 0 + 31 + read-write + + + + + 8 + 4 + MSID[%s] + Message Index Register + 0x0180 + 32 + 0x00000020 + 0xFFFFFFFF + + + INDEX + Message Pending Index + 0 + 5 + read-only + + + + + MSIMASK + Message Index Mask Register + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IM + Message Index Mask + 0 + 31 + read-write + + + + + PANCTR + Panel Control Register + 0x01C4 + 32 + 0x00000301 + 0xFFFFFFFF + + + PANCMD + Panel Command + 0 + 7 + read-write + + + BUSY + Panel Busy Flag + 8 + 8 + read-only + + + value1 + Panel has finished command and is ready to accept a new command. + #0 + + + value2 + Panel operation is in progress. + #1 + + + + + RBUSY + Result Busy Flag + 9 + 9 + read-only + + + value1 + No update of PANAR1 and PANAR2 is scheduled by the list controller. + #0 + + + value2 + A list command is running (BUSY = 1) that will write results to PANAR1 and PANAR2, but the results are not yet available. + #1 + + + + + PANAR1 + Panel Argument 1 + 16 + 23 + read-write + + + PANAR2 + Panel Argument 2 + 24 + 31 + read-write + + + + + MCR + Module Control Register + 0x01C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLKSEL + Baud Rate Logic Clock Select + 0 + 3 + read-write + + + value1 + No clock supplied + #0000 + + + value2 + fPERIPH + #0001 + + + value3 + fOHP + #0010 + + + value4 + hard wired to 0 + #0100 + + + value5 + hard wired to 0 + #1000 + + + + + MPSEL + Message Pending Selector + 12 + 15 + read-write + + + + + MITR + Module Interrupt Trigger Register + 0x01CC + 32 + 0x00000000 + 0xFFFFFFFF + + + IT + Interrupt Trigger + 0 + 7 + write-only + + + + + + + CAN_NODE0 + Controller Area Networks + CAN + CAN_NODE + 0x48014200 + + 0x0 + 0x100 + registers + + + + NCR + Node Control Register + 0x00 + 32 + 0x00000041 + 0xFFFFFFFF + + + INIT + Node Initialization + 0 + 0 + read-write + + + value1 + Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic. + #0 + + + value2 + Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set. + #1 + + + + + TRIE + Transfer Interrupt Enable + 1 + 1 + read-write + + + value1 + Transfer interrupt is disabled. + #0 + + + value2 + Transfer interrupt is enabled. + #1 + + + + + LECIE + LEC Indicated Error Interrupt Enable + 2 + 2 + read-write + + + value1 + Last error code interrupt is disabled. + #0 + + + value2 + Last error code interrupt is enabled. + #1 + + + + + ALIE + Alert Interrupt Enable + 3 + 3 + read-write + + + value1 + Alert interrupt is disabled. + #0 + + + value2 + Alert interrupt is enabled. + #1 + + + + + CANDIS + CAN Disable + 4 + 4 + read-write + + + TXDIS + Transmit Disable + 5 + 5 + read-write + + + CCE + Configuration Change Enable + 6 + 6 + read-write + + + value1 + The Bit Timing Register, the Port Control Register, Error Counter Register may only be read. All attempts to modify them are ignored. + #0 + + + value2 + The Bit Timing Register, the Port Control Register, Error Counter Register may be read and written. + #1 + + + + + CALM + CAN Analyzer Mode + 7 + 7 + read-write + + + + + NSR + Node Status Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + LEC + Last Error Code + 0 + 2 + read-write + + + TXOK + Message Transmitted Successfully + 3 + 3 + read-write + + + value1 + No successful transmission since last (most recent) flag reset. + #0 + + + value2 + A message has been transmitted successfully (error-free and acknowledged by at least another node). + #1 + + + + + RXOK + Message Received Successfully + 4 + 4 + read-write + + + value1 + No successful reception since last (most recent) flag reset. + #0 + + + value2 + A message has been received successfully. + #1 + + + + + ALERT + Alert Warning + 5 + 5 + read-write + + + EWRN + Error Warning Status + 6 + 6 + read-only + + + value1 + No warning limit exceeded. + #0 + + + value2 + One of the error counters REC or TEC reached the warning limit EWRNLVL. + #1 + + + + + BOFF + Bus-off Status + 7 + 7 + read-only + + + value1 + CAN controller is not in the bus-off state. + #0 + + + value2 + CAN controller is in the bus-off state. + #1 + + + + + LLE + List Length Error + 8 + 8 + read-write + + + value1 + No List Length Error since last (most recent) flag reset. + #0 + + + value2 + A List Length Error has been detected during message acceptance filtering. The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list termination pointer. + #1 + + + + + LOE + List Object Error + 9 + 9 + read-write + + + value1 + No List Object Error since last (most recent) flag reset. + #0 + + + value2 + A List Object Error has been detected during message acceptance filtering. A message object with wrong LIST index entry in the Message Object Status Register has been detected. + #1 + + + + + + + NIPR + Node Interrupt Pointer Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALINP + Alert Interrupt Node Pointer + 0 + 3 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + LECINP + Last Error Code Interrupt Node Pointer + 4 + 7 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + TRINP + Transfer OK Interrupt Node Pointer + 8 + 11 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + CFCINP + Frame Counter Interrupt Node Pointer + 12 + 15 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + + + NPCR + Node Port Control Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXSEL + Receive Select + 0 + 2 + read-write + + + LBM + Loop-Back Mode + 8 + 8 + read-write + + + value1 + Loop-Back Mode is disabled. + #0 + + + value2 + Loop-Back Mode is enabled. This node is connected to an internal (virtual) loop-back CAN bus. All CAN nodes which are in Loop-Back Mode are connected to this virtual CAN bus so that they can communicate with each other internally. The external transmit line is forced recessive in Loop-Back Mode. + #1 + + + + + + + NBTR + Node Bit Timing Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + BRP + Baud Rate Prescaler + 0 + 5 + read-write + + + SJW + (Re) Synchronization Jump Width + 6 + 7 + read-write + + + TSEG1 + Time Segment Before Sample Point + 8 + 11 + read-write + + + TSEG2 + Time Segment After Sample Point + 12 + 14 + read-write + + + DIV8 + Divide Prescaler Clock by 8 + 15 + 15 + read-write + + + value1 + A time quantum lasts (BRP+1) clock cycles. + #0 + + + value2 + A time quantum lasts 8 (BRP+1) clock cycles. + #1 + + + + + + + NECNT + Node Error Counter Register + 0x14 + 32 + 0x00600000 + 0xFFFFFFFF + + + REC + Receive Error Counter + 0 + 7 + read-write + + + TEC + Transmit Error Counter + 8 + 15 + read-write + + + EWRNLVL + Error Warning Level + 16 + 23 + read-write + + + LETD + Last Error Transfer Direction + 24 + 24 + read-only + + + value1 + The last error occurred while the CAN node x was receiver (REC has been incremented). + #0 + + + value2 + The last error occurred while the CAN node x was transmitter (TEC has been incremented). + #1 + + + + + LEINC + Last Error Increment + 25 + 25 + read-only + + + value1 + The last error led to an error counter increment of 1. + #0 + + + value2 + The last error led to an error counter increment of 8. + #1 + + + + + + + NFCR + Node Frame Counter Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFC + CAN Frame Counter + 0 + 15 + read-write + + + CFSEL + CAN Frame Count Selection + 16 + 18 + read-write + + + CFMOD + CAN Frame Counter Mode + 19 + 20 + read-write + + + value1 + Frame Count Mode: The frame counter is incremented upon the reception and transmission of frames. + #00 + + + value2 + Time Stamp Mode: The frame counter is used to count bit times. + #01 + + + value3 + Bit Timing Mode: The frame counter is used for analysis of the bit timing. + #10 + + + value4 + Error Count Mode: The frame counter is used for counting when an error frame is received or an error is detected by the node. + #11 + + + + + CFCIE + CAN Frame Count Interrupt Enable + 22 + 22 + read-write + + + value1 + CAN frame counter overflow interrupt is disabled. + #0 + + + value2 + CAN frame counter overflow interrupt is enabled. + #1 + + + + + CFCOV + CAN Frame Counter Overflow Flag + 23 + 23 + read-write + + + value1 + No overflow has occurred since last flag reset. + #0 + + + value2 + An overflow has occurred since last flag reset. + #1 + + + + + + + + + CAN_NODE1 + Controller Area Networks + CAN + 0x48014300 + + 0x0 + 0x100 + registers + + + + CAN_NODE2 + Controller Area Networks + CAN + 0x48014400 + + 0x0 + 0x100 + registers + + + + CAN_NODE3 + Controller Area Networks + CAN + 0x48014500 + + 0x0 + 0x100 + registers + + + + CAN_NODE4 + Controller Area Networks + CAN + 0x48014600 + + 0x0 + 0x100 + registers + + + + CAN_NODE5 + Controller Area Networks + CAN + 0x48014700 + + 0x0 + 0x100 + registers + + + + CAN_MO + Controller Area Networks + CAN + CAN_MO_CLUSTER + 0x48015000 + + 0x0 + 0x2000 + registers + + + + 256 + 0x20 + MO[%s] + Message Object Registers + CAN_MO + 0 + + MOFCR + Message Object Function Control Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + MMC + Message Mode Control + 0 + 3 + read-write + + + value1 + Standard Message Object + #0000 + + + value2 + Receive FIFO Base Object + #0001 + + + value3 + Transmit FIFO Base Object + #0010 + + + value4 + Transmit FIFO Slave Object + #0011 + + + value5 + Gateway Source Object + #0100 + + + + + RXTOE + Receive Time-Out Enable + 4 + 4 + read-write + + + value1 + Message does not take part in receive time-out check + #0 + + + value2 + Message takes part in receive time-out check + #1 + + + + + GDFS + Gateway Data Frame Send + 8 + 8 + read-write + + + value1 + TXRQ is unchanged in the destination object. + #0 + + + value2 + TXRQ is set in the gateway destination object after the internal transfer from the gateway source to the gateway destination object. + #1 + + + + + IDC + Identifier Copy + 9 + 9 + read-write + + + value1 + The identifier of the gateway source object is not copied. + #0 + + + value2 + The identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. + #1 + + + + + DLCC + Data Length Code Copy + 10 + 10 + read-write + + + value1 + Data length code is not copied. + #0 + + + value2 + Data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. + #1 + + + + + DATC + Data Copy + 11 + 11 + read-write + + + value1 + Data fields are not copied. + #0 + + + value2 + Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) are copied to the gateway destination. + #1 + + + + + RXIE + Receive Interrupt Enable + 16 + 16 + read-write + + + value1 + Message receive interrupt is disabled. + #0 + + + value2 + Message receive interrupt is enabled. + #1 + + + + + TXIE + Transmit Interrupt Enable + 17 + 17 + read-write + + + value1 + Message transmit interrupt is disabled. + #0 + + + value2 + Message transmit interrupt is enabled. + #1 + + + + + OVIE + Overflow Interrupt Enable + 18 + 18 + read-write + + + value1 + FIFO full interrupt is disabled. + #0 + + + value2 + FIFO full interrupt is enabled. + #1 + + + + + FRREN + Foreign Remote Request Enable + 20 + 20 + read-write + + + value1 + TXRQ of message object n is set on reception of a matching Remote Frame. + #0 + + + value2 + TXRQ of the message object referenced by the pointer CUR is set on reception of a matching Remote Frame. + #1 + + + + + RMM + Transmit Object Remote Monitoring + 21 + 21 + read-write + + + value1 + Remote monitoring is disabled: Identifier, IDE bit, and DLC of message object n remain unchanged upon the reception of a matching Remote Frame. + #0 + + + value2 + Remote monitoring is enabled: Identifier, IDE bit, and DLC of a matching Remote Frame are copied to transmit object n in order to monitor incoming Remote Frames. + #1 + + + + + SDT + Single Data Transfer + 22 + 22 + read-write + + + STT + Single Transmit Trial + 23 + 23 + read-write + + + DLC + Data Length Code + 24 + 27 + read-write + + + + + MOFGPR + Message Object FIFO/Gateway Pointer Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOT + Bottom Pointer + 0 + 7 + read-write + + + TOP + Top Pointer + 8 + 15 + read-write + + + CUR + Current Object Pointer + 16 + 23 + read-write + + + SEL + Object Select Pointer + 24 + 31 + read-write + + + + + MOIPR + Message Object Interrupt Pointer Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXINP + Receive Interrupt Node Pointer + 0 + 3 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + TXINP + Transmit Interrupt Node Pointer + 4 + 7 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + MPN + Message Pending Number + 8 + 15 + read-write + + + CFCVAL + CAN Frame Counter Value + 16 + 31 + read-write + + + + + MOAMR + Message Object Acceptance Mask Register + 0x0C + 32 + 0x3FFFFFFF + 0xFFFFFFFF + + + AM + Acceptance Mask for Message Identifier + 0 + 28 + read-write + + + MIDE + Acceptance Mask Bit for Message IDE Bit + 29 + 29 + read-write + + + value1 + Message object n accepts the reception of both, standard and extended frames. + #0 + + + value2 + Message object n receives frames only with matching IDE bit. + #1 + + + + + + + MODATAL + Message Object Data Register Low + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DB0 + Data Byte 0 of Message Object n + 0 + 7 + read-write + + + DB1 + Data Byte 1 of Message Object n + 8 + 15 + read-write + + + DB2 + Data Byte 2 of Message Object n + 16 + 23 + read-write + + + DB3 + Data Byte 3 of Message Object n + 24 + 31 + read-write + + + + + MODATAH + Message Object Data Register High + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + DB4 + Data Byte 4 of Message Object n + 0 + 7 + read-write + + + DB5 + Data Byte 5 of Message Object n + 8 + 15 + read-write + + + DB6 + Data Byte 6 of Message Object n + 16 + 23 + read-write + + + DB7 + Data Byte 7 of Message Object n + 24 + 31 + read-write + + + + + MOAR + Message Object Arbitration Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ID + CAN Identifier of Message Object n + 0 + 28 + read-write + + + IDE + Identifier Extension Bit of Message Object n + 29 + 29 + read-write + + + value1 + Message object n handles standard frames with 11-bit identifier. + #0 + + + value2 + Message object n handles extended frames with 29-bit identifier. + #1 + + + + + PRI + Priority Class + 30 + 31 + read-write + + + value2 + Transmit acceptance filtering is based on the list order. This means that message object n is considered for transmission only if there is no other message object with valid transmit request (MSGVAL & TXEN0 & TXEN1 = 1) somewhere before this object in the list. + #01 + + + value3 + Transmit acceptance filtering is based on the CAN identifier. This means, message object n is considered for transmission only if there is no other message object with higher priority identifier + IDE + DIR (with respect to CAN arbitration rules) somewhere in the list (see ). + #10 + + + value4 + Transmit acceptance filtering is based on the list order (as PRI = 01B). + #11 + + + + + + + MOCTR + Message Object Control Register + 0x1C + 32 + 0x00000000 + 0x0000FFFF + + + RESRXPND + Reset/Set Receive Pending + 0 + 0 + write-only + + + SETRXPND + Reset/Set Receive Pending + 16 + 16 + write-only + + + RESTXPND + Reset/Set Transmit Pending + 1 + 1 + write-only + + + SETTXPND + Reset/Set Transmit Pending + 17 + 17 + write-only + + + RESRXUPD + Reset/Set Receive Updating + 2 + 2 + write-only + + + SETRXUPD + Reset/Set Receive Updating + 18 + 18 + write-only + + + RESNEWDAT + Reset/Set New Data + 3 + 3 + write-only + + + SETNEWDAT + Reset/Set New Data + 19 + 19 + write-only + + + RESMSGLST + Reset/Set Message Lost + 4 + 4 + write-only + + + SETMSGLST + Reset/Set Message Lost + 20 + 20 + write-only + + + RESMSGVAL + Reset/Set Message Valid + 5 + 5 + write-only + + + SETMSGVAL + Reset/Set Message Valid + 21 + 21 + write-only + + + RESRTSEL + Reset/Set Receive/Transmit Selected + 6 + 6 + write-only + + + SETRTSEL + Reset/Set Receive/Transmit Selected + 22 + 22 + write-only + + + RESRXEN + Reset/Set Receive Enable + 7 + 7 + write-only + + + SETRXEN + Reset/Set Receive Enable + 23 + 23 + write-only + + + RESTXRQ + Reset/Set Transmit Request + 8 + 8 + write-only + + + SETTXRQ + Reset/Set Transmit Request + 24 + 24 + write-only + + + RESTXEN0 + Reset/Set Transmit Enable 0 + 9 + 9 + write-only + + + SETTXEN0 + Reset/Set Transmit Enable 0 + 25 + 25 + write-only + + + RESTXEN1 + Reset/Set Transmit Enable 1 + 10 + 10 + write-only + + + SETTXEN1 + Reset/Set Transmit Enable 1 + 26 + 26 + write-only + + + RESDIR + Reset/Set Message Direction + 11 + 11 + write-only + + + SETDIR + Reset/Set Message Direction + 27 + 27 + write-only + + + + + MOSTAT + Message Object Status Register + MOCTR + 0x1C + 32 + 0x00000000 + 0x0000FFFF + + + RXPND + Receive Pending + 0 + 0 + read-only + + + value1 + No CAN message has been received. + #0 + + + value2 + A CAN message has been received by the message object n, either directly or via gateway copy action. + #1 + + + + + TXPND + Transmit Pending + 1 + 1 + read-only + + + value1 + No CAN message has been transmitted. + #0 + + + value2 + A CAN message from message object n has been transmitted successfully over the CAN bus. + #1 + + + + + RXUPD + Receive Updating + 2 + 2 + read-only + + + value1 + No receive update ongoing. + #0 + + + value2 + Message identifier, DLC, and data of the message object are currently updated. + #1 + + + + + NEWDAT + New Data + 3 + 3 + read-only + + + value1 + No update of the message object n since last flag reset. + #0 + + + value2 + Message object n has been updated. + #1 + + + + + MSGLST + Message Lost + 4 + 4 + read-only + + + value1 + No CAN message is lost. + #0 + + + value2 + A CAN message is lost because NEWDAT has become set again when it has already been set. + #1 + + + + + MSGVAL + Message Valid + 5 + 5 + read-only + + + value1 + Message object n is not valid. + #0 + + + value2 + Message object n is valid. + #1 + + + + + RTSEL + Receive/Transmit Selected + 6 + 6 + read-only + + + value1 + Message object n is not selected for receive or transmit operation. + #0 + + + value2 + Message object n is selected for receive or transmit operation. + #1 + + + + + RXEN + Receive Enable + 7 + 7 + read-only + + + value1 + Message object n is not enabled for frame reception. + #0 + + + value2 + Message object n is enabled for frame reception. + #1 + + + + + TXRQ + Transmit Request + 8 + 8 + read-only + + + value1 + No transmission of message object n is requested. + #0 + + + value2 + Transmission of message object n on the CAN bus is requested. + #1 + + + + + TXEN0 + Transmit Enable 0 + 9 + 9 + read-only + + + value1 + Message object n is not enabled for frame transmission. + #0 + + + value2 + Message object n is enabled for frame transmission. + #1 + + + + + TXEN1 + Transmit Enable 1 + 10 + 10 + read-only + + + value1 + Message object n is not enabled for frame transmission. + #0 + + + value2 + Message object n is enabled for frame transmission. + #1 + + + + + DIR + Message Direction + 11 + 11 + read-only + + + value1 + Receive Object selected: With TXRQ = 1, a Remote Frame with the identifier of message object n is scheduled for transmission. On reception of a Data Frame with matching identifier, the message is stored in message object n. + #0 + + + value2 + Transmit Object selected: If TXRQ = 1, message object n is scheduled for transmission of a Data Frame. On reception of a Remote Frame with matching identifier, bit TXRQ is set. + #1 + + + + + LIST + List Allocation + 12 + 15 + read-only + + + PPREV + Pointer to Previous Message Object + 16 + 23 + read-only + + + PNEXT + Pointer to Next Message Object + 24 + 31 + read-only + + + + + + + + VADC + Analog to Digital Converter + VADC + 0x40004000 + + 0x0 + 0x400 + registers + + + VADC0_C0_0 + Analog to Digital Converter Common Block 0 + 14 + + + VADC0_C0_1 + Analog to Digital Converter Common Block 0 + 15 + + + VADC0_C0_2 + Analog to Digital Converter Common Block 0 + 16 + + + VADC0_C0_3 + Analog to Digital Converter Common Block 0 + 17 + + + + CLC + Clock Control Register + 0x0000 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + value1 + On request: enable the module clock + #0 + + + value2 + Off request: stop the module clock + #1 + + + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + value1 + Module clock is enabled + #0 + + + value2 + Off: module is not clocked + #1 + + + + + EDIS + Sleep Mode Enable Control + 3 + 3 + read-write + + + value1 + Sleep mode request is enabled and functional + #0 + + + value2 + Module disregards the sleep mode control signal + #1 + + + + + + + ID + Module Identification Register + 0x0008 + 32 + 0x00C5C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + OCS + OCDS Control and Status Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + TGS + Trigger Set for OTGB0/1 + 0 + 1 + read-write + + + value1 + No Trigger Set output + #00 + + + value2 + Trigger Set 1: TS16_SSIG, input sample signals + #01 + + + + + TGB + OTGB0/1 Bus Select + 2 + 2 + read-write + + + value1 + Trigger Set is output on OTGB0 + #0 + + + value2 + Trigger Set is output on OTGB1 + #1 + + + + + TG_P + TGS, TGB Write Protection + 3 + 3 + write-only + + + SUS + OCDS Suspend Control + 24 + 27 + read-write + + + value1 + Will not suspend + #0000 + + + value2 + Hard suspend: Clock is switched off immediately. + #0001 + + + value3 + Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter. + #0010 + + + value4 + Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round. + #0011 + + + + + SUS_P + SUS Write Protection + 28 + 28 + write-only + + + SUSSTA + Suspend State + 29 + 29 + read-only + + + value1 + Module is not (yet) suspended + #0 + + + value2 + Module is suspended + #1 + + + + + + + GLOBCFG + Global Configuration Register + 0x0080 + 32 + 0x0000000F + 0xFFFFFFFF + + + DIVA + Divider Factor for the Analog Internal Clock + 0 + 4 + read-write + + + value1 + fADCI = fADC / 2 + 0x00 + + + value2 + fADCI = fADC / 2 + 0x01 + + + value3 + fADCI = fADC / 3 + 0x02 + + + value4 + fADCI = fADC / 32 + 0x1F + + + + + DCMSB + Double Clock for the MSB Conversion + 7 + 7 + read-write + + + value1 + 1 clock cycles for the MSB (standard) + #0 + + + value2 + 2 clock cycles for the MSB (fADCI > 20 MHz) + #1 + + + + + DIVD + Divider Factor for the Arbiter Clock + 8 + 9 + read-write + + + value1 + fADCD = fADC + #00 + + + value2 + fADCD = fADC / 2 + #01 + + + value3 + fADCD = fADC / 3 + #10 + + + value4 + fADCD = fADC / 4 + #11 + + + + + DIVWC + Write Control for Divider Parameters + 15 + 15 + write-only + + + value1 + No write access to divider parameters + #0 + + + value2 + Bitfields DIVA, DCMSB, DIVD can be written + #1 + + + + + DPCAL0 + Disable Post-Calibration + 16 + 16 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + DPCAL1 + Disable Post-Calibration + 17 + 17 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + DPCAL2 + Disable Post-Calibration + 18 + 18 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + DPCAL3 + Disable Post-Calibration + 19 + 19 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + SUCAL + Start-Up Calibration + 31 + 31 + write-only + + + value1 + No action + #0 + + + value2 + Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL) + #1 + + + + + + + 2 + 4 + GLOBICLASS[%s] + Input Class Register, Global + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + STCS + Sample Time Control for Standard Conversions + 0 + 4 + read-write + + + CMS + Conversion Mode for Standard Conversions + 8 + 10 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + STCE + Sample Time Control for EMUX Conversions + 16 + 20 + read-write + + + CME + Conversion Mode for EMUX Conversions + 24 + 26 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + + + GLOBBOUND + Global Boundary Select Register + 0x00B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOUNDARY0 + Boundary Value 0 for Limit Checking + 0 + 11 + read-write + + + BOUNDARY1 + Boundary Value 1 for Limit Checking + 16 + 27 + read-write + + + + + GLOBEFLAG + Global Event Flag Register + 0x00E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEVGLB + Source Event (Background) + 0 + 0 + read-write + + + value1 + No source event + #0 + + + value2 + A source event has occurred + #1 + + + + + REVGLB + Global Result Event + 8 + 8 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GLOBRES + #1 + + + + + SEVGLBCLR + Clear Source Event (Background) + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Clear the source event flag SEVGLB + #1 + + + + + REVGLBCLR + Clear Global Result Event + 24 + 24 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag REVGLB + #1 + + + + + + + GLOBEVNP + Global Event Node Pointer Register + 0x0140 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0NP + Service Request Node Pointer Backgr. Source + 0 + 3 + read-write + + + value1 + Select shared service request line 0 of common service request group 0 + #0000 + + + value2 + Select shared service request line 3 of common service request group 0 + #0011 + + + value3 + Select shared service request line 0 of common service request group 1 + #0100 + + + value4 + Select shared service request line 3 of common service request group 1 + #0111 + + + + + REV0NP + Service Request Node Pointer Backgr. Result + 16 + 19 + read-write + + + value1 + Select shared service request line 0 of common service request group 0 + #0000 + + + value2 + Select shared service request line 3 of common service request group 0 + #0011 + + + value3 + Select shared service request line 0 of common service request group 1 + #0100 + + + value4 + Select shared service request line 3 of common service request group 1 + #0111 + + + + + + + GLOBTF + Global Test Functions Register + 0x0160 + 32 + 0x00000000 + 0xFFFFFFFF + + + CDGR + Converter Diagnostics Group + 4 + 7 + read-write + + + CDEN + Converter Diagnostics Enable + 8 + 8 + read-write + + + value1 + All diagnostic pull devices are disconnected + #0 + + + value2 + Diagnostic pull devices connected as selected by bitfield CDSEL + #1 + + + + + CDSEL + Converter Diagnostics Pull-Devices Select + 9 + 10 + read-write + + + value1 + Connected to VAREF + #00 + + + value2 + Connected to VAGND + #01 + + + value3 + Connected to 1/3rd VAREF + #10 + + + value4 + Connected to 2/3rd VAREF + #11 + + + + + CDWC + Write Control for Conversion Diagnostics + 15 + 15 + write-only + + + value1 + No write access to parameters + #0 + + + value2 + Bitfields CDSEL, CDEN, CDGR can be written + #1 + + + + + PDD + Pull-Down Diagnostics Enable + 16 + 16 + read-write + + + value1 + Disconnected + #0 + + + value2 + The pull-down diagnostics device is active + #1 + + + + + MDWC + Write Control for Multiplexer Diagnostics + 23 + 23 + write-only + + + value1 + No write access to parameters + #0 + + + value2 + Bitfield PDD can be written + #1 + + + + + + + 4 + 4 + BRSSEL[%s] + Background Request Source Channel Select Register + 0x0180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHSELG0 + Channel Selection Group x + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG1 + Channel Selection Group x + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG2 + Channel Selection Group x + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG3 + Channel Selection Group x + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG4 + Channel Selection Group x + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG5 + Channel Selection Group x + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG6 + Channel Selection Group x + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG7 + Channel Selection Group x + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + + + 4 + 4 + BRSPND[%s] + Background Request Source Pending Register + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHPNDG0 + Channels Pending Group x + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG1 + Channels Pending Group x + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG2 + Channels Pending Group x + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG3 + Channels Pending Group x + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG4 + Channels Pending Group x + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG5 + Channels Pending Group x + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG6 + Channels Pending Group x + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG7 + Channels Pending Group x + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + + + BRSCTRL + Background Request Source Control Register + 0x0200 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCRESREG + Source-specific Result Register + 0 + 3 + read-write + + + value1 + Use GxCHCTRy.RESREG to select a group result register + #0000 + + + value2 + Store result in group result register GxRES1 + #0001 + + + value3 + Store result in group result register GxRES15 + #1111 + + + + + XTSEL + External Trigger Input Selection + 8 + 11 + read-write + + + XTLVL + External Trigger Level + 12 + 12 + read-only + + + XTMODE + Trigger Operating Mode + 13 + 14 + read-write + + + value1 + No external trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon any edge + #11 + + + + + XTWC + Write Control for Trigger Configuration + 15 + 15 + write-only + + + value1 + No write access to trigger configuration + #0 + + + value2 + Bitfields XTMODE and XTSEL can be written + #1 + + + + + GTSEL + Gate Input Selection + 16 + 19 + read-write + + + GTLVL + Gate Input Level + 20 + 20 + read-only + + + GTWC + Write Control for Gate Configuration + 23 + 23 + write-only + + + value1 + No write access to gate configuration + #0 + + + value2 + Bitfield GTSEL can be written + #1 + + + + + + + BRSMR + Background Request Source Mode Register + 0x0204 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENGT + Enable Gate + 0 + 1 + read-write + + + value1 + No conversion requests are issued + #00 + + + value2 + Conversion requests are issued if at least one pending bit is set + #01 + + + value3 + Conversion requests are issued if at least one pending bit is set and REQGTx = 1. + #10 + + + value4 + Conversion requests are issued if at least one pending bit is set and REQGTx = 0. + #11 + + + + + ENTR + Enable External Trigger + 2 + 2 + read-write + + + value1 + External trigger disabled + #0 + + + value2 + The selected edge at the selected trigger input signal REQTR generates the load event + #1 + + + + + ENSI + Enable Source Interrupt + 3 + 3 + read-write + + + value1 + No request source interrupt + #0 + + + value2 + A request source interrupt is generated upon a request source event (last pending conversion is finished) + #1 + + + + + SCAN + Autoscan Enable + 4 + 4 + read-write + + + value1 + No autoscan + #0 + + + value2 + Autoscan functionality enabled: a request source event automatically generates a load event + #1 + + + + + LDM + Autoscan Source Load Event Mode + 5 + 5 + read-write + + + value1 + Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event + #0 + + + value2 + Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) + #1 + + + + + REQGT + Request Gate Level + 7 + 7 + read-only + + + value1 + The gate input is low + #0 + + + value2 + The gate input is high + #1 + + + + + CLRPND + Clear Pending Bits + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + The bits in registers BRSPNDx are cleared + #1 + + + + + LDEV + Generate Load Event + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + A load event is generated + #1 + + + + + RPTDIS + Repeat Disable + 16 + 16 + read-write + + + value1 + A cancelled conversion is repeated + #0 + + + value2 + A cancelled conversion is discarded + #1 + + + + + + + GLOBRCR + Global Result Control Register + 0x0280 + 32 + 0x00000000 + 0xFFFFFFFF + + + DRCTR + Data Reduction Control + 16 + 19 + read-write + + + value1 + Data reduction disabled + #0000 + + + + + WFR + Wait-for-Read Mode Enable + 24 + 24 + read-write + + + value1 + Overwrite mode + #0 + + + value2 + Wait-for-read mode enabled for this register + #1 + + + + + SRGEN + Service Request Generation Enable + 31 + 31 + read-write + + + value1 + No service request + #0 + + + value2 + Service request after a result event + #1 + + + + + + + GLOBRES + Global Result Register + 0x0300 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + RESULT + Result of most recent conversion + 0 + 15 + read-write + + + GNR + Group Number + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) + #1 + + + + + + + GLOBRESD + Global Result Register, Debug + 0x0380 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-write + + + GNR + Group Number + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) + #1 + + + + + + + EMUXSEL + External Multiplexer Select Register + 0x03F0 + 32 + 0x00000000 + 0xFFFFFFFF + + + EMUXGRP0 + External Multiplexer Group for Interface x + 0 + 3 + read-write + + + EMUXGRP1 + External Multiplexer Group for Interface x + 4 + 7 + read-write + + + + + + + VADC_G0 + Analog to Digital Converter + VADC + VADC_G + 0x40004400 + + 0x0 + 0x400 + registers + + + VADC0_G0_0 + Analog to Digital Converter Group 0 + 18 + + + VADC0_G0_1 + Analog to Digital Converter Group 0 + 19 + + + VADC0_G0_2 + Analog to Digital Converter Group 0 + 20 + + + VADC0_G0_3 + Analog to Digital Converter Group 0 + 21 + + + + ARBCFG + Arbitration Configuration Register + 0x0080 + 32 + 0x00000000 + 0xFFFFFFFF + + + ANONC + Analog Converter Control + 0 + 1 + read-write + + + ARBRND + Arbitration Round Length + 4 + 5 + read-write + + + value1 + 4 arbitration slots per round (tARB = 4 / fADCD) + #00 + + + value2 + 8 arbitration slots per round (tARB = 8 / fADCD) + #01 + + + value3 + 16 arbitration slots per round (tARB = 16 / fADCD) + #10 + + + value4 + 20 arbitration slots per round (tARB = 20 / fADCD) + #11 + + + + + ARBM + Arbitration Mode + 7 + 7 + read-write + + + value1 + The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ). + #0 + + + value2 + The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported. + #1 + + + + + ANONS + Analog Converter Control Status + 16 + 17 + read-only + + + value1 + Analog converter off + #00 + + + value4 + Normal operation (permanently on) + #11 + + + + + CAL + Start-Up Calibration Active Indication + 28 + 28 + read-only + + + value1 + Completed or not yet started + #0 + + + value2 + Start-up calibration phase is active + #1 + + + + + BUSY + Converter Busy Flag + 30 + 30 + read-only + + + value1 + Not busy + #0 + + + value2 + Converter is busy with a conversion + #1 + + + + + SAMPLE + Sample Phase Flag + 31 + 31 + read-only + + + value1 + Converting or idle + #0 + + + value2 + Input signal is currently sampled + #1 + + + + + + + ARBPR + Arbitration Priority Register + 0x0084 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIO0 + Priority of Request Source x + 0 + 1 + read-write + + + value1 + Lowest priority is selected. + #00 + + + value2 + Highest priority is selected. + #11 + + + + + PRIO1 + Priority of Request Source x + 4 + 5 + read-write + + + value1 + Lowest priority is selected. + #00 + + + value2 + Highest priority is selected. + #11 + + + + + PRIO2 + Priority of Request Source x + 8 + 9 + read-write + + + value1 + Lowest priority is selected. + #00 + + + value2 + Highest priority is selected. + #11 + + + + + CSM0 + Conversion Start Mode of Request Source x + 3 + 3 + read-write + + + value1 + Wait-for-start mode + #0 + + + value2 + Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. + #1 + + + + + CSM1 + Conversion Start Mode of Request Source x + 7 + 7 + read-write + + + value1 + Wait-for-start mode + #0 + + + value2 + Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. + #1 + + + + + CSM2 + Conversion Start Mode of Request Source x + 11 + 11 + read-write + + + value1 + Wait-for-start mode + #0 + + + value2 + Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. + #1 + + + + + ASEN0 + Arbitration Slot 0 Enable + 24 + 24 + read-write + + + value1 + The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. + #0 + + + value2 + The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. + #1 + + + + + ASEN1 + Arbitration Slot 1 Enable + 25 + 25 + read-write + + + value1 + The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. + #0 + + + value2 + The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. + #1 + + + + + ASEN2 + Arbitration Slot 2 Enable + 26 + 26 + read-write + + + value1 + The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. + #0 + + + value2 + The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. + #1 + + + + + + + CHASS + Channel Assignment Register + 0x0088 + 32 + 0x00000000 + 0xFFFFFFFF + + + ASSCH0 + Assignment for Channel 0 + 0 + 0 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH1 + Assignment for Channel 1 + 1 + 1 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH2 + Assignment for Channel 2 + 2 + 2 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH3 + Assignment for Channel 3 + 3 + 3 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH4 + Assignment for Channel 4 + 4 + 4 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH5 + Assignment for Channel 5 + 5 + 5 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH6 + Assignment for Channel 6 + 6 + 6 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH7 + Assignment for Channel 7 + 7 + 7 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + + + 2 + 4 + ICLASS[%s] + Input Class Register + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + STCS + Sample Time Control for Standard Conversions + 0 + 4 + read-write + + + CMS + Conversion Mode for Standard Conversions + 8 + 10 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + STCE + Sample Time Control for EMUX Conversions + 16 + 20 + read-write + + + CME + Conversion Mode for EMUX Conversions + 24 + 26 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + + + ALIAS + Alias Register + 0x00B0 + 32 + 0x00000100 + 0xFFFFFFFF + + + ALIAS0 + Alias Value for CH0 Conversion Requests + 0 + 4 + read-write + + + ALIAS1 + Alias Value for CH1 Conversion Requests + 8 + 12 + read-write + + + + + BOUND + Boundary Select Register + 0x00B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOUNDARY0 + Boundary Value 0 for Limit Checking + 0 + 11 + read-write + + + BOUNDARY1 + Boundary Value 1 for Limit Checking + 16 + 27 + read-write + + + + + SYNCTR + Synchronization Control Register + 0x00C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + STSEL + Start Selection + 0 + 1 + read-write + + + value1 + Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC + #00 + + + value2 + Kernel is synchronization slave: Control information from input CI1 + #01 + + + value3 + Kernel is synchronization slave: Control information from input CI2 + #10 + + + value4 + Kernel is synchronization slave: Control information from input CI3 + #11 + + + + + EVALR1 + Evaluate Ready Input Rx + 4 + 4 + read-write + + + value1 + No ready input control + #0 + + + value2 + Ready input Rx is considered for the start of a parallel conversion of this conversion group + #1 + + + + + EVALR2 + Evaluate Ready Input Rx + 5 + 5 + read-write + + + value1 + No ready input control + #0 + + + value2 + Ready input Rx is considered for the start of a parallel conversion of this conversion group + #1 + + + + + EVALR3 + Evaluate Ready Input Rx + 6 + 6 + read-write + + + value1 + No ready input control + #0 + + + value2 + Ready input Rx is considered for the start of a parallel conversion of this conversion group + #1 + + + + + + + BFL + Boundary Flag Register + 0x00C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BFL0 + Boundary Flag 0 + 0 + 0 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFL1 + Boundary Flag 1 + 1 + 1 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFL2 + Boundary Flag 2 + 2 + 2 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFL3 + Boundary Flag 3 + 3 + 3 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFA0 + Boundary Flag 0 Activation Select + 8 + 8 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFA1 + Boundary Flag 1 Activation Select + 9 + 9 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFA2 + Boundary Flag 2 Activation Select + 10 + 10 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFA3 + Boundary Flag 3 Activation Select + 11 + 11 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFI0 + Boundary Flag 0 Inversion Control + 16 + 16 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + BFI1 + Boundary Flag 1 Inversion Control + 17 + 17 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + BFI2 + Boundary Flag 2 Inversion Control + 18 + 18 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + BFI3 + Boundary Flag 3 Inversion Control + 19 + 19 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + + + BFLS + Boundary Flag Software Register + 0x00CC + 32 + 0x00000000 + 0xFFFFFFFF + + + BFC0 + Boundary Flag 0 Clear + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFC1 + Boundary Flag 1 Clear + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFC2 + Boundary Flag 2 Clear + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFC3 + Boundary Flag 3 Clear + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFS0 + Boundary Flag 0 Set + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + BFS1 + Boundary Flag 1 Set + 17 + 17 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + BFS2 + Boundary Flag 2 Set + 18 + 18 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + BFS3 + Boundary Flag 3 Set + 19 + 19 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + + + BFLC + Boundary Flag Control Register + 0x00D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BFM0 + Boundary Flag y Mode Control + 0 + 3 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + BFM1 + Boundary Flag y Mode Control + 4 + 7 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + BFM2 + Boundary Flag y Mode Control + 8 + 11 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + BFM3 + Boundary Flag y Mode Control + 12 + 15 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + + + BFLNP + Boundary Flag Node Pointer Register + 0x00D4 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + BFL0NP + Boundary Flag y Node Pointer + 0 + 3 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + BFL1NP + Boundary Flag y Node Pointer + 4 + 7 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + BFL2NP + Boundary Flag y Node Pointer + 8 + 11 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + BFL3NP + Boundary Flag y Node Pointer + 12 + 15 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + + + QCTRL0 + Queue 0 Source Control Register + 0x0100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCRESREG + Source-specific Result Register + 0 + 3 + read-write + + + value1 + Use GxCHCTRy.RESREG to select a group result register + #0000 + + + value2 + Store result in group result register GxRES1 + #0001 + + + value3 + Store result in group result register GxRES15 + #1111 + + + + + XTSEL + External Trigger Input Selection + 8 + 11 + read-write + + + XTLVL + External Trigger Level + 12 + 12 + read-only + + + XTMODE + Trigger Operating Mode + 13 + 14 + read-write + + + value1 + No external trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon any edge + #11 + + + + + XTWC + Write Control for Trigger Configuration + 15 + 15 + write-only + + + value1 + No write access to trigger configuration + #0 + + + value2 + Bitfields XTMODE and XTSEL can be written + #1 + + + + + GTSEL + Gate Input Selection + 16 + 19 + read-write + + + GTLVL + Gate Input Level + 20 + 20 + read-only + + + GTWC + Write Control for Gate Configuration + 23 + 23 + write-only + + + value1 + No write access to gate configuration + #0 + + + value2 + Bitfield GTSEL can be written + #1 + + + + + TMEN + Timer Mode Enable + 28 + 28 + read-write + + + value1 + No timer mode: standard gating mechanism can be used + #0 + + + value2 + Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled + #1 + + + + + TMWC + Write Control for Timer Mode + 31 + 31 + write-only + + + value1 + No write access to timer mode + #0 + + + value2 + Bitfield TMEN can be written + #1 + + + + + + + QMR0 + Queue 0 Mode Register + 0x0104 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENGT + Enable Gate + 0 + 1 + read-write + + + value1 + No conversion requests are issued + #00 + + + value2 + Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register + #01 + + + value3 + Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1 + #10 + + + value4 + Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0 + #11 + + + + + ENTR + Enable External Trigger + 2 + 2 + read-write + + + value1 + External trigger disabled + #0 + + + value2 + The selected edge at the selected trigger input signal REQTR generates the trigger event + #1 + + + + + CLRV + Clear Valid Bit + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. + #1 + + + + + TREV + Trigger Event + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Generate a trigger event by software + #1 + + + + + FLUSH + Flush Queue + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry. + #1 + + + + + CEV + Clear Event Flag + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit EV + #1 + + + + + RPTDIS + Repeat Disable + 16 + 16 + read-write + + + value1 + A cancelled conversion is repeated + #0 + + + value2 + A cancelled conversion is discarded + #1 + + + + + + + QSR0 + Queue 0 Status Register + 0x0108 + 32 + 0x00000020 + 0xFFFFFFFF + + + FILL + Filling Level for Queue 2 + 0 + 3 + read-only + + + value1 + There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue + #0000 + + + value2 + There are 2 valid entries in the queue + #0001 + + + value3 + There are 3 valid entries in the queue + #0010 + + + value4 + There are 8 valid entries in the queue + #0111 + + + + + EMPTY + Queue Empty + 5 + 5 + read-only + + + value1 + There are valid entries in the queue (see FILL) + #0 + + + value2 + No valid entries (queue is empty) + #1 + + + + + REQGT + Request Gate Level + 7 + 7 + read-only + + + value1 + The gate input is low + #0 + + + value2 + The gate input is high + #1 + + + + + EV + Event Detected + 8 + 8 + read-only + + + value1 + No trigger event + #0 + + + value2 + A trigger event has been detected + #1 + + + + + + + Q0R0 + Queue 0 Register 0 + 0x010C + 32 + 0x00000000 + 0xFFFFFFFF + + + REQCHNR + Request Channel Number + 0 + 4 + read-only + + + RF + Refill + 5 + 5 + read-only + + + value1 + The request is discarded after the conversion start. + #0 + + + value2 + The request is automatically refilled into the queue after the conversion start. + #1 + + + + + ENSI + Enable Source Interrupt + 6 + 6 + read-only + + + value1 + No request source interrupt + #0 + + + value2 + A request source event interrupt is generated upon a request source event (related conversion is finished) + #1 + + + + + EXTR + External Trigger + 7 + 7 + read-only + + + value1 + A valid queue entry immediately leads to a conversion request + #0 + + + value2 + The request handler waits for a trigger event + #1 + + + + + V + Request Channel Number Valid + 8 + 8 + read-only + + + value1 + No valid queue entry + #0 + + + value2 + The queue entry is valid and leads to a conversion request + #1 + + + + + + + QINR0 + Queue 0 Input Register + 0x0110 + 32 + 0x00000000 + 0xFFFFFFFF + + + REQCHNR + Request Channel Number + 0 + 4 + write-only + + + RF + Refill + 5 + 5 + write-only + + + value1 + No refill: this queue entry is converted once and then invalidated + #0 + + + value2 + Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started + #1 + + + + + ENSI + Enable Source Interrupt + 6 + 6 + write-only + + + value1 + No request source interrupt + #0 + + + value2 + A request source event interrupt is generated upon a request source event (related conversion is finished) + #1 + + + + + EXTR + External Trigger + 7 + 7 + write-only + + + value1 + A valid queue entry immediately leads to a conversion request. + #0 + + + value2 + A valid queue entry waits for a trigger event to occur before issuing a conversion request. + #1 + + + + + + + QBUR0 + Queue 0 Backup Register + QINR0 + 0x0110 + 32 + 0x00000000 + 0xFFFFFFFF + + + REQCHNR + Request Channel Number + 0 + 4 + read-only + + + RF + Refill + 5 + 5 + read-only + + + ENSI + Enable Source Interrupt + 6 + 6 + read-only + + + EXTR + External Trigger + 7 + 7 + read-only + + + V + Request Channel Number Valid + 8 + 8 + read-only + + + value1 + Backup register not valid + #0 + + + value2 + Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested. + #1 + + + + + + + ASCTRL + Autoscan Source Control Register + 0x0120 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCRESREG + Source-specific Result Register + 0 + 3 + read-write + + + value1 + Use GxCHCTRy.RESREG to select a group result register + #0000 + + + value2 + Store result in group result register GxRES1 + #0001 + + + value3 + Store result in group result register GxRES15 + #1111 + + + + + XTSEL + External Trigger Input Selection + 8 + 11 + read-write + + + XTLVL + External Trigger Level + 12 + 12 + read-only + + + XTMODE + Trigger Operating Mode + 13 + 14 + read-write + + + value1 + No external trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon any edge + #11 + + + + + XTWC + Write Control for Trigger Configuration + 15 + 15 + write-only + + + value1 + No write access to trigger configuration + #0 + + + value2 + Bitfields XTMODE and XTSEL can be written + #1 + + + + + GTSEL + Gate Input Selection + 16 + 19 + read-write + + + GTLVL + Gate Input Level + 20 + 20 + read-only + + + GTWC + Write Control for Gate Configuration + 23 + 23 + write-only + + + value1 + No write access to gate configuration + #0 + + + value2 + Bitfield GTSEL can be written + #1 + + + + + TMEN + Timer Mode Enable + 28 + 28 + read-write + + + value1 + No timer mode: standard gating mechanism can be used + #0 + + + value2 + Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled + #1 + + + + + TMWC + Write Control for Timer Mode + 31 + 31 + write-only + + + value1 + No write access to timer mode + #0 + + + value2 + Bitfield TMEN can be written + #1 + + + + + + + ASMR + Autoscan Source Mode Register + 0x0124 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENGT + Enable Gate + 0 + 1 + read-write + + + value1 + No conversion requests are issued + #00 + + + value2 + Conversion requests are issued if at least one pending bit is set + #01 + + + value3 + Conversion requests are issued if at least one pending bit is set and REQGTx = 1. + #10 + + + value4 + Conversion requests are issued if at least one pending bit is set and REQGTx = 0. + #11 + + + + + ENTR + Enable External Trigger + 2 + 2 + read-write + + + value1 + External trigger disabled + #0 + + + value2 + The selected edge at the selected trigger input signal REQTR generates the load event + #1 + + + + + ENSI + Enable Source Interrupt + 3 + 3 + read-write + + + value1 + No request source interrupt + #0 + + + value2 + A request source interrupt is generated upon a request source event (last pending conversion is finished) + #1 + + + + + SCAN + Autoscan Enable + 4 + 4 + read-write + + + value1 + No autoscan + #0 + + + value2 + Autoscan functionality enabled: a request source event automatically generates a load event + #1 + + + + + LDM + Autoscan Source Load Event Mode + 5 + 5 + read-write + + + value1 + Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event + #0 + + + value2 + Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) + #1 + + + + + REQGT + Request Gate Level + 7 + 7 + read-only + + + value1 + The gate input is low + #0 + + + value2 + The gate input is high + #1 + + + + + CLRPND + Clear Pending Bits + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + The bits in register GxASPNDx are cleared + #1 + + + + + LDEV + Generate Load Event + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + A load event is generated + #1 + + + + + RPTDIS + Repeat Disable + 16 + 16 + read-write + + + value1 + A cancelled conversion is repeated + #0 + + + value2 + A cancelled conversion is discarded + #1 + + + + + + + ASSEL + Autoscan Source Channel Select Register + 0x0128 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHSEL0 + Channel Selection + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL1 + Channel Selection + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL2 + Channel Selection + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL3 + Channel Selection + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL4 + Channel Selection + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL5 + Channel Selection + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL6 + Channel Selection + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL7 + Channel Selection + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + + + ASPND + Autoscan Source Pending Register + 0x012C + 32 + 0x00000000 + 0xFFFFFFFF + + + CHPND0 + Channels Pending + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND1 + Channels Pending + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND2 + Channels Pending + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND3 + Channels Pending + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND4 + Channels Pending + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND5 + Channels Pending + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND6 + Channels Pending + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND7 + Channels Pending + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + + + CEFLAG + Channel Event Flag Register + 0x0180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CEV0 + Channel Event for Channel 0 + 0 + 0 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV1 + Channel Event for Channel 1 + 1 + 1 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV2 + Channel Event for Channel 2 + 2 + 2 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV3 + Channel Event for Channel 3 + 3 + 3 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV4 + Channel Event for Channel 4 + 4 + 4 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV5 + Channel Event for Channel 5 + 5 + 5 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV6 + Channel Event for Channel 6 + 6 + 6 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV7 + Channel Event for Channel 7 + 7 + 7 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + + + REFLAG + Result Event Flag Register + 0x0184 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV0 + Result Event for Result Register 0 + 0 + 0 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV1 + Result Event for Result Register 1 + 1 + 1 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV2 + Result Event for Result Register 2 + 2 + 2 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV3 + Result Event for Result Register 3 + 3 + 3 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV4 + Result Event for Result Register 4 + 4 + 4 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV5 + Result Event for Result Register 5 + 5 + 5 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV6 + Result Event for Result Register 6 + 6 + 6 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV7 + Result Event for Result Register 7 + 7 + 7 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV8 + Result Event for Result Register 8 + 8 + 8 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV9 + Result Event for Result Register 9 + 9 + 9 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV10 + Result Event for Result Register 10 + 10 + 10 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV11 + Result Event for Result Register 11 + 11 + 11 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV12 + Result Event for Result Register 12 + 12 + 12 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV13 + Result Event for Result Register 13 + 13 + 13 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV14 + Result Event for Result Register 14 + 14 + 14 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV15 + Result Event for Result Register 15 + 15 + 15 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + + + SEFLAG + Source Event Flag Register + 0x0188 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0 + Source Event 0/1 + 0 + 0 + read-write + + + value1 + No source event + #0 + + + value2 + A source event has occurred + #1 + + + + + SEV1 + Source Event 0/1 + 1 + 1 + read-write + + + value1 + No source event + #0 + + + value2 + A source event has occurred + #1 + + + + + + + CEFCLR + Channel Event Flag Clear Register + 0x0190 + 32 + 0x00000000 + 0xFFFFFFFF + + + CEV0 + Clear Channel Event for Channel 0 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV1 + Clear Channel Event for Channel 1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV2 + Clear Channel Event for Channel 2 + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV3 + Clear Channel Event for Channel 3 + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV4 + Clear Channel Event for Channel 4 + 4 + 4 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV5 + Clear Channel Event for Channel 5 + 5 + 5 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV6 + Clear Channel Event for Channel 6 + 6 + 6 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV7 + Clear Channel Event for Channel 7 + 7 + 7 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + + + REFCLR + Result Event Flag Clear Register + 0x0194 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV0 + Clear Result Event for Result Register 0 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV1 + Clear Result Event for Result Register 1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV2 + Clear Result Event for Result Register 2 + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV3 + Clear Result Event for Result Register 3 + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV4 + Clear Result Event for Result Register 4 + 4 + 4 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV5 + Clear Result Event for Result Register 5 + 5 + 5 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV6 + Clear Result Event for Result Register 6 + 6 + 6 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV7 + Clear Result Event for Result Register 7 + 7 + 7 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV8 + Clear Result Event for Result Register 8 + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV9 + Clear Result Event for Result Register 9 + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV10 + Clear Result Event for Result Register 10 + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV11 + Clear Result Event for Result Register 11 + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV12 + Clear Result Event for Result Register 12 + 12 + 12 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV13 + Clear Result Event for Result Register 13 + 13 + 13 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV14 + Clear Result Event for Result Register 14 + 14 + 14 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV15 + Clear Result Event for Result Register 15 + 15 + 15 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + + + SEFCLR + Source Event Flag Clear Register + 0x0198 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0 + Clear Source Event 0/1 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear the source event flag in GxSEFLAG + #1 + + + + + SEV1 + Clear Source Event 0/1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear the source event flag in GxSEFLAG + #1 + + + + + + + CEVNP0 + Channel Event Node Pointer Register 0 + 0x01A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CEV0NP + Service Request Node Pointer Channel Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV1NP + Service Request Node Pointer Channel Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV2NP + Service Request Node Pointer Channel Event i + 8 + 11 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV3NP + Service Request Node Pointer Channel Event i + 12 + 15 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV4NP + Service Request Node Pointer Channel Event i + 16 + 19 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV5NP + Service Request Node Pointer Channel Event i + 20 + 23 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV6NP + Service Request Node Pointer Channel Event i + 24 + 27 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV7NP + Service Request Node Pointer Channel Event i + 28 + 31 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + REVNP0 + Result Event Node Pointer Register 0 + 0x01B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV0NP + Service Request Node Pointer Result Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV1NP + Service Request Node Pointer Result Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV2NP + Service Request Node Pointer Result Event i + 8 + 11 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV3NP + Service Request Node Pointer Result Event i + 12 + 15 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV4NP + Service Request Node Pointer Result Event i + 16 + 19 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV5NP + Service Request Node Pointer Result Event i + 20 + 23 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV6NP + Service Request Node Pointer Result Event i + 24 + 27 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV7NP + Service Request Node Pointer Result Event i + 28 + 31 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + REVNP1 + Result Event Node Pointer Register 1 + 0x01B4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV8NP + Service Request Node Pointer Result Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV9NP + Service Request Node Pointer Result Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV10NP + Service Request Node Pointer Result Event i + 8 + 11 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV11NP + Service Request Node Pointer Result Event i + 12 + 15 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV12NP + Service Request Node Pointer Result Event i + 16 + 19 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV13NP + Service Request Node Pointer Result Event i + 20 + 23 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV14NP + Service Request Node Pointer Result Event i + 24 + 27 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV15NP + Service Request Node Pointer Result Event i + 28 + 31 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + SEVNP + Source Event Node Pointer Register + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0NP + Service Request Node Pointer Source Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + SEV1NP + Service Request Node Pointer Source Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + SRACT + Service Request Software Activation Trigger + 0x01C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AGSR0 + Activate Group Service Request Node 0 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + AGSR1 + Activate Group Service Request Node 1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + AGSR2 + Activate Group Service Request Node 2 + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + AGSR3 + Activate Group Service Request Node 3 + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR0 + Activate Shared Service Request Node 0 + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR1 + Activate Shared Service Request Node 1 + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR2 + Activate Shared Service Request Node 2 + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR3 + Activate Shared Service Request Node 3 + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + + + EMUXCTR + E0ternal Multiplexer Control Register + 0x01F0 + 32 + 0x00000000 + 0xFFFFFFFF + + + EMUXSET + External Multiplexer Start Selection + 0 + 2 + read-write + + + EMUXACT + External Multiplexer Actual Selection + 8 + 10 + read-only + + + EMUXCH + External Multiplexer Channel Select + 16 + 25 + read-write + + + EMUXMODE + External Multiplexer Mode + 26 + 27 + read-write + + + value1 + Software control (no hardware action) + #00 + + + value2 + Steady mode (use EMUXSET value) + #01 + + + value3 + Single-step mode + #10 + + + value4 + Sequence mode + #11 + + + + + EMXCOD + External Multiplexer Coding Scheme + 28 + 28 + read-write + + + value1 + Output the channel number in binary code + #0 + + + value2 + Output the channel number in Gray code + #1 + + + + + EMXST + External Multiplexer Sample Time Control + 29 + 29 + read-write + + + value1 + Use STCE whenever the setting changes + #0 + + + value2 + Use STCE for each conversion of an external channel + #1 + + + + + EMXCSS + External Multiplexer Channel Selection Style + 30 + 30 + read-only + + + value1 + Channel number: Bitfield EMUXCH selects an arbitrary channel + #0 + + + value2 + Channel enable: Each bit of bitfield EMUXCH selects the associated channel for EMUX control + #1 + + + + + EMXWC + Write Control for EMUX Configuration + 31 + 31 + write-only + + + value1 + No write access to EMUX cfg. + #0 + + + value2 + Bitfields EMXMODE, EMXCOD, EMXST, EMXCSS can be written + #1 + + + + + + + VFR + Valid Flag Register + 0x01F8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VF0 + Valid Flag of Result Register x + 0 + 0 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF1 + Valid Flag of Result Register x + 1 + 1 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF2 + Valid Flag of Result Register x + 2 + 2 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF3 + Valid Flag of Result Register x + 3 + 3 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF4 + Valid Flag of Result Register x + 4 + 4 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF5 + Valid Flag of Result Register x + 5 + 5 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF6 + Valid Flag of Result Register x + 6 + 6 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF7 + Valid Flag of Result Register x + 7 + 7 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF8 + Valid Flag of Result Register x + 8 + 8 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF9 + Valid Flag of Result Register x + 9 + 9 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF10 + Valid Flag of Result Register x + 10 + 10 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF11 + Valid Flag of Result Register x + 11 + 11 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF12 + Valid Flag of Result Register x + 12 + 12 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF13 + Valid Flag of Result Register x + 13 + 13 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF14 + Valid Flag of Result Register x + 14 + 14 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF15 + Valid Flag of Result Register x + 15 + 15 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + + + 8 + 4 + CHCTR[%s] + Channel Ctrl. Reg. + 0x0200 + 32 + 0x00000000 + 0xFFFFFFFF + + + ICLSEL + Input Class Select + 0 + 1 + read-write + + + value1 + Use group-specific class 0 + #00 + + + value2 + Use group-specific class 1 + #01 + + + value3 + Use global class 0 + #10 + + + value4 + Use global class 1 + #11 + + + + + BNDSELL + Lower Boundary Select + 4 + 5 + read-write + + + value1 + Use group-specific boundary 0 + #00 + + + value2 + Use group-specific boundary 1 + #01 + + + value3 + Use global boundary 0 + #10 + + + value4 + Use global boundary 1 + #11 + + + + + BNDSELU + Upper Boundary Select + 6 + 7 + read-write + + + value1 + Use group-specific boundary 0 + #00 + + + value2 + Use group-specific boundary 1 + #01 + + + value3 + Use global boundary 0 + #10 + + + value4 + Use global boundary 1 + #11 + + + + + CHEVMODE + Channel Event Mode + 8 + 9 + read-write + + + value1 + Never + #00 + + + value2 + NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) + #01 + + + value3 + NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) + #10 + + + value4 + NCM: Always (ignore band) FCM: If result switches to either level + #11 + + + + + SYNC + Synchronization Request + 10 + 10 + read-write + + + value1 + No synchroniz. request, standalone operation + #0 + + + value2 + Request a synchronized conversion of this channel (only taken into account for a master) + #1 + + + + + REFSEL + Reference Input Selection + 11 + 11 + read-write + + + value1 + Standard reference input VAREF + #0 + + + value2 + Alternate reference input from CH0 + #1 + + + + + RESREG + Result Register + 16 + 19 + read-write + + + value1 + Store result in group result register GxRES0 + #0000 + + + value2 + Store result in group result register GxRES15 + #1111 + + + + + RESTBS + Result Target for Background Source + 20 + 20 + read-write + + + value1 + Store results in the selected group result register + #0 + + + value2 + Store results in the global result register + #1 + + + + + RESPOS + Result Position + 21 + 21 + read-write + + + value1 + Store results left-aligned + #0 + + + value2 + Store results right-aligned + #1 + + + + + BWDCH + Broken Wire Detection Channel + 28 + 29 + read-write + + + value1 + Select VAGND + #00 + + + value2 + Select VAREF + #01 + + + + + BWDEN + Broken Wire Detection Enable + 30 + 30 + read-write + + + value1 + Normal operation + #0 + + + value2 + Additional preparation phase is enabled + #1 + + + + + + + 16 + 4 + RCR[%s] + Result Control Register + 0x0280 + 32 + 0x00000000 + 0xFFFFFFFF + + + DRCTR + Data Reduction Control + 16 + 19 + read-write + + + DMM + Data Modification Mode + 20 + 21 + read-write + + + value1 + Standard data reduction (accumulation) + #00 + + + value2 + Result filtering mode + #01 + + + value3 + Difference mode + #10 + + + + + WFR + Wait-for-Read Mode Enable + 24 + 24 + read-write + + + value1 + Overwrite mode + #0 + + + value2 + Wait-for-read mode enabled for this register + #1 + + + + + FEN + FIFO Mode Enable + 25 + 26 + read-write + + + value1 + Separate result register + #00 + + + value2 + Part of a FIFO structure: copy each new valid result + #01 + + + + + SRGEN + Service Request Generation Enable + 31 + 31 + read-write + + + value1 + No service request + #0 + + + value2 + Service request after a result event + #1 + + + + + + + 16 + 4 + RES[%s] + Result Register + 0x0300 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + RESULT + Result of Most Recent Conversion + 0 + 15 + read-write + + + DRC + Data Reduction Counter + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + value1 + Request source 0 + #00 + + + value2 + Request source 1 + #01 + + + value3 + Request source 2 + #10 + + + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-only + + + value1 + No new result available + #0 + + + value2 + Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated + #1 + + + + + + + 16 + 4 + RESD[%s] + Result Register, Debug + 0x0380 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of Most Recent Conversion + 0 + 15 + read-only + + + DRC + Data Reduction Counter + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + value1 + Request source 0 + #00 + + + value2 + Request source 1 + #01 + + + value3 + Request source 2 + #10 + + + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-only + + + value1 + No new result available + #0 + + + value2 + Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated + #1 + + + + + + + + + VADC_G1 + Analog to Digital Converter + VADC + 0x40004800 + + 0x0 + 0x400 + registers + + + VADC0_G1_0 + Analog to Digital Converter Group 1 + 22 + + + VADC0_G1_1 + Analog to Digital Converter Group 1 + 23 + + + VADC0_G1_2 + Analog to Digital Converter Group 1 + 24 + + + VADC0_G1_3 + Analog to Digital Converter Group 1 + 25 + + + + VADC_G2 + Analog to Digital Converter + VADC + 0x40004C00 + + 0x0 + 0x400 + registers + + + VADC0_G2_0 + Analog to Digital Converter Group 2 + 26 + + + VADC0_G2_1 + Analog to Digital Converter Group 2 + 27 + + + VADC0_G2_2 + Analog to Digital Converter Group 2 + 28 + + + VADC0_G2_3 + Analog to Digital Converter Group 2 + 29 + + + + VADC_G3 + Analog to Digital Converter + VADC + 0x40005000 + + 0x0 + 0x400 + registers + + + VADC0_G3_0 + Analog to Digital Converter Group 3 + 30 + + + VADC0_G3_1 + Analog to Digital Converter Group 3 + 31 + + + VADC0_G3_2 + Analog to Digital Converter Group 3 + 32 + + + VADC0_G3_3 + Analog to Digital Converter Group 3 + 33 + + + + DSD + Delta Sigma Demodulator + DSD + 0x40008000 + + 0x0 + 0x100 + registers + + + + CLC + Clock Control Register + 0x0000 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + value1 + On request: enable the module clock + #0 + + + value2 + Off request: stop the module clock + #1 + + + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + value1 + Module clock is enabled + #0 + + + value2 + Off: module is not clocked + #1 + + + + + EDIS + Sleep Mode Enable Control + 3 + 3 + read-write + + + value1 + Sleep mode request is enabled and functional + #0 + + + value2 + Module disregards the sleep mode control signal + #1 + + + + + + + ID + Module Identification Register + 0x0008 + 32 + 0x00A4C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + OCS + OCDS Control and Status Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUS + OCDS Suspend Control + 24 + 27 + read-write + + + value1 + Will not suspend + #0000 + + + value2 + Hard suspend: Clock is switched off immediately. + #0001 + + + value3 + Soft suspend channel 0 + #0010 + + + value4 + Soft suspend channel 1 + #0011 + + + value5 + Soft suspend channel 3 + #0101 + + + + + SUS_P + SUS Write Protection + 28 + 28 + write-only + + + SUSSTA + Suspend State + 29 + 29 + read-only + + + value1 + Module is not (yet) suspended + #0 + + + value2 + Module is suspended + #1 + + + + + + + GLOBCFG + Global Configuration Register + 0x0080 + 32 + 0x00000000 + 0xFFFFFFFF + + + MCSEL + Modulator Clock Select + 0 + 2 + read-write + + + value1 + Internal clock off, no source selected + #000 + + + value2 + fDSD + #001 + + + + + + + GLOBRC + Global Run Control Register + 0x0088 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0RUN + Channel 0 Run Control + 0 + 0 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + CH1RUN + Channel 1 Run Control + 1 + 1 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + CH2RUN + Channel 2 Run Control + 2 + 2 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + CH3RUN + Channel 3 Run Control + 3 + 3 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + + + CGCFG + Carrier Generator Configuration Register + 0x00A0 + 32 + 0x07100000 + 0xFFFFFFFF + + + CGMOD + Carrier Generator Operating Mode + 0 + 1 + read-write + + + value1 + Stopped + #00 + + + value2 + Square wave + #01 + + + value3 + Triangle + #10 + + + value4 + Sine wave + #11 + + + + + BREV + Bit-Reverse PWM Generation + 2 + 2 + read-write + + + value1 + Normal mode + #0 + + + value2 + Bit-reverse mode + #1 + + + + + SIGPOL + Signal Polarity + 3 + 3 + read-write + + + value1 + Normal: carrier signal begins with +1 + #0 + + + value2 + Inverted: carrier signal begins with -1 + #1 + + + + + DIVCG + Divider Factor for the PWM Pattern Signal Generator + 4 + 7 + read-write + + + value1 + fCG = fCLK / 2 + 0x0 + + + value2 + fCG = fCLK / 4 + 0x1 + + + value3 + fCG = fCLK / 6 + 0x2 + + + value4 + fCG = fCLK / 32 + 0xF + + + + + RUN + Run Indicator + 15 + 15 + read-only + + + value1 + Stopped (cleared at the end of a period) + #0 + + + value2 + Running + #1 + + + + + BITCOUNT + Bit Counter + 16 + 20 + read-only + + + STEPCOUNT + Step Counter + 24 + 27 + read-only + + + STEPS + Step Counter Sign + 28 + 28 + read-only + + + value1 + Step counter value is positive + #0 + + + value2 + Step counter value is negative + #1 + + + + + STEPD + Step Counter Direction + 29 + 29 + read-only + + + value1 + Step counter is counting up + #0 + + + value2 + Step counter is counting down + #1 + + + + + SGNCG + Sign Signal from Carrier Generator + 30 + 30 + read-only + + + value1 + Positive values + #0 + + + value2 + Negative values + #1 + + + + + + + EVFLAG + Event Flag Register + 0x00E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESEV0 + Result Event + 0 + 0 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + RESEV1 + Result Event + 1 + 1 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + RESEV2 + Result Event + 2 + 2 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + RESEV3 + Result Event + 3 + 3 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + ALEV0 + Alarm Event + 16 + 16 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + ALEV1 + Alarm Event + 17 + 17 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + ALEV2 + Alarm Event + 18 + 18 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + ALEV3 + Alarm Event + 19 + 19 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + + + EVFLAGCLR + Event Flag Clear Register + 0x00E4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESEC0 + Result Event Clear + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + RESEC1 + Result Event Clear + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + RESEC2 + Result Event Clear + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + RESEC3 + Result Event Clear + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + ALEC0 + Alarm Event Clear + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + ALEC1 + Alarm Event Clear + 17 + 17 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + ALEC2 + Alarm Event Clear + 18 + 18 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + ALEC3 + Alarm Event Clear + 19 + 19 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + + + + + DSD_CH0 + Delta Sigma Demodulator + DSD + DSD_CH + 0x40008100 + + 0x0 + 0x100 + registers + + + DSD0_M_0 + Delta Sigma Demodulator Main + 34 + + + DSD0_A_4 + Delta Sigma Demodulator Auxiliary + 38 + + + + MODCFG + Modulator Configuration Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIVM + Divider Factor for Modulator Clock + 16 + 19 + read-write + + + value1 + fMOD = fCLK / 2 + 0x0 + + + value2 + fMOD = fCLK / 4 + 0x1 + + + value3 + fMOD = fCLK / 6 + 0x2 + + + value4 + fMOD = fCLK / 32 + 0xF + + + + + DWC + Write Control for Divider Factor + 23 + 23 + write-only + + + value1 + No write access to divider factor + #0 + + + value2 + Bitfield DIVM can be written + #1 + + + + + + + DICFG + Demodulator Input Configuration Register + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSRC + Input Data Source Select + 0 + 3 + read-write + + + value1 + Disconnected + #000X + + + value2 + External, from input A, direct + #0010 + + + value3 + External, from input A, inverted + #0011 + + + value4 + External, from input B, direct + #0100 + + + value5 + External, from input B, inverted + #0101 + + + + + DSWC + Write Control for Data Selection + 7 + 7 + write-only + + + value1 + No write access to data parameters + #0 + + + value2 + Bitfield DSRC can be written + #1 + + + + + ITRMODE + Integrator Trigger Mode + 8 + 9 + read-write + + + value1 + No integration trigger, integrator bypassed, INTEN = 0 all the time + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + No trigger, integrator active all the time, INTEN = 1 all the time + #11 + + + + + TSTRMODE + Timestamp Trigger Mode + 10 + 11 + read-write + + + value1 + No timestamp trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon each edge + #11 + + + + + TRSEL + Trigger Select + 12 + 14 + read-write + + + TRWC + Write Control for Trigger Parameters + 15 + 15 + write-only + + + value1 + No write access to trigger parameters + #0 + + + value2 + Bitfields TRSEL, TSTRMODE, ITRMODE can be written + #1 + + + + + CSRC + Sample Clock Source Select + 16 + 19 + read-write + + + value2 + External, from input A + #0001 + + + value3 + External, from input B + #0010 + + + value4 + External, from input C + #0011 + + + value5 + External, from input D + #0100 + + + value6 + Internal clock + #1111 + + + + + STROBE + Data Strobe Generatoion Mode + 20 + 23 + read-write + + + value1 + No data strobe + #0000 + + + value2 + Direct clock, a sample trigger is generated at each rising clock edge + #0001 + + + value3 + Direct clock, a sample trigger is generated at each falling clock edge + #0010 + + + value4 + Double data, a sample trigger is generated at each rising and falling clock edge + #0011 + + + value6 + Double clock, a sample trigger is generated at every 2nd rising clock edge + #0101 + + + value7 + Double clock, a sample trigger is generated at every 2nd falling clock edge + #0110 + + + + + SCWC + Write Control for Strobe/Clock Selection + 31 + 31 + write-only + + + value1 + No write access to strobe/clock parameters + #0 + + + value2 + Bitfields STROBE, CSRC can be written + #1 + + + + + + + FCFGC + Filter Configuration Register, Main CIC Filter + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFMDF + CIC Filter (Main Chain) Decimation Factor + 0 + 7 + read-write + + + CFMC + CIC Filter (Main Chain) Configuration + 8 + 9 + read-write + + + value1 + CIC1 + #00 + + + value2 + CIC2 + #01 + + + value3 + CIC3 + #10 + + + value4 + CICF + #11 + + + + + CFEN + CIC Filter Enable + 10 + 10 + read-write + + + value1 + CIC filter disabled and bypassed + #0 + + + value2 + Enable CIC filter + #1 + + + + + SRGM + Service Request Generation Main Chain + 14 + 15 + read-write + + + value1 + Never, service requests disabled + #00 + + + value4 + Always, for each new result value + #11 + + + + + CFMSV + CIC Filter (Main Chain) Start Value + 16 + 23 + read-write + + + CFMDCNT + CIC Filter (Main Chain) Decimation Counter + 24 + 31 + read-only + + + + + FCFGA + Filter Configuration Register, Auxiliary Filter + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFADF + CIC Filter (Auxiliary) Decimation Factor + 0 + 7 + read-write + + + CFAC + CIC Filter (Auxiliary) Configuration + 8 + 9 + read-write + + + value1 + CIC1 + #00 + + + value2 + CIC2 + #01 + + + value3 + CIC3 + #10 + + + value4 + CICF + #11 + + + + + SRGA + Service Request Generation Auxiliary Filter + 10 + 11 + read-write + + + value1 + Never, service requests disabled + #00 + + + value2 + Auxiliary filter: As selected by bitfields ESEL and EGT (if integrator enabled) + #01 + + + value3 + Alternate source: Capturing of a sign delay value to register CGSYNCx (x = 0 - 3) + #10 + + + + + ESEL + Event Select + 12 + 13 + read-write + + + value1 + Always, for each new result value + #00 + + + value2 + If result is inside the boundary band + #01 + + + value3 + If result is outside the boundary band + #10 + + + + + EGT + Event Gating + 14 + 14 + read-write + + + value1 + Separate: generate events according to ESEL + #0 + + + value2 + Coupled: generate events only when the integrator is enabled and after the discard phase defined by bitfield NVALDISWhile the integrator is bypassed, event gating is disabled, i.e. service requests are generated according to bitfield ESEL. The event gating suppresses service requests, result values are still stored in register RESAx. + #1 + + + + + CFADCNT + CIC Filter (Auxiliary) Decimation Counter + 24 + 31 + read-only + + + + + IWCTR + Integration Window Control Register + 0x0020 + 32 + 0x00000000 + 0xFFFFFFFF + + + NVALCNT + Number of Values Counted + 0 + 5 + read-only + + + INTEN + Integration Enable + 7 + 7 + read-only + + + value1 + Integration stopped. INTEN is cleared at the end of the integration window, i.e. upon the inverse trigger event transition of the external trigger signal. + #0 + + + value2 + Integration enabled. INTEN is set upon the defined trigger event. + #1 + + + + + REPCNT + Integration Cycle Counter + 8 + 11 + read-only + + + REPVAL + Number of Integration Cycles + 12 + 15 + read-write + + + NVALDIS + Number of Values Discarded + 16 + 21 + read-write + + + IWS + Integration Window SIze + 23 + 23 + read-write + + + value1 + Internal control: stop integrator after REPVAL+1 integration cycles + #0 + + + value2 + External control: stop integrator when bit INTEN becomes 0 + #1 + + + + + NVALINT + Number of Values Integrated + 24 + 29 + read-write + + + + + BOUNDSEL + Boundary Select Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOUNDARYL + Lower Boundary Value for Limit Checking + 0 + 15 + read-write + + + BOUNDARYU + Upper Boundary Value for Limit Checking + 16 + 31 + read-write + + + + + RESM + Result Register, Main Filter + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-only + + + + + OFFM + Offset Register, Main Filter + 0x0038 + 32 + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Offset Value + 0 + 15 + read-write + + + + + RESA + Result Register, Auxiliary Filter + 0x0040 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-only + + + + + TSTMP + Time-Stamp Register + 0x0050 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-only + + + CFMDCNT + CIC Filter (Main Chain) Decimation Counter + 16 + 23 + read-only + + + NVALCNT + Number of Values Counted + 24 + 29 + read-only + + + + + CGSYNC + Carrier Generator Synchronization Register + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SDCOUNT + Sign Delay Counter + 0 + 7 + read-only + + + SDCAP + Sign Delay Capture Value + 8 + 15 + read-only + + + SDPOS + Sign Delay Value for Positive Halfwave + 16 + 23 + read-write + + + SDNEG + Sign Delay Value for Negative Halfwave + 24 + 31 + read-write + + + + + RECTCFG + Rectification Configuration Register + 0x00A8 + 32 + 0x80000000 + 0xFFFFFFFF + + + RFEN + Rectification Enable + 0 + 0 + read-write + + + value1 + No rectification, data not altered + #0 + + + value2 + Data are rectified according to SGND + #1 + + + + + SSRC + Sign Source + 4 + 5 + read-write + + + value1 + On-chip carrier generator + #00 + + + value2 + Sign of result of next channel + #01 + + + value3 + External sign signal A + #10 + + + value4 + External sign signal B + #11 + + + + + SDVAL + Valid Flag + 15 + 15 + read-only + + + value1 + No new result available + #0 + + + value2 + Bitfield SDCAP has been updated with a new captured value and has not yet been read + #1 + + + + + SGNCS + Selected Carrier Sign Signal + 30 + 30 + read-only + + + value1 + Positive values + #0 + + + value2 + Negative values + #1 + + + + + SGND + Sign Signal Delayed + 31 + 31 + read-only + + + value1 + Positive values + #0 + + + value2 + Negative values + #1 + + + + + + + + + DSD_CH1 + Delta Sigma Demodulator + DSD + 0x40008200 + + 0x0 + 0x100 + registers + + + DSD0_M_1 + Delta Sigma Demodulator Main + 35 + + + DSD0_A_5 + Delta Sigma Demodulator Auxiliary + 39 + + + + DSD_CH2 + Delta Sigma Demodulator + DSD + 0x40008300 + + 0x0 + 0x100 + registers + + + DSD0_M_2 + Delta Sigma Demodulator Main + 36 + + + DSD0_A_6 + Delta Sigma Demodulator Auxiliary + 40 + + + + DSD_CH3 + Delta Sigma Demodulator + DSD + 0x40008400 + + 0x0 + 0x100 + registers + + + DSD0_M_3 + Delta Sigma Demodulator Main + 37 + + + DSD0_A_7 + Delta Sigma Demodulator Auxiliary + 41 + + + + DAC + Digital to Analog Converter + 0x48018000 + + 0x0 + 0x4000 + registers + + + DAC0_0 + Digital to Analog Converter + 42 + + + DAC0_1 + Digital to Analog Converter + 43 + + + + ID + Module Identification Register + 0x000 + 32 + 0x00A5C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + DAC0CFG0 + DAC0 Configuration Register 0 + 0x004 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQ + Integer Frequency Divider Value + 0 + 19 + read-write + + + MODE + Enables and Sets the Mode for DAC0 + 20 + 22 + read-write + + + value1 + disable/switch-off DAC + #000 + + + value2 + Single Value Mode + #001 + + + value3 + Data Mode + #010 + + + value4 + Patgen Mode + #011 + + + value5 + Noise Mode + #100 + + + value6 + Ramp Mode + #101 + + + value7 + na + #110 + + + value8 + na + #111 + + + + + SIGN + Selects Between Signed and Unsigned DAC0 Mode + 23 + 23 + read-write + + + value1 + DAC expects unsigned input data + #0 + + + value2 + DAC expects signed input data + #1 + + + + + FIFOIND + Current write position inside the data FIFO + 24 + 25 + read-only + + + FIFOEMP + Indicate if the FIFO is empty + 26 + 26 + read-only + + + value1 + FIFO not empty + #0 + + + value2 + FIFO empty + #1 + + + + + FIFOFUL + Indicate if the FIFO is full + 27 + 27 + read-only + + + value1 + FIFO not full + #0 + + + value2 + FIFO full + #1 + + + + + NEGATE + Negates the DAC0 output + 28 + 28 + read-write + + + value1 + DAC output not negated + #0 + + + value2 + DAC output negated + #1 + + + + + SIGNEN + Enable Sign Output of DAC0 Pattern Generator + 29 + 29 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + SREN + Enable DAC0 service request interrupt generation + 30 + 30 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + RUN + RUN indicates the current DAC0 operation status + 31 + 31 + read-only + + + value1 + DAC0 channel disabled + #0 + + + value2 + DAC0 channel in operation + #1 + + + + + + + DAC0CFG1 + DAC0 Configuration Register 1 + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCALE + Scale value for up- or downscale of the DAC0 input data in steps by the power of 2 (=shift operation) + 0 + 2 + read-write + + + value1 + no shift = multiplication/division by 1 + #000 + + + value2 + shift by 1 = multiplication/division by 2 + #001 + + + value3 + shift by 2 = multiplication/division by 4 + #010 + + + value4 + shift left by 3 = multiplication/division by 8 + #011 + + + value5 + shift left by 4 = multiplication/division by 16 + #100 + + + value6 + shift left by 5 = multiplication/division by 32 + #101 + + + value7 + shift left by 6 = multiplication/division by 64 + #110 + + + value8 + shift left by 7 = multiplication/division by 128 + #111 + + + + + MULDIV + Switch between up- and downscale of the DAC0 input data values + 3 + 3 + read-write + + + value1 + downscale = division (shift SCALE positions to the right) + #0 + + + value2 + upscale = multiplication (shift SCALE positions to the left) + #1 + + + + + OFFS + 8-bit offset value addition + 4 + 11 + read-write + + + TRIGSEL + Selects one of the eight external trigger sources for DAC0 + 12 + 14 + read-write + + + DATMOD + Switch between independent or simultaneous DAC mode and select the input data register for DAC0 and DAC1 + 15 + 15 + read-write + + + value1 + independent data handling - process data from DATA0 register (bits 11:0) to DAC0 and data from DATA1 register (bits 11:0) to DAC1 + #0 + + + value2 + simultaneous data handling - process data from DAC01 register to both DACs (bits 11:0 to DAC0 and bits 23:12 to DAC1). + #1 + + + + + SWTRIG + Software Trigger + 16 + 16 + read-write + + + TRIGMOD + Select the trigger source for channel 0 + 17 + 18 + read-write + + + value1 + internal Trigger (integer divided clock - see FREQ parameter) + #00 + + + value2 + external Trigger (preselected trigger by TRIGSEL parameter) + #01 + + + value3 + software Trigger (see SWTRIG parameter) + #10 + + + + + ANACFG + DAC0 analog configuration/calibration parameters + 19 + 23 + read-write + + + ANAEN + Enable analog DAC for channel 0 + 24 + 24 + read-write + + + value1 + DAC0 is set to standby (analog output only) + #0 + + + value2 + enable DAC0 (analog output only) + #1 + + + + + REFCFGL + Lower 4 band-gap configuration/calibration parameters + 28 + 31 + read-write + + + + + DAC1CFG0 + DAC1 Configuration Register 0 + 0x00C + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQ + Integer Frequency Divider Value + 0 + 19 + read-write + + + MODE + Enables and sets the Mode for DAC1 + 20 + 22 + read-write + + + value1 + disable/switch-off DAC + #000 + + + value2 + Single Value Mode + #001 + + + value3 + Data Mode + #010 + + + value4 + Patgen Mode + #011 + + + value5 + Noise Mode + #100 + + + value6 + Ramp Mode + #101 + + + value7 + na + #110 + + + value8 + na + #111 + + + + + SIGN + Selects between signed and unsigned DAC1 mode + 23 + 23 + read-write + + + value1 + DAC expects unsigned input data + #0 + + + value2 + DAC expects signed input data + #1 + + + + + FIFOIND + Current write position inside the data FIFO + 24 + 25 + read-only + + + FIFOEMP + Indicate if the FIFO is empty + 26 + 26 + read-only + + + value1 + FIFO not empty + #0 + + + value2 + FIFO empty + #1 + + + + + FIFOFUL + Indicate if the FIFO is full + 27 + 27 + read-only + + + value1 + FIFO not full + #0 + + + value2 + FIFO full + #1 + + + + + NEGATE + Negates the DAC1 output + 28 + 28 + read-write + + + value1 + DAC output not negated + #0 + + + value2 + DAC output negated + #1 + + + + + SIGNEN + Enable sign output of DAC1 pattern generator + 29 + 29 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + SREN + Enable DAC1 service request interrupt generation + 30 + 30 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + RUN + RUN indicates the current DAC1 operation status + 31 + 31 + read-only + + + value1 + DAC1 channel disabled + #0 + + + value2 + DAC1 channel in operation + #1 + + + + + + + DAC1CFG1 + DAC1 Configuration Register 1 + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCALE + Scale value for up- or downscale of the DAC1 input data in steps by the power of 2 (=shift operation) + 0 + 2 + read-write + + + value1 + no shift = multiplication/division by 1 + #000 + + + value2 + shift by 1 = multiplication/division by 2 + #001 + + + value3 + shift by 2 = multiplication/division by 4 + #010 + + + value4 + shift left by 3 = multiplication/division by 8 + #011 + + + value5 + shift left by 4 = multiplication/division by 16 + #100 + + + value6 + shift left by 5 = multiplication/division by 32 + #101 + + + value7 + shift left by 6 = multiplication/division by 64 + #110 + + + value8 + shift left by 7 = multiplication/division by 128 + #111 + + + + + MULDIV + Switch between up- and downscale of the DAC1 input data values + 3 + 3 + read-write + + + value1 + downscale = division (shift SCALE positions to the right) + #0 + + + value2 + upscale = multiplication (shift SCALE positions to the left) + #1 + + + + + OFFS + 8-bit offset value addition + 4 + 11 + read-write + + + TRIGSEL + Selects one of the eight external trigger sources for DAC1 + 12 + 14 + read-write + + + SWTRIG + Software Trigger + 16 + 16 + read-write + + + TRIGMOD + Select the trigger source for channel 1 + 17 + 18 + read-write + + + value1 + internal Trigger (integer divided clock - see FREQ parameter) + #00 + + + value2 + external Trigger (preselected trigger by TRIGSEL parameter) + #01 + + + value3 + software Trigger (see SWTRIG parameter) + #10 + + + + + ANACFG + DAC1 analog configuration/calibration parameters + 19 + 23 + read-write + + + ANAEN + Enable analog DAC for channel 1 + 24 + 24 + read-write + + + value1 + DAC1 is set to standby (analog output only) + #0 + + + value2 + enable DAC1 (analog output only) + #1 + + + + + REFCFGH + Higher 4 band-gap configuration/calibration parameters + 28 + 31 + read-write + + + + + DAC0DATA + DAC0 Data Register + 0x014 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA0 + DAC0 Data Bits + 0 + 11 + read-write + + + + + DAC1DATA + DAC1 Data Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA1 + DAC1 Data Bits + 0 + 11 + read-write + + + + + DAC01DATA + DAC01 Data Register + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA0 + DAC0 Data Bits + 0 + 11 + read-write + + + DATA1 + DAC1 Data Bits + 16 + 27 + read-write + + + + + DAC0PATL + DAC0 Lower Pattern Register + 0x020 + 32 + 0x3568B0C0 + 0xFFFFFFFF + + + PAT0 + Pattern Number 0 for PATGEN of DAC0 + 0 + 4 + read-write + + + PAT1 + Pattern Number 1 for PATGEN of DAC0 + 5 + 9 + read-write + + + PAT2 + Pattern Number 2 for PATGEN of DAC0 + 10 + 14 + read-write + + + PAT3 + Pattern Number 3 for PATGEN of DAC0 + 15 + 19 + read-write + + + PAT4 + Pattern Number 4 for PATGEN of DAC0 + 20 + 24 + read-write + + + PAT5 + Pattern Number 5 for PATGEN of DAC0 + 25 + 29 + read-write + + + + + DAC0PATH + DAC0 Higher Pattern Register + 0x024 + 32 + 0x00007FDD + 0xFFFFFFFF + + + PAT6 + Pattern Number 6 for PATGEN of DAC0 + 0 + 4 + read-write + + + PAT7 + Pattern Number 7 for PATGEN of DAC0 + 5 + 9 + read-write + + + PAT8 + Pattern Number 8 for PATGEN of DAC0 + 10 + 14 + read-write + + + + + DAC1PATL + DAC1 Lower Pattern Register + 0x028 + 32 + 0x3568B0C0 + 0xFFFFFFFF + + + PAT0 + Pattern Number 0 for PATGEN of DAC1 + 0 + 4 + read-write + + + PAT1 + Pattern Number 1 for PATGEN of DAC1 + 5 + 9 + read-write + + + PAT2 + Pattern Number 2 for PATGEN of DAC1 + 10 + 14 + read-write + + + PAT3 + Pattern Number 3 for PATGEN of DAC1 + 15 + 19 + read-write + + + PAT4 + Pattern Number 4 for PATGEN of DAC1 + 20 + 24 + read-write + + + PAT5 + Pattern Number 5 for PATGEN of DAC1 + 25 + 29 + read-write + + + + + DAC1PATH + DAC1 Higher Pattern Register + 0x02C + 32 + 0x00007FDD + 0xFFFFFFFF + + + PAT6 + Pattern Number 6 for PATGEN of DAC1 + 0 + 4 + read-write + + + PAT7 + Pattern Number 7 for PATGEN of DAC1 + 5 + 9 + read-write + + + PAT8 + Pattern Number 8 for PATGEN of DAC1 + 10 + 14 + read-write + + + + + + + CCU40 + Capture Compare Unit 4 - Unit 0 + CCU4 + CCU4 + 0x4000C000 + + 0x0 + 0x100 + registers + + + CCU40_0 + Capture Compare Unit 4 (Module 0) + 44 + + + CCU40_1 + Capture Compare Unit 4 (Module 0) + 45 + + + CCU40_2 + Capture Compare Unit 4 (Module 0) + 46 + + + CCU40_3 + Capture Compare Unit 4 (Module 0) + 47 + + + + GCTRL + Global Control Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRBC + Prescaler Clear Configuration + 0 + 2 + read-write + + + value1 + SW only + #000 + + + value2 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared. + #001 + + + value3 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared. + #010 + + + value4 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared. + #011 + + + value5 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared. + #100 + + + + + PCIS + Prescaler Input Clock Selection + 4 + 5 + read-write + + + value1 + Module clock + #00 + + + value2 + CCU4x.ECLKA + #01 + + + value3 + CCU4x.ECLKB + #10 + + + value4 + CCU4x.ECLKC + #11 + + + + + SUSCFG + Suspend Mode Configuration + 8 + 9 + read-write + + + value1 + Suspend request ignored. The module never enters in suspend + #00 + + + value2 + Stops all the running slices immediately. Safe stop is not applied. + #01 + + + value3 + Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. + #10 + + + value4 + Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. + #11 + + + + + MSE0 + Slice 0 Multi Channel shadow transfer enable + 10 + 10 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSE1 + Slice 1 Multi Channel shadow transfer enable + 11 + 11 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSE2 + Slice 2 Multi Channel shadow transfer enable + 12 + 12 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSE3 + Slice 3 Multi Channel shadow transfer enable + 13 + 13 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSDE + Multi Channel shadow transfer request configuration + 14 + 15 + read-write + + + value1 + Only the shadow transfer for period and compare values is requested + #00 + + + value2 + Shadow transfer for the compare, period and prescaler compare values is requested + #01 + + + value4 + Shadow transfer for the compare, period, prescaler and dither compare values is requested + #11 + + + + + + + GSTAT + Global Status Register + 0x0004 + 32 + 0x0000000F + 0xFFFFFFFF + + + S0I + CC40 IDLE status + 0 + 0 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S1I + CC41 IDLE status + 1 + 1 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S2I + CC42 IDLE status + 2 + 2 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S3I + CC43 IDLE status + 3 + 3 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + PRB + Prescaler Run Bit + 8 + 8 + read-only + + + value1 + Prescaler is stopped + #0 + + + value2 + Prescaler is running + #1 + + + + + + + GIDLS + Global Idle Set + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SS0I + CC40 IDLE mode set + 0 + 0 + write-only + + + SS1I + CC41 IDLE mode set + 1 + 1 + write-only + + + SS2I + CC42 IDLE mode set + 2 + 2 + write-only + + + SS3I + CC43 IDLE mode set + 3 + 3 + write-only + + + CPRB + Prescaler Run Bit Clear + 8 + 8 + write-only + + + PSIC + Prescaler clear + 9 + 9 + write-only + + + + + GIDLC + Global Idle Clear + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + CS0I + CC40 IDLE mode clear + 0 + 0 + write-only + + + CS1I + CC41 IDLE mode clear + 1 + 1 + write-only + + + CS2I + CC42 IDLE mode clear + 2 + 2 + write-only + + + CS3I + CC43 IDLE mode clear + 3 + 3 + write-only + + + SPRB + Prescaler Run Bit Set + 8 + 8 + write-only + + + + + GCSS + Global Channel Set + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SE + Slice 0 shadow transfer set enable + 0 + 0 + write-only + + + S0DSE + Slice 0 Dither shadow transfer set enable + 1 + 1 + write-only + + + S0PSE + Slice 0 Prescaler shadow transfer set enable + 2 + 2 + write-only + + + S1SE + Slice 1 shadow transfer set enable + 4 + 4 + write-only + + + S1DSE + Slice 1 Dither shadow transfer set enable + 5 + 5 + write-only + + + S1PSE + Slice 1 Prescaler shadow transfer set enable + 6 + 6 + write-only + + + S2SE + Slice 2 shadow transfer set enable + 8 + 8 + write-only + + + S2DSE + Slice 2 Dither shadow transfer set enable + 9 + 9 + write-only + + + S2PSE + Slice 2 Prescaler shadow transfer set enable + 10 + 10 + write-only + + + S3SE + Slice 3 shadow transfer set enable + 12 + 12 + write-only + + + S3DSE + Slice 3 Dither shadow transfer set enable + 13 + 13 + write-only + + + S3PSE + Slice 3 Prescaler shadow transfer set enable + 14 + 14 + write-only + + + S0STS + Slice 0 status bit set + 16 + 16 + write-only + + + S1STS + Slice 1 status bit set + 17 + 17 + write-only + + + S2STS + Slice 2 status bit set + 18 + 18 + write-only + + + S3STS + Slice 3 status bit set + 19 + 19 + write-only + + + + + GCSC + Global Channel Clear + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SC + Slice 0 shadow transfer clear + 0 + 0 + write-only + + + S0DSC + Slice 0 Dither shadow transfer clear + 1 + 1 + write-only + + + S0PSC + Slice 0 Prescaler shadow transfer clear + 2 + 2 + write-only + + + S1SC + Slice 1 shadow transfer clear + 4 + 4 + write-only + + + S1DSC + Slice 1 Dither shadow transfer clear + 5 + 5 + write-only + + + S1PSC + Slice 1 Prescaler shadow transfer clear + 6 + 6 + write-only + + + S2SC + Slice 2 shadow transfer clear + 8 + 8 + write-only + + + S2DSC + Slice 2 Dither shadow transfer clear + 9 + 9 + write-only + + + S2PSC + Slice 2 Prescaler shadow transfer clear + 10 + 10 + write-only + + + S3SC + Slice 3 shadow transfer clear + 12 + 12 + write-only + + + S3DSC + Slice 3 Dither shadow transfer clear + 13 + 13 + write-only + + + S3PSC + Slice 3 Prescaler shadow transfer clear + 14 + 14 + write-only + + + S0STC + Slice 0 status bit clear + 16 + 16 + write-only + + + S1STC + Slice 1 status bit clear + 17 + 17 + write-only + + + S2STC + Slice 2 status bit clear + 18 + 18 + write-only + + + S3STC + Slice 3 status bit clear + 19 + 19 + write-only + + + + + GCST + Global Channel Status + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SS + Slice 0 shadow transfer status + 0 + 0 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S0DSS + Slice 0 Dither shadow transfer status + 1 + 1 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S0PSS + Slice 0 Prescaler shadow transfer status + 2 + 2 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S1SS + Slice 1 shadow transfer status + 4 + 4 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S1DSS + Slice 1 Dither shadow transfer status + 5 + 5 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S1PSS + Slice 1 Prescaler shadow transfer status + 6 + 6 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S2SS + Slice 2 shadow transfer status + 8 + 8 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S2DSS + Slice 2 Dither shadow transfer status + 9 + 9 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S2PSS + Slice 2 Prescaler shadow transfer status + 10 + 10 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S3SS + Slice 3 shadow transfer status + 12 + 12 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S3DSS + Slice 3 Dither shadow transfer status + 13 + 13 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S3PSS + Slice 3 Prescaler shadow transfer status + 14 + 14 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + CC40ST + Slice 0 status bit + 16 + 16 + read-only + + + CC41ST + Slice 1 status bit + 17 + 17 + read-only + + + CC42ST + Slice 2 status bit + 18 + 18 + read-only + + + CC43ST + Slice 3 status bit + 19 + 19 + read-only + + + + + MIDR + Module Identification + 0x0080 + 32 + 0x00A6C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + + + CCU41 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010000 + + 0x0 + 0x100 + registers + + + CCU41_0 + Capture Compare Unit 4 (Module 1) + 48 + + + CCU41_1 + Capture Compare Unit 4 (Module 1) + 49 + + + CCU41_2 + Capture Compare Unit 4 (Module 1) + 50 + + + CCU41_3 + Capture Compare Unit 4 (Module 1) + 51 + + + + CCU42 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014000 + + 0x0 + 0x100 + registers + + + CCU42_0 + Capture Compare Unit 4 (Module 2) + 52 + + + CCU42_1 + Capture Compare Unit 4 (Module 2) + 53 + + + CCU42_2 + Capture Compare Unit 4 (Module 2) + 54 + + + CCU42_3 + Capture Compare Unit 4 (Module 2) + 55 + + + + CCU43 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004000 + + 0x0 + 0x100 + registers + + + CCU43_0 + Capture Compare Unit 4 (Module 3) + 56 + + + CCU43_1 + Capture Compare Unit 4 (Module 3) + 57 + + + CCU43_2 + Capture Compare Unit 4 (Module 3) + 58 + + + CCU43_3 + Capture Compare Unit 4 (Module 3) + 59 + + + + CCU40_CC40 + Capture Compare Unit 4 - Unit 0 + CCU4 + CCU4_CC4 + 0x4000C100 + + 0x0 + 0x100 + registers + + + + INS + Input Selector Configuration + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + EV0IS + Event 0 signal selection + 0 + 3 + read-write + + + value1 + CCU4x.INyA + #0000 + + + value2 + CCU4x.INyB + #0001 + + + value3 + CCU4x.INyC + #0010 + + + value4 + CCU4x.INyD + #0011 + + + value5 + CCU4x.INyE + #0100 + + + value6 + CCU4x.INyF + #0101 + + + value7 + CCU4x.INyG + #0110 + + + value8 + CCU4x.INyH + #0111 + + + value9 + CCU4x.INyI + #1000 + + + value10 + CCU4x.INyJ + #1001 + + + value11 + CCU4x.INyK + #1010 + + + value12 + CCU4x.INyL + #1011 + + + value13 + CCU4x.INyM + #1100 + + + value14 + CCU4x.INyN + #1101 + + + value15 + CCU4x.INyO + #1110 + + + value16 + CCU4x.INyP + #1111 + + + + + EV1IS + Event 1 signal selection + 4 + 7 + read-write + + + value1 + CCU4x.INyA + #0000 + + + value2 + CCU4x.INyB + #0001 + + + value3 + CCU4x.INyC + #0010 + + + value4 + CCU4x.INyD + #0011 + + + value5 + CCU4x.INyE + #0100 + + + value6 + CCU4x.INyF + #0101 + + + value7 + CCU4x.INyG + #0110 + + + value8 + CCU4x.INyH + #0111 + + + value9 + CCU4x.INyI + #1000 + + + value10 + CCU4x.INyJ + #1001 + + + value11 + CCU4x.INyK + #1010 + + + value12 + CCU4x.INyL + #1011 + + + value13 + CCU4x.INyM + #1100 + + + value14 + CCU4x.INyN + #1101 + + + value15 + CCU4x.INyO + #1110 + + + value16 + CCU4x.INyP + #1111 + + + + + EV2IS + Event 2 signal selection + 8 + 11 + read-write + + + value1 + CCU4x.INyA + #0000 + + + value2 + CCU4x.INyB + #0001 + + + value3 + CCU4x.INyC + #0010 + + + value4 + CCU4x.INyD + #0011 + + + value5 + CCU4x.INyE + #0100 + + + value6 + CCU4x.INyF + #0101 + + + value7 + CCU4x.INyG + #0110 + + + value8 + CCU4x.INyH + #0111 + + + value9 + CCU4x.INyI + #1000 + + + value10 + CCU4x.INyJ + #1001 + + + value11 + CCU4x.INyK + #1010 + + + value12 + CCU4x.INyL + #1011 + + + value13 + CCU4x.INyM + #1100 + + + value14 + CCU4x.INyN + #1101 + + + value15 + CCU4x.INyO + #1110 + + + value16 + CCU4x.INyP + #1111 + + + + + EV0EM + Event 0 Edge Selection + 16 + 17 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV1EM + Event 1 Edge Selection + 18 + 19 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV2EM + Event 2 Edge Selection + 20 + 21 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV0LM + Event 0 Level Selection + 22 + 22 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV1LM + Event 1 Level Selection + 23 + 23 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV2LM + Event 2 Level Selection + 24 + 24 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + LPF0M + Event 0 Low Pass Filter Configuration + 25 + 26 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU4 + #01 + + + value3 + 5 clock cycles of fCCU4 + #10 + + + value4 + 7 clock cycles of fCCU4 + #11 + + + + + LPF1M + Event 1 Low Pass Filter Configuration + 27 + 28 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU4 + #01 + + + value3 + 5 clock cycles of fCCU4 + #10 + + + value4 + 7 clock cycles of fCCU4 + #11 + + + + + LPF2M + Event 2 Low Pass Filter Configuration + 29 + 30 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU4 + #01 + + + value3 + 5 clock cycles of fCCU4 + #10 + + + value4 + 7 clock cycles of fCCU4 + #11 + + + + + + + CMC + Connection Matrix Control + 0x004 + 32 + 0x00000000 + 0xFFFFFFFF + + + STRTS + External Start Functionality Selector + 0 + 1 + read-write + + + value1 + External Start Function deactivated + #00 + + + value2 + External Start Function triggered by Event 0 + #01 + + + value3 + External Start Function triggered by Event 1 + #10 + + + value4 + External Start Function triggered by Event 2 + #11 + + + + + ENDS + External Stop Functionality Selector + 2 + 3 + read-write + + + value1 + External Stop Function deactivated + #00 + + + value2 + External Stop Function triggered by Event 0 + #01 + + + value3 + External Stop Function triggered by Event 1 + #10 + + + value4 + External Stop Function triggered by Event 2 + #11 + + + + + CAP0S + External Capture 0 Functionality Selector + 4 + 5 + read-write + + + value1 + External Capture 0 Function deactivated + #00 + + + value2 + External Capture 0 Function triggered by Event 0 + #01 + + + value3 + External Capture 0 Function triggered by Event 1 + #10 + + + value4 + External Capture 0 Function triggered by Event 2 + #11 + + + + + CAP1S + External Capture 1 Functionality Selector + 6 + 7 + read-write + + + value1 + External Capture 1 Function deactivated + #00 + + + value2 + External Capture 1 Function triggered by Event 0 + #01 + + + value3 + External Capture 1 Function triggered by Event 1 + #10 + + + value4 + External Capture 1 Function triggered by Event 2 + #11 + + + + + GATES + External Gate Functionality Selector + 8 + 9 + read-write + + + value1 + External Gating Function deactivated + #00 + + + value2 + External Gating Function triggered by Event 0 + #01 + + + value3 + External Gating Function triggered by Event 1 + #10 + + + value4 + External Gating Function triggered by Event 2 + #11 + + + + + UDS + External Up/Down Functionality Selector + 10 + 11 + read-write + + + value1 + External Up/Down Function deactivated + #00 + + + value2 + External Up/Down Function triggered by Event 0 + #01 + + + value3 + External Up/Down Function triggered by Event 1 + #10 + + + value4 + External Up/Down Function triggered by Event 2 + #11 + + + + + LDS + External Timer Load Functionality Selector + 12 + 13 + read-write + + + CNTS + External Count Selector + 14 + 15 + read-write + + + value1 + External Count Function deactivated + #00 + + + value2 + External Count Function triggered by Event 0 + #01 + + + value3 + External Count Function triggered by Event 1 + #10 + + + value4 + External Count Function triggered by Event 2 + #11 + + + + + OFS + Override Function Selector + 16 + 16 + read-write + + + value1 + Override functionality disabled + #0 + + + value2 + Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 + #1 + + + + + TS + Trap Function Selector + 17 + 17 + read-write + + + value1 + Trap function disabled + #0 + + + value2 + TRAP function connected to Event 2 + #1 + + + + + MOS + External Modulation Functionality Selector + 18 + 19 + read-write + + + TCE + Timer Concatenation Enable + 20 + 20 + read-write + + + value1 + Timer concatenation is disabled + #0 + + + value2 + Timer concatenation is enabled + #1 + + + + + + + TCST + Slice Timer Status + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRB + Timer Run Bit + 0 + 0 + read-only + + + value1 + Timer is stopped + #0 + + + value2 + Timer is running + #1 + + + + + CDIR + Timer Counting Direction + 1 + 1 + read-only + + + value1 + Timer is counting up + #0 + + + value2 + Timer is counting down + #1 + + + + + + + TCSET + Slice Timer Run Set + 0x00C + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBS + Timer Run Bit set + 0 + 0 + write-only + + + + + TCCLR + Slice Timer Clear + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBC + Timer Run Bit Clear + 0 + 0 + write-only + + + TCC + Timer Clear + 1 + 1 + write-only + + + DITC + Dither Counter Clear + 2 + 2 + write-only + + + + + TC + Slice Timer Control + 0x014 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCM + Timer Counting Mode + 0 + 0 + read-write + + + value1 + Edge aligned mode + #0 + + + value2 + Center aligned mode + #1 + + + + + TSSM + Timer Single Shot Mode + 1 + 1 + read-write + + + value1 + Single shot mode is disabled + #0 + + + value2 + Single shot mode is enabled + #1 + + + + + CLST + Shadow Transfer on Clear + 2 + 2 + read-write + + + CMOD + Capture Compare Mode + 3 + 3 + read-only + + + value1 + Compare Mode + #0 + + + value2 + Capture Mode + #1 + + + + + ECM + Extended Capture Mode + 4 + 4 + read-write + + + value1 + Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. + #0 + + + value2 + Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared. + #1 + + + + + CAPC + Clear on Capture Control + 5 + 6 + read-write + + + value1 + Timer is never cleared on a capture event + #00 + + + value2 + Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) + #01 + + + value3 + Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) + #10 + + + value4 + Timer is always cleared in a capture event. + #11 + + + + + ENDM + Extended Stop Function Control + 8 + 9 + read-write + + + value1 + Clears the timer run bit only (default stop) + #00 + + + value2 + Clears the timer only (flush) + #01 + + + value3 + Clears the timer and run bit (flush/stop) + #10 + + + + + STRM + Extended Start Function Control + 10 + 10 + read-write + + + value1 + Sets run bit only (default start) + #0 + + + value2 + Clears the timer and sets run bit (flush/start) + #1 + + + + + SCE + Equal Capture Event enable + 11 + 11 + read-write + + + value1 + Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #0 + + + value2 + Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #1 + + + + + CCS + Continuous Capture Enable + 12 + 12 + read-write + + + value1 + The capture into a specific capture register is done with the rules linked with the full flags, described at . + #0 + + + value2 + The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). + #1 + + + + + DITHE + Dither Enable + 13 + 14 + read-write + + + value1 + Dither is disabled + #00 + + + value2 + Dither is applied to the Period + #01 + + + value3 + Dither is applied to the Compare + #10 + + + value4 + Dither is applied to the Period and Compare + #11 + + + + + DIM + Dither input selector + 15 + 15 + read-write + + + value1 + Slice is using its own dither unit + #0 + + + value2 + Slice is connected to the dither unit of slice 0. + #1 + + + + + FPE + Floating Prescaler enable + 16 + 16 + read-write + + + value1 + Floating prescaler mode is disabled + #0 + + + value2 + Floating prescaler mode is enabled + #1 + + + + + TRAPE + TRAP enable + 17 + 17 + read-write + + + value1 + TRAP functionality has no effect on the output + #0 + + + value2 + TRAP functionality affects the output + #1 + + + + + TRPSE + TRAP Synchronization Enable + 21 + 21 + read-write + + + value1 + Exiting from TRAP state isn't synchronized with the PWM signal + #0 + + + value2 + Exiting from TRAP state is synchronized with the PWM signal + #1 + + + + + TRPSW + TRAP State Clear Control + 22 + 22 + read-write + + + value1 + The slice exits the TRAP state automatically when the TRAP condition is not present + #0 + + + value2 + The TRAP state can only be exited by a SW request. + #1 + + + + + EMS + External Modulation Synchronization + 23 + 23 + read-write + + + value1 + External Modulation functionality is not synchronized with the PWM signal + #0 + + + value2 + External Modulation functionality is synchronized with the PWM signal + #1 + + + + + EMT + External Modulation Type + 24 + 24 + read-write + + + value1 + External Modulation functionality is clearing the CC4yST bit. + #0 + + + value2 + External Modulation functionality is gating the outputs. + #1 + + + + + MCME + Multi Channel Mode Enable + 25 + 25 + read-write + + + value1 + Multi Channel Mode is disabled + #0 + + + value2 + Multi Channel Mode is enabled + #1 + + + + + + + PSL + Passive Level Config + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSL + Output Passive Level + 0 + 0 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + + + DIT + Dither Config + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + DCV + Dither compare Value + 0 + 3 + read-only + + + DCNT + Dither counter actual value + 8 + 11 + read-only + + + + + DITS + Dither Shadow Register + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCVS + Dither Shadow Compare Value + 0 + 3 + read-write + + + + + PSC + Prescaler Control + 0x024 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSIV + Prescaler Initial Value + 0 + 3 + read-write + + + + + FPC + Floating Prescaler Control + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Compare Value + 0 + 3 + read-only + + + PVAL + Actual Prescaler Value + 8 + 11 + read-write + + + + + FPCS + Floating Prescaler Shadow + 0x02C + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Shadow Compare Value + 0 + 3 + read-write + + + + + PR + Timer Period Value + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + PR + Period Register + 0 + 15 + read-only + + + + + PRS + Timer Shadow Period Value + 0x034 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRS + Period Register + 0 + 15 + read-write + + + + + CR + Timer Compare Value + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Compare Register + 0 + 15 + read-only + + + + + CRS + Timer Shadow Compare Value + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + CRS + Compare Register + 0 + 15 + read-write + + + + + TIMER + Timer Value + 0x070 + 32 + 0x00000000 + 0xFFFFFFFF + + + TVAL + Timer Value + 0 + 15 + read-write + + + + + C0V + Capture Register 0 + 0x074 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C1V + Capture Register 1 + 0x078 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C2V + Capture Register 2 + 0x07C + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C3V + Capture Register 3 + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + INTS + Interrupt Status + 0x0A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PMUS + Period Match while Counting Up + 0 + 0 + read-only + + + value1 + Period match while counting up not detected + #0 + + + value2 + Period match while counting up detected + #1 + + + + + OMDS + One Match while Counting Down + 1 + 1 + read-only + + + value1 + One match while counting down not detected + #0 + + + value2 + One match while counting down detected + #1 + + + + + CMUS + Compare Match while Counting Up + 2 + 2 + read-only + + + value1 + Compare match while counting up not detected + #0 + + + value2 + Compare match while counting up detected + #1 + + + + + CMDS + Compare Match while Counting Down + 3 + 3 + read-only + + + value1 + Compare match while counting down not detected + #0 + + + value2 + Compare match while counting down detected + #1 + + + + + E0AS + Event 0 Detection Status + 8 + 8 + read-only + + + value1 + Event 0 not detected + #0 + + + value2 + Event 0 detected + #1 + + + + + E1AS + Event 1 Detection Status + 9 + 9 + read-only + + + value1 + Event 1 not detected + #0 + + + value2 + Event 1 detected + #1 + + + + + E2AS + Event 2 Detection Status + 10 + 10 + read-only + + + value1 + Event 2 not detected + #0 + + + value2 + Event 2 detected + #1 + + + + + TRPF + Trap Flag Status + 11 + 11 + read-only + + + + + INTE + Interrupt Enable Control + 0x0A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + PME + Period match while counting up enable + 0 + 0 + read-write + + + value1 + Period Match interrupt is disabled + #0 + + + value2 + Period Match interrupt is enabled + #1 + + + + + OME + One match while counting down enable + 1 + 1 + read-write + + + value1 + One Match interrupt is disabled + #0 + + + value2 + One Match interrupt is enabled + #1 + + + + + CMUE + Compare match while counting up enable + 2 + 2 + read-write + + + value1 + Compare Match while counting up interrupt is disabled + #0 + + + value2 + Compare Match while counting up interrupt is enabled + #1 + + + + + CMDE + Compare match while counting down enable + 3 + 3 + read-write + + + value1 + Compare Match while counting down interrupt is disabled + #0 + + + value2 + Compare Match while counting down interrupt is enabled + #1 + + + + + E0AE + Event 0 interrupt enable + 8 + 8 + read-write + + + value1 + Event 0 detection interrupt is disabled + #0 + + + value2 + Event 0 detection interrupt is enabled + #1 + + + + + E1AE + Event 1 interrupt enable + 9 + 9 + read-write + + + value1 + Event 1 detection interrupt is disabled + #0 + + + value2 + Event 1 detection interrupt is enabled + #1 + + + + + E2AE + Event 2 interrupt enable + 10 + 10 + read-write + + + value1 + Event 2 detection interrupt is disabled + #0 + + + value2 + Event 2 detection interrupt is enabled + #1 + + + + + + + SRS + Service Request Selector + 0x0A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSR + Period/One match Service request selector + 0 + 1 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + CMSR + Compare match Service request selector + 2 + 3 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + E0SR + Event 0 Service request selector + 8 + 9 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + E1SR + Event 1 Service request selector + 10 + 11 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + E2SR + Event 2 Service request selector + 12 + 13 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + + + SWS + Interrupt Status Set + 0x0AC + 32 + 0x00000000 + 0xFFFFFFFF + + + SPM + Period match while counting up set + 0 + 0 + write-only + + + SOM + One match while counting down set + 1 + 1 + write-only + + + SCMU + Compare match while counting up set + 2 + 2 + write-only + + + SCMD + Compare match while counting down set + 3 + 3 + write-only + + + SE0A + Event 0 detection set + 8 + 8 + write-only + + + SE1A + Event 1 detection set + 9 + 9 + write-only + + + SE2A + Event 2 detection set + 10 + 10 + write-only + + + STRPF + Trap Flag status set + 11 + 11 + write-only + + + + + SWR + Interrupt Status Clear + 0x0B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPM + Period match while counting up clear + 0 + 0 + write-only + + + ROM + One match while counting down clear + 1 + 1 + write-only + + + RCMU + Compare match while counting up clear + 2 + 2 + write-only + + + RCMD + Compare match while counting down clear + 3 + 3 + write-only + + + RE0A + Event 0 detection clear + 8 + 8 + write-only + + + RE1A + Event 1 detection clear + 9 + 9 + write-only + + + RE2A + Event 2 detection clear + 10 + 10 + write-only + + + RTRPF + Trap Flag status clear + 11 + 11 + write-only + + + + + ECRD0 + Extended Read Back 0 + 0x0B8 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC40 + #00 + + + value2 + CC41 + #01 + + + value3 + CC42 + #10 + + + value4 + CC43 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + ECRD1 + Extended Read Back 1 + 0x0BC + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC40 + #00 + + + value2 + CC41 + #01 + + + value3 + CC42 + #10 + + + value4 + CC43 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + + + CCU40_CC41 + Capture Compare Unit 4 - Unit 0 + CCU4 + 0x4000C200 + + 0x0 + 0x100 + registers + + + + CCU40_CC42 + Capture Compare Unit 4 - Unit 0 + CCU4 + 0x4000C300 + + 0x0 + 0x100 + registers + + + + CCU40_CC43 + Capture Compare Unit 4 - Unit 0 + CCU4 + 0x4000C400 + + 0x0 + 0x100 + registers + + + + CCU41_CC40 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010100 + + 0x0 + 0x100 + registers + + + + CCU41_CC41 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010200 + + 0x0 + 0x100 + registers + + + + CCU41_CC42 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010300 + + 0x0 + 0x100 + registers + + + + CCU41_CC43 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010400 + + 0x0 + 0x100 + registers + + + + CCU42_CC40 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014100 + + 0x0 + 0x100 + registers + + + + CCU42_CC41 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014200 + + 0x0 + 0x100 + registers + + + + CCU42_CC42 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014300 + + 0x0 + 0x100 + registers + + + + CCU42_CC43 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014400 + + 0x0 + 0x100 + registers + + + + CCU43_CC40 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004100 + + 0x0 + 0x100 + registers + + + + CCU43_CC41 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004200 + + 0x0 + 0x100 + registers + + + + CCU43_CC42 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004300 + + 0x0 + 0x100 + registers + + + + CCU43_CC43 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004400 + + 0x0 + 0x100 + registers + + + + CCU80 + Capture Compare Unit 8 - Unit 0 + CCU8 + CCU8 + 0x40020000 + + 0x0 + 0x100 + registers + + + CCU80_0 + Capture Compare Unit 8 (Module 0) + 60 + + + CCU80_1 + Capture Compare Unit 8 (Module 0) + 61 + + + CCU80_2 + Capture Compare Unit 8 (Module 0) + 62 + + + CCU80_3 + Capture Compare Unit 8 (Module 0) + 63 + + + + GCTRL + Global Control Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRBC + Prescaler Clear Configuration + 0 + 2 + read-write + + + value1 + SW only + #000 + + + value2 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC80 is cleared. + #001 + + + value3 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC81 is cleared. + #010 + + + value4 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC82 is cleared. + #011 + + + value5 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC83 is cleared. + #100 + + + + + PCIS + Prescaler Input Clock Selection + 4 + 5 + read-write + + + value1 + Module clock + #00 + + + value2 + CCU8x.ECLKA + #01 + + + value3 + CCU8x.ECLKB + #10 + + + value4 + CCU8x.ECLKC + #11 + + + + + SUSCFG + Suspend Mode Configuration + 8 + 9 + read-write + + + value1 + Suspend request ignored. The module never enters in suspend + #00 + + + value2 + Stops all the running slices immediately. Safe stop is not applied. + #01 + + + value3 + Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. + #10 + + + value4 + Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. + #11 + + + + + MSE0 + Slice 0 Multi Channel shadow transfer enable + 10 + 10 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8x.MCSS input. + #1 + + + + + MSE1 + Slice 1 Multi Channel shadow transfer enable + 11 + 11 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8x.MCSS input. + #1 + + + + + MSE2 + Slice 2 Multi Channel shadow transfer enable + 12 + 12 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8xMCSS input. + #1 + + + + + MSE3 + Slice 3 Multi Channel shadow transfer enable + 13 + 13 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8x.MCSS input. + #1 + + + + + MSDE + Multi Channel shadow transfer request configuration + 14 + 15 + read-write + + + value1 + Only the shadow transfer for period and compare values is requested + #00 + + + value2 + Shadow transfer for the compare, period and prescaler compare values is requested + #01 + + + value4 + Shadow transfer for the compare, period, prescaler and dither compare values is requested + #11 + + + + + + + GSTAT + Global Status Register + 0x0004 + 32 + 0x0000000F + 0xFFFFFFFF + + + S0I + CC80 IDLE status + 0 + 0 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S1I + CC81 IDLE status + 1 + 1 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S2I + CC82 IDLE status + 2 + 2 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S3I + CC83 IDLE status + 3 + 3 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + PRB + Prescaler Run Bit + 8 + 8 + read-only + + + value1 + Prescaler is stopped + #0 + + + value2 + Prescaler is running + #1 + + + + + PCRB + Parity Checker Run Bit + 10 + 10 + read-only + + + value1 + Parity Checker is stopped + #0 + + + value2 + Parity Checker is running + #1 + + + + + + + GIDLS + Global Idle Set + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SS0I + CC80 IDLE mode set + 0 + 0 + write-only + + + SS1I + CC81 IDLE mode set + 1 + 1 + write-only + + + SS2I + CC82 IDLE mode set + 2 + 2 + write-only + + + SS3I + CC83 IDLE mode set + 3 + 3 + write-only + + + CPRB + Prescaler# Run Bit Clear + 8 + 8 + write-only + + + PSIC + Prescaler clear + 9 + 9 + write-only + + + CPCH + Parity Checker Run bit clear + 10 + 10 + write-only + + + + + GIDLC + Global Idle Clear + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + CS0I + CC80 IDLE mode clear + 0 + 0 + write-only + + + CS1I + CC81 IDLE mode clear + 1 + 1 + write-only + + + CS2I + CC82 IDLE mode clear + 2 + 2 + write-only + + + CS3I + CC83 IDLE mode clear + 3 + 3 + write-only + + + SPRB + Prescaler Run Bit Set + 8 + 8 + write-only + + + SPCH + Parity Checker run bit set + 10 + 10 + write-only + + + + + GCSS + Global Channel Set + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SE + Slice 0 shadow transfer set enable + 0 + 0 + write-only + + + S0DSE + Slice 0 Dither shadow transfer set enable + 1 + 1 + write-only + + + S0PSE + Slice 0 Prescaler shadow transfer set enable + 2 + 2 + write-only + + + S1SE + Slice 1 shadow transfer set enable + 4 + 4 + write-only + + + S1DSE + Slice 1 Dither shadow transfer set enable + 5 + 5 + write-only + + + S1PSE + Slice 1 Prescaler shadow transfer set enable + 6 + 6 + write-only + + + S2SE + Slice 2 shadow transfer set enable + 8 + 8 + write-only + + + S2DSE + Slice 2 Dither shadow transfer set enable + 9 + 9 + write-only + + + S2PSE + Slice 2 Prescaler shadow transfer set enable + 10 + 10 + write-only + + + S3SE + Slice 3 shadow transfer set enable + 12 + 12 + write-only + + + S3DSE + Slice 3 Dither shadow transfer set enable + 13 + 13 + write-only + + + S3PSE + Slice 3 Prescaler shadow transfer set enable + 14 + 14 + write-only + + + S0ST1S + Slice 0 status bit 1 set + 16 + 16 + write-only + + + S1ST1S + Slice 1 status bit 1 set + 17 + 17 + write-only + + + S2ST1S + Slice 2 status bit 1 set + 18 + 18 + write-only + + + S3ST1S + Slice 3 status bit 1 set + 19 + 19 + write-only + + + S0ST2S + Slice 0 status bit 2 set + 20 + 20 + write-only + + + S1ST2S + Slice 1 status bit 2 set + 21 + 21 + write-only + + + S2ST2S + Slice 2 status bit 2 set + 22 + 22 + write-only + + + S3ST2S + Slice 3 status bit 2 set + 23 + 23 + write-only + + + + + GCSC + Global Channel Clear + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SC + Slice 0 shadow transfer request clear + 0 + 0 + write-only + + + S0DSC + Slice 0 Dither shadow transfer clear + 1 + 1 + write-only + + + S0PSC + Slice 0 Prescaler shadow transfer clear + 2 + 2 + write-only + + + S1SC + Slice 1 shadow transfer clear + 4 + 4 + write-only + + + S1DSC + Slice 1 Dither shadow transfer clear + 5 + 5 + write-only + + + S1PSC + Slice 1 Prescaler shadow transfer clear + 6 + 6 + write-only + + + S2SC + Slice 2 shadow transfer clear + 8 + 8 + write-only + + + S2DSC + Slice 2 Dither shadow transfer clear + 9 + 9 + write-only + + + S2PSC + Slice 2 Prescaler shadow transfer clear + 10 + 10 + write-only + + + S3SC + Slice 3 shadow transfer clear + 12 + 12 + write-only + + + S3DSC + Slice 3 Dither shadow transfer clear + 13 + 13 + write-only + + + S3PSC + Slice 3 Prescaler shadow transfer clear + 14 + 14 + write-only + + + S0ST1C + Slice 0 status bit 1 clear + 16 + 16 + write-only + + + S1ST1C + Slice 1 status bit 1 clear + 17 + 17 + write-only + + + S2ST1C + Slice 2 status bit 1 clear + 18 + 18 + write-only + + + S3ST1C + Slice 3 status bit 1 clear + 19 + 19 + write-only + + + S0ST2C + Slice 0 status bit 2 clear + 20 + 20 + write-only + + + S1ST2C + Slice 1 status bit 2 clear + 21 + 21 + write-only + + + S2ST2C + Slice 2 status bit 2 clear + 22 + 22 + write-only + + + S3ST2C + Slice 3 status bit 2 clear + 23 + 23 + write-only + + + + + GCST + Global Channel status + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SS + Slice 0 shadow transfer status + 0 + 0 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S0DSS + Slice 0 Dither shadow transfer status + 1 + 1 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S0PSS + Slice 0 Prescaler shadow transfer status + 2 + 2 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S1SS + Slice 1 shadow transfer status + 4 + 4 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S1DSS + Slice 1 Dither shadow transfer status + 5 + 5 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S1PSS + Slice 1 Prescaler shadow transfer status + 6 + 6 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S2SS + Slice 2 shadow transfer status + 8 + 8 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S2DSS + Slice 2 Dither shadow transfer status + 9 + 9 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S2PSS + Slice 2 Prescaler shadow transfer status + 10 + 10 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S3SS + Slice 3 shadow transfer status + 12 + 12 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S3DSS + Slice 3 Dither shadow transfer status + 13 + 13 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S3PSS + Slice 3 Prescaler shadow transfer status + 14 + 14 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + CC80ST1 + Slice 0 compare channel 1 status bit + 16 + 16 + read-only + + + CC81ST1 + Slice 1 compare channel 1 status bit + 17 + 17 + read-only + + + CC82ST1 + Slice 2 compare channel 1 status bit + 18 + 18 + read-only + + + CC83ST1 + Slice 3 compare channel 1 status bit + 19 + 19 + read-only + + + CC80ST2 + Slice 0 compare channel 2 status bit + 20 + 20 + read-only + + + CC81ST2 + Slice 1 compare channel 2 status bit + 21 + 21 + read-only + + + CC82ST2 + Slice 2 compare channel 2 status bit + 22 + 22 + read-only + + + CC83ST2 + Slice 3 compare channel 2 status bit + 23 + 23 + read-only + + + + + GPCHK + Parity Checker Configuration + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + PASE + Parity Checker Automatic start/stop + 0 + 0 + read-write + + + PACS + Parity Checker Automatic start/stop selector + 1 + 2 + read-write + + + value1 + CC80 + #00 + + + value2 + CC81 + #01 + + + value3 + CC82 + #10 + + + value4 + CC83 + #11 + + + + + PISEL + Driver Input signal selector + 3 + 4 + read-write + + + value1 + CC8x.GP01 - driver output is connected to event 1 of slice 0 + #00 + + + value2 + CC8x.GP11 - drive output is connected to event 1 of slice 1 + #01 + + + value3 + CC8x.GP21 - driver output is connected to event 1 of slice 2 + #10 + + + value4 + CC8x.GP31 - driver output is connected to event 1 of slice 3 + #11 + + + + + PCDS + Parity Checker Delay Input Selector + 5 + 6 + read-write + + + value1 + CCU8x.IGBTA + #00 + + + value2 + CCU8x.IGBTB + #01 + + + value3 + CCU8x.IGBTC + #10 + + + value4 + CCU8x.IGBTD + #11 + + + + + PCTS + Parity Checker type selector + 7 + 7 + read-write + + + value1 + Even parity enabled + #0 + + + value2 + Odd parity enabled + #1 + + + + + PCST + Parity Checker XOR status + 15 + 15 + read-only + + + PCSEL0 + Parity Checker Slice 0 output selection + 16 + 19 + read-write + + + PCSEL1 + Parity Checker Slice 1 output selection + 20 + 23 + read-write + + + PCSEL2 + Parity Checker Slice 2 output selection + 24 + 27 + read-write + + + PCSEL3 + Parity Checker Slice 3 output selection + 28 + 31 + read-write + + + + + MIDR + Module Identification + 0x0080 + 32 + 0x00A7C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + + + CCU81 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024000 + + 0x0 + 0x100 + registers + + + CCU81_0 + Capture Compare Unit 8 (Module 1) + 64 + + + CCU81_1 + Capture Compare Unit 8 (Module 1) + 65 + + + CCU81_2 + Capture Compare Unit 8 (Module 1) + 66 + + + CCU81_3 + Capture Compare Unit 8 (Module 1) + 67 + + + + CCU80_CC80 + Capture Compare Unit 8 - Unit 0 + CCU8 + CCU8_CC8 + 0x40020100 + + 0x0 + 0x100 + registers + + + + INS + Input Selector Configuration + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + EV0IS + Event 0 signal selection + 0 + 3 + read-write + + + value1 + CCU8x.INyA + #0000 + + + value2 + CCU8x.INyB + #0001 + + + value3 + CCU8x.INyC + #0010 + + + value4 + CCU8x.INyD + #0011 + + + value5 + CCU8x.INyE + #0100 + + + value6 + CCU8x.INyF + #0101 + + + value7 + CCU8x.INyG + #0110 + + + value8 + CCU8x.INyH + #0111 + + + value9 + CCU8x.INyI + #1000 + + + value10 + CCU8x.INyJ + #1001 + + + value11 + CCU8x.INyK + #1010 + + + value12 + CCU8x.INyL + #1011 + + + value13 + CCU8x.INyM + #1100 + + + value14 + CCU8x.INyN + #1101 + + + value15 + CCU8x.INyO + #1110 + + + value16 + CCU8x.INyP + #1111 + + + + + EV1IS + Event 1 signal selection + 4 + 7 + read-write + + + value1 + CCU8x.INyA + #0000 + + + value2 + CCU8x.INyB + #0001 + + + value3 + CCU8x.INyC + #0010 + + + value4 + CCU8x.INyD + #0011 + + + value5 + CCU8x.INyE + #0100 + + + value6 + CCU8x.INyF + #0101 + + + value7 + CCU8x.INyG + #0110 + + + value8 + CCU8x.INyH + #0111 + + + value9 + CCU8x.INyI + #1000 + + + value10 + CCU8x.INyJ + #1001 + + + value11 + CCU8x.INyK + #1010 + + + value12 + CCU8x.INyL + #1011 + + + value13 + CCU8x.INyM + #1100 + + + value14 + CCU8x.INyN + #1101 + + + value15 + CCU8x.INyO + #1110 + + + value16 + CCU8x.INyP + #1111 + + + + + EV2IS + Event 2 signal selection + 8 + 11 + read-write + + + value1 + CCU8x.INyA + #0000 + + + value2 + CCU8x.INyB + #0001 + + + value3 + CCU8x.INyC + #0010 + + + value4 + CCU8x.INyD + #0011 + + + value5 + CCU8x.INyE + #0100 + + + value6 + CCU8x.INyF + #0101 + + + value7 + CCU8x.INyG + #0110 + + + value8 + CCU8x.INyH + #0111 + + + value9 + CCU8x.INyI + #1000 + + + value10 + CCU8x.INyJ + #1001 + + + value11 + CCU8x.INyK + #1010 + + + value12 + CCU8x.INyL + #1011 + + + value13 + CCU8x.INyM + #1100 + + + value14 + CCU8x.INyN + #1101 + + + value15 + CCU8x.INyO + #1110 + + + value16 + CCU8x.INyP + #1111 + + + + + EV0EM + Event 0 Edge Selection + 16 + 17 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV1EM + Event 1 Edge Selection + 18 + 19 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV2EM + Event 2 Edge Selection + 20 + 21 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV0LM + Event 0 Level Selection + 22 + 22 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV1LM + Event 1 Level Selection + 23 + 23 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV2LM + Event 2 Level Selection + 24 + 24 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + LPF0M + Event 0 Low Pass Filter Configuration + 25 + 26 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU8 + #01 + + + value3 + 5 clock cycles of fCCU8 + #10 + + + value4 + 7 clock cycles of fCCU8 + #11 + + + + + LPF1M + Event 1 Low Pass Filter Configuration + 27 + 28 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU8 + #01 + + + value3 + 5 clock cycles of fCCU8 + #10 + + + value4 + 7 clock cycles of fCCU8 + #11 + + + + + LPF2M + Event 2 Low Pass Filter Configuration + 29 + 30 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU8 + #01 + + + value3 + 5 clock cycles of fCCU8 + #10 + + + value4 + 7 clock cycles of fCCU8 + #11 + + + + + + + CMC + Connection Matrix Control + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + STRTS + External Start Functionality Selector + 0 + 1 + read-write + + + value1 + External Start Function deactivated + #00 + + + value2 + External Start Function triggered by Event 0 + #01 + + + value3 + External Start Function triggered by Event 1 + #10 + + + value4 + External Start Function triggered by Event 2 + #11 + + + + + ENDS + External Stop Functionality Selector + 2 + 3 + read-write + + + value1 + External Stop Function deactivated + #00 + + + value2 + External Stop Function triggered by Event 0 + #01 + + + value3 + External Stop Function triggered by Event 1 + #10 + + + value4 + External Stop Function triggered by Event 2 + #11 + + + + + CAP0S + External Capture 0 Functionality Selector + 4 + 5 + read-write + + + value1 + External Capture 0 Function deactivated + #00 + + + value2 + External Capture 0 Function triggered by Event 0 + #01 + + + value3 + External Capture 0 Function triggered by Event 1 + #10 + + + value4 + External Capture 0 Function triggered by Event 2 + #11 + + + + + CAP1S + External Capture 1 Functionality Selector + 6 + 7 + read-write + + + value1 + External Capture 1 Function deactivated + #00 + + + value2 + External Capture 1 Function triggered by Event 0 + #01 + + + value3 + External Capture 1 Function triggered by Event 1 + #10 + + + value4 + External Capture 1 Function triggered by Event 2 + #11 + + + + + GATES + External Gate Functionality Selector + 8 + 9 + read-write + + + value1 + External Gating Function deactivated + #00 + + + value2 + External Gating Function triggered by Event 0 + #01 + + + value3 + External Gating Function triggered by Event 1 + #10 + + + value4 + External Gating Function triggered by Event 2 + #11 + + + + + UDS + External Up/Down Functionality Selector + 10 + 11 + read-write + + + value1 + External Up/Down Function deactivated + #00 + + + value2 + External Up/Down Function triggered by Event 0 + #01 + + + value3 + External Up/Down Function triggered by Event 1 + #10 + + + value4 + External Up/Down Function triggered by Event 2 + #11 + + + + + LDS + External Timer Load Functionality Selector + 12 + 13 + read-write + + + CNTS + External Count Selector + 14 + 15 + read-write + + + value1 + External Count Function deactivated + #00 + + + value2 + External Count Function triggered by Event 0 + #01 + + + value3 + External Count Function triggered by Event 1 + #10 + + + value4 + External Count Function triggered by Event 2 + #11 + + + + + OFS + Override Function Selector + 16 + 16 + read-write + + + value1 + Override functionality disabled + #0 + + + value2 + Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 + #1 + + + + + TS + Trap Function Selector + 17 + 17 + read-write + + + value1 + Trap function disabled + #0 + + + value2 + TRAP function connected to Event 2 + #1 + + + + + MOS + External Modulation Functionality Selector + 18 + 19 + read-write + + + TCE + Timer Concatenation Enable + 20 + 20 + read-write + + + value1 + Timer concatenation is disabled + #0 + + + value2 + Timer concatenation is enabled + #1 + + + + + + + TCST + Slice Timer Status + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRB + Timer Run Bit + 0 + 0 + read-only + + + value1 + Timer is stopped + #0 + + + value2 + Timer is running + #1 + + + + + CDIR + Timer Counting Direction + 1 + 1 + read-only + + + value1 + Timer is counting up + #0 + + + value2 + Timer is counting down + #1 + + + + + DTR1 + Dead Time Counter 1 Run bit + 3 + 3 + read-only + + + value1 + Dead Time counter is idle + #0 + + + value2 + Dead Time counter is running + #1 + + + + + DTR2 + Dead Time Counter 2 Run bit + 4 + 4 + read-only + + + value1 + Dead Time counter is idle + #0 + + + value2 + Dead Time counter is running + #1 + + + + + + + TCSET + Slice Timer Run Set + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBS + Timer Run Bit set + 0 + 0 + write-only + + + + + TCCLR + Slice Timer Clear + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBC + Timer Run Bit Clear + 0 + 0 + write-only + + + TCC + Timer Clear + 1 + 1 + write-only + + + DITC + Dither Counter Clear + 2 + 2 + write-only + + + DTC1C + Dead Time Counter 1 Clear + 3 + 3 + write-only + + + DTC2C + Dead Time Counter 2 Clear + 4 + 4 + write-only + + + + + TC + Slice Timer Control + 0x0014 + 32 + 0x18000000 + 0xFFFFFFFF + + + TCM + Timer Counting Mode + 0 + 0 + read-write + + + value1 + Edge aligned mode + #0 + + + value2 + Center aligned mode + #1 + + + + + TSSM + Timer Single Shot Mode + 1 + 1 + read-write + + + value1 + Single shot mode is disabled + #0 + + + value2 + Single shot mode is enabled + #1 + + + + + CLST + Shadow Transfer on Clear + 2 + 2 + read-write + + + CMOD + Capture Compare Mode + 3 + 3 + read-only + + + value1 + Compare Mode + #0 + + + value2 + Capture Mode + #1 + + + + + ECM + Extended Capture Mode + 4 + 4 + read-write + + + value1 + Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. + #0 + + + value2 + Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared + #1 + + + + + CAPC + Clear on Capture Control + 5 + 6 + read-write + + + value1 + Timer is never cleared on a capture event + #00 + + + value2 + Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) + #01 + + + value3 + Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) + #10 + + + value4 + Timer is always cleared in a capture event. + #11 + + + + + TLS + Timer Load selector + 7 + 7 + read-write + + + value1 + Timer is loaded with the value of CR1 + #0 + + + value2 + Timer is loaded with the value of CR2 + #1 + + + + + ENDM + Extended Stop Function Control + 8 + 9 + read-write + + + value1 + Clears the timer run bit only (default stop) + #00 + + + value2 + Clears the timer only (flush) + #01 + + + value3 + Clears the timer and run bit (flush/stop) + #10 + + + + + STRM + Extended Start Function Control + 10 + 10 + read-write + + + value1 + Sets run bit only (default start) + #0 + + + value2 + Clears the timer and sets run bit, if not set (flush/start) + #1 + + + + + SCE + Equal Capture Event enable + 11 + 11 + read-write + + + value1 + Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #0 + + + value2 + Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #1 + + + + + CCS + Continuous Capture Enable + 12 + 12 + read-write + + + value1 + The capture into a specific capture register is done with the rules linked with the full flags, described at . + #0 + + + value2 + The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). + #1 + + + + + DITHE + Dither Enable + 13 + 14 + read-write + + + value1 + Dither is disabled + #00 + + + value2 + Dither is applied to the Period + #01 + + + value3 + Dither is applied to the Compare + #10 + + + value4 + Dither is applied to the Period and Compare + #11 + + + + + DIM + Dither input selector + 15 + 15 + read-write + + + value1 + Slice is using it own dither unit + #0 + + + value2 + Slice is connected to the dither unit of slice 0. + #1 + + + + + FPE + Floating Prescaler enable + 16 + 16 + read-write + + + value1 + Floating prescaler mode is disabled + #0 + + + value2 + Floating prescaler mode is enabled + #1 + + + + + TRAPE0 + TRAP enable for CCU8x.OUTy0 + 17 + 17 + read-write + + + value1 + TRAP functionality has no effect on the CCU8x.OUTy0 output + #0 + + + value2 + TRAP functionality affects the CCU8x.OUTy0 output + #1 + + + + + TRAPE1 + TRAP enable for CCU8x.OUTy1 + 18 + 18 + read-write + + + TRAPE2 + TRAP enable for CCU8x.OUTy2 + 19 + 19 + read-write + + + TRAPE3 + TRAP enable for CCU8x.OUTy3 + 20 + 20 + read-write + + + TRPSE + TRAP Synchronization Enable + 21 + 21 + read-write + + + value1 + Exiting from TRAP state isn't synchronized with the PWM signal + #0 + + + value2 + Exiting from TRAP state is synchronized with the PWM signal + #1 + + + + + TRPSW + TRAP State Clear Control + 22 + 22 + read-write + + + value1 + The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW) + #0 + + + value2 + The TRAP state can only be exited by a SW request. + #1 + + + + + EMS + External Modulation Synchronization + 23 + 23 + read-write + + + value1 + External Modulation functionality is not synchronized with the PWM signal + #0 + + + value2 + External Modulation functionality is synchronized with the PWM signal + #1 + + + + + EMT + External Modulation Type + 24 + 24 + read-write + + + value1 + External Modulation functionality is clearing the CC8ySTx bits. + #0 + + + value2 + External Modulation functionality is gating the outputs. + #1 + + + + + MCME1 + Multi Channel Mode Enable for Channel 1 + 25 + 25 + read-write + + + value1 + Multi Channel Mode in Channel 1 is disabled + #0 + + + value2 + Multi Channel Mode in Channel 1 is enabled + #1 + + + + + MCME2 + Multi Channel Mode Enable for Channel 2 + 26 + 26 + read-write + + + value1 + Multi Channel Mode in Channel 2 is disabled + #0 + + + value2 + Multi Channel Mode in Channel 2 is enabled + #1 + + + + + EME + External Modulation Channel enable + 27 + 28 + read-write + + + value1 + External Modulation functionality doesn't affect any channel + #00 + + + value2 + External Modulation only applied on channel 1 + #01 + + + value3 + External Modulation only applied on channel 2 + #10 + + + value4 + External Modulation applied on both channels + #11 + + + + + STOS + Status bit output selector + 29 + 30 + read-write + + + value1 + CC8yST1 forward to CCU8x.STy + #00 + + + value2 + CC8yST2 forward to CCU8x.STy + #01 + + + value3 + CC8yST1 AND CC8yST2 forward to CCU8x.STy + #10 + + + value4 + CC8yST1 OR CC8yST2 forward to CCU8x.STy + #11 + + + + + + + PSL + Passive Level Config + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSL11 + Output Passive Level for CCU8x.OUTy0 + 0 + 0 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + PSL12 + Output Passive Level for CCU8x.OUTy1 + 1 + 1 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + PSL21 + Output Passive Level for CCU8x.OUTy2 + 2 + 2 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + PSL22 + Output Passive Level for CCU8x.OUTy3 + 3 + 3 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + + + DIT + Dither Config + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + DCV + Dither compare Value + 0 + 3 + read-only + + + DCNT + Dither counter actual value + 8 + 11 + read-only + + + + + DITS + Dither Shadow Register + 0x0020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCVS + Dither Shadow Compare Value + 0 + 3 + read-write + + + + + PSC + Prescaler Control + 0x0024 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSIV + Prescaler Initial Value + 0 + 3 + read-write + + + + + FPC + Floating Prescaler Control + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Compare Value + 0 + 3 + read-only + + + PVAL + Actual Prescaler Value + 8 + 11 + read-write + + + + + FPCS + Floating Prescaler Shadow + 0x002C + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Shadow Compare Value + 0 + 3 + read-write + + + + + PR + Timer Period Value + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + PR + Period Register + 0 + 15 + read-only + + + + + PRS + Timer Shadow Period Value + 0x0034 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRS + Period Register + 0 + 15 + read-write + + + + + CR1 + Channel 1 Compare Value + 0x0038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR1 + Compare Register for Channel 1 + 0 + 15 + read-only + + + + + CR1S + Channel 1 Compare Shadow Value + 0x003C + 32 + 0x00000000 + 0xFFFFFFFF + + + CR1S + Shadow Compare Register for Channel 1 + 0 + 15 + read-write + + + + + CR2 + Channel 2 Compare Value + 0x0040 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR2 + Compare Register for Channel 2 + 0 + 15 + read-only + + + + + CR2S + Channel 2 Compare Shadow Value + 0x0044 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR2S + Shadow Compare Register for Channel 2 + 0 + 15 + read-write + + + + + CHC + Channel Control + 0x0048 + 32 + 0x00000000 + 0xFFFFFFFF + + + ASE + Asymmetric PWM mode Enable + 0 + 0 + read-write + + + value1 + Asymmetric PWM is disabled + #0 + + + value2 + Asymmetric PWM is enabled + #1 + + + + + OCS1 + Output selector for CCU8x.OUTy0 + 1 + 1 + read-write + + + value1 + CC8yST1 signal path is connected to the CCU8x.OUTy0 + #0 + + + value2 + Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0 + #1 + + + + + OCS2 + Output selector for CCU8x.OUTy1 + 2 + 2 + read-write + + + value1 + Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1 + #0 + + + value2 + CC8yST1 signal path is connected to the CCU8x.OUTy1 + #1 + + + + + OCS3 + Output selector for CCU8x.OUTy2 + 3 + 3 + read-write + + + value1 + CC8yST2 signal path is connected to the CCU8x.OUTy2 + #0 + + + value2 + Inverted CCST2 signal path is connected to the CCU8x.OUTy2 + #1 + + + + + OCS4 + Output selector for CCU8x.OUTy3 + 4 + 4 + read-write + + + value1 + Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3 + #0 + + + value2 + CC8yST2 signal path is connected to the CCU8x.OUTy3 + #1 + + + + + + + DTC + Dead Time Control + 0x004C + 32 + 0x00000000 + 0xFFFFFFFF + + + DTE1 + Dead Time Enable for Channel 1 + 0 + 0 + read-write + + + value1 + Dead Time for channel 1 is disabled + #0 + + + value2 + Dead Time for channel 1 is enabled + #1 + + + + + DTE2 + Dead Time Enable for Channel 2 + 1 + 1 + read-write + + + value1 + Dead Time for channel 2 is disabled + #0 + + + value2 + Dead Time for channel 2 is enabled + #1 + + + + + DCEN1 + Dead Time Enable for CC8yST1 + 2 + 2 + read-write + + + value1 + Dead Time for CC8yST1 path is disabled + #0 + + + value2 + Dead Time for CC8yST1 path is enabled + #1 + + + + + DCEN2 + Dead Time Enable for inverted CC8yST1 + 3 + 3 + read-write + + + value1 + Dead Time for inverted CC8yST1 path is disabled + #0 + + + value2 + Dead Time for inverted CC8yST1 path is enabled + #1 + + + + + DCEN3 + Dead Time Enable for CC8yST2 + 4 + 4 + read-write + + + value1 + Dead Time for CC8yST2 path is disabled + #0 + + + value2 + Dead Time for CC8yST2 path is enabled + #1 + + + + + DCEN4 + Dead Time Enable for inverted CC8yST2 + 5 + 5 + read-write + + + value1 + Dead Time for inverted CC8yST2 path is disabled + #0 + + + value2 + Dead Time for inverted CC8yST2 path is enabled + #1 + + + + + DTCC + Dead Time clock control + 6 + 7 + read-write + + + value1 + ftclk + #00 + + + value2 + ftclk/2 + #01 + + + value3 + ftclk/4 + #10 + + + value4 + ftclk/8 + #11 + + + + + + + DC1R + Channel 1 Dead Time Values + 0x0050 + 32 + 0x00000000 + 0xFFFFFFFF + + + DT1R + Rise Value for Dead Time of Channel 1 + 0 + 7 + read-write + + + DT1F + Fall Value for Dead Time of Channel 1 + 8 + 15 + read-write + + + + + DC2R + Channel 2 Dead Time Values + 0x0054 + 32 + 0x00000000 + 0xFFFFFFFF + + + DT2R + Rise Value for Dead Time of Channel 2 + 0 + 7 + read-write + + + DT2F + Fall Value for Dead Time of Channel 2 + 8 + 15 + read-write + + + + + TIMER + Timer Value + 0x0070 + 32 + 0x00000000 + 0xFFFFFFFF + + + TVAL + Timer Value + 0 + 15 + read-write + + + + + C0V + Capture Register 0 + 0x0074 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C1V + Capture Register 1 + 0x0078 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C2V + Capture Register 2 + 0x007C + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C3V + Capture Register 3 + 0x0080 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + INTS + Interrupt Status + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PMUS + Period Match while Counting Up + 0 + 0 + read-only + + + value1 + Period match while counting up not detected + #0 + + + value2 + Period match while counting up detected + #1 + + + + + OMDS + One Match while Counting Down + 1 + 1 + read-only + + + value1 + One match while counting down not detected + #0 + + + value2 + One match while counting down detected + #1 + + + + + CMU1S + Channel 1 Compare Match while Counting Up + 2 + 2 + read-only + + + value1 + Compare match while counting up not detected + #0 + + + value2 + Compare match while counting up detected + #1 + + + + + CMD1S + Channel 1 Compare Match while Counting Down + 3 + 3 + read-only + + + value1 + Compare match while counting down not detected + #0 + + + value2 + Compare match while counting down detected + #1 + + + + + CMU2S + Channel 2 Compare Match while Counting Up + 4 + 4 + read-only + + + value1 + Compare match while counting up not detected + #0 + + + value2 + Compare match while counting up detected + #1 + + + + + CMD2S + Channel 2 Compare Match while Counting Down + 5 + 5 + read-only + + + value1 + Compare match while counting down not detected + #0 + + + value2 + Compare match while counting down detected + #1 + + + + + E0AS + Event 0 Detection Status + 8 + 8 + read-only + + + value1 + Event 0 not detected + #0 + + + value2 + Event 0 detected + #1 + + + + + E1AS + Event 1 Detection Status + 9 + 9 + read-only + + + value1 + Event 1 not detected + #0 + + + value2 + Event 1 detected + #1 + + + + + E2AS + Event 2 Detection Status + 10 + 10 + read-only + + + value1 + Event 2 not detected + #0 + + + value2 + Event 2 detected + #1 + + + + + TRPF + Trap Flag Status + 11 + 11 + read-only + + + + + INTE + Interrupt Enable Control + 0x00A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + PME + Period match while counting up enable + 0 + 0 + read-write + + + value1 + Period Match interrupt is disabled + #0 + + + value2 + Period Match interrupt is enabled + #1 + + + + + OME + One match while counting down enable + 1 + 1 + read-write + + + value1 + One Match interrupt is disabled + #0 + + + value2 + One Match interrupt is enabled + #1 + + + + + CMU1E + Channel 1 Compare match while counting up enable + 2 + 2 + read-write + + + value1 + Compare Match while counting up interrupt is disabled + #0 + + + value2 + Compare Match while counting up interrupt is enabled + #1 + + + + + CMD1E + Channel 1 Compare match while counting down enable + 3 + 3 + read-write + + + value1 + Compare Match while counting down interrupt is disabled + #0 + + + value2 + Compare Match while counting down interrupt is enabled + #1 + + + + + CMU2E + Channel 2 Compare match while counting up enable + 4 + 4 + read-write + + + value1 + Compare Match while counting up interrupt is disabled + #0 + + + value2 + Compare Match while counting up interrupt is enabled + #1 + + + + + CMD2E + Channel 2 Compare match while counting down enable + 5 + 5 + read-write + + + value1 + Compare Match while counting down interrupt is disabled + #0 + + + value2 + Compare Match while counting down interrupt is enabled + #1 + + + + + E0AE + Event 0 interrupt enable + 8 + 8 + read-write + + + value1 + Event 0 detection interrupt is disabled + #0 + + + value2 + Event 0 detection interrupt is enabled + #1 + + + + + E1AE + Event 1 interrupt enable + 9 + 9 + read-write + + + value1 + Event 1 detection interrupt is disabled + #0 + + + value2 + Event 1 detection interrupt is enabled + #1 + + + + + E2AE + Event 2 interrupt enable + 10 + 10 + read-write + + + value1 + Event 2 detection interrupt is disabled + #0 + + + value2 + Event 2 detection interrupt is enabled + #1 + + + + + + + SRS + Service Request Selector + 0x00A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSR + Period/One match Service request selector + 0 + 1 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + CM1SR + Channel 1 Compare match Service request selector + 2 + 3 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + CM2SR + Channel 2 Compare match Service request selector + 4 + 5 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + E0SR + Event 0 Service request selector + 8 + 9 + read-write + + + value1 + Forward to CCvySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + E1SR + Event 1 Service request selector + 10 + 11 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + E2SR + Event 2 Service request selector + 12 + 13 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CCvySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + + + SWS + Interrupt Status Set + 0x00AC + 32 + 0x00000000 + 0xFFFFFFFF + + + SPM + Period match while counting up set + 0 + 0 + write-only + + + SOM + One match while counting down set + 1 + 1 + write-only + + + SCM1U + Channel 1 Compare match while counting up set + 2 + 2 + write-only + + + SCM1D + Channel 1 Compare match while counting down set + 3 + 3 + write-only + + + SCM2U + Compare match while counting up set + 4 + 4 + write-only + + + SCM2D + Compare match while counting down set + 5 + 5 + write-only + + + SE0A + Event 0 detection set + 8 + 8 + write-only + + + SE1A + Event 1 detection set + 9 + 9 + write-only + + + SE2A + Event 2 detection set + 10 + 10 + write-only + + + STRPF + Trap Flag status set + 11 + 11 + write-only + + + + + SWR + Interrupt Status Clear + 0x00B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPM + Period match while counting up clear + 0 + 0 + write-only + + + ROM + One match while counting down clear + 1 + 1 + write-only + + + RCM1U + Channel 1 Compare match while counting up clear + 2 + 2 + write-only + + + RCM1D + Channel 1 Compare match while counting down clear + 3 + 3 + write-only + + + RCM2U + Channel 2 Compare match while counting up clear + 4 + 4 + write-only + + + RCM2D + Channel 2 Compare match while counting down clear + 5 + 5 + write-only + + + RE0A + Event 0 detection clear + 8 + 8 + write-only + + + RE1A + Event 1 detection clear + 9 + 9 + write-only + + + RE2A + Event 2 detection clear + 10 + 10 + write-only + + + RTRPF + Trap Flag status clear + 11 + 11 + write-only + + + + + STC + Shadow transfer control + 0x00B4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CSE + Cascaded shadow transfer enable + 0 + 0 + read-write + + + value1 + Cascaded shadow transfer disabled + #0 + + + value2 + Cascaded shadow transfer enabled + #1 + + + + + STM + Shadow transfer mode + 1 + 2 + read-write + + + value1 + Shadow transfer is done in Period Match and One match. + #00 + + + value2 + Shadow transfer is done only in Period Match. + #01 + + + value3 + Shadow transfer is done only in One Match. + #10 + + + + + + + ECRD0 + Extended Read Back 0 + 0x00B8 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC80 + #00 + + + value2 + CC81 + #01 + + + value3 + CC82 + #10 + + + value4 + CC83 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + ECRD1 + Extended Read Back 1 + 0x00BC + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC80 + #00 + + + value2 + CC81 + #01 + + + value3 + CC82 + #10 + + + value4 + CC83 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + + + CCU80_CC81 + Capture Compare Unit 8 - Unit 0 + CCU8 + 0x40020200 + + 0x0 + 0x100 + registers + + + + CCU80_CC82 + Capture Compare Unit 8 - Unit 0 + CCU8 + 0x40020300 + + 0x0 + 0x100 + registers + + + + CCU80_CC83 + Capture Compare Unit 8 - Unit 0 + CCU8 + 0x40020400 + + 0x0 + 0x100 + registers + + + + CCU81_CC80 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024100 + + 0x0 + 0x100 + registers + + + + CCU81_CC81 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024200 + + 0x0 + 0x100 + registers + + + + CCU81_CC82 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024300 + + 0x0 + 0x100 + registers + + + + CCU81_CC83 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024400 + + 0x0 + 0x100 + registers + + + + POSIF0 + Position Interface 0 + POSIF + POSIF + 0x40028000 + + 0x0 + 0x4000 + registers + + + POSIF0_0 + Position Interface (Module 0) + 68 + + + POSIF0_1 + Position Interface (Module 0) + 69 + + + + PCONF + POSIF configuration + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + FSEL + Function Selector + 0 + 1 + read-write + + + value1 + Hall Sensor Mode enabled + #00 + + + value2 + Quadrature Decoder Mode enabled + #01 + + + value3 + stand-alone Multi-Channel Mode enabled + #10 + + + value4 + Quadrature Decoder and stand-alone Multi-Channel Mode enabled + #11 + + + + + QDCM + Position Decoder Mode selection + 2 + 2 + read-write + + + value1 + Position encoder is in Quadrature Mode + #0 + + + value2 + Position encoder is in Direction Count Mode. + #1 + + + + + HIDG + Idle generation enable + 4 + 4 + read-write + + + MCUE + Multi-Channel Pattern SW update enable + 5 + 5 + read-write + + + value1 + Multi-Channel pattern update is controlled via HW + #0 + + + value2 + Multi-Channel pattern update is controlled via SW + #1 + + + + + INSEL0 + PhaseA/Hal input 1 selector + 8 + 9 + read-write + + + value1 + POSIFx.IN0A + #00 + + + value2 + POSIFx.IN0B + #01 + + + value3 + POSIFx.IN0C + #10 + + + value4 + POSIFx.IN0D + #11 + + + + + INSEL1 + PhaseB/Hall input 2 selector + 10 + 11 + read-write + + + value1 + POSIFx.IN1A + #00 + + + value2 + POSIFx.IN1B + #01 + + + value3 + POSIFx.IN1C + #10 + + + value4 + POSIFx.IN1D + #11 + + + + + INSEL2 + Index/Hall input 3 selector + 12 + 13 + read-write + + + value1 + POSIFx.IN2A + #00 + + + value2 + POSIFx.IN2B + #01 + + + value3 + POSIFx.IN2C + #10 + + + value4 + POSIFx.IN2D + #11 + + + + + DSEL + Delay Pin selector + 16 + 16 + read-write + + + value1 + POSIFx.HSDA + #0 + + + value2 + POSIFx.HSDB + #1 + + + + + SPES + Edge selector for the sampling trigger + 17 + 17 + read-write + + + value1 + Rising edge + #0 + + + value2 + Falling edge + #1 + + + + + MSETS + Pattern update signal select + 18 + 20 + read-write + + + value1 + POSIFx.MSETA + #000 + + + value2 + POSIFx.MSETB + #001 + + + value3 + POSIFx.MSETC + #010 + + + value4 + POSIFx.MSETD + #011 + + + value5 + POSIFx.MSETE + #100 + + + value6 + POSIFx.MSETF + #101 + + + value7 + POSIFx.MSETG + #110 + + + value8 + POSIFx.MSETH + #111 + + + + + MSES + Multi-Channel pattern update trigger edge + 21 + 21 + read-write + + + value1 + The signal used to enable a pattern update is active on the rising edge + #0 + + + value2 + The signal used to enable a pattern update is active on the falling edge + #1 + + + + + MSYNS + PWM synchronization signal selector + 22 + 23 + read-write + + + value1 + POSIFx.MSYNCA + #00 + + + value2 + POSIFx.MSYNCB + #01 + + + value3 + POSIFx.MSYNCC + #10 + + + value4 + POSIFx.MSYNCD + #11 + + + + + EWIS + Wrong Hall Event selection + 24 + 25 + read-write + + + value1 + POSIFx.EWHEA + #00 + + + value2 + POSIFx.EWHEB + #01 + + + value3 + POSIFx.EWHEC + #10 + + + value4 + POSIFx.EWHED + #11 + + + + + EWIE + External Wrong Hall Event enable + 26 + 26 + read-write + + + value1 + External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled + #0 + + + value2 + External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled. + #1 + + + + + EWIL + External Wrong Hall Event active level + 27 + 27 + read-write + + + value1 + POSIFx.EWHE[D...A] signal is active HIGH + #0 + + + value2 + POSIFx.EWHE[D...A] signal is active LOW + #1 + + + + + LPC + Low Pass Filters Configuration + 28 + 30 + read-write + + + value1 + Low pass filter disabled + #000 + + + value2 + Low pass of 1 clock cycle + #001 + + + value3 + Low pass of 2 clock cycles + #010 + + + value4 + Low pass of 4 clock cycles + #011 + + + value5 + Low pass of 8 clock cycles + #100 + + + value6 + Low pass of 16 clock cycles + #101 + + + value7 + Low pass of 32 clock cycles + #110 + + + value8 + Low pass of 64 clock cycles + #111 + + + + + + + PSUS + POSIF Suspend Config + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + QSUS + Quadrature Mode Suspend Config + 0 + 1 + read-write + + + value1 + Suspend request ignored + #00 + + + value2 + Stop immediately + #01 + + + value3 + Suspend in the next index occurrence + #10 + + + value4 + Suspend in the next phase (PhaseA or PhaseB) occurrence + #11 + + + + + MSUS + Multi-Channel Mode Suspend Config + 2 + 3 + read-write + + + value1 + Suspend request ignored + #00 + + + value2 + Stop immediately. Multi-Channel pattern is not set to the reset value. + #01 + + + value3 + Stop immediately. Multi-Channel pattern is set to the reset value. + #10 + + + value4 + Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization. + #11 + + + + + + + PRUNS + POSIF Run Bit Set + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRB + Set Run bit + 0 + 0 + write-only + + + + + PRUNC + POSIF Run Bit Clear + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + CRB + Clear Run bit + 0 + 0 + write-only + + + CSM + Clear Current internal status + 1 + 1 + write-only + + + + + PRUN + POSIF Run Bit Status + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + RB + Run Bit + 0 + 0 + read-only + + + value1 + IDLE + #0 + + + value2 + Running + #1 + + + + + + + MIDR + Module Identification register + 0x0020 + 32 + 0x00A8C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + HALP + Hall Sensor Patterns + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + HCP + Hall Current Pattern + 0 + 2 + read-only + + + HEP + Hall Expected Pattern + 3 + 5 + read-only + + + + + HALPS + Hall Sensor Shadow Patterns + 0x0034 + 32 + 0x00000000 + 0xFFFFFFFF + + + HCPS + Shadow Hall Current Pattern + 0 + 2 + read-write + + + HEPS + Shadow Hall expected Pattern + 3 + 5 + read-write + + + + + MCM + Multi-Channel Pattern + 0x0040 + 32 + 0x00000000 + 0xFFFFFFFF + + + MCMP + Multi-Channel Pattern + 0 + 15 + read-only + + + + + MCSM + Multi-Channel Shadow Pattern + 0x0044 + 32 + 0x00000000 + 0xFFFFFFFF + + + MCMPS + Shadow Multi-Channel Pattern + 0 + 15 + read-write + + + + + MCMS + Multi-Channel Pattern Control set + 0x0048 + 32 + 0x00000000 + 0xFFFFFFFF + + + MNPS + Multi-Channel Pattern Update Enable Set + 0 + 0 + write-only + + + STHR + Hall Pattern Shadow Transfer Request + 1 + 1 + write-only + + + STMR + Multi-Channel Shadow Transfer Request + 2 + 2 + write-only + + + + + MCMC + Multi-Channel Pattern Control clear + 0x004C + 32 + 0x00000000 + 0xFFFFFFFF + + + MNPC + Multi-Channel Pattern Update Enable Clear + 0 + 0 + write-only + + + MPC + Multi-Channel Pattern clear + 1 + 1 + write-only + + + + + MCMF + Multi-Channel Pattern Control flag + 0x0050 + 32 + 0x00000000 + 0xFFFFFFFF + + + MSS + Multi-Channel Pattern update status + 0 + 0 + read-only + + + value1 + Update of the Multi-Channel pattern is set + #0 + + + value2 + Update of the Multi-Channel pattern is not set + #1 + + + + + + + QDC + Quadrature Decoder Control + 0x0060 + 32 + 0x00000000 + 0xFFFFFFFF + + + PALS + Phase A Level selector + 0 + 0 + read-write + + + value1 + Phase A is active HIGH + #0 + + + value2 + Phase A is active LOW + #1 + + + + + PBLS + Phase B Level selector + 1 + 1 + read-write + + + value1 + Phase B is active HIGH + #0 + + + value2 + Phase B is active LOW + #1 + + + + + PHS + Phase signals swap + 2 + 2 + read-write + + + value1 + Phase A is the leading signal for clockwise rotation + #0 + + + value2 + Phase B is the leading signal for clockwise rotation + #1 + + + + + ICM + Index Marker generations control + 4 + 5 + read-write + + + value1 + No index marker generation on POSIFx.OUT3 + #00 + + + value2 + Only first index occurrence generated on POSIFx.OUT3 + #01 + + + value3 + All index occurrences generated on POSIFx.OUT3 + #10 + + + + + DVAL + Current rotation direction + 8 + 8 + read-only + + + value1 + Counterclockwise rotation + #0 + + + value2 + Clockwise rotation + #1 + + + + + + + PFLG + POSIF Interrupt Flags + 0x0070 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHES + Correct Hall Event Status + 0 + 0 + read-only + + + value1 + Correct Hall Event not detected + #0 + + + value2 + Correct Hall Event detected + #1 + + + + + WHES + Wrong Hall Event Status + 1 + 1 + read-only + + + value1 + Wrong Hall Event not detected + #0 + + + value2 + Wrong Hall Event detected + #1 + + + + + HIES + Hall Inputs Update Status + 2 + 2 + read-only + + + value1 + Transition on the Hall Inputs not detected + #0 + + + value2 + Transition on the Hall Inputs detected + #1 + + + + + MSTS + Multi-Channel pattern shadow transfer status + 4 + 4 + read-only + + + value1 + Shadow transfer not done + #0 + + + value2 + Shadow transfer done + #1 + + + + + INDXS + Quadrature Index Status + 8 + 8 + read-only + + + value1 + Index event not detected + #0 + + + value2 + Index event detected + #1 + + + + + ERRS + Quadrature Phase Error Status + 9 + 9 + read-only + + + value1 + Phase Error event not detected + #0 + + + value2 + Phase Error event detected + #1 + + + + + CNTS + Quadrature CLK Status + 10 + 10 + read-only + + + value1 + Quadrature clock not generated + #0 + + + value2 + Quadrature clock generated + #1 + + + + + DIRS + Quadrature Direction Change + 11 + 11 + read-only + + + value1 + Change on direction not detected + #0 + + + value2 + Change on direction detected + #1 + + + + + PCLKS + Quadrature Period Clk Status + 12 + 12 + read-only + + + value1 + Period clock not generated + #0 + + + value2 + Period clock generated + #1 + + + + + + + PFLGE + POSIF Interrupt Enable + 0x0074 + 32 + 0x00000000 + 0xFFFFFFFF + + + ECHE + Correct Hall Event Enable + 0 + 0 + read-write + + + value1 + Correct Hall Event interrupt disabled + #0 + + + value2 + Correct Hall Event interrupt enabled + #1 + + + + + EWHE + Wrong Hall Event Enable + 1 + 1 + read-write + + + value1 + Wrong Hall Event interrupt disabled + #0 + + + value2 + Wrong Hall Event interrupt enabled + #1 + + + + + EHIE + Hall Input Update Enable + 2 + 2 + read-write + + + value1 + Update of the Hall Inputs interrupt is disabled + #0 + + + value2 + Update of the Hall Inputs interrupt is enabled + #1 + + + + + EMST + Multi-Channel pattern shadow transfer enable + 4 + 4 + read-write + + + value1 + Shadow transfer event interrupt disabled + #0 + + + value2 + Shadow transfer event interrupt enabled + #1 + + + + + EINDX + Quadrature Index Event Enable + 8 + 8 + read-write + + + value1 + Index event interrupt disabled + #0 + + + value2 + Index event interrupt enabled + #1 + + + + + EERR + Quadrature Phase Error Enable + 9 + 9 + read-write + + + value1 + Phase error event interrupt disabled + #0 + + + value2 + Phase error event interrupt enabled + #1 + + + + + ECNT + Quadrature CLK interrupt Enable + 10 + 10 + read-write + + + value1 + Quadrature CLK event interrupt disabled + #0 + + + value2 + Quadrature CLK event interrupt enabled + #1 + + + + + EDIR + Quadrature direction change interrupt Enable + 11 + 11 + read-write + + + value1 + Direction change event interrupt disabled + #0 + + + value2 + Direction change event interrupt enabled + #1 + + + + + EPCLK + Quadrature Period CLK interrupt Enable + 12 + 12 + read-write + + + value1 + Quadrature Period CLK event interrupt disabled + #0 + + + value2 + Quadrature Period CLK event interrupt enabled + #1 + + + + + CHESEL + Correct Hall Event Service Request Selector + 16 + 16 + read-write + + + value1 + Correct Hall Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Correct Hall Event interrupt forward to POSIFx.SR1 + #1 + + + + + WHESEL + Wrong Hall Event Service Request Selector + 17 + 17 + read-write + + + value1 + Wrong Hall Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Wrong Hall Event interrupt forward to POSIFx.SR1 + #1 + + + + + HIESEL + Hall Inputs Update Event Service Request Selector + 18 + 18 + read-write + + + value1 + Hall Inputs Update Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Hall Inputs Update Event interrupt forward to POSIFx.SR1 + #1 + + + + + MSTSEL + Multi-Channel pattern Update Event Service Request Selector + 20 + 20 + read-write + + + value1 + Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1 + #1 + + + + + INDSEL + Quadrature Index Event Service Request Selector + 24 + 24 + read-write + + + value1 + Quadrature Index Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Index Event interrupt forward to POSIFx.SR1 + #1 + + + + + ERRSEL + Quadrature Phase Error Event Service Request Selector + 25 + 25 + read-write + + + value1 + Quadrature Phase error Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Phase error Event interrupt forward to POSIFx.SR1 + #1 + + + + + CNTSEL + Quadrature Clock Event Service Request Selector + 26 + 26 + read-write + + + value1 + Quadrature Clock Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Clock Event interrupt forward to POSIFx.SR1 + #1 + + + + + DIRSEL + Quadrature Direction Update Event Service Request Selector + 27 + 27 + read-write + + + value1 + Quadrature Direction Update Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Direction Update Event interrupt forward to POSIFx.SR1 + #1 + + + + + PCLSEL + Quadrature Period clock Event Service Request Selector + 28 + 28 + read-write + + + value1 + Quadrature Period clock Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Period clock Event interrupt forward to POSIFx.SR1 + #1 + + + + + + + SPFLG + POSIF Interrupt Set + 0x0078 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCHE + Correct Hall Event flag set + 0 + 0 + write-only + + + SWHE + Wrong Hall Event flag set + 1 + 1 + write-only + + + SHIE + Hall Inputs Update Event flag set + 2 + 2 + write-only + + + SMST + Multi-Channel Pattern shadow transfer flag set + 4 + 4 + write-only + + + SINDX + Quadrature Index flag set + 8 + 8 + write-only + + + SERR + Quadrature Phase Error flag set + 9 + 9 + write-only + + + SCNT + Quadrature CLK flag set + 10 + 10 + write-only + + + SDIR + Quadrature Direction flag set + 11 + 11 + write-only + + + SPCLK + Quadrature period clock flag set + 12 + 12 + write-only + + + + + RPFLG + POSIF Interrupt Clear + 0x007C + 32 + 0x00000000 + 0xFFFFFFFF + + + RCHE + Correct Hall Event flag clear + 0 + 0 + write-only + + + RWHE + Wrong Hall Event flag clear + 1 + 1 + write-only + + + RHIE + Hall Inputs Update Event flag clear + 2 + 2 + write-only + + + RMST + Multi-Channel Pattern shadow transfer flag clear + 4 + 4 + write-only + + + RINDX + Quadrature Index flag clear + 8 + 8 + write-only + + + RERR + Quadrature Phase Error flag clear + 9 + 9 + write-only + + + RCNT + Quadrature CLK flag clear + 10 + 10 + write-only + + + RDIR + Quadrature Direction flag clear + 11 + 11 + write-only + + + RPCLK + Quadrature period clock flag clear + 12 + 12 + write-only + + + + + PDBG + POSIF Debug register + 0x0100 + 32 + 0x00000000 + 0xFFFFFFFF + + + QCSV + Quadrature Decoder Current state + 0 + 1 + read-only + + + QPSV + Quadrature Decoder Previous state + 2 + 3 + read-only + + + IVAL + Current Index Value + 4 + 4 + read-only + + + HSP + Hall Current Sampled Pattern + 5 + 7 + read-only + + + LPP0 + Actual count of the Low Pass Filter for POSI0 + 8 + 13 + read-only + + + LPP1 + Actual count of the Low Pass Filter for POSI1 + 16 + 21 + read-only + + + LPP2 + Actual count of the Low Pass Filter for POSI2 + 22 + 27 + read-only + + + + + + + POSIF1 + Position Interface 1 + POSIF + 0x4002C000 + + 0x0 + 0x4000 + registers + + + POSIF1_0 + Position Interface (Module 1) + 70 + + + POSIF1_1 + Position Interface (Module 1) + 71 + + + + PORT0 + Port 0 + PORTS + 0x48028000 + + 0x0 + 0x0100 + registers + + + + OUT + Port 0 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 0 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 0 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 0 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 0 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 0 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 0 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 0 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDR1 + Port 0 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDISC + Port 0 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 0 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 0 Pin Hardware Select Register + 0x74 + 32 + 0x00014000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT1 + Port 1 + PORTS + 0x48028100 + + 0x0 + 0x0100 + registers + + + + OUT + Port 1 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 1 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 1 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 1 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 1 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 1 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 1 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 1 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDR1 + Port 1 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 1 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 1 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 1 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT2 + Port 2 + PORTS + 0x48028200 + + 0x0 + 0x0100 + registers + + + + OUT + Port 2 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 2 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 2 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 2 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 2 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 2 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 2 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 2 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 2 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 2 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 2 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 2 Pin Hardware Select Register + 0x74 + 32 + 0x00000004 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT3 + Port 3 + PORTS + 0x48028300 + + 0x0 + 0x0100 + registers + + + + OUT + Port 3 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 3 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 3 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 3 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 3 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 3 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 3 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 3 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 3 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDISC + Port 3 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 3 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 3 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT4 + Port 4 + PORTS + 0x48028400 + + 0x0 + 0x0100 + registers + + + + OUT + Port 4 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 4 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 4 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 4 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 4 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 4 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDISC + Port 4 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 4 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 4 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT5 + Port 5 + PORTS + 0x48028500 + + 0x0 + 0x0100 + registers + + + + OUT + Port 5 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 5 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 5 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 5 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 5 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 5 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 5 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 5 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 5 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 5 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 5 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT6 + Port 6 + PORTS + 0x48028600 + + 0x0 + 0x0100 + registers + + + + OUT + Port 6 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 6 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 6 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 6 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 6 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 6 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 6 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 6 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 6 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT7 + Port 7 + PORTS + 0x48028700 + + 0x0 + 0x0100 + registers + + + + OUT + Port 7 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 7 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 7 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 7 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 7 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 7 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 7 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 7 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 7 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 7 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 7 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT8 + Port 8 + PORTS + 0x48028800 + + 0x0 + 0x0100 + registers + + + + OUT + Port 8 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 8 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 8 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 8 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 8 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 8 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 8 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 8 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 8 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 8 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 8 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT9 + Port 9 + PORTS + 0x48028900 + + 0x0 + 0x0100 + registers + + + + OUT + Port 9 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 9 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 9 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 5 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 9 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 9 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 9 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 9 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 9 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 9 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 9 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT14 + Port 14 + PORTS + 0x48028E00 + + 0x0 + 0x0100 + registers + + + + OUT + Port 14 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 14 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 14 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 14 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 14 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 14 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 14 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDISC + Port 14 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port 14 Pin 0 + 0 + 0 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 0 selected. + #1 + + + + + PDIS1 + Pad Disable for Port 14 Pin 1 + 1 + 1 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 1 selected. + #1 + + + + + PDIS2 + Pad Disable for Port 14 Pin 2 + 2 + 2 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 and ADC 1 analog input 2 selected. + #1 + + + + + PDIS3 + Pad Disable for Port 14 Pin 3 + 3 + 3 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 and ADC 1 analog input 3 selected. + #1 + + + + + PDIS4 + Pad Disable for Port 14 Pin 4 + 4 + 4 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 4 and ADC 2 analog input 0 and DAC Reference selected. + #1 + + + + + PDIS5 + Pad Disable for Port 14 Pin 5 + 5 + 5 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 5 and ADC 2 analog input 1 selected. + #1 + + + + + PDIS6 + Pad Disable for Port 14 Pin 6 + 6 + 6 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 6 selected. + #1 + + + + + PDIS7 + Pad Disable for Port 14 Pin 7 + 7 + 7 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC0 analog input 7 selected. + #1 + + + + + PDIS8 + Pad Disable for Port 14 Pin 8 + 8 + 8 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 0 and ADC 2 analog input 4 and DAC output 0 selected. + #1 + + + + + PDIS9 + Pad Disable for Port 14 Pin 9 + 9 + 9 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 1 and ADC 2 analog input 5 and DAC output 1 selected. + #1 + + + + + PDIS12 + Pad Disable for Port 14 Pin 12 + 12 + 12 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 4 selected. + #1 + + + + + PDIS13 + Pad Disable for Port 14 Pin 13 + 13 + 13 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 5 selected. + #1 + + + + + PDIS14 + Pad Disable for Port 14 Pin 14 + 14 + 14 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 6 selected. + #1 + + + + + PDIS15 + Pad Disable for Port 14 Pin 15 + 15 + 15 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 7 selected. + #1 + + + + + + + PPS + Port 14 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 14 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT15 + Port 15 + PORTS + 0x48028F00 + + 0x0 + 0x0100 + registers + + + + OUT + Port 15 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 15 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 15 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 15 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 15 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 15 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 15 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDISC + Port 15 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS2 + Pad Disable for Port 15 Pin 2 + 2 + 2 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 2. + #1 + + + + + PDIS3 + Pad Disable for Port 15 Pin 3 + 3 + 3 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 3. + #1 + + + + + PDIS4 + Pad Disable for Port 15 Pin 4 + 4 + 4 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 4. + #1 + + + + + PDIS5 + Pad Disable for Port 15 Pin 5 + 5 + 5 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 5. + #1 + + + + + PDIS6 + Pad Disable for Port 15 Pin 6 + 6 + 6 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 6. + #1 + + + + + PDIS7 + Pad Disable for Port 15 Pin 7 + 7 + 7 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 7. + #1 + + + + + PDIS8 + Pad Disable for Port 15 Pin 8 + 8 + 8 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 0. + #1 + + + + + PDIS9 + Pad Disable for Port 15 Pin 9 + 9 + 9 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 1. + #1 + + + + + PDIS12 + Pad Disable for Port 15 Pin 12 + 12 + 12 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 4. + #1 + + + + + PDIS13 + Pad Disable for Port 15 Pin 13 + 13 + 13 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 5. + #1 + + + + + PDIS14 + Pad Disable for Port 15 Pin 14 + 14 + 14 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 6. + #1 + + + + + PDIS15 + Pad Disable for Port 15 Pin 15 + 15 + 15 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 7. + #1 + + + + + + + PPS + Port 15 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 15 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.depend b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.depend index 9816c7d3..d7c71cb7 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.depend +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.depend @@ -1035,7 +1035,7 @@ 1469435361 c:\work\software\openblt\target\source\assert.h -1477061178 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\blt_conf.h +1477217517 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\blt_conf.h 1469435361 c:\work\software\openblt\target\source\plausibility.h @@ -1387,10 +1387,11 @@ "xmc_common.h" "xmc_scu.h" -1477053301 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\main.c +1477218134 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\main.c "boot.h" "xmc_gpio.h" "xmc_uart.h" + "xmc_can.h" 1477086453 source:c:\work\software\openblt\target\source\armcm4_xmc4\cpu.c "boot.h" @@ -1414,7 +1415,7 @@ 1477052921 source:c:\work\software\openblt\target\source\armcm4_xmc4\timer.c "boot.h" -1477052653 source:c:\work\software\openblt\target\source\armcm4_xmc4\uart.c +1477217846 source:c:\work\software\openblt\target\source\armcm4_xmc4\uart.c "boot.h" "xmc_uart.h" @@ -1512,3 +1513,8 @@ "xmc_scu.h" "xmc_gpio.h" +1477217805 source:c:\work\software\openblt\target\source\armcm4_xmc4\can.c + "boot.h" + "xmc_can.h" + "xmc_gpio.h" + diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.ebp b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.ebp index 768a0433..94cd3837 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.ebp +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Boot/ide/xmc4700.ebp @@ -404,6 +404,10 @@

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zuDLU$m=4nQ9^BO7MYCHs+0Wqi*D&Ptq&>}@LB7eJV))Ai7$vrF zju3OY(54oM``zs(I35SmIevX@u;7T#Phy5MMhTlKIQ*$ZhO@95i{C>`SEw1T@oV*t z`x|KpN~qn_B}cz_TFS4_j+7kt{OAb3J~Yj8wD6%{c`bwYS&p;RxrGzEGFm$QeF`kJ e9R3LNav8mW8nkpqgq8lna-?Ajya)Q@KK>7EIB1Cg diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/bin/demoprog_xmc4700.map b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/bin/demoprog_xmc4700.map index 44951469..87a62307 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/bin/demoprog_xmc4700.map +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/bin/demoprog_xmc4700.map @@ -70,6 +70,9 @@ Discarded input sections .group 0x00000000 0x8 ..\obj\boot.o .group 0x00000000 0x8 ..\obj\boot.o .group 0x00000000 0x8 ..\obj\boot.o + .group 0x00000000 0x8 ..\obj\boot.o + .group 0x00000000 0x8 ..\obj\boot.o + .group 0x00000000 0x8 ..\obj\boot.o .text 0x00000000 0x0 ..\obj\boot.o .data 0x00000000 0x0 ..\obj\boot.o .bss 0x00000000 0x0 ..\obj\boot.o @@ -109,7 +112,7 @@ Discarded input sections .data 0x00000000 0x0 ..\obj\led.o .bss 0x00000000 0x0 ..\obj\led.o .debug_macro 0x00000000 0x892 ..\obj\led.o - .debug_macro 0x00000000 0x65 ..\obj\led.o + .debug_macro 0x00000000 0x93 ..\obj\led.o .debug_macro 0x00000000 0x2d ..\obj\led.o .debug_macro 0x00000000 0x22 ..\obj\led.o .debug_macro 0x00000000 0x87 ..\obj\led.o @@ -137,6 +140,7 @@ Discarded input sections .debug_macro 0x00000000 0x35 ..\obj\led.o .debug_macro 0x00000000 0x183 ..\obj\led.o .debug_macro 0x00000000 0x46 ..\obj\led.o + .debug_macro 0x00000000 0x22 ..\obj\led.o .debug_macro 0x00000000 0xdc4 ..\obj\led.o .debug_macro 0x00000000 0xba ..\obj\led.o .group 0x00000000 0x8 ..\obj\lib\system_xmc4700.o @@ -1045,22 +1049,8 @@ Discarded input sections .text 0x00000000 0x0 ..\obj\lib\xmclib\src\xmc_can.o .data 0x00000000 0x0 ..\obj\lib\xmclib\src\xmc_can.o .bss 0x00000000 0x0 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_NODE_NominalBitTimeConfigure - 0x00000000 0x10c ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_AllocateMOtoNodeList - 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_Disable 0x00000000 0x1c ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_Enable - 0x00000000 0x28 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_SetBaudrateClockSource - 0x00000000 0x10 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_GetBaudrateClockSource - 0x00000000 0xc ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_GetBaudrateClockFrequency - 0x00000000 0x20 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_Init - 0x00000000 0x80 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_SetIdentifier 0x00000000 0x3c ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_GetIdentifier @@ -1069,14 +1059,8 @@ Discarded input sections 0x00000000 0x24 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_SetAcceptanceMask 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_UpdateData - 0x00000000 0x40 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_Config - 0x00000000 0x94 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_Transmit 0x00000000 0x24 ..\obj\lib\xmclib\src\xmc_can.o - .text.XMC_CAN_MO_ReceiveData - 0x00000000 0x3c ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_MO_Receive 0x00000000 0xc8 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_NODE_EnableEvent @@ -1093,13 +1077,6 @@ Discarded input sections 0x00000000 0x34 ..\obj\lib\xmclib\src\xmc_can.o .text.XMC_CAN_GATEWAY_InitSourceObject 0x00000000 0x5c ..\obj\lib\xmclib\src\xmc_can.o - .debug_info 0x00000000 0x13c4 ..\obj\lib\xmclib\src\xmc_can.o - .debug_abbrev 0x00000000 0x3b3 ..\obj\lib\xmclib\src\xmc_can.o - .debug_loc 0x00000000 0xc86 ..\obj\lib\xmclib\src\xmc_can.o - .debug_aranges - 0x00000000 0xd8 ..\obj\lib\xmclib\src\xmc_can.o - .debug_ranges 0x00000000 0xe0 ..\obj\lib\xmclib\src\xmc_can.o - .debug_macro 0x00000000 0x1c1 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x892 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x174 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x22 ..\obj\lib\xmclib\src\xmc_can.o @@ -1132,12 +1109,6 @@ Discarded input sections .debug_macro 0x00000000 0xa5 ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x70a ..\obj\lib\xmclib\src\xmc_can.o .debug_macro 0x00000000 0x20 ..\obj\lib\xmclib\src\xmc_can.o - .debug_line 0x00000000 0x69c ..\obj\lib\xmclib\src\xmc_can.o - .debug_str 0x00000000 0x79448 ..\obj\lib\xmclib\src\xmc_can.o - .comment 0x00000000 0x6f ..\obj\lib\xmclib\src\xmc_can.o - .debug_frame 0x00000000 0x20c ..\obj\lib\xmclib\src\xmc_can.o - .ARM.attributes - 0x00000000 0x39 ..\obj\lib\xmclib\src\xmc_can.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc_ccu4.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc_ccu4.o .group 0x00000000 0x8 ..\obj\lib\xmclib\src\xmc_ccu4.o @@ -4284,7 +4255,7 @@ Discarded input sections .data 0x00000000 0x0 ..\obj\main.o .bss 0x00000000 0x0 ..\obj\main.o .debug_macro 0x00000000 0x892 ..\obj\main.o - .debug_macro 0x00000000 0x65 ..\obj\main.o + .debug_macro 0x00000000 0x93 ..\obj\main.o .debug_macro 0x00000000 0x2d ..\obj\main.o .debug_macro 0x00000000 0x22 ..\obj\main.o .debug_macro 0x00000000 0x87 ..\obj\main.o @@ -4319,7 +4290,7 @@ Discarded input sections .text.TimerDeinit 0x00000000 0xc ..\obj\timer.o .debug_macro 0x00000000 0x892 ..\obj\timer.o - .debug_macro 0x00000000 0x65 ..\obj\timer.o + .debug_macro 0x00000000 0x93 ..\obj\timer.o .debug_macro 0x00000000 0x2d ..\obj\timer.o .debug_macro 0x00000000 0x22 ..\obj\timer.o .debug_macro 0x00000000 0x87 ..\obj\timer.o @@ -4379,7 +4350,7 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- 0x00000000 __HEAP_SIZE = 0x0 0x00000100 __STACK_SIZE = 0x100 -.text 0x08004000 0xd08 +.text 0x08004000 0x11c8 *(.isr_vector) .isr_vector 0x08004000 0x204 ..\obj\startup_xmc4700.o 0x08004000 __isr_vector @@ -4390,221 +4361,255 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- 0x08004260 _mainCRTStartup .text.BootComUartInit 0x080042d4 0xa4 ..\obj\boot.o + .text.BootComCanInit + 0x08004378 0x134 ..\obj\boot.o .text.UartReceiveByte - 0x08004378 0x24 ..\obj\boot.o + 0x080044ac 0x24 ..\obj\boot.o .text.BootComInit - 0x0800439c 0x8 ..\obj\boot.o - 0x0800439c BootComInit + 0x080044d0 0xc ..\obj\boot.o + 0x080044d0 BootComInit .text.BootActivate - 0x080043a4 0x24 ..\obj\boot.o - 0x080043a4 BootActivate + 0x080044dc 0x24 ..\obj\boot.o + 0x080044dc BootActivate .text.BootComUartCheckActivationRequest - 0x080043c8 0x6c ..\obj\boot.o + 0x08004500 0x6c ..\obj\boot.o + .text.BootComCanCheckActivationRequest + 0x0800456c 0x68 ..\obj\boot.o .text.BootComCheckActivationRequest - 0x08004434 0x8 ..\obj\boot.o - 0x08004434 BootComCheckActivationRequest - .text.LedInit 0x0800443c 0x1c ..\obj\led.o - 0x0800443c LedInit + 0x080045d4 0xc ..\obj\boot.o + 0x080045d4 BootComCheckActivationRequest + .text.LedInit 0x080045e0 0x1c ..\obj\led.o + 0x080045e0 LedInit .text.LedToggle - 0x08004458 0x48 ..\obj\led.o - 0x08004458 LedToggle - .text.delay 0x080044a0 0x1c ..\obj\lib\system_xmc4700.o + 0x080045fc 0x48 ..\obj\led.o + 0x080045fc LedToggle + .text.delay 0x08004644 0x1c ..\obj\lib\system_xmc4700.o .text.SystemCoreSetup - 0x080044bc 0x44 ..\obj\lib\system_xmc4700.o - 0x080044bc SystemCoreSetup + 0x08004660 0x44 ..\obj\lib\system_xmc4700.o + 0x08004660 SystemCoreSetup .text.OSCHP_GetFrequency - 0x08004500 0x8 ..\obj\lib\system_xmc4700.o - 0x08004500 OSCHP_GetFrequency + 0x080046a4 0x8 ..\obj\lib\system_xmc4700.o + 0x080046a4 OSCHP_GetFrequency .text.SystemCoreClockUpdate - 0x08004508 0x8c ..\obj\lib\system_xmc4700.o - 0x08004508 SystemCoreClockUpdate + 0x080046ac 0x8c ..\obj\lib\system_xmc4700.o + 0x080046ac SystemCoreClockUpdate .text.SystemCoreClockSetup - 0x08004594 0x198 ..\obj\lib\system_xmc4700.o - 0x08004594 SystemCoreClockSetup + 0x08004738 0x198 ..\obj\lib\system_xmc4700.o + 0x08004738 SystemCoreClockSetup .text.SystemInit - 0x0800472c 0x1c ..\obj\lib\system_xmc4700.o - 0x0800472c SystemInit + 0x080048d0 0x1c ..\obj\lib\system_xmc4700.o + 0x080048d0 SystemInit .text.XMC_GPIO_Init - 0x08004748 0x94 ..\obj\lib\xmclib\src\xmc4_gpio.o - 0x08004748 XMC_GPIO_Init + 0x080048ec 0x94 ..\obj\lib\xmclib\src\xmc4_gpio.o + 0x080048ec XMC_GPIO_Init .text.XMC_SCU_RESET_DeassertPeripheralReset - 0x080047dc 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o - 0x080047dc XMC_SCU_RESET_DeassertPeripheralReset + 0x08004980 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o + 0x08004980 XMC_SCU_RESET_DeassertPeripheralReset .text.XMC_SCU_CLOCK_GetPeripheralClockFrequency - 0x080047f4 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o - 0x080047f4 XMC_SCU_CLOCK_GetPeripheralClockFrequency + 0x08004998 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o + 0x08004998 XMC_SCU_CLOCK_GetPeripheralClockFrequency .text.XMC_SCU_CLOCK_UngatePeripheralClock - 0x0800480c 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o - 0x0800480c XMC_SCU_CLOCK_UngatePeripheralClock + 0x080049b0 0x18 ..\obj\lib\xmclib\src\xmc4_scu.o + 0x080049b0 XMC_SCU_CLOCK_UngatePeripheralClock + .text.XMC_CAN_NODE_NominalBitTimeConfigure + 0x080049c8 0x10c ..\obj\lib\xmclib\src\xmc_can.o + 0x080049c8 XMC_CAN_NODE_NominalBitTimeConfigure + .text.XMC_CAN_AllocateMOtoNodeList + 0x08004ad4 0x1c ..\obj\lib\xmclib\src\xmc_can.o + 0x08004ad4 XMC_CAN_AllocateMOtoNodeList + .text.XMC_CAN_Enable + 0x08004af0 0x28 ..\obj\lib\xmclib\src\xmc_can.o + 0x08004af0 XMC_CAN_Enable + .text.XMC_CAN_SetBaudrateClockSource + 0x08004b18 0x10 ..\obj\lib\xmclib\src\xmc_can.o + 0x08004b18 XMC_CAN_SetBaudrateClockSource + .text.XMC_CAN_GetBaudrateClockSource + 0x08004b28 0xc ..\obj\lib\xmclib\src\xmc_can.o + 0x08004b28 XMC_CAN_GetBaudrateClockSource + .text.XMC_CAN_GetBaudrateClockFrequency + 0x08004b34 0x20 ..\obj\lib\xmclib\src\xmc_can.o + 0x08004b34 XMC_CAN_GetBaudrateClockFrequency + .text.XMC_CAN_Init + 0x08004b54 0x80 ..\obj\lib\xmclib\src\xmc_can.o + 0x08004b54 XMC_CAN_Init + .text.XMC_CAN_MO_UpdateData + 0x08004bd4 0x40 ..\obj\lib\xmclib\src\xmc_can.o + 0x08004bd4 XMC_CAN_MO_UpdateData + .text.XMC_CAN_MO_Config + 0x08004c14 0x94 ..\obj\lib\xmclib\src\xmc_can.o + 0x08004c14 XMC_CAN_MO_Config + .text.XMC_CAN_MO_ReceiveData + 0x08004ca8 0x3c ..\obj\lib\xmclib\src\xmc_can.o + 0x08004ca8 XMC_CAN_MO_ReceiveData .text.XMC_GPIO_SetMode - 0x08004824 0x30 ..\obj\lib\xmclib\src\xmc_gpio.o - 0x08004824 XMC_GPIO_SetMode + 0x08004ce4 0x30 ..\obj\lib\xmclib\src\xmc_gpio.o + 0x08004ce4 XMC_GPIO_SetMode .text.XMC_UART_CH_Init - 0x08004854 0x6c ..\obj\lib\xmclib\src\xmc_uart.o - 0x08004854 XMC_UART_CH_Init + 0x08004d14 0x6c ..\obj\lib\xmclib\src\xmc_uart.o + 0x08004d14 XMC_UART_CH_Init .text.XMC_UART_CH_GetReceivedData - 0x080048c0 0x18 ..\obj\lib\xmclib\src\xmc_uart.o - 0x080048c0 XMC_UART_CH_GetReceivedData + 0x08004d80 0x18 ..\obj\lib\xmclib\src\xmc_uart.o + 0x08004d80 XMC_UART_CH_GetReceivedData .text.XMC_USIC_CH_SetBaudrate - 0x080048d8 0x8c ..\obj\lib\xmclib\src\xmc_usic.o - 0x080048d8 XMC_USIC_CH_SetBaudrate + 0x08004d98 0x8c ..\obj\lib\xmclib\src\xmc_usic.o + 0x08004d98 XMC_USIC_CH_SetBaudrate .text.XMC_USIC_CH_TXFIFO_Configure - 0x08004964 0x30 ..\obj\lib\xmclib\src\xmc_usic.o - 0x08004964 XMC_USIC_CH_TXFIFO_Configure + 0x08004e24 0x30 ..\obj\lib\xmclib\src\xmc_usic.o + 0x08004e24 XMC_USIC_CH_TXFIFO_Configure .text.XMC_USIC_CH_RXFIFO_Configure - 0x08004994 0x34 ..\obj\lib\xmclib\src\xmc_usic.o - 0x08004994 XMC_USIC_CH_RXFIFO_Configure + 0x08004e54 0x34 ..\obj\lib\xmclib\src\xmc_usic.o + 0x08004e54 XMC_USIC_CH_RXFIFO_Configure .text.XMC_USIC_Enable - 0x080049c8 0x5c ..\obj\lib\xmclib\src\xmc_usic.o - 0x080049c8 XMC_USIC_Enable + 0x08004e88 0x5c ..\obj\lib\xmclib\src\xmc_usic.o + 0x08004e88 XMC_USIC_Enable .text.XMC_USIC_CH_Enable - 0x08004a24 0x74 ..\obj\lib\xmclib\src\xmc_usic.o - 0x08004a24 XMC_USIC_CH_Enable - .text.Init 0x08004a98 0x10 ..\obj\main.o - .text.main 0x08004aa8 0x14 ..\obj\main.o - 0x08004aa8 main - .text 0x08004abc 0x134 ..\obj\startup_xmc4700.o - 0x08004abc Reset_Handler - 0x08004b0a NMI_Handler - 0x08004b0c HardFault_Handler - 0x08004b0e MemManage_Handler - 0x08004b10 BusFault_Handler - 0x08004b12 UsageFault_Handler - 0x08004b14 SVC_Handler - 0x08004b16 DebugMon_Handler - 0x08004b18 PendSV_Handler - 0x08004b1c Default_Handler - 0x08004b1e SCU_0_IRQHandler - 0x08004b20 ERU0_0_IRQHandler - 0x08004b22 ERU0_1_IRQHandler - 0x08004b24 ERU0_2_IRQHandler - 0x08004b26 ERU0_3_IRQHandler - 0x08004b28 ERU1_0_IRQHandler - 0x08004b2a ERU1_1_IRQHandler - 0x08004b2c ERU1_2_IRQHandler - 0x08004b2e ERU1_3_IRQHandler - 0x08004b30 PMU0_0_IRQHandler - 0x08004b32 VADC0_C0_0_IRQHandler - 0x08004b34 VADC0_C0_1_IRQHandler - 0x08004b36 VADC0_C0_2_IRQHandler - 0x08004b38 VADC0_C0_3_IRQHandler - 0x08004b3a VADC0_G0_0_IRQHandler - 0x08004b3c VADC0_G0_1_IRQHandler - 0x08004b3e VADC0_G0_2_IRQHandler - 0x08004b40 VADC0_G0_3_IRQHandler - 0x08004b42 VADC0_G1_0_IRQHandler - 0x08004b44 VADC0_G1_1_IRQHandler - 0x08004b46 VADC0_G1_2_IRQHandler - 0x08004b48 VADC0_G1_3_IRQHandler - 0x08004b4a VADC0_G2_0_IRQHandler - 0x08004b4c VADC0_G2_1_IRQHandler - 0x08004b4e VADC0_G2_2_IRQHandler - 0x08004b50 VADC0_G2_3_IRQHandler - 0x08004b52 VADC0_G3_0_IRQHandler - 0x08004b54 VADC0_G3_1_IRQHandler - 0x08004b56 VADC0_G3_2_IRQHandler - 0x08004b58 VADC0_G3_3_IRQHandler - 0x08004b5a DSD0_0_IRQHandler - 0x08004b5c DSD0_1_IRQHandler - 0x08004b5e DSD0_2_IRQHandler - 0x08004b60 DSD0_3_IRQHandler - 0x08004b62 DSD0_4_IRQHandler - 0x08004b64 DSD0_5_IRQHandler - 0x08004b66 DSD0_6_IRQHandler - 0x08004b68 DSD0_7_IRQHandler - 0x08004b6a DAC0_0_IRQHandler - 0x08004b6c DAC0_1_IRQHandler - 0x08004b6e CCU40_0_IRQHandler - 0x08004b70 CCU40_1_IRQHandler - 0x08004b72 CCU40_2_IRQHandler - 0x08004b74 CCU40_3_IRQHandler - 0x08004b76 CCU41_0_IRQHandler - 0x08004b78 CCU41_1_IRQHandler - 0x08004b7a CCU41_2_IRQHandler - 0x08004b7c CCU41_3_IRQHandler - 0x08004b7e CCU42_0_IRQHandler - 0x08004b80 CCU42_1_IRQHandler - 0x08004b82 CCU42_2_IRQHandler - 0x08004b84 CCU42_3_IRQHandler - 0x08004b86 CCU43_0_IRQHandler - 0x08004b88 CCU43_1_IRQHandler - 0x08004b8a CCU43_2_IRQHandler - 0x08004b8c CCU43_3_IRQHandler - 0x08004b8e CCU80_0_IRQHandler - 0x08004b90 CCU80_1_IRQHandler - 0x08004b92 CCU80_2_IRQHandler - 0x08004b94 CCU80_3_IRQHandler - 0x08004b96 CCU81_0_IRQHandler - 0x08004b98 CCU81_1_IRQHandler - 0x08004b9a CCU81_2_IRQHandler - 0x08004b9c CCU81_3_IRQHandler - 0x08004b9e POSIF0_0_IRQHandler - 0x08004ba0 POSIF0_1_IRQHandler - 0x08004ba2 POSIF1_0_IRQHandler - 0x08004ba4 POSIF1_1_IRQHandler - 0x08004ba6 CAN0_0_IRQHandler - 0x08004ba8 CAN0_1_IRQHandler - 0x08004baa CAN0_2_IRQHandler - 0x08004bac CAN0_3_IRQHandler - 0x08004bae CAN0_4_IRQHandler - 0x08004bb0 CAN0_5_IRQHandler - 0x08004bb2 CAN0_6_IRQHandler - 0x08004bb4 CAN0_7_IRQHandler - 0x08004bb6 USIC0_0_IRQHandler - 0x08004bb8 USIC0_1_IRQHandler - 0x08004bba USIC0_2_IRQHandler - 0x08004bbc USIC0_3_IRQHandler - 0x08004bbe USIC0_4_IRQHandler - 0x08004bc0 USIC0_5_IRQHandler - 0x08004bc2 USIC1_0_IRQHandler - 0x08004bc4 USIC1_1_IRQHandler - 0x08004bc6 USIC1_2_IRQHandler - 0x08004bc8 USIC1_3_IRQHandler - 0x08004bca USIC1_4_IRQHandler - 0x08004bcc USIC1_5_IRQHandler - 0x08004bce USIC2_0_IRQHandler - 0x08004bd0 USIC2_1_IRQHandler - 0x08004bd2 USIC2_2_IRQHandler - 0x08004bd4 USIC2_3_IRQHandler - 0x08004bd6 USIC2_4_IRQHandler - 0x08004bd8 USIC2_5_IRQHandler - 0x08004bda LEDTS0_0_IRQHandler - 0x08004bdc FCE0_0_IRQHandler - 0x08004bde GPDMA0_0_IRQHandler - 0x08004be0 SDMMC0_0_IRQHandler - 0x08004be2 USB0_0_IRQHandler - 0x08004be4 ETH0_0_IRQHandler - 0x08004be6 GPDMA1_0_IRQHandler + 0x08004ee4 0x74 ..\obj\lib\xmclib\src\xmc_usic.o + 0x08004ee4 XMC_USIC_CH_Enable + .text.Init 0x08004f58 0x10 ..\obj\main.o + .text.main 0x08004f68 0x14 ..\obj\main.o + 0x08004f68 main + .text 0x08004f7c 0x134 ..\obj\startup_xmc4700.o + 0x08004f7c Reset_Handler + 0x08004fca NMI_Handler + 0x08004fcc HardFault_Handler + 0x08004fce MemManage_Handler + 0x08004fd0 BusFault_Handler + 0x08004fd2 UsageFault_Handler + 0x08004fd4 SVC_Handler + 0x08004fd6 DebugMon_Handler + 0x08004fd8 PendSV_Handler + 0x08004fdc Default_Handler + 0x08004fde SCU_0_IRQHandler + 0x08004fe0 ERU0_0_IRQHandler + 0x08004fe2 ERU0_1_IRQHandler + 0x08004fe4 ERU0_2_IRQHandler + 0x08004fe6 ERU0_3_IRQHandler + 0x08004fe8 ERU1_0_IRQHandler + 0x08004fea ERU1_1_IRQHandler + 0x08004fec ERU1_2_IRQHandler + 0x08004fee ERU1_3_IRQHandler + 0x08004ff0 PMU0_0_IRQHandler + 0x08004ff2 VADC0_C0_0_IRQHandler + 0x08004ff4 VADC0_C0_1_IRQHandler + 0x08004ff6 VADC0_C0_2_IRQHandler + 0x08004ff8 VADC0_C0_3_IRQHandler + 0x08004ffa VADC0_G0_0_IRQHandler + 0x08004ffc VADC0_G0_1_IRQHandler + 0x08004ffe VADC0_G0_2_IRQHandler + 0x08005000 VADC0_G0_3_IRQHandler + 0x08005002 VADC0_G1_0_IRQHandler + 0x08005004 VADC0_G1_1_IRQHandler + 0x08005006 VADC0_G1_2_IRQHandler + 0x08005008 VADC0_G1_3_IRQHandler + 0x0800500a VADC0_G2_0_IRQHandler + 0x0800500c VADC0_G2_1_IRQHandler + 0x0800500e VADC0_G2_2_IRQHandler + 0x08005010 VADC0_G2_3_IRQHandler + 0x08005012 VADC0_G3_0_IRQHandler + 0x08005014 VADC0_G3_1_IRQHandler + 0x08005016 VADC0_G3_2_IRQHandler + 0x08005018 VADC0_G3_3_IRQHandler + 0x0800501a DSD0_0_IRQHandler + 0x0800501c DSD0_1_IRQHandler + 0x0800501e DSD0_2_IRQHandler + 0x08005020 DSD0_3_IRQHandler + 0x08005022 DSD0_4_IRQHandler + 0x08005024 DSD0_5_IRQHandler + 0x08005026 DSD0_6_IRQHandler + 0x08005028 DSD0_7_IRQHandler + 0x0800502a DAC0_0_IRQHandler + 0x0800502c DAC0_1_IRQHandler + 0x0800502e CCU40_0_IRQHandler + 0x08005030 CCU40_1_IRQHandler + 0x08005032 CCU40_2_IRQHandler + 0x08005034 CCU40_3_IRQHandler + 0x08005036 CCU41_0_IRQHandler + 0x08005038 CCU41_1_IRQHandler + 0x0800503a CCU41_2_IRQHandler + 0x0800503c CCU41_3_IRQHandler + 0x0800503e CCU42_0_IRQHandler + 0x08005040 CCU42_1_IRQHandler + 0x08005042 CCU42_2_IRQHandler + 0x08005044 CCU42_3_IRQHandler + 0x08005046 CCU43_0_IRQHandler + 0x08005048 CCU43_1_IRQHandler + 0x0800504a CCU43_2_IRQHandler + 0x0800504c CCU43_3_IRQHandler + 0x0800504e CCU80_0_IRQHandler + 0x08005050 CCU80_1_IRQHandler + 0x08005052 CCU80_2_IRQHandler + 0x08005054 CCU80_3_IRQHandler + 0x08005056 CCU81_0_IRQHandler + 0x08005058 CCU81_1_IRQHandler + 0x0800505a CCU81_2_IRQHandler + 0x0800505c CCU81_3_IRQHandler + 0x0800505e POSIF0_0_IRQHandler + 0x08005060 POSIF0_1_IRQHandler + 0x08005062 POSIF1_0_IRQHandler + 0x08005064 POSIF1_1_IRQHandler + 0x08005066 CAN0_0_IRQHandler + 0x08005068 CAN0_1_IRQHandler + 0x0800506a CAN0_2_IRQHandler + 0x0800506c CAN0_3_IRQHandler + 0x0800506e CAN0_4_IRQHandler + 0x08005070 CAN0_5_IRQHandler + 0x08005072 CAN0_6_IRQHandler + 0x08005074 CAN0_7_IRQHandler + 0x08005076 USIC0_0_IRQHandler + 0x08005078 USIC0_1_IRQHandler + 0x0800507a USIC0_2_IRQHandler + 0x0800507c USIC0_3_IRQHandler + 0x0800507e USIC0_4_IRQHandler + 0x08005080 USIC0_5_IRQHandler + 0x08005082 USIC1_0_IRQHandler + 0x08005084 USIC1_1_IRQHandler + 0x08005086 USIC1_2_IRQHandler + 0x08005088 USIC1_3_IRQHandler + 0x0800508a USIC1_4_IRQHandler + 0x0800508c USIC1_5_IRQHandler + 0x0800508e USIC2_0_IRQHandler + 0x08005090 USIC2_1_IRQHandler + 0x08005092 USIC2_2_IRQHandler + 0x08005094 USIC2_3_IRQHandler + 0x08005096 USIC2_4_IRQHandler + 0x08005098 USIC2_5_IRQHandler + 0x0800509a LEDTS0_0_IRQHandler + 0x0800509c FCE0_0_IRQHandler + 0x0800509e GPDMA0_0_IRQHandler + 0x080050a0 SDMMC0_0_IRQHandler + 0x080050a2 USB0_0_IRQHandler + 0x080050a4 ETH0_0_IRQHandler + 0x080050a6 GPDMA1_0_IRQHandler .text.TimerSet - 0x08004bf0 0xc ..\obj\timer.o - 0x08004bf0 TimerSet + 0x080050b0 0xc ..\obj\timer.o + 0x080050b0 TimerSet .text.TimerInit - 0x08004bfc 0x44 ..\obj\timer.o - 0x08004bfc TimerInit + 0x080050bc 0x44 ..\obj\timer.o + 0x080050bc TimerInit .text.TimerGet - 0x08004c40 0xc ..\obj\timer.o - 0x08004c40 TimerGet + 0x08005100 0xc ..\obj\timer.o + 0x08005100 TimerGet .text.SysTick_Handler - 0x08004c4c 0x10 ..\obj\timer.o - 0x08004c4c SysTick_Handler - .text.exit 0x08004c5c 0x28 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) - 0x08004c5c exit + 0x0800510c 0x10 ..\obj\timer.o + 0x0800510c SysTick_Handler + .text.exit 0x0800511c 0x28 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) + 0x0800511c exit .text.__libc_init_array - 0x08004c84 0x4c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) - 0x08004c84 __libc_init_array - .text.memset 0x08004cd0 0x10 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) - 0x08004cd0 memset - .text._exit 0x08004ce0 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) - 0x08004ce0 _exit + 0x08005144 0x4c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) + 0x08005144 __libc_init_array + .text.memset 0x08005190 0x10 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) + 0x08005190 memset + .text._exit 0x080051a0 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) + 0x080051a0 _exit *(.init) - *fill* 0x08004ce2 0x2 - .init 0x08004ce4 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o - 0x08004ce4 _init - .init 0x08004ce8 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o + *fill* 0x080051a2 0x2 + .init 0x080051a4 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o + 0x080051a4 _init + .init 0x080051a8 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o *(.fini) - .fini 0x08004cf0 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o - 0x08004cf0 _fini - .fini 0x08004cf4 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o + .fini 0x080051b0 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crti.o + 0x080051b0 _fini + .fini 0x080051b4 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors) @@ -4617,44 +4622,44 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- *(.dtors) *(.rodata*) .rodata.str1.1 - 0x08004cfc 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) - *fill* 0x08004cfe 0x2 + 0x080051bc 0x2 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) + *fill* 0x080051be 0x2 .rodata._global_impure_ptr - 0x08004d00 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) - 0x08004d00 _global_impure_ptr + 0x080051c0 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) + 0x080051c0 _global_impure_ptr *(.eh_frame*) - .eh_frame 0x08004d04 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o - .eh_frame 0x08004d04 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o + .eh_frame 0x080051c4 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o + .eh_frame 0x080051c4 0x4 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o -.glue_7 0x08004d08 0x0 - .glue_7 0x08004d08 0x0 linker stubs +.glue_7 0x080051c8 0x0 + .glue_7 0x080051c8 0x0 linker stubs -.glue_7t 0x08004d08 0x0 - .glue_7t 0x08004d08 0x0 linker stubs +.glue_7t 0x080051c8 0x0 + .glue_7t 0x080051c8 0x0 linker stubs -.vfp11_veneer 0x08004d08 0x0 - .vfp11_veneer 0x08004d08 0x0 linker stubs +.vfp11_veneer 0x080051c8 0x0 + .vfp11_veneer 0x080051c8 0x0 linker stubs -.v4_bx 0x08004d08 0x0 - .v4_bx 0x08004d08 0x0 linker stubs +.v4_bx 0x080051c8 0x0 + .v4_bx 0x080051c8 0x0 linker stubs -.iplt 0x08004d08 0x0 - .iplt 0x08004d08 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o +.iplt 0x080051c8 0x0 + .iplt 0x080051c8 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o .ARM.extab *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x08004d08 __exidx_start = . + 0x080051c8 __exidx_start = . -.ARM.exidx 0x08004d08 0x8 +.ARM.exidx 0x080051c8 0x8 *(.ARM.exidx* .gnu.linkonce.armexidx.*) - .ARM.exidx 0x08004d08 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o - 0x08004d10 __exidx_end = . - 0x08004d10 __etext = . + .ARM.exidx 0x080051c8 0x8 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o + 0x080051d0 __exidx_end = . + 0x080051d0 __etext = . -.rel.dyn 0x08004d10 0x0 - .rel.iplt 0x08004d10 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o +.rel.dyn 0x080051d0 0x0 + .rel.iplt 0x080051d0 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o -.data 0x20000000 0x68 load address 0x08004d10 +.data 0x20000000 0x68 load address 0x080051d0 0x20000000 __data_start__ = . *(vtable) *(.data*) @@ -4679,48 +4684,50 @@ LOAD c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none- 0x20000068 . = ALIGN (0x4) 0x20000068 __data_end__ = . -.jcr 0x20000068 0x0 load address 0x08004d78 +.jcr 0x20000068 0x0 load address 0x08005238 .jcr 0x20000068 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o -.igot.plt 0x20000068 0x0 load address 0x08004d78 +.igot.plt 0x20000068 0x0 load address 0x08005238 .igot.plt 0x20000068 0x0 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o -.no_init 0x20000068 0x14 load address 0x08004d78 +.no_init 0x20000068 0x14 load address 0x08005238 .no_init 0x20000068 0x14 ..\obj\lib\system_xmc4700.o 0x20000068 SystemCoreClock 0x2000006c g_chipid -.bss 0x2000007c 0x6c load address 0x08004d8c - 0x2000007c __bss_start__ = . +.bss 0x20000080 0x8c load address 0x08005250 + 0x20000080 __bss_start__ = . *(.bss*) - .bss 0x2000007c 0x1c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o - .bss.xcpCtoReqPacket.7706 - 0x20000098 0x41 ..\obj\boot.o - .bss.xcpCtoRxLength.7707 - 0x200000d9 0x1 ..\obj\boot.o - .bss.xcpCtoRxInProgress.7708 - 0x200000da 0x1 ..\obj\boot.o - *fill* 0x200000db 0x1 + .bss 0x20000080 0x1c c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtbegin.o + .bss.xcpCtoReqPacket.8793 + 0x2000009c 0x41 ..\obj\boot.o + .bss.xcpCtoRxLength.8794 + 0x200000dd 0x1 ..\obj\boot.o + .bss.xcpCtoRxInProgress.8795 + 0x200000de 0x1 ..\obj\boot.o + *fill* 0x200000df 0x1 + .bss.receiveMsgObj + 0x200000e0 0x20 ..\obj\boot.o .bss.timer_counter_last.7074 - 0x200000dc 0x4 ..\obj\led.o + 0x20000100 0x4 ..\obj\led.o .bss.led_toggle_state.7073 - 0x200000e0 0x1 ..\obj\led.o - *fill* 0x200000e1 0x3 + 0x20000104 0x1 ..\obj\led.o + *fill* 0x20000105 0x3 .bss.millisecond_counter - 0x200000e4 0x4 ..\obj\timer.o + 0x20000108 0x4 ..\obj\timer.o *(COMMON) - 0x200000e8 __bss_end__ = . + 0x2000010c __bss_end__ = . -.heap 0x200000e8 0x0 - 0x200000e8 __end__ = . - 0x200000e8 end = __end__ +.heap 0x20000110 0x0 + 0x20000110 __end__ = . + 0x20000110 end = __end__ *(.heap*) - .heap 0x200000e8 0x0 ..\obj\startup_xmc4700.o - 0x200000e8 __HeapLimit = . + .heap 0x20000110 0x0 ..\obj\startup_xmc4700.o + 0x20000110 __HeapLimit = . -.stack_dummy 0x200000e8 0x100 +.stack_dummy 0x20000110 0x100 *(.stack) - .stack 0x200000e8 0x100 ..\obj\startup_xmc4700.o + .stack 0x20000110 0x100 ..\obj\startup_xmc4700.o 0x20020000 __StackTop = (ORIGIN (RAM) + LENGTH (RAM)) 0x2001ff00 __StackLimit = (__StackTop - SIZEOF (.stack_dummy)) 0x20020000 PROVIDE (__stack, __StackTop) @@ -4801,31 +4808,33 @@ OUTPUT(..\bin\demoprog_xmc4700.elf elf32-littlearm) .ARM.attributes 0x0000015a 0x39 ..\obj\lib\xmclib\src\xmc4_scu.o .ARM.attributes - 0x00000193 0x39 ..\obj\lib\xmclib\src\xmc_gpio.o + 0x00000193 0x39 ..\obj\lib\xmclib\src\xmc_can.o .ARM.attributes - 0x000001cc 0x39 ..\obj\lib\xmclib\src\xmc_uart.o + 0x000001cc 0x39 ..\obj\lib\xmclib\src\xmc_gpio.o .ARM.attributes - 0x00000205 0x39 ..\obj\lib\xmclib\src\xmc_usic.o + 0x00000205 0x39 ..\obj\lib\xmclib\src\xmc_uart.o .ARM.attributes - 0x0000023e 0x39 ..\obj\main.o + 0x0000023e 0x39 ..\obj\lib\xmclib\src\xmc_usic.o .ARM.attributes - 0x00000277 0x1f ..\obj\startup_xmc4700.o + 0x00000277 0x39 ..\obj\main.o .ARM.attributes - 0x00000296 0x39 ..\obj\timer.o + 0x000002b0 0x1f ..\obj\startup_xmc4700.o .ARM.attributes - 0x000002cf 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) + 0x000002cf 0x39 ..\obj\timer.o .ARM.attributes - 0x00000303 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) + 0x00000308 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-exit.o) .ARM.attributes - 0x00000337 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) + 0x0000033c 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-impure.o) .ARM.attributes - 0x0000036b 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) + 0x00000370 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-init.o) .ARM.attributes - 0x0000039f 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) + 0x000003a4 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_n.a(lib_a-memset.o) .ARM.attributes - 0x000003d3 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o + 0x000003d8 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys_s.a(_exit.o) .ARM.attributes - 0x00000407 0x22 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o + 0x0000040c 0x34 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtend.o + .ARM.attributes + 0x00000440 0x22 c:/program files (x86)/embitz/1.00/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/5.4.1/armv7e-m/fpu/crtn.o .comment 0x00000000 0x6e .comment 0x00000000 0x6e ..\obj\boot.o @@ -4834,183 +4843,197 @@ OUTPUT(..\bin\demoprog_xmc4700.elf elf32-littlearm) .comment 0x0000006e 0x6f ..\obj\lib\system_xmc4700.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc4_gpio.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc4_scu.o + .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_can.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_gpio.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_uart.o .comment 0x0000006e 0x6f ..\obj\lib\xmclib\src\xmc_usic.o .comment 0x0000006e 0x6f ..\obj\main.o .comment 0x0000006e 0x6f ..\obj\timer.o -.debug_info 0x00000000 0x64cf - .debug_info 0x00000000 0xc7c ..\obj\boot.o - .debug_info 0x00000c7c 0x449 ..\obj\led.o - .debug_info 0x000010c5 0x943 ..\obj\lib\system_xmc4700.o - .debug_info 0x00001a08 0x412 ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_info 0x00001e1a 0x2311 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_info 0x0000412b 0x38e ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_info 0x000044b9 0x8fd ..\obj\lib\xmclib\src\xmc_uart.o - .debug_info 0x00004db6 0xd78 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_info 0x00005b2e 0x14f ..\obj\main.o - .debug_info 0x00005c7d 0x8d ..\obj\startup_xmc4700.o - .debug_info 0x00005d0a 0x7c5 ..\obj\timer.o +.debug_info 0x00000000 0x833c + .debug_info 0x00000000 0x1725 ..\obj\boot.o + .debug_info 0x00001725 0x449 ..\obj\led.o + .debug_info 0x00001b6e 0x943 ..\obj\lib\system_xmc4700.o + .debug_info 0x000024b1 0x412 ..\obj\lib\xmclib\src\xmc4_gpio.o + .debug_info 0x000028c3 0x2311 ..\obj\lib\xmclib\src\xmc4_scu.o + .debug_info 0x00004bd4 0x13c4 ..\obj\lib\xmclib\src\xmc_can.o + .debug_info 0x00005f98 0x38e ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_info 0x00006326 0x8fd ..\obj\lib\xmclib\src\xmc_uart.o + .debug_info 0x00006c23 0xd78 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_info 0x0000799b 0x14f ..\obj\main.o + .debug_info 0x00007aea 0x8d ..\obj\startup_xmc4700.o + .debug_info 0x00007b77 0x7c5 ..\obj\timer.o -.debug_abbrev 0x00000000 0x12f6 - .debug_abbrev 0x00000000 0x2e4 ..\obj\boot.o - .debug_abbrev 0x000002e4 0x181 ..\obj\led.o - .debug_abbrev 0x00000465 0x1c1 ..\obj\lib\system_xmc4700.o - .debug_abbrev 0x00000626 0x136 ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_abbrev 0x0000075c 0x301 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_abbrev 0x00000a5d 0x11e ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_abbrev 0x00000b7b 0x265 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_abbrev 0x00000de0 0x279 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_abbrev 0x00001059 0xa5 ..\obj\main.o - .debug_abbrev 0x000010fe 0x14 ..\obj\startup_xmc4700.o - .debug_abbrev 0x00001112 0x1e4 ..\obj\timer.o +.debug_abbrev 0x00000000 0x1742 + .debug_abbrev 0x00000000 0x37d ..\obj\boot.o + .debug_abbrev 0x0000037d 0x181 ..\obj\led.o + .debug_abbrev 0x000004fe 0x1c1 ..\obj\lib\system_xmc4700.o + .debug_abbrev 0x000006bf 0x136 ..\obj\lib\xmclib\src\xmc4_gpio.o + .debug_abbrev 0x000007f5 0x301 ..\obj\lib\xmclib\src\xmc4_scu.o + .debug_abbrev 0x00000af6 0x3b3 ..\obj\lib\xmclib\src\xmc_can.o + .debug_abbrev 0x00000ea9 0x11e ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_abbrev 0x00000fc7 0x265 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_abbrev 0x0000122c 0x279 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_abbrev 0x000014a5 0xa5 ..\obj\main.o + .debug_abbrev 0x0000154a 0x14 ..\obj\startup_xmc4700.o + .debug_abbrev 0x0000155e 0x1e4 ..\obj\timer.o -.debug_loc 0x00000000 0x1930 - .debug_loc 0x00000000 0xa7 ..\obj\boot.o - .debug_loc 0x000000a7 0xc4 ..\obj\led.o - .debug_loc 0x0000016b 0xa8 ..\obj\lib\system_xmc4700.o - .debug_loc 0x00000213 0x9d ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_loc 0x000002b0 0xdf8 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_loc 0x000010a8 0x84 ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_loc 0x0000112c 0x277 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_loc 0x000013a3 0x533 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_loc 0x000018d6 0x5a ..\obj\timer.o +.debug_loc 0x00000000 0x27a4 + .debug_loc 0x00000000 0x295 ..\obj\boot.o + .debug_loc 0x00000295 0xc4 ..\obj\led.o + .debug_loc 0x00000359 0xa8 ..\obj\lib\system_xmc4700.o + .debug_loc 0x00000401 0x9d ..\obj\lib\xmclib\src\xmc4_gpio.o + .debug_loc 0x0000049e 0xdf8 ..\obj\lib\xmclib\src\xmc4_scu.o + .debug_loc 0x00001296 0xc86 ..\obj\lib\xmclib\src\xmc_can.o + .debug_loc 0x00001f1c 0x84 ..\obj\lib\xmclib\src\xmc_gpio.o + .debug_loc 0x00001fa0 0x277 ..\obj\lib\xmclib\src\xmc_uart.o + .debug_loc 0x00002217 0x533 ..\obj\lib\xmclib\src\xmc_usic.o + .debug_loc 0x0000274a 0x5a ..\obj\timer.o -.debug_aranges 0x00000000 0x610 +.debug_aranges 0x00000000 0x6f8 .debug_aranges - 0x00000000 0x48 ..\obj\boot.o + 0x00000000 0x58 ..\obj\boot.o .debug_aranges - 0x00000048 0x28 ..\obj\led.o + 0x00000058 0x28 ..\obj\led.o .debug_aranges - 0x00000070 0x48 ..\obj\lib\system_xmc4700.o + 0x00000080 0x48 ..\obj\lib\system_xmc4700.o .debug_aranges - 0x000000b8 0x28 ..\obj\lib\xmclib\src\xmc4_gpio.o + 0x000000c8 0x28 ..\obj\lib\xmclib\src\xmc4_gpio.o .debug_aranges - 0x000000e0 0x3b0 ..\obj\lib\xmclib\src\xmc4_scu.o + 0x000000f0 0x3b0 ..\obj\lib\xmclib\src\xmc4_scu.o .debug_aranges - 0x00000490 0x28 ..\obj\lib\xmclib\src\xmc_gpio.o + 0x000004a0 0xd8 ..\obj\lib\xmclib\src\xmc_can.o .debug_aranges - 0x000004b8 0x50 ..\obj\lib\xmclib\src\xmc_uart.o + 0x00000578 0x28 ..\obj\lib\xmclib\src\xmc_gpio.o .debug_aranges - 0x00000508 0x80 ..\obj\lib\xmclib\src\xmc_usic.o + 0x000005a0 0x50 ..\obj\lib\xmclib\src\xmc_uart.o .debug_aranges - 0x00000588 0x28 ..\obj\main.o + 0x000005f0 0x80 ..\obj\lib\xmclib\src\xmc_usic.o .debug_aranges - 0x000005b0 0x20 ..\obj\startup_xmc4700.o + 0x00000670 0x28 ..\obj\main.o .debug_aranges - 0x000005d0 0x40 ..\obj\timer.o + 0x00000698 0x20 ..\obj\startup_xmc4700.o + .debug_aranges + 0x000006b8 0x40 ..\obj\timer.o -.debug_ranges 0x00000000 0x550 - .debug_ranges 0x00000000 0x38 ..\obj\boot.o - .debug_ranges 0x00000038 0x18 ..\obj\led.o - .debug_ranges 0x00000050 0x38 ..\obj\lib\system_xmc4700.o - .debug_ranges 0x00000088 0x18 ..\obj\lib\xmclib\src\xmc4_gpio.o - .debug_ranges 0x000000a0 0x3a0 ..\obj\lib\xmclib\src\xmc4_scu.o - .debug_ranges 0x00000440 0x18 ..\obj\lib\xmclib\src\xmc_gpio.o - .debug_ranges 0x00000458 0x40 ..\obj\lib\xmclib\src\xmc_uart.o - .debug_ranges 0x00000498 0x70 ..\obj\lib\xmclib\src\xmc_usic.o - .debug_ranges 0x00000508 0x18 ..\obj\main.o - .debug_ranges 0x00000520 0x30 ..\obj\timer.o +.debug_ranges 0x00000000 0x640 + .debug_ranges 0x00000000 0x48 ..\obj\boot.o + .debug_ranges 0x00000048 0x18 ..\obj\led.o + .debug_ranges 0x00000060 0x38 ..\obj\lib\system_xmc4700.o + .debug_ranges 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+S31508005180600000206000002064000020600000200D +S3150800519002440346934202D003F8011BFAE770471C +S315080051A0FEE70000F8B500BFF8BC08BC9E4670478D +S315080051B0F8B500BFF8BC08BC9E467047430000001F +S30D080051C00000002000000000B9 +S30D080051C898F0FF7F01000000CA +S315080051D000000000000000000000000000000000C1 +S315080051E000000000000000000000000000000000B1 +S315080051F0BC5100080000000000000000000000008C +S315080052000000000000000000000000000000000090 +S315080052100000000000000000000000000000000080 +S315080052200000000000000000000000000000000070 +S30D080052302942000805420008A6 +S315080052380000000000000000000000000000000058 +S309080052480000000054 S70508004000B2 diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/boot.c b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/boot.c index b835c7ff..32edb6f9 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/boot.c +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/boot.c @@ -30,8 +30,9 @@ * Include files ****************************************************************************************/ #include "header.h" /* generic header */ -#include "xmc_uart.h" /* UART driver header */ #include "xmc_gpio.h" /* GPIO module */ +#include "xmc_uart.h" /* UART driver header */ +#include "xmc_can.h" /* CAN driver header */ /**************************************************************************************** @@ -41,6 +42,10 @@ static void BootComUartInit(void); static void BootComUartCheckActivationRequest(void); #endif +#if (BOOT_COM_CAN_ENABLE > 0) +static void BootComCanInit(void); +static void BootComCanCheckActivationRequest(void); +#endif /************************************************************************************//** ** \brief Initializes the communication interface. @@ -52,6 +57,9 @@ void BootComInit(void) #if (BOOT_COM_UART_ENABLE > 0) BootComUartInit(); #endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanInit(); +#endif } /*** end of BootComInit ***/ @@ -66,6 +74,9 @@ void BootComCheckActivationRequest(void) #if (BOOT_COM_UART_ENABLE > 0) BootComUartCheckActivationRequest(); #endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanCheckActivationRequest(); +#endif } /*** end of BootComCheckActivationRequest ***/ @@ -206,4 +217,141 @@ static unsigned char UartReceiveByte(unsigned char *data) #endif /* BOOT_COM_UART_ENABLE > 0 */ +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Receive message object data structure. */ +static XMC_CAN_MO_t receiveMsgObj; + + +/************************************************************************************//** +** \brief Initializes the CAN communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComCanInit(void) +{ + XMC_GPIO_CONFIG_t rx_can_config; + XMC_GPIO_CONFIG_t tx_can_config; + unsigned char byteIdx; + unsigned long canModuleFreqHz; + XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t baud; + + /* decide on fCAN frequency. it should be in the 5-120MHz range. according to the + * datasheet, it must be at least 12MHz if 1 node (channel) is used with up to + * 16 message objects. This is sufficient for this CAN driver. + */ + canModuleFreqHz = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + /* increase if too low */ + while (canModuleFreqHz < 12000000) + { + canModuleFreqHz *= 2; + } + /* decrease if too high */ + while (canModuleFreqHz > 120000000) + { + canModuleFreqHz /= 2; + } + + /* configure CAN module*/ + XMC_CAN_Init(CAN, XMC_CAN_CANCLKSRC_FPERI, canModuleFreqHz); + + /* configure CAN node baudrate */ + baud.can_frequency = canModuleFreqHz; + baud.baudrate = BOOT_COM_CAN_BAUDRATE; + baud.sample_point = 8000; + baud.sjw = 1, + XMC_CAN_NODE_NominalBitTimeConfigure(CAN_NODE1, &baud); + + /* set CCE and INIT bit NCR for node configuration */ + XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE1); + XMC_CAN_NODE_SetInitBit(CAN_NODE1); + + /* configure the receive message object */ + receiveMsgObj.can_mo_ptr = CAN_MO1; + receiveMsgObj.can_priority = XMC_CAN_ARBITRATION_MODE_IDE_DIR_BASED_PRIO_2; + receiveMsgObj.can_identifier = BOOT_COM_CAN_RX_MSG_ID; + receiveMsgObj.can_id_mask= BOOT_COM_CAN_RX_MSG_ID; + receiveMsgObj.can_id_mode = XMC_CAN_FRAME_TYPE_STANDARD_11BITS; + receiveMsgObj.can_ide_mask = 1; + receiveMsgObj.can_data_length = BOOT_COM_CAN_RX_MAX_DATA; + for (byteIdx=0; byteIdx 0 */ + + /*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/xmc4500.svd b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/xmc4700.svd similarity index 68% rename from Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/xmc4500.svd rename to Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/xmc4700.svd index 6a7370da..5411b7ad 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/xmc4500.svd +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/cfg/xmc4700.svd @@ -1,95720 +1,123178 @@ - - - - - - - - - - - Infineon - XMC4500 - 1.2.0 (Reference Manual v1.2) - SVD file - - CM4 - r2p0 - little - true - true - 6 - false - - 8 - 32 - - - PPB - Cortex-M4 Private Peripheral Block - 0xE000E000 - - 0x0 - 0x1000 - registers - - - - ACTLR - Auxiliary Control Register - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - DISMCYCINT - Disable load/store multiple - 0 - 0 - read-write - - - DISDEFWBUF - Disable write buffer - 1 - 1 - read-write - - - DISFOLD - Disable IT folding - 2 - 2 - read-write - - - DISFPCA - Disable FPCA update - 8 - 8 - read-write - - - DISOOFP - Disable out of order FP execution - 9 - 9 - read-write - - - - - SYST_CSR - SysTick Control and Status Register - 0x010 - 32 - 0x00000004 - 0xFFFFFFFF - - - ENABLE - Enable - 0 - 0 - read-write - - - value1 - counter disabled - 0b0 - - - value2 - counter enabled. - 0b1 - - - - - TICKINT - Tick Interrupt Enable - 1 - 1 - read-write - - - value1 - counting down to zero does not assert the SysTick exception request - 0b0 - - - value2 - counting down to zero to asserts the SysTick exception request. - 0b1 - - - - - CLKSOURCE - Indicates the clock source: - 2 - 2 - read-write - - - value1 - external clock - 0b0 - - - value2 - processor clock. - 0b1 - - - - - COUNTFLAG - Counter Flag - 16 - 16 - read-write - - - - - SYST_RVR - SysTick Reload Value Register - 0x014 - 32 - 0x00000000 - 0x00000000 - - - RELOAD - Reload Value - 0 - 23 - read-write - - - - - SYST_CVR - SysTick Current Value Register - 0x018 - 32 - 0x00000000 - 0x00000000 - - - CURRENT - Current Value - 0 - 23 - read-write - - - - - SYST_CALIB - SysTick Calibration Value Register r - 0x01C - 32 - 0xC0000000 - 0xFFFFFFFF - - - TENMS - Ten Milliseconds Reload Value - 0 - 23 - read-write - - - SKEW - Ten Milliseconds Skewed - 30 - 30 - read-write - - - value1 - TENMS value is exact - 0b0 - - - value2 - TENMS value is inexact, or not given. - 0b1 - - - - - NOREF - No Reference Clock - 31 - 31 - read-write - - - value1 - reference clock provided - 0b0 - - - value2 - no reference clock provided. - 0b1 - - - - - - - NVIC_ISER0 - Interrupt Set-enable Register 0 - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISER1 - Interrupt Set-enable Register 1 - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISER2 - Interrupt Set-enable Register 2 - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISER3 - Interrupt Set-enable Register 3 - 0x10C - 32 - 0x00000000 - 0xFFFFFFFF - - - SETENA - Interrupt set-enable bits - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER0 - Interrupt Clear-enable Register 0 - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER1 - Interrupt Clear-enable Register 1 - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER2 - Interrupt Clear-enable Register 2 - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ICER3 - Interrupt Clear-enable Register 3 - 0x18C - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRENA - Interrupt clear-enable bits. - 0 - 31 - read-write - - - value3 - interrupt disabled - 0b0 - - - value4 - interrupt enabled. - 0b1 - - - - - - - NVIC_ISPR0 - Interrupt Set-pending Register 0 - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ISPR1 - Interrupt Set-pending Register 1 - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ISPR2 - Interrupt Set-pending Register 2 - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ISPR3 - Interrupt Set-pending Register 3 - 0x20C - 32 - 0x00000000 - 0xFFFFFFFF - - - SETPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR0 - Interrupt Clear-pending Register 0 - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR1 - Interrupt Clear-pending Register 1 - 0x284 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR2 - Interrupt Clear-pending Register 2 - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_ICPR3 - Interrupt Clear-pending Register 3 - 0x28C - 32 - 0x00000000 - 0xFFFFFFFF - - - CLRPEND - Interrupt set-pending bits. - 0 - 31 - read-write - - - value3 - interrupt is not pending - 0b0 - - - value4 - interrupt is pending. - 0b1 - - - - - - - NVIC_IABR0 - Interrupt Active Bit Register 0 - 0x300 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IABR1 - Interrupt Active Bit Register 1 - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IABR2 - Interrupt Active Bit Register 2 - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IABR3 - Interrupt Active Bit Register 3 - 0x30C - 32 - 0x00000000 - 0xFFFFFFFF - - - ACTIVE - Interrupt active flags: - 0 - 31 - read-write - - - value1 - interrupt not active - 0b0 - - - value2 - interrupt active - 0b1 - - - - - - - NVIC_IPR0 - Interrupt Priority Register 0 - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR1 - Interrupt Priority Register 1 - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR2 - Interrupt Priority Register 2 - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR3 - Interrupt Priority Register 3 - 0x40C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR4 - Interrupt Priority Register 4 - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR5 - Interrupt Priority Register 5 - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR6 - Interrupt Priority Register 6 - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR7 - Interrupt Priority Register 7 - 0x41C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR8 - Interrupt Priority Register 8 - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR9 - Interrupt Priority Register 9 - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR10 - Interrupt Priority Register 10 - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR11 - Interrupt Priority Register 11 - 0x42C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR12 - Interrupt Priority Register 12 - 0x430 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR13 - Interrupt Priority Register 13 - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR14 - Interrupt Priority Register 14 - 0x438 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR15 - Interrupt Priority Register 15 - 0x43C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR16 - Interrupt Priority Register 16 - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR17 - Interrupt Priority Register 17 - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR18 - Interrupt Priority Register 18 - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR19 - Interrupt Priority Register 19 - 0x44C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR20 - Interrupt Priority Register 20 - 0x450 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR21 - Interrupt Priority Register 21 - 0x454 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR22 - Interrupt Priority Register 22 - 0x458 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR23 - Interrupt Priority Register 23 - 0x45C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR24 - Interrupt Priority Register 24 - 0x460 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR25 - Interrupt Priority Register 25 - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR26 - Interrupt Priority Register 26 - 0x468 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - NVIC_IPR27 - Interrupt Priority Register 27 - 0x46C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_0 - Priority value 0 - 0 - 7 - read-write - - - PRI_1 - Priority value 1 - 8 - 15 - read-write - - - PRI_2 - Priority value 2 - 16 - 23 - read-write - - - PRI_3 - Priority value 3 - 24 - 31 - read-write - - - - - CPUID - CPUID Base Register - 0xD00 - 32 - 0x410FC241 - 0xFFFFFFFF - - - Revision - Revision number - 0 - 3 - read-only - - - value1 - Patch 1 - 0x1 - - - - - PartNo - Part number of the processor - 4 - 15 - read-only - - - value1 - Cortex-M4 - 0xC24 - - - - - Constant - Reads as 0xF - 16 - 19 - read-only - - - Variant - Variant number - 20 - 23 - read-only - - - value1 - Revision 0 - 0x0 - - - - - Implementer - Implementer code - 24 - 31 - read-only - - - value1 - ARM - 0x41 - - - - - - - ICSR - Interrupt Control and State Register - 0xD04 - 32 - 0x00000000 - 0xFFFFFFFF - - - VECTACTIVE - Active exception number - 0 - 8 - read-only - - - value1 - Thread mode - 0x00 - - - - - RETTOBASE - Return to Base - 11 - 11 - read-only - - - value1 - there are preempted active exceptions to execute - 0b0 - - - value2 - there are no active exceptions, or the currently-executing exception is the only active exception. - 0b1 - - - - - VECTPENDING - Vector Pending - 12 - 17 - read-only - - - value1 - no pending exceptions - 0x0 - - - - - ISRPENDING - Interrupt pending flag - 22 - 22 - read-only - - - value1 - interrupt not pending - 0b0 - - - value2 - interrupt pending. - 0b1 - - - - - Res - Reserved - 23 - 23 - read-only - - - PENDSTCLR - SysTick exception clear-pending bit - 25 - 25 - write-only - - - value1 - no effect - 0b0 - - - value2 - removes the pending state from the SysTick exception. - 0b1 - - - - - PENDSTSET - SysTick exception set-pending bit - 26 - 26 - read-write - - - value1 - no effect - 0b0 - - - value2 - changes SysTick exception state to pending. - 0b1 - - - - - PENDSVCLR - PendSV clear-pending bit - 27 - 27 - write-only - - - value1 - no effect - 0b0 - - - value2 - removes the pending state from the PendSV exception. - 0b1 - - - - - PENDSVSET - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending., - 28 - 28 - read-write - - - NMIPENDSET - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending., - 31 - 31 - read-write - - - - - VTOR - Vector Table Offset Register - 0xD08 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBLOFF - Vector table base offset field - 10 - 31 - read-write - - - - - AIRCR - Application Interrupt and Reset Control Register - 0xD0C - 32 - 0xFA050000 - 0xFFFFFFFF - - - VECTRESET - Reserved for Debug use. - 0 - 0 - write-only - - - VECTCLRACTIVE - Reserved for Debug use. - 1 - 1 - write-only - - - SYSRESETREQ - System reset request - 2 - 2 - write-only - - - value1 - no system reset request - 0b0 - - - value2 - asserts a signal to the outer system that requests a reset. - 0b1 - - - - - PRIGROUP - Interrupt priority grouping field - 8 - 10 - read-write - - - ENDIANNESS - Data endianness bit - 15 - 15 - read-only - - - value1 - Little-endian - 0b0 - - - value2 - Big-endian. - 0b1 - - - - - VECTKEY - Register key - 16 - 31 - read-write - - - - - SCR - System Control Register - 0xD10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLEEPONEXIT - Sleep on Exit - 1 - 1 - read-write - - - value1 - do not sleep when returning to Thread mode. - 0b0 - - - value2 - enter sleep, or deep sleep, on return from an ISR. - 0b1 - - - - - SLEEPDEEP - Sleep or Deep Sleep - 2 - 2 - read-write - - - value1 - sleep - 0b0 - - - value2 - deep sleep - 0b1 - - - - - SEVONPEND - Send Event on Pending bit: - 4 - 4 - read-write - - - value1 - only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded - 0b0 - - - value2 - enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - 0b1 - - - - - - - CCR - Configuration and Control Register - 0xD14 - 32 - 0x00000200 - 0xFFFFFFFF - - - NONBASETHRDENA - Non Base Thread Mode Enable - 0 - 0 - read-write - - - value1 - processor can enter Thread mode only when no exception is active. - 0b0 - - - value2 - processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. . - 0b1 - - - - - USERSETMPEND - User Set Pending Enable - 1 - 1 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - UNALIGN_TRP - Unaligned Access Trap Enable - 3 - 3 - read-write - - - value1 - do not trap unaligned halfword and word accesses - 0b0 - - - value2 - trap unaligned halfword and word accesses. - 0b1 - - - - - DIV_0_TRP - Divide by Zero Trap Enable - 4 - 4 - read-write - - - value1 - do not trap divide by 0 - 0b0 - - - value2 - trap divide by 0. - 0b1 - - - - - BFHFNMIGN - Bus Fault Hard Fault and NMI Ignore - 8 - 8 - read-write - - - value1 - data bus faults caused by load and store instructions cause a lock-up - 0b0 - - - value2 - handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. - 0b1 - - - - - STKALIGN - Stack Alignment - 9 - 9 - read-write - - - value1 - 4-byte aligned - 0b0 - - - value2 - 8-byte aligned. - 0b1 - - - - - - - SHPR1 - System Handler Priority Register 1 - 0xD18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_4 - Priority of system handler 4, MemManage - 0 - 7 - read-write - - - PRI_5 - Priority of system handler 5, BusFault - 8 - 15 - read-write - - - PRI_6 - Priority of system handler 6, UsageFault - 16 - 23 - read-write - - - - - SHPR2 - System Handler Priority Register 2 - 0xD1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_11 - Priority of system handler 11, SVCall - 24 - 31 - read-write - - - - - SHPR3 - System Handler Priority Register 3 - 0xD20 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRI_14 - Priority of system handler 14 - 16 - 23 - read-write - - - PRI_15 - Priority of system handler 15 - 24 - 31 - read-write - - - - - SHCSR - System Handler Control and State Register - 0xD24 - 32 - 0x00000000 - 0xFFFFFFFF - - - MEMFAULTACT - MemManage exception active bit - 0 - 0 - read-write - - - BUSFAULTACT - BusFault exception active bit - 1 - 1 - read-write - - - USGFAULTACT - UsageFault exception active bit - 3 - 3 - read-write - - - SVCALLACT - SVCall active bit - 7 - 7 - read-write - - - MONITORACT - Debug monitor active bit - 8 - 8 - read-write - - - PENDSVACT - PendSV exception active bit - 10 - 10 - read-write - - - SYSTICKACT - SysTick exception active bit - 11 - 11 - read-write - - - USGFAULTPENDED - UsageFault exception pending bit - 12 - 12 - read-write - - - MEMFAULTPENDED - MemManage exception pending bit - 13 - 13 - read-write - - - BUSFAULTPENDED - BusFault exception pending bit - 14 - 14 - read-write - - - SVCALLPENDED - SVCall pending bit - 15 - 15 - read-write - - - MEMFAULTENA - MemManage enable bit - 16 - 16 - read-write - - - BUSFAULTENA - BusFault enable bit - 17 - 17 - read-write - - - USGFAULTENA - UsageFault enable bit - 18 - 18 - read-write - - - - - CFSR - Configurable Fault Status Register - 0xD28 - 32 - 0x00000000 - 0xFFFFFFFF - - - IACCVIOL - Instruction access violation flag - 0 - 0 - read-write - - - value1 - no instruction access violation fault - 0b0 - - - value2 - the processor attempted an instruction fetch from a location that does not permit execution. - 0b1 - - - - - DACCVIOL - Data access violation flag - 1 - 1 - read-write - - - value1 - no data access violation fault - 0b0 - - - value2 - the processor attempted a load or store at a location that does not permit the operation. - 0b1 - - - - - MUNSTKERR - MemManage fault on unstacking for a return from exception - 3 - 3 - read-write - - - value1 - no unstacking fault - 0b0 - - - value2 - unstack for an exception return has caused one or more access violations. - 0b1 - - - - - MSTKERR - MemManage fault on stacking for exception entry - 4 - 4 - read-write - - - value1 - no stacking fault - 0b0 - - - value2 - stacking for an exception entry has caused one or more access violations. - 0b1 - - - - - MLSPERR - MemManage fault during floating point lazy state preservation - 5 - 5 - read-write - - - value1 - No MemManage fault occurred during floating-point lazy state preservation - 0b0 - - - value2 - A MemManage fault occurred during floating-point lazy state preservation - 0b1 - - - - - MMARVALID - MemManage Fault Address Register (MMFAR) valid flag - 7 - 7 - read-write - - - value1 - value in MMAR is not a valid fault address - 0b0 - - - value2 - MMAR holds a valid fault address. - 0b1 - - - - - IBUSERR - Instruction bus error - 8 - 8 - read-write - - - value1 - no instruction bus error - 0b0 - - - value2 - instruction bus error. - 0b1 - - - - - PRECISERR - Precise data bus error - 9 - 9 - read-write - - - value1 - no precise data bus error - 0b0 - - - value2 - a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. - 0b1 - - - - - IMPRECISERR - Imprecise data bus error - 10 - 10 - read-write - - - value1 - no imprecise data bus error - 0b0 - - - value2 - a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. - 0b1 - - - - - UNSTKERR - BusFault on unstacking for a return from exception - 11 - 11 - read-write - - - value1 - no unstacking fault - 0b0 - - - value2 - stacking for an exception entry has caused one or more BusFaults. - 0b1 - - - - - STKERR - BusFault on stacking for exception entry - 12 - 12 - read-write - - - value1 - no stacking fault - 0b0 - - - value2 - stacking for an exception entry has caused one or more BusFaults. - 0b1 - - - - - LSPERR - BusFault during floating point lazy state preservation - 13 - 13 - read-write - - - value1 - No bus fault occurred during floating-point lazy state preservation. - 0b0 - - - value2 - A bus fault occurred during floating-point lazy state preservation - 0b1 - - - - - BFARVALID - BusFault Address Register (BFAR) valid flag - 15 - 15 - read-write - - - value1 - value in BFAR is not a valid fault address - 0b0 - - - value2 - BFAR holds a valid fault address. - 0b1 - - - - - UNDEFINSTR - Undefined instruction UsageFault - 16 - 16 - read-write - - - value1 - no undefined instruction UsageFault - 0b0 - - - value2 - the processor has attempted to execute an undefined instruction. - 0b1 - - - - - INVSTATE - Invalid state UsageFault - 17 - 17 - read-write - - - value1 - no invalid state UsageFault - 0b0 - - - value2 - the processor has attempted to execute an instruction that makes illegal use of the EPSR. - 0b1 - - - - - INVPC - Invalid PC load UsageFault - 18 - 18 - read-write - - - value1 - no invalid PC load UsageFault - 0b0 - - - value2 - the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. - 0b1 - - - - - NOCP - No coprocessor UsageFault - 19 - 19 - read-write - - - value1 - no UsageFault caused by attempting to access a coprocessor - 0b0 - - - value2 - the processor has attempted to access a coprocessor. - 0b1 - - - - - UNALIGNED - Unaligned access UsageFault - 24 - 24 - read-write - - - value1 - no unaligned access fault, or unaligned access trapping not enabled - 0b0 - - - value2 - the processor has made an unaligned memory access. - 0b1 - - - - - DIVBYZERO - Divide by zero UsageFault - 25 - 25 - read-write - - - value1 - no divide by zero fault, or divide by zero trapping not enabled - 0b0 - - - value2 - the processor has executed an SDIV or UDIV instruction with a divisor of 0 - 0b1 - - - - - - - HFSR - HardFault Status Register - 0xD2C - 32 - 0x00000000 - 0xFFFFFFFF - - - VECTTBL - BusFault on vector table read - 1 - 1 - read-write - - - value1 - no BusFault on vector table read - 0b0 - - - value2 - BusFault on vector table read - 0b1 - - - - - FORCED - Forced HardFault - 30 - 30 - read-write - - - value1 - no forced HardFault - 0b0 - - - value2 - forced HardFault. - 0b1 - - - - - DEBUGEVT - Reserved for Debug use - 31 - 31 - read-write - - - - - MMFAR - MemManage Fault Address Register - 0xD34 - 32 - 0x00000000 - 0x00000000 - - - ADDRESS - Address causing the fault - 0 - 31 - read-write - - - - - BFAR - BusFault Address Register - 0xD38 - 32 - 0x00000000 - 0x00000000 - - - ADDRESS - Address causing the fault - 0 - 31 - read-write - - - - - AFSR - Auxiliary Fault Status Register - 0xD3C - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Reserved - 0 - 31 - read-write - - - - - CPACR - Coprocessor Access Control Register - 0xD88 - 32 - 0x00000000 - 0xFFFFFFFF - - - CP10 - Access privileges for coprocessor 10 - 20 - 21 - read-write - - - value1 - Access denied. Any attempted access generates a NOCP UsageFault. - 0b00 - - - value2 - Privileged access only. An unprivileged access generates a NOCP fault. - 0b01 - - - value3 - Reserved. The result of any access is Unpredictable. - 0b10 - - - value4 - Full access. - 0b11 - - - - - CP11 - Access privileges for coprocessor 11 - 22 - 23 - read-write - - - value1 - Access denied. Any attempted access generates a NOCP UsageFault. - 0b00 - - - value2 - Privileged access only. An unprivileged access generates a NOCP fault. - 0b01 - - - value3 - Reserved. The result of any access is Unpredictable. - 0b10 - - - value4 - Full access. - 0b11 - - - - - - - MPU_TYPE - MPU Type Register - 0xD90 - 32 - 0x00000800 - 0xFFFFFFFF - - - SEPARATE - Support for unified or separate instruction and date memory maps - 0 - 0 - read-only - - - DREGION - Number of supported MPU data regions - 8 - 15 - read-only - - - IREGION - Number of supported MPU instruction regions - 16 - 23 - read-only - - - - - MPU_CTRL - MPU Control Register - 0xD94 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Enable MPU - 0 - 0 - read-write - - - value1 - MPU disabled - 0b0 - - - value2 - MPU enabled. - 0b1 - - - - - HFNMIENA - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers - 1 - 1 - read-write - - - value1 - MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit - 0b0 - - - value2 - the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. - 0b1 - - - - - PRIVDEFENA - Enables privileged software access to the default memory map - 2 - 2 - read-write - - - value1 - If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. - 0b0 - - - value2 - If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - 0b1 - - - - - - - MPU_RNR - MPU Region Number Register - 0xD98 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - Region - 0 - 7 - read-write - - - - - MPU_RBAR - MPU Region Base Address Register - 0xD9C - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR - MPU Region Attribute and Size Register - 0xDA0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - MPU_RBAR_A1 - MPU Region Base Address Register A1 - 0xDA4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR_A1 - MPU Region Attribute and Size Register A1 - 0xDA8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - MPU_RBAR_A2 - MPU Region Base Address Register A2 - 0xDAC - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR_A2 - MPU Region Attribute and Size Register A2 - 0xDB0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - MPU_RBAR_A3 - MPU Region Base Address Register A3 - 0xDB4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGION - MPU region field - 0 - 3 - read-write - - - VALID - MPU Region Number valid bit - 4 - 4 - read-write - - - value1 - MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field - 0b0 - - - value2 - the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. - 0b1 - - - - - ADDR - Region base address field - 9 - 31 - read-write - - - - - MPU_RASR_A3 - MPU Region Attribute and Size Register A3 - 0xDB8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - Region enable bit. - 0 - 0 - read-write - - - SIZE - MPU protection region size - 1 - 5 - read-write - - - SRD - Subregion disable bits - 8 - 15 - read-write - - - value1 - corresponding sub-region is enabled - 0b0 - - - value2 - corresponding sub-region is disabled - 0b1 - - - - - B - Memory access attribute - 16 - 16 - read-write - - - C - Memory access attribute - 17 - 17 - read-write - - - S - Shareable bit - 18 - 18 - read-write - - - TEX - Memory access attribute - 19 - 21 - read-write - - - AP - Access permission field - 24 - 26 - read-write - - - XN - Instruction access disable bit - 28 - 28 - read-write - - - value1 - instruction fetches enabled - 0b0 - - - value2 - instruction fetches disabled. - 0b1 - - - - - - - STIR - Software Trigger Interrupt Register - 0xF00 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTID - Interrupt ID of the interrupt to trigger - 0 - 8 - write-only - - - - - FPCCR - Floating-point Context Control Register - 0xF34 - 32 - 0x00000000 - 0xFFFFFFFF - - - LSPACT - Lazy State Preservation Active - 0 - 0 - read-write - - - value1 - Lazy state preservation is not active. - 0b0 - - - value2 - Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. - 0b1 - - - - - USER - User allocated Stack Frame - 1 - 1 - read-write - - - value1 - Privilege level was not user when the floating-point stack frame was allocated. - 0b0 - - - value2 - Privilege level was user when the floating-point stack frame was allocated. - 0b1 - - - - - THREAD - Thread Mode allocated Stack Frame - 3 - 3 - read-write - - - value1 - Mode was not Thread Mode when the floating-point stack frame was allocated. - 0b0 - - - value2 - Mode was Thread Mode when the floating-point stack frame was allocated. - 0b1 - - - - - HFRDY - HardFault Ready - 4 - 4 - read-write - - - value1 - Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. - 0b0 - - - value2 - Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. - 0b1 - - - - - MMRDY - MemManage Ready - 5 - 5 - read-write - - - value1 - MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. - 0b0 - - - value2 - MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. - 0b1 - - - - - BFRDY - BusFault Ready - 6 - 6 - read-write - - - value1 - BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. - 0b0 - - - value2 - BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. - 0b1 - - - - - MONRDY - Monitor Ready - 8 - 8 - read-write - - - value1 - Debug Monitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. - 0b0 - - - value2 - Debug Monitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. - 0b1 - - - - - LSPEN - Lazy State Preservation Enabled - 30 - 30 - read-write - - - value1 - Disable automatic lazy state preservation for floating-point context. - 0b0 - - - value2 - Enable automatic lazy state preservation for floating-point context. - 0b1 - - - - - ASPEN - Automatic State Preservation - 31 - 31 - read-write - - - value1 - Disable CONTROL setting on execution of a floating-point instruction. - 0b0 - - - value2 - Enable CONTROL setting on execution of a floating-point instruction. - 0b1 - - - - - - - FPCAR - Floating-point Context Address Register - 0xF38 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRESS - Address - 3 - 31 - read-write - - - - - FPDSCR - Floating-point Default Status Control Register - 0xF3C - 32 - 0x00000000 - 0xFFFFFFFF - - - RMode - Default value for FPSCR.RMode - 22 - 23 - read-write - - - FZ - Default value for FPSCR.FZ - 24 - 24 - read-write - - - DN - Default value for FPSCR.DN - 25 - 25 - read-write - - - AHP - Default value for FPSCR.AHP - 26 - 26 - read-write - - - - - - - DLR - DMA Line Router - 0x50004900 - - 0x0 - 0x0100 - registers - - - - OVRSTAT - Overrun Status - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - LN0 - Line 0 Overrun Status - 0 - 0 - read-only - - - LN1 - Line 1 Overrun Status - 1 - 1 - read-only - - - LN2 - Line 2 Overrun Status - 2 - 2 - read-only - - - LN3 - Line 3 Overrun Status - 3 - 3 - read-only - - - LN4 - Line 4 Overrun Status - 4 - 4 - read-only - - - LN5 - Line 5 Overrun Status - 5 - 5 - read-only - - - LN6 - Line 6 Overrun Status - 6 - 6 - read-only - - - LN7 - Line 7 Overrun Status - 7 - 7 - read-only - - - LN8 - Line 8 Overrun Status - 8 - 8 - read-only - - - LN9 - Line 9 Overrun Status - 9 - 9 - read-only - - - LN10 - Line 10 Overrun Status - 10 - 10 - read-only - - - LN11 - Line 11 Overrun Status - 11 - 11 - read-only - - - - - OVRCLR - Overrun Clear - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - LN0 - Line 0 Overrun Status Clear - 0 - 0 - write-only - - - LN1 - Line 1 Overrun Status Clear - 1 - 1 - write-only - - - LN2 - Line 2 Overrun Status Clear - 2 - 2 - write-only - - - LN3 - Line 3 Overrun Status Clear - 3 - 3 - write-only - - - LN4 - Line 4 Overrun Status Clear - 4 - 4 - write-only - - - LN5 - Line 5 Overrun Status Clear - 5 - 5 - write-only - - - LN6 - Line 6 Overrun Status Clear - 6 - 6 - write-only - - - LN7 - Line 7 Overrun Status Clear - 7 - 7 - write-only - - - LN8 - Line 8 Overrun Status Clear - 8 - 8 - write-only - - - LN9 - Line 9 Overrun Status Clear - 9 - 9 - write-only - - - LN10 - Line 10 Overrun Status Clear - 10 - 10 - write-only - - - LN11 - Line 11 Overrun Status Clear - 11 - 11 - write-only - - - - - SRSEL0 - Service Request Selection 0 - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RS0 - Request Source for Line 0 - 0 - 3 - read-write - - - RS1 - Request Source for Line 1 - 4 - 7 - read-write - - - RS2 - Request Source for Line 2 - 8 - 11 - read-write - - - RS3 - Request Source for Line 3 - 12 - 15 - read-write - - - RS4 - Request Source for Line 4 - 16 - 19 - read-write - - - RS5 - Request Source for Line 5 - 20 - 23 - read-write - - - RS6 - Request Source for Line 6 - 24 - 27 - read-write - - - RS7 - Request Source for Line 7 - 28 - 31 - read-write - - - - - SRSEL1 - Service Request Selection 1 - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - RS8 - Request Source for Line 8 - 0 - 3 - read-write - - - RS9 - Request Source for Line 9 - 4 - 7 - read-write - - - RS10 - Request Source for Line 10 - 8 - 11 - read-write - - - RS11 - Request Source for Line 11 - 12 - 15 - read-write - - - - - LNEN - Line Enable - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - LN0 - Line 0 Enable - 0 - 0 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN1 - Line 1 Enable - 1 - 1 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN2 - Line 2 Enable - 2 - 2 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN3 - Line 3 Enable - 3 - 3 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN4 - Line 4 Enable - 4 - 4 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN5 - Line 5 Enable - 5 - 5 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN6 - Line 6 Enable - 6 - 6 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN7 - Line 7 Enable - 7 - 7 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN8 - Line 8 Enable - 8 - 8 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN9 - Line 9 Enable - 9 - 9 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN10 - Line 10 Enable - 10 - 10 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - LN11 - Line 11 Enable - 11 - 11 - read-write - - - value1 - Disables the line - 0b0 - - - value2 - Enables the line and resets a pending request - 0b1 - - - - - - - - - ERU0 - Event Request Unit 0 - ERU - ERU - 0x50004800 - - 0x0 - 0x0100 - registers - - - - EXISEL - Event Input Select - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - EXS0A - Event Source Select for A0 (ERS0) - 0 - 1 - read-write - - - value1 - Input ERU_0A0 is selected - 0b00 - - - value2 - Input ERU_0A1 is selected - 0b01 - - - value3 - Input ERU_0A2 is selected - 0b10 - - - value4 - Input ERU_0A3 is selected - 0b11 - - - - - EXS0B - Event Source Select for B0 (ERS0) - 2 - 3 - read-write - - - value1 - Input ERU_0B0 is selected - 0b00 - - - value2 - Input ERU_0B1 is selected - 0b01 - - - value3 - Input ERU_0B2 is selected - 0b10 - - - value4 - Input ERU_0B3 is selected - 0b11 - - - - - EXS1A - Event Source Select for A1 (ERS1) - 4 - 5 - read-write - - - value1 - Input ERU_1A0 is selected - 0b00 - - - value2 - Input ERU_1A1 is selected - 0b01 - - - value3 - Input ERU_1A2 is selected - 0b10 - - - value4 - Input ERU_1A3 is selected - 0b11 - - - - - EXS1B - Event Source Select for B1 (ERS1) - 6 - 7 - read-write - - - value1 - Input ERU_1B0 is selected - 0b00 - - - value2 - Input ERU_1B1 is selected - 0b01 - - - value3 - Input ERU_1B2 is selected - 0b10 - - - value4 - Input ERU_1B3 is selected - 0b11 - - - - - EXS2A - Event Source Select for A2 (ERS2) - 8 - 9 - read-write - - - value1 - Input ERU_2A0 is selected - 0b00 - - - value2 - Input ERU_2A1 is selected - 0b01 - - - value3 - Input ERU_2A2 is selected - 0b10 - - - value4 - Input ERU_2A3 is selected - 0b11 - - - - - EXS2B - Event Source Select for B2 (ERS2) - 10 - 11 - read-write - - - value1 - Input ERU_2B0 is selected - 0b00 - - - value2 - Input ERU_2B1 is selected - 0b01 - - - value3 - Input ERU_2B2 is selected - 0b10 - - - value4 - Input ERU_2B3 is selected - 0b11 - - - - - EXS3A - Event Source Select for A3 (ERS3) - 12 - 13 - read-write - - - value1 - Input ERU_3A0 is selected - 0b00 - - - value2 - Input ERU_3A1 is selected - 0b01 - - - value3 - Input ERU_3A2 is selected - 0b10 - - - value4 - Input ERU_3A3 is selected - 0b11 - - - - - EXS3B - Event Source Select for B3 (ERS3) - 14 - 15 - read-write - - - value1 - Input ERU_3B0 is selected - 0b00 - - - value2 - Input ERU_3B1 is selected - 0b01 - - - value3 - Input ERU_3B2 is selected - 0b10 - - - value4 - Input ERU_3B3 is selected - 0b11 - - - - - - - 4 - 4 - EXICON[%s] - Event Input Control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PE - Output Trigger Pulse Enable for ETLx - 0 - 0 - read-write - - - value1 - The trigger pulse generation is disabled - 0b0 - - - value2 - The trigger pulse generation is enabled - 0b1 - - - - - LD - Rebuild Level Detection for Status Flag for ETLx - 1 - 1 - read-write - - - value1 - The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software. - 0b0 - - - value2 - The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0. - 0b1 - - - - - RE - Rising Edge Detection Enable ETLx - 2 - 2 - read-write - - - value1 - A rising edge is not considered as edge event - 0b0 - - - value2 - A rising edge is considered as edge event - 0b1 - - - - - FE - Falling Edge Detection Enable ETLx - 3 - 3 - read-write - - - value1 - A falling edge is not considered as edge event - 0b0 - - - value2 - A falling edge is considered as edge event - 0b1 - - - - - OCS - Output Channel Select for ETLx Output Trigger Pulse - 4 - 6 - read-write - - - value1 - Trigger pulses are sent to OGU0 - 0b000 - - - value2 - Trigger pulses are sent to OGU1 - 0b001 - - - value3 - Trigger pulses are sent to OGU2 - 0b010 - - - value4 - Trigger pulses are sent to OGU3 - 0b011 - - - - - FL - Status Flag for ETLx - 7 - 7 - read-write - - - value1 - The enabled edge event has not been detected - 0b0 - - - value2 - The enabled edge event has been detected - 0b1 - - - - - SS - Input Source Select for ERSx - 8 - 9 - read-write - - - value1 - Input A without additional combination - 0b00 - - - value2 - Input B without additional combination - 0b01 - - - value3 - Input A OR input B - 0b10 - - - value4 - Input A AND input B - 0b11 - - - - - NA - Input A Negation Select for ERSx - 10 - 10 - read-write - - - value1 - Input A is used directly - 0b0 - - - value2 - Input A is inverted - 0b1 - - - - - NB - Input B Negation Select for ERSx - 11 - 11 - read-write - - - value1 - Input B is used directly - 0b0 - - - value2 - Input B is inverted - 0b1 - - - - - - - 4 - 4 - EXOCON[%s] - Event Output Trigger Control - 0x20 - 32 - 0x00000008 - 0xFFFFFFFF - - - ISS - Internal Trigger Source Selection - 0 - 1 - read-write - - - value1 - The peripheral trigger function is disabled - 0b00 - - - value2 - Input ERU_OGUy1 is selected - 0b01 - - - value3 - Input ERU_OGUy2 is selected - 0b10 - - - value4 - Input ERU_OGUy3 is selected - 0b11 - - - - - GEEN - Gating Event Enable - 2 - 2 - read-write - - - value1 - The event detection is disabled - 0b0 - - - value2 - The event detection is enabled - 0b1 - - - - - PDR - Pattern Detection Result Flag - 3 - 3 - read-only - - - value1 - A pattern miss is detected - 0b0 - - - value2 - A pattern match is detected - 0b1 - - - - - GP - Gating Selection for Pattern Detection Result - 4 - 5 - read-write - - - value1 - ERU_GOUTy is always disabled and ERU_IOUTy can not be activated - 0b00 - - - value2 - ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy - 0b01 - - - value3 - ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1) - 0b10 - - - value4 - ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0) - 0b11 - - - - - IPEN0 - Pattern Detection Enable for ETL0 - 12 - 12 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - IPEN1 - Pattern Detection Enable for ETL1 - 13 - 13 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - IPEN2 - Pattern Detection Enable for ETL2 - 14 - 14 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - IPEN3 - Pattern Detection Enable for ETL3 - 15 - 15 - read-write - - - value1 - Flag EXICONx.FL is excluded from the pattern detection - 0b0 - - - value2 - Flag EXICONx.FL is included in the pattern detection - 0b1 - - - - - - - - - ERU1 - Event Request Unit 1 - ERU - 0x40044000 - - 0x0 - 0x4000 - registers - - - - GPDMA0 - General Purpose DMA Unit 0 - GPDMA - 0x500142C0 - - 0x0 - 0x3D40 - registers - - - - RAWTFR - Raw IntTfr Status - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWBLOCK - Raw IntBlock Status - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWSRCTRAN - Raw IntSrcTran Status - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWDSTTRAN - Raw IntBlock Status - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - RAWERR - Raw IntErr Status - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - CH4 - Raw Interrupt Status for channel 4 - 4 - 4 - read-write - - - CH5 - Raw Interrupt Status for channel 5 - 5 - 5 - read-write - - - CH6 - Raw Interrupt Status for channel 6 - 6 - 6 - read-write - - - CH7 - Raw Interrupt Status for channel 7 - 7 - 7 - read-write - - - - - STATUSTFR - IntTfr Status - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSBLOCK - IntBlock Status - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSSRCTRAN - IntSrcTran Status - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSDSTTRAN - IntBlock Status - 0x040 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - STATUSERR - IntErr Status - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - CH4 - Interrupt Status for channel 4 - 4 - 4 - read-only - - - CH5 - Interrupt Status for channel 5 - 5 - 5 - read-only - - - CH6 - Interrupt Status for channel 6 - 6 - 6 - read-only - - - CH7 - Interrupt Status for channel 7 - 7 - 7 - read-only - - - - - MASKTFR - Mask for Raw IntTfr Status - 0x050 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKBLOCK - Mask for Raw IntBlock Status - 0x058 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKSRCTRAN - Mask for Raw IntSrcTran Status - 0x060 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKDSTTRAN - Mask for Raw IntBlock Status - 0x068 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKERR - Mask for Raw IntErr Status - 0x070 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Write enable for mask bit of channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Write enable for mask bit of channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Write enable for mask bit of channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Write enable for mask bit of channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH4 - Mask bit for channel 4 - 4 - 4 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH5 - Mask bit for channel 5 - 5 - 5 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH6 - Mask bit for channel 6 - 6 - 6 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH7 - Mask bit for channel 7 - 7 - 7 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - CLEARTFR - IntTfr Status - 0x078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARBLOCK - IntBlock Status - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARSRCTRAN - IntSrcTran Status - 0x088 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARDSTTRAN - IntBlock Status - 0x090 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARERR - IntErr Status - 0x098 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH4 - Clear Interrupt Status and Raw Status for channel 4 - 4 - 4 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH5 - Clear Interrupt Status and Raw Status for channel 5 - 5 - 5 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH6 - Clear Interrupt Status and Raw Status for channel 6 - 6 - 6 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH7 - Clear Interrupt Status and Raw Status for channel 7 - 7 - 7 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - STATUSINT - Combined Interrupt Status Register - 0x0A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ERR - OR of the contents of STATUSERR register - 4 - 4 - read-only - - - DSTT - OR of the contents of STATUSDSTTRAN register - 3 - 3 - read-only - - - SRCT - OR of the contents of STATUSSRCTRAN register - 2 - 2 - read-only - - - BLOCK - OR of the contents of STATUSBLOCK register - 1 - 1 - read-only - - - TFR - OR of the contents of STATUSTFR register - 0 - 0 - read-only - - - - - REQSRCREG - Source Software Transaction Request Register - 0x0A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - REQDSTREG - Destination Software Transaction Request Register - 0x0B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - SGLREQSRCREG - Single Source Transaction Request Register - 0x0B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - SGLREQDSTREG - Single Destination Transaction Request Register - 0x0C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - CH4 - Source request for channel 4 - 4 - 4 - read-write - - - CH5 - Source request for channel 5 - 5 - 5 - read-write - - - CH6 - Source request for channel 6 - 6 - 6 - read-write - - - CH7 - Source request for channel 7 - 7 - 7 - read-write - - - - - LSTSRCREG - Last Source Transaction Request Register - 0x0C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Source last transaction request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Source last transaction request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Source last transaction request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Source last transaction request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Source last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Source last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Source last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH4 - Source last request for channel 4 - 4 - 4 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH5 - Source last request for channel 5 - 5 - 5 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH6 - Source last request for channel 6 - 6 - 6 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH7 - Source last request for channel 7 - 7 - 7 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - LSTDSTREG - Last Destination Transaction Request Register - 0x0D0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Destination last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Destination last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Destination last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Destination last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH4 - Destination last transaction request write enable for channel 4 - 12 - 12 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH5 - Destination last transaction request write enable for channel 5 - 13 - 13 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH6 - Destination last transaction request write enable for channel 6 - 14 - 14 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH7 - Destination last transaction request write enable for channel 7 - 15 - 15 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Destination last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Destination last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Destination last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Destination last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH4 - Destination last request for channel 4 - 4 - 4 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH5 - Destination last request for channel 5 - 5 - 5 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH6 - Destination last request for channel 6 - 6 - 6 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH7 - Destination last request for channel 7 - 7 - 7 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - DMACFGREG - GPDMA Configuration Register - 0x0D8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMA_EN - GPDMA Enable bit. - 0 - 0 - read-write - - - value1 - GPDMA Disabled - 0b0 - - - value2 - GPDMA Enabled. - 0b1 - - - - - - - CHENREG - GPDMA Channel Enable Register - 0x0E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH - Channel enable write enable - 8 - 15 - write-only - - - CH - Enables/Disables the channel - 0 - 7 - read-write - - - value1 - Disable the Channel - 0b0 - - - value2 - Enable the Channel - 0b1 - - - - - - - ID - GPDMA0 ID Register - 0x0E8 - 32 - 0x00AFC000 - 0xFFFFFF00 - - - VALUE - Hardcoded GPDMA Peripheral ID - 0 - 31 - read-only - - - - - TYPE - GPDMA Component Type - 0x138 - 32 - 0x44571110 - 0xFFFFFFFF - - - VALUE - Component Type - 0 - 31 - read-only - - - - - VERSION - DMA Component Version - 0x13C - 32 - 0x3231342A - 0xFFFFFFFF - - - VALUE - Version number of the component - 0 - 31 - read-only - - - - - - - GPDMA0_CH0 - General Purpose DMA Unit 0 - GPDMA - GPDMA0_CH0_1 - 0x50014000 - - 0x0 - 0x55 - registers - - - - SAR - Source Address Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SAR - Current Source Address of DMA transfer - 0 - 31 - read-write - - - - - DAR - Destination Address Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAR - Current Destination address of DMA transfer - 0 - 31 - read-write - - - - - LLP - Linked List Pointer Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - Starting Address In Memory - 2 - 31 - read-write - - - - - CTLL - Control Register Low - 0x18 - 32 - 0x00304801 - 0xFFFFFFFF - - - LLP_SRC_EN - Linked List Pointer for Source Enable - 28 - 28 - read-write - - - LLP_DST_EN - Linked List Pointer for Destination Enable - 27 - 27 - read-write - - - TT_FC - Transfer Type and Flow Control - 20 - 22 - read-write - - - DST_SCATTER_EN - Destination scatter enable - 18 - 18 - read-write - - - value1 - Scatter disabled - 0b0 - - - value2 - Scatter enabled - 0b1 - - - - - SRC_GATHER_EN - Source gather enable - 17 - 17 - read-write - - - value1 - Gather disabled - 0b0 - - - value2 - Gather enabled - 0b1 - - - - - SRC_MSIZE - Source Burst Transaction Length - 14 - 16 - read-write - - - DEST_MSIZE - Destination Burst Transaction Length - 11 - 13 - read-write - - - SINC - Source Address Increment - 9 - 10 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - DINC - Destination Address Increment - 7 - 8 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - SRC_TR_WIDTH - Source Transfer Width - 4 - 6 - read-write - - - DST_TR_WIDTH - Destination Transfer Width - 1 - 3 - read-write - - - INT_EN - Interrupt Enable Bit - 0 - 0 - read-write - - - - - CTLH - Control Register High - 0x1C - 32 - 0x00000002 - 0xFFFFFFFF - - - DONE - Done bit - 12 - 12 - read-write - - - BLOCK_TS - Block Transfer Size - 0 - 11 - read-write - - - - - SSTAT - Source Status Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SSTAT - Source Status - 0 - 31 - read-write - - - - - DSTAT - Destination Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTAT - Destination Status - 0 - 31 - read-write - - - - - SSTATAR - Source Status Address Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - SSTATAR - Source Status Address - 0 - 31 - read-write - - - - - DSTATAR - Destination Status Address Register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTATAR - Destination Status Address - 0 - 31 - read-write - - - - - CFGL - Configuration Register Low - 0x40 - 32 - 0x00000E00 - 0xFFFFFF0F - - - RELOAD_DST - Automatic Destination Reload - 31 - 31 - read-write - - - RELOAD_SRC - Automatic Source Reload - 30 - 30 - read-write - - - MAX_ABRST - Maximum AMBA Burst Length - 20 - 29 - read-write - - - SRC_HS_POL - Source Handshaking Interface Polarity - 19 - 19 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - DST_HS_POL - Destination Handshaking Interface Polarity - 18 - 18 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - LOCK_B - Bus Lock Bit - 17 - 17 - read-write - - - LOCK_CH - Channel Lock Bit - 16 - 16 - read-write - - - LOCK_B_L - Bus Lock Level - 14 - 15 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - LOCK_CH_L - Channel Lock Level - 12 - 13 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - HS_SEL_SRC - Source Software or Hardware Handshaking Select - 11 - 11 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware-initiated transaction requests are ignored. - 0b1 - - - - - HS_SEL_DST - Destination Software or Hardware Handshaking Select - 10 - 10 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware- initiated transaction requests are ignored. - 0b1 - - - - - FIFO_EMPTY - Indicates if there is data left in the channel FIFO - 9 - 9 - read-only - - - value1 - Channel FIFO empty - 0b1 - - - value2 - Channel FIFO not empty - 0b0 - - - - - CH_SUSP - Channel Suspend - 8 - 8 - read-write - - - value1 - Not suspended. - 0b0 - - - value2 - Suspend DMA transfer from the source. - 0b1 - - - - - CH_PRIOR - Channel priority - 5 - 7 - read-write - - - - - CFGH - Configuration Register High - 0x44 - 32 - 0x00000004 - 0xFFFFFFFF - - - DEST_PER - Destination Peripheral - 11 - 14 - read-write - - - SRC_PER - Source Peripheral - 7 - 10 - read-write - - - SS_UPD_EN - Source Status Update Enable - 6 - 6 - read-write - - - DS_UPD_EN - Destination Status Update Enable - 5 - 5 - read-write - - - PROTCTL - Protection Control - 2 - 4 - read-write - - - FIFO_MODE - FIFO Mode Select - 1 - 1 - read-write - - - value1 - Space/data available for single AHB transfer of the specified transfer width. - 0b0 - - - value2 - Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. - 0b1 - - - - - FCMODE - Flow Control Mode - 0 - 0 - read-write - - - value1 - Source transaction requests are serviced when they occur. Data pre-fetching is enabled. - 0b0 - - - value2 - Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. - 0b1 - - - - - - - SGR - Source Gather Register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - SGC - Source gather count - 20 - 31 - read-write - - - SGI - Source gather interval - 0 - 19 - read-write - - - - - DSR - Destination Scatter Register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSC - Destination scatter count - 20 - 31 - read-write - - - DSI - Destination scatter interval - 0 - 19 - read-write - - - - - - - GPDMA0_CH1 - General Purpose DMA Unit 0 - GPDMA - 0x50014058 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH2 - General Purpose DMA Unit 0 - GPDMA - GPDMA0_CH2_7 - 0x500140B0 - - 0x0 - 0x55 - registers - - - - SAR - Source Address Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SAR - Current Source Address of DMA transfer - 0 - 31 - read-write - - - - - DAR - Destination Address Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAR - Current Destination address of DMA transfer - 0 - 31 - read-write - - - - - CTLL - Control Register Low - 0x18 - 32 - 0x00304801 - 0xFFFFFFFF - - - TT_FC - Transfer Type and Flow Control - 20 - 22 - read-write - - - SRC_MSIZE - Source Burst Transaction Length - 14 - 16 - read-write - - - DEST_MSIZE - Destination Burst Transaction Length - 11 - 13 - read-write - - - SINC - Source Address Increment - 9 - 10 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - DINC - Destination Address Increment - 7 - 8 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - SRC_TR_WIDTH - Source Transfer Width - 4 - 6 - read-write - - - DST_TR_WIDTH - Destination Transfer Width - 1 - 3 - read-write - - - INT_EN - Interrupt Enable Bit - 0 - 0 - read-write - - - - - CTLH - Control Register High - 0x1C - 32 - 0x00000002 - 0xFFFFFFFF - - - DONE - Done bit - 12 - 12 - read-write - - - BLOCK_TS - Block Transfer Size - 0 - 11 - read-write - - - - - CFGL - Configuration Register Low - 0x40 - 32 - 0x00000E00 - 0xFFFFFF0F - - - MAX_ABRST - Maximum AMBA Burst Length - 20 - 29 - read-write - - - SRC_HS_POL - Source Handshaking Interface Polarity - 19 - 19 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - DST_HS_POL - Destination Handshaking Interface Polarity - 18 - 18 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - LOCK_B - Bus Lock Bit - 17 - 17 - read-write - - - LOCK_CH - Channel Lock Bit - 16 - 16 - read-write - - - LOCK_B_L - Bus Lock Level - 14 - 15 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - LOCK_CH_L - Channel Lock Level - 12 - 13 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - HS_SEL_SRC - Source Software or Hardware Handshaking Select - 11 - 11 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware-initiated transaction requests are ignored. - 0b1 - - - - - HS_SEL_DST - Destination Software or Hardware Handshaking Select - 10 - 10 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware- initiated transaction requests are ignored. - 0b1 - - - - - FIFO_EMPTY - Indicates if there is data left in the channel FIFO - 9 - 9 - read-only - - - value1 - Channel FIFO empty - 0b1 - - - value2 - Channel FIFO not empty - 0b0 - - - - - CH_SUSP - Channel Suspend - 8 - 8 - read-write - - - value1 - Not suspended. - 0b0 - - - value2 - Suspend DMA transfer from the source. - 0b1 - - - - - CH_PRIOR - Channel priority - 5 - 7 - read-write - - - - - CFGH - Configuration Register High - 0x44 - 32 - 0x00000004 - 0xFFFFFFFF - - - DEST_PER - Destination Peripheral - 11 - 14 - read-write - - - SRC_PER - Source Peripheral - 7 - 10 - read-write - - - PROTCTL - Protection Control - 2 - 4 - read-write - - - FIFO_MODE - FIFO Mode Select - 1 - 1 - read-write - - - value1 - Space/data available for single AHB transfer of the specified transfer width. - 0b0 - - - value2 - Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. - 0b1 - - - - - FCMODE - Flow Control Mode - 0 - 0 - read-write - - - value1 - Source transaction requests are serviced when they occur. Data pre-fetching is enabled. - 0b0 - - - value2 - Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. - 0b1 - - - - - - - - - GPDMA0_CH3 - General Purpose DMA Unit 0 - GPDMA - 0x50014108 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH4 - General Purpose DMA Unit 0 - GPDMA - 0x50014160 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH5 - General Purpose DMA Unit 0 - GPDMA - 0x500141B8 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH6 - General Purpose DMA Unit 0 - GPDMA - 0x50014210 - - 0x0 - 0x55 - registers - - - - GPDMA0_CH7 - General Purpose DMA Unit 0 - GPDMA - 0x50014268 - - 0x0 - 0x55 - registers - - - - GPDMA1 - General Purpose DMA Unit 1 - GPDMA - 0x500182C0 - - 0x0 - 0x7D40 - registers - - - - RAWTFR - Raw IntTfr Status - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWBLOCK - Raw IntBlock Status - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWSRCTRAN - Raw IntSrcTran Status - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWDSTTRAN - Raw IntBlock Status - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - RAWERR - Raw IntErr Status - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Raw Interrupt Status for channel 0 - 0 - 0 - read-write - - - CH1 - Raw Interrupt Status for channel 1 - 1 - 1 - read-write - - - CH2 - Raw Interrupt Status for channel 2 - 2 - 2 - read-write - - - CH3 - Raw Interrupt Status for channel 3 - 3 - 3 - read-write - - - - - STATUSTFR - IntTfr Status - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSBLOCK - IntBlock Status - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSSRCTRAN - IntSrcTran Status - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSDSTTRAN - IntBlock Status - 0x040 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - STATUSERR - IntErr Status - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Interrupt Status for channel 0 - 0 - 0 - read-only - - - CH1 - Interrupt Status for channel 1 - 1 - 1 - read-only - - - CH2 - Interrupt Status for channel 2 - 2 - 2 - read-only - - - CH3 - Interrupt Status for channel 3 - 3 - 3 - read-only - - - - - MASKTFR - Mask for Raw IntTfr Status - 0x050 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKBLOCK - Mask for Raw IntBlock Status - 0x058 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKSRCTRAN - Mask for Raw IntSrcTran Status - 0x060 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKDSTTRAN - Mask for Raw IntBlock Status - 0x068 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - MASKERR - Mask for Raw IntErr Status - 0x070 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Write enable for mask bit of channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Write enable for mask bit of channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Write enable for mask bit of channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Write enable for mask bit of channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Mask bit for channel 0 - 0 - 0 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH1 - Mask bit for channel 1 - 1 - 1 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH2 - Mask bit for channel 2 - 2 - 2 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - CH3 - Mask bit for channel 3 - 3 - 3 - read-write - - - value1 - masked - 0b0 - - - value2 - unmasked - 0b1 - - - - - - - CLEARTFR - IntTfr Status - 0x078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARBLOCK - IntBlock Status - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARSRCTRAN - IntSrcTran Status - 0x088 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARDSTTRAN - IntBlock Status - 0x090 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - CLEARERR - IntErr Status - 0x098 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0 - Clear Interrupt Status and Raw Status for channel 0 - 0 - 0 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH1 - Clear Interrupt Status and Raw Status for channel 1 - 1 - 1 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH2 - Clear Interrupt Status and Raw Status for channel 2 - 2 - 2 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - CH3 - Clear Interrupt Status and Raw Status for channel 3 - 3 - 3 - write-only - - - value1 - no effect - 0b0 - - - value2 - clear status - 0b1 - - - - - - - STATUSINT - Combined Interrupt Status Register - 0x0A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ERR - OR of the contents of STATUSERR register - 4 - 4 - read-only - - - DSTT - OR of the contents of STATUSDSTTRAN register - 3 - 3 - read-only - - - SRCT - OR of the contents of STATUSSRCTRAN register - 2 - 2 - read-only - - - BLOCK - OR of the contents of STATUSBLOCK register - 1 - 1 - read-only - - - TFR - OR of the contents of STATUSTFR register - 0 - 0 - read-only - - - - - REQSRCREG - Source Software Transaction Request Register - 0x0A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - REQDSTREG - Destination Software Transaction Request Register - 0x0B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - SGLREQSRCREG - Single Source Transaction Request Register - 0x0B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - SGLREQDSTREG - Single Destination Transaction Request Register - 0x0C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source request for channel 0 - 0 - 0 - read-write - - - CH1 - Source request for channel 1 - 1 - 1 - read-write - - - CH2 - Source request for channel 2 - 2 - 2 - read-write - - - CH3 - Source request for channel 3 - 3 - 3 - read-write - - - - - LSTSRCREG - Last Source Transaction Request Register - 0x0C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Source last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Source last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Source last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Source last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Source last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Source last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Source last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Source last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - LSTDSTREG - Last Destination Transaction Request Register - 0x0D0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH0 - Destination last transaction request write enable for channel 0 - 8 - 8 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH1 - Destination last transaction request write enable for channel 1 - 9 - 9 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH2 - Destination last transaction request write enable for channel 2 - 10 - 10 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - WE_CH3 - Destination last transaction request write enable for channel 3 - 11 - 11 - write-only - - - value1 - write disabled - 0b0 - - - value2 - write enabled - 0b1 - - - - - CH0 - Destination last request for channel 0 - 0 - 0 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH1 - Destination last request for channel 1 - 1 - 1 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH2 - Destination last request for channel 2 - 2 - 2 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - CH3 - Destination last request for channel 3 - 3 - 3 - read-write - - - value1 - Not last transaction in current block - 0b0 - - - value2 - Last transaction in current block - 0b1 - - - - - - - DMACFGREG - GPDMA Configuration Register - 0x0D8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMA_EN - GPDMA Enable bit. - 0 - 0 - read-write - - - value1 - GPDMA Disabled - 0b0 - - - value2 - GPDMA Enabled. - 0b1 - - - - - - - CHENREG - GPDMA Channel Enable Register - 0x0E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WE_CH - Channel enable write enable - 8 - 11 - write-only - - - CH - Enables/Disables the channel - 0 - 3 - read-write - - - value1 - Disable the Channel - 0b0 - - - value2 - Enable the Channel - 0b1 - - - - - - - ID - GPDMA1 ID Register - 0x0E8 - 32 - 0x00B0C000 - 0xFFFFFF00 - - - VALUE - Hardcoded GPDMA Peripheral ID - 0 - 31 - read-only - - - - - TYPE - GPDMA Component Type - 0x138 - 32 - 0x44571110 - 0xFFFFFFFF - - - VALUE - Component Type - 0 - 31 - read-only - - - - - VERSION - DMA Component Version - 0x13C - 32 - 0x3231342A - 0xFFFFFFFF - - - VALUE - Version number of the component - 0 - 31 - read-only - - - - - - - GPDMA1_CH0 - General Purpose DMA Unit 1 - GPDMA - GPDMA1_CH - 0x50018000 - - 0x0 - 0x55 - registers - - - - SAR - Source Address Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SAR - Current Source Address of DMA transfer - 0 - 31 - read-write - - - - - DAR - Destination Address Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAR - Current Destination address of DMA transfer - 0 - 31 - read-write - - - - - CTLL - Control Register Low - 0x18 - 32 - 0x00304801 - 0xFFFFFFFF - - - TT_FC - Transfer Type and Flow Control - 20 - 22 - read-write - - - SRC_MSIZE - Source Burst Transaction Length - 14 - 16 - read-write - - - DEST_MSIZE - Destination Burst Transaction Length - 11 - 13 - read-write - - - SINC - Source Address Increment - 9 - 10 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - DINC - Destination Address Increment - 7 - 8 - read-write - - - value1 - Increment - 0b00 - - - value2 - Decrement - 0b01 - - - value3 - No change - 0b10 - - - - - SRC_TR_WIDTH - Source Transfer Width - 4 - 6 - read-write - - - DST_TR_WIDTH - Destination Transfer Width - 1 - 3 - read-write - - - INT_EN - Interrupt Enable Bit - 0 - 0 - read-write - - - - - CTLH - Control Register High - 0x1C - 32 - 0x00000002 - 0xFFFFFFFF - - - DONE - Done bit - 12 - 12 - read-write - - - BLOCK_TS - Block Transfer Size - 0 - 11 - read-write - - - - - CFGL - Configuration Register Low - 0x40 - 32 - 0x00000E00 - 0xFFFFFF0F - - - MAX_ABRST - Maximum AMBA Burst Length - 20 - 29 - read-write - - - SRC_HS_POL - Source Handshaking Interface Polarity - 19 - 19 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - DST_HS_POL - Destination Handshaking Interface Polarity - 18 - 18 - read-write - - - value1 - Active high - 0b0 - - - value2 - Active low - 0b1 - - - - - LOCK_B - Bus Lock Bit - 17 - 17 - read-write - - - LOCK_CH - Channel Lock Bit - 16 - 16 - read-write - - - LOCK_B_L - Bus Lock Level - 14 - 15 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - LOCK_CH_L - Channel Lock Level - 12 - 13 - read-write - - - value1 - Over complete DMA transfer - 0b00 - - - value2 - Over complete DMA block transfer - 0b01 - - - value3 - Over complete DMA transaction - 0b10 - - - - - HS_SEL_SRC - Source Software or Hardware Handshaking Select - 11 - 11 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware-initiated transaction requests are ignored. - 0b1 - - - - - HS_SEL_DST - Destination Software or Hardware Handshaking Select - 10 - 10 - read-write - - - value1 - Hardware handshaking interface. Software-initiated transaction requests are ignored. - 0b0 - - - value2 - Software handshaking interface. Hardware- initiated transaction requests are ignored. - 0b1 - - - - - FIFO_EMPTY - Indicates if there is data left in the channel FIFO - 9 - 9 - read-only - - - value1 - Channel FIFO empty - 0b1 - - - value2 - Channel FIFO not empty - 0b0 - - - - - CH_SUSP - Channel Suspend - 8 - 8 - read-write - - - value1 - Not suspended. - 0b0 - - - value2 - Suspend DMA transfer from the source. - 0b1 - - - - - CH_PRIOR - Channel priority - 5 - 7 - read-write - - - - - CFGH - Configuration Register High - 0x44 - 32 - 0x00000004 - 0xFFFFFFFF - - - DEST_PER - Destination Peripheral - 11 - 14 - read-write - - - SRC_PER - Source Peripheral - 7 - 10 - read-write - - - PROTCTL - Protection Control - 2 - 4 - read-write - - - FIFO_MODE - FIFO Mode Select - 1 - 1 - read-write - - - value1 - Space/data available for single AHB transfer of the specified transfer width. - 0b0 - - - value2 - Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. - 0b1 - - - - - FCMODE - Flow Control Mode - 0 - 0 - read-write - - - value1 - Source transaction requests are serviced when they occur. Data pre-fetching is enabled. - 0b0 - - - value2 - Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. - 0b1 - - - - - - - - - GPDMA1_CH1 - General Purpose DMA Unit 1 - GPDMA - 0x50018058 - - 0x0 - 0x55 - registers - - - - GPDMA1_CH2 - General Purpose DMA Unit 1 - GPDMA - 0x500180B0 - - 0x0 - 0x55 - registers - - - - GPDMA1_CH3 - General Purpose DMA Unit 1 - GPDMA - 0x50018108 - - 0x0 - 0x55 - registers - - - - FCE - Flexible CRC Engine - FCE - 0x50020000 - - 0x0 - 0x1D - registers - - - - CLC - Clock Control Register - 0x00 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - - - ID - Module Identification Register - 0x08 - 32 - 0x00CAC001 - 0xFFFFFFFF - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - - - FCE_KE0 - Flexible CRC Engine - FCE - FCE_KE - 0x50020020 - - 0x0 - 0x1D - registers - - - - IR - Input Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - IR - Input Register - 0 - 31 - read-write - - - - - RES - CRC Result Register - 0x04 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RES - Result Register - 0 - 31 - read-only - - - - - CFG - CRC Configuration Register - 0x08 - 32 - 0x00000700 - 0xFFFFFFFF - - - CMI - CRC Mismatch Interrupt - 0 - 0 - read-write - - - value1 - CRC Mismatch Interrupt is disabled - 0b0 - - - value2 - CRC Mismatch Interrupt is enabled - 0b1 - - - - - CEI - Configuration Error Interrupt - 1 - 1 - read-write - - - value1 - Configuration Error Interrupt is disabled - 0b0 - - - value2 - Configuration Error Interrupt is enabled - 0b1 - - - - - LEI - Length Error Interrupt - 2 - 2 - read-write - - - value1 - Length Error Interrupt is disabled - 0b0 - - - value2 - Length Error Interrupt is enabled - 0b1 - - - - - BEI - Bus Error Interrupt - 3 - 3 - read-write - - - value1 - Bus Error Interrupt is disabled - 0b0 - - - value2 - Bus Error Interrupt is enabled - 0b1 - - - - - CCE - CRC Check Comparison - 4 - 4 - read-write - - - value1 - CRC check comparison at the end of a message is disabled - 0b0 - - - value2 - CRC check comparison at the end of a message is enabled - 0b1 - - - - - ALR - Automatic Length Reload - 5 - 5 - read-write - - - value1 - Disables automatic reload of the LENGTH field. - 0b0 - - - value2 - Enables automatic reload of the LENGTH field at the end of a message. - 0b1 - - - - - REFIN - IR Byte Wise Reflection - 8 - 8 - read-write - - - value1 - IR Byte Wise Reflection is disabled - 0b0 - - - value2 - IR Byte Wise Reflection is enabled - 0b1 - - - - - REFOUT - CRC 32-Bit Wise Reflection - 9 - 9 - read-write - - - value1 - CRC 32-bit wise is disabled - 0b0 - - - value2 - CRC 32-bit wise is enabled - 0b1 - - - - - XSEL - Selects the value to be xored with the final CRC - 10 - 10 - read-write - - - value1 - 0x00000000 - 0b0 - - - value2 - 0xFFFFFFFF - 0b1 - - - - - - - STS - CRC Status Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - CMF - CRC Mismatch Flag - 0 - 0 - read-write - - - CEF - Configuration Error Flag - 1 - 1 - read-write - - - LEF - Length Error Flag - 2 - 2 - read-write - - - BEF - Bus Error Flag - 3 - 3 - read-write - - - - - LENGTH - CRC Length Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - LENGTH - Message Length Register - 0 - 15 - read-write - - - - - CHECK - CRC Check Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHECK - CHECK Register - 0 - 31 - read-write - - - - - CRC - CRC Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC - CRC Register - 0 - 31 - read-write - - - - - CTR - CRC Test Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - FCM - Force CRC Mismatch - 0 - 0 - read-write - - - FRM_CFG - Force CFG Register Mismatch - 1 - 1 - read-write - - - FRM_CHECK - Force Check Register Mismatch - 2 - 2 - read-write - - - - - - - FCE_KE1 - Flexible CRC Engine - FCE - 0x50020040 - - 0x0 - 0x1D - registers - - - - FCE_KE2 - Flexible CRC Engine - FCE - 0x50020060 - - 0x0 - 0x1D - registers - - - - FCE_KE3 - Flexible CRC Engine - FCE - 0x50020080 - - 0x0 - 0x1D - registers - - - - PBA0 - Peripheral Bridge AHB 0 - PBA - PBA - 0x40000000 - - 0x0 - 0x4000 - registers - - - - STS - Peripheral Bridge Status Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - WERR - Bufferable Write Access Error - 0 - 0 - read-write - - - value1 - no write error occurred. - 0b0 - - - value2 - write error occurred, interrupt request is pending. - 0b1 - - - - - - - WADDR - PBA Write Error Address Register - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - WADDR - Write Error Address - 0 - 31 - read-only - - - - - - - PBA1 - Peripheral Bridge AHB 1 - PBA - 0x48000000 - - 0x0 - 0x4000 - registers - - - - FLASH0 - Flash Memory Controller - FLASH - 0x58001000 - - 0x0 - 0x1400 - registers - - - - ID - Flash Module Identification Register - 0x1008 - 32 - 0x00A2C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - FSR - Flash Status Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - PBUSY - Program Flash Busy - 0 - 0 - read-only - - - value1 - PFLASH ready, not busy; PFLASH in read mode. - 0b0 - - - value2 - PFLASH busy; PFLASH not in read mode. - 0b1 - - - - - FABUSY - Flash Array Busy - 1 - 1 - read-only - - - PROG - Programming State - 4 - 4 - read-only - - - value1 - There is no program operation requested or in progress or just finished. - 0b0 - - - value2 - Programming operation (write page) requested (from FIM) or in action or finished. - 0b1 - - - - - ERASE - Erase State - 5 - 5 - read-only - - - value1 - There is no erase operation requested or in progress or just finished - 0b0 - - - value2 - Erase operation requested (from FIM) or in action or finished. - 0b1 - - - - - PFPAGE - Program Flash in Page Mode - 6 - 6 - read-only - - - value1 - Program Flash not in page mode - 0b0 - - - value2 - Program Flash in page mode; assembly buffer of PFLASH (256 byte) is in use (being filled up) - 0b1 - - - - - PFOPER - Program Flash Operation Error - 8 - 8 - read-only - - - value1 - No operation error reported by Program Flash - 0b0 - - - value2 - Flash array operation aborted, because of a Flash array failure, e.g. an ECC error in microcode. - 0b1 - - - - - SQER - Command Sequence Error - 10 - 10 - read-only - - - value1 - No sequence error - 0b0 - - - value2 - Command state machine operation unsuccessful because of improper address or command sequence. - 0b1 - - - - - PROER - Protection Error - 11 - 11 - read-only - - - value1 - No protection error - 0b0 - - - value2 - Protection error. - 0b1 - - - - - PFSBER - PFLASH Single-Bit Error and Correction - 12 - 12 - read-only - - - value1 - No Single-Bit Error detected during read access to PFLASH - 0b0 - - - value2 - Single-Bit Error detected and corrected - 0b1 - - - - - PFDBER - PFLASH Double-Bit Error - 14 - 14 - read-only - - - value1 - No Double-Bit Error detected during read access to PFLASH - 0b0 - - - value2 - Double-Bit Error detected in PFLASH - 0b1 - - - - - PROIN - Protection Installed - 16 - 16 - read-only - - - value1 - No protection is installed - 0b0 - - - value2 - Read or/and write protection for one or more users is configured and correctly confirmed in the User Configuration Block(s). - 0b1 - - - - - RPROIN - Read Protection Installed - 18 - 18 - read-only - - - value1 - No read protection installed - 0b0 - - - value2 - Read protection and global write protection is configured and correctly confirmed in the User Configuration Block 0. - 0b1 - - - - - RPRODIS - Read Protection Disable State - 19 - 19 - read-only - - - value1 - Read protection (if installed) is not disabled - 0b0 - - - value2 - Read and global write protection is temporarily disabled. - 0b1 - - - - - WPROIN0 - Sector Write Protection Installed for User 0 - 21 - 21 - read-only - - - value1 - No write protection installed for user 0 - 0b0 - - - value2 - Sector write protection for user 0 is configured and correctly confirmed in the User Configuration Block 0. - 0b1 - - - - - WPROIN1 - Sector Write Protection Installed for User 1 - 22 - 22 - read-only - - - value1 - No write protection installed for user 1 - 0b0 - - - value2 - Sector write protection for user 1 is configured and correctly confirmed in the User Configuration Block 1. - 0b1 - - - - - WPROIN2 - Sector OTP Protection Installed for User 2 - 23 - 23 - read-only - - - value1 - No OTP write protection installed for user 2 - 0b0 - - - value2 - Sector OTP write protection with ROM functionality is configured and correctly confirmed in the UCB2. The protection is locked for ever. - 0b1 - - - - - WPRODIS0 - Sector Write Protection Disabled for User 0 - 25 - 25 - read-only - - - value1 - All protected sectors of user 0 are locked if write protection is installed - 0b0 - - - value2 - All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection. - 0b1 - - - - - WPRODIS1 - Sector Write Protection Disabled for User 1 - 26 - 26 - read-only - - - value1 - All protected sectors of user 1 are locked if write protection is installed - 0b0 - - - value2 - All write-protected sectors of user 1 are temporarily unlocked, if not coincidently locked by user 0 or user 2 or via read protection. - 0b1 - - - - - SLM - Flash Sleep Mode - 28 - 28 - read-only - - - value1 - Flash not in sleep mode - 0b0 - - - value2 - Flash is in sleep or shut down mode - 0b1 - - - - - X - Reserved - 30 - 30 - read-only - - - VER - Verify Error - 31 - 31 - read-only - - - value1 - The page is correctly programmed or the sector correctly erased. All programmed or erased bits have full expected quality. - 0b0 - - - value2 - A program verify error or an erase verify error has been detected. Full quality (retention time) of all programmed ("1") or erased ("0") bits cannot be guaranteed. - 0b1 - - - - - - - FCON - Flash Configuration Register - 0x1014 - 32 - 0x00000006 - 0xFFF0FFFF - - - WSPFLASH - Wait States for read access to PFLASH - 0 - 3 - read-write - - - value1 - PFLASH access in one clock cycle - 0b0000 - - - value2 - PFLASH access in one clock cycle - 0b0001 - - - value3 - PFLASH access in two clock cycles - 0b0010 - - - value4 - PFLASH access in three clock cycles - 0b0011 - - - value5 - PFLASH access in fifteen clock cycles. - 0b1111 - - - - - WSECPF - Wait State for Error Correction of PFLASH - 4 - 4 - read-write - - - value1 - No additional wait state for error correction - 0b0 - - - value2 - One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer. - 0b1 - - - - - IDLE - Dynamic Flash Idle - 13 - 13 - read-write - - - value1 - Normal/standard Flash read operation - 0b0 - - - value2 - Dynamic idle of Program Flash enabled for power saving; static prefetching disabled - 0b1 - - - - - ESLDIS - External Sleep Request Disable - 14 - 14 - read-write - - - value1 - External sleep request signal input is enabled - 0b0 - - - value2 - Externally requested Flash sleep is disabled - 0b1 - - - - - SLEEP - Flash SLEEP - 15 - 15 - read-write - - - value1 - Normal state or wake-up - 0b0 - - - value2 - Flash sleep mode is requested - 0b1 - - - - - RPA - Read Protection Activated - 16 - 16 - read-only - - - value1 - The Flash-internal read protection is not activated. Bits DCF, DDF are not taken into account. Bits DCF, DDFx can be cleared - 0b0 - - - value2 - The Flash-internal read protection is activated. Bits DCF, DDF are enabled and evaluated. - 0b1 - - - - - DCF - Disable Code Fetch from Flash Memory - 17 - 17 - read-write - - - value1 - Code fetching from the Flash memory area is allowed. - 0b0 - - - value2 - Code fetching from the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. - 0b1 - - - - - DDF - Disable Any Data Fetch from Flash - 18 - 18 - read-write - - - value1 - Data read access to the Flash memory area is allowed. - 0b0 - - - value2 - Data read access to the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. - 0b1 - - - - - VOPERM - Verify and Operation Error Interrupt Mask - 24 - 24 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - Flash interrupt because of Verify Error or Operation Error in Flash array (FSI) is enabled - 0b1 - - - - - SQERM - Command Sequence Error Interrupt Mask - 25 - 25 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - Flash interrupt because of Sequence Error is enabled - 0b1 - - - - - PROERM - Protection Error Interrupt Mask - 26 - 26 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - Flash interrupt because of Protection Error is enabled - 0b1 - - - - - PFSBERM - PFLASH Single-Bit Error Interrupt Mask - 27 - 27 - read-write - - - value1 - No Single-Bit Error interrupt enabled - 0b0 - - - value2 - Single-Bit Error interrupt enabled for PFLASH - 0b1 - - - - - PFDBERM - PFLASH Double-Bit Error Interrupt Mask - 29 - 29 - read-write - - - value1 - Double-Bit Error interrupt for PFLASH not enabled - 0b0 - - - value2 - Double-Bit Error interrupt for PFLASH enabled. Especially intended for margin check - 0b1 - - - - - EOBM - End of Busy Interrupt Mask - 31 - 31 - read-write - - - value1 - Interrupt not enabled - 0b0 - - - value2 - EOB interrupt is enabled - 0b1 - - - - - - - MARP - Margin Control Register PFLASH - 0x1018 - 32 - 0x00000000 - 0xFFFFFFFF - - - MARGIN - PFLASH Margin Selection - 0 - 3 - read-write - - - value1 - Standard (default) margin. - 0b0000 - - - value2 - Tight margin for 0 (low) level. Suboptimal 0-bits are read as 1s. - 0b0001 - - - value3 - Tight margin for 1 (high) level. Suboptimal 1-bits are read as 0s. - 0b0100 - - - - - TRAPDIS - PFLASH Double-Bit Error Trap Disable - 15 - 15 - read-write - - - value1 - If a double-bit error occurs in PFLASH, a bus error trap is generated. - 0b0 - - - value2 - The double-bit error trap is disabled. Shall be used only during margin check - 0b1 - - - - - - - PROCON0 - Flash Protection Configuration Register User 0 - 0x1020 - 32 - 0x00000000 - 0xFFFF0000 - - - S0L - Sector 0 Locked for Write Protection by User 0 - 0 - 0 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S1L - Sector 1 Locked for Write Protection by User 0 - 1 - 1 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S2L - Sector 2 Locked for Write Protection by User 0 - 2 - 2 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S3L - Sector 3 Locked for Write Protection by User 0 - 3 - 3 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S4L - Sector 4 Locked for Write Protection by User 0 - 4 - 4 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S5L - Sector 5 Locked for Write Protection by User 0 - 5 - 5 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S6L - Sector 6 Locked for Write Protection by User 0 - 6 - 6 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S7L - Sector 7 Locked for Write Protection by User 0 - 7 - 7 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S8L - Sector 8 Locked for Write Protection by User 0 - 8 - 8 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S9L - Sector 9 Locked for Write Protection by User 0 - 9 - 9 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S10_S11L - Sectors 10 and 11 Locked for Write Protection by User 0 - 10 - 10 - read-only - - - value1 - No write protection is configured for sectors 10+11. - 0b0 - - - value2 - Write protection is configured for sectors 10+11. - 0b1 - - - - - RPRO - Read Protection Configuration - 15 - 15 - read-only - - - value1 - No read protection configured - 0b0 - - - value2 - Read protection and global write protection is configured by user 0 (master user) - 0b1 - - - - - - - PROCON1 - Flash Protection Configuration Register User 1 - 0x1024 - 32 - 0x00000000 - 0xFFFF0000 - - - S0L - Sector 0 Locked for Write Protection by User 1 - 0 - 0 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S1L - Sector 1 Locked for Write Protection by User 1 - 1 - 1 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S2L - Sector 2 Locked for Write Protection by User 1 - 2 - 2 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S3L - Sector 3 Locked for Write Protection by User 1 - 3 - 3 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S4L - Sector 4 Locked for Write Protection by User 1 - 4 - 4 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S5L - Sector 5 Locked for Write Protection by User 1 - 5 - 5 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S6L - Sector 6 Locked for Write Protection by User 1 - 6 - 6 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S7L - Sector 7 Locked for Write Protection by User 1 - 7 - 7 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S8L - Sector 8 Locked for Write Protection by User 1 - 8 - 8 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S9L - Sector 9 Locked for Write Protection by User 1 - 9 - 9 - read-only - - - value1 - No write protection is configured for sector n. - 0b0 - - - value2 - Write protection is configured for sector n. - 0b1 - - - - - S10_S11L - Sectors 10 and 11 Locked for Write Protection by User 1 - 10 - 10 - read-only - - - value1 - No write protection is configured for sectors 10+11. - 0b0 - - - value2 - Write protection is configured for sectors 10+11. - 0b1 - - - - - - - PROCON2 - Flash Protection Configuration Register User 2 - 0x1028 - 32 - 0x00000000 - 0xFFFF0000 - - - S0ROM - Sector 0 Locked Forever by User 2 - 0 - 0 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S1ROM - Sector 1 Locked Forever by User 2 - 1 - 1 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S2ROM - Sector 2 Locked Forever by User 2 - 2 - 2 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S3ROM - Sector 3 Locked Forever by User 2 - 3 - 3 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S4ROM - Sector 4 Locked Forever by User 2 - 4 - 4 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S5ROM - Sector 5 Locked Forever by User 2 - 5 - 5 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S6ROM - Sector 6 Locked Forever by User 2 - 6 - 6 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S7ROM - Sector 7 Locked Forever by User 2 - 7 - 7 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S8ROM - Sector 8 Locked Forever by User 2 - 8 - 8 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S9ROM - Sector 9 Locked Forever by User 2 - 9 - 9 - read-only - - - value1 - No ROM functionality configured for sector n. - 0b0 - - - value2 - ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. - 0b1 - - - - - S10_S11ROM - Sectors 10 and 11 Locked Forever by User 2 - 10 - 10 - read-only - - - value1 - No ROM functionality is configured for sectors 10+11. - 0b0 - - - value2 - ROM functionality is configured for sectors 10+11. - 0b1 - - - - - - - - - PREF - Prefetch Unit - 0x58004000 - - 0 - 4 - registers - - - - PCON - Prefetch Configuration Register - 0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IBYP - Instruction Prefetch Buffer Bypass - 0 - 0 - read-write - - - value1 - Instruction prefetch buffer not bypassed. - 0b0 - - - value2 - Instruction prefetch buffer bypassed. - 0b1 - - - - - IINV - Instruction Prefetch Buffer Invalidate - 1 - 1 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Initiate invalidation of entire instruction cache. - 0b1 - - - - - - - - - PMU0 - Program Management Unit - PMU - 0x58000508 - - 0 - 4 - registers - - - - ID - PMU0 Identification Register - 0 - 32 - 0x00A1C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - - - WDT - Watch Dog Timer - 0x50008000 - - 0x0 - 0x4000 - registers - - - - ID - WDT ID Register - 0x00 - 32 - 0x00ADC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - CTR - WDT Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENB - Enable - 0 - 0 - read-write - - - PRE - Pre-warning - 1 - 1 - read-write - - - DSP - Debug Suspend - 4 - 4 - read-write - - - SPW - Service Indication Pulse Width - 8 - 15 - read-write - - - - - SRV - WDT Service Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRV - Service - 0 - 31 - write-only - - - - - TIM - WDT Timer Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - TIM - Timer Value - 0 - 31 - read-only - - - - - WLB - WDT Window Lower Bound Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLB - Window Lower Bound - 0 - 31 - read-write - - - - - WUB - WDT Window Upper Bound Register - 0x14 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WUB - Window Upper Bound - 0 - 31 - read-write - - - - - WDTSTS - WDT Status Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALMS - Pre-warning Alarm - 0 - 0 - read-only - - - - - WDTCLR - WDT Clear Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - ALMC - Pre-warning Alarm - 0 - 0 - write-only - - - - - - - RTC - Real Time Clock - 0x50004A00 - - 0x0 - 0x0200 - registers - - - - ID - RTC ID Register - 0x00 - 32 - 0x00A3C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - CTR - RTC Control Register - 0x04 - 32 - 0x7FFF0000 - 0xFFFFFFFF - - - ENB - RTC Module Enable - 0 - 0 - read-write - - - TAE - Timer Alarm Enable for Hibernation Wake-up - 2 - 2 - read-write - - - ESEC - Enable Seconds Comparison for Hibernation Wake-up - 8 - 8 - read-write - - - EMIC - Enable Minutes Comparison for Hibernation Wake-up - 9 - 9 - read-write - - - EHOC - Enable Hours Comparison for Hibernation Wake-up - 10 - 10 - read-write - - - EDAC - Enable Days Comparison for Hibernation Wake-up - 11 - 11 - read-write - - - EMOC - Enable Months Comparison for Hibernation Wake-up - 13 - 13 - read-write - - - EYEC - Enable Years Comparison for Hibernation Wake-up - 14 - 14 - read-write - - - DIV - RTC Clock Divider Value - 16 - 31 - read-write - - - - - RAWSTAT - RTC Raw Service Request Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPSE - Raw Periodic Seconds Service Request - 0 - 0 - read-only - - - RPMI - Raw Periodic Minutes Service Request - 1 - 1 - read-only - - - RPHO - Raw Periodic Hours Service Request - 2 - 2 - read-only - - - RPDA - Raw Periodic Days Service Request - 3 - 3 - read-only - - - RPMO - Raw Periodic Months Service Request - 5 - 5 - read-only - - - RPYE - Raw Periodic Years Service Request - 6 - 6 - read-only - - - RAI - Raw Alarm Service Request - 8 - 8 - read-only - - - - - STSSR - RTC Service Request Status Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - SPSE - Periodic Seconds Service Request Status after Masking - 0 - 0 - read-only - - - SPMI - Periodic Minutes Service Request Status after Masking - 1 - 1 - read-only - - - SPHO - Periodic Hours Service Request Status after Masking - 2 - 2 - read-only - - - SPDA - Periodic Days Service Request Status after Masking - 3 - 3 - read-only - - - SPMO - Periodic Months Service Request Status after Masking - 5 - 5 - read-only - - - SPYE - Periodic Years Service Request Status after Masking - 6 - 6 - read-only - - - SAI - Alarm Service Request Status after Masking - 8 - 8 - read-only - - - - - MSKSR - RTC Service Request Mask Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPSE - Periodic Seconds Interrupt Mask - 0 - 0 - read-write - - - MPMI - Periodic Minutes Interrupt Mask - 1 - 1 - read-write - - - MPHO - Periodic Hours Interrupt Mask - 2 - 2 - read-write - - - MPDA - Periodic Days Interrupt Mask - 3 - 3 - read-write - - - MPMO - Periodic Months Interrupt Mask - 5 - 5 - read-write - - - MPYE - Periodic Years Interrupt Mask - 6 - 6 - read-write - - - MAI - Alarm Interrupt Mask - 8 - 8 - read-write - - - - - CLRSR - RTC Clear Service Request Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPSE - Periodic Seconds Interrupt Clear - 0 - 0 - write-only - - - RPMI - Periodic Minutes Interrupt Clear - 1 - 1 - write-only - - - RPHO - Periodic Hours Interrupt Clear - 2 - 2 - write-only - - - RPDA - Periodic Days Interrupt Clear - 3 - 3 - write-only - - - RPMO - Periodic Months Interrupt Clear - 5 - 5 - write-only - - - RPYE - Periodic Years Interrupt Clear - 6 - 6 - write-only - - - RAI - Alarm Interrupt Clear - 8 - 8 - write-only - - - - - ATIM0 - RTC Alarm Time Register 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ASE - Alarm Seconds Compare Value - 0 - 5 - read-write - - - AMI - Alarm Minutes Compare Value - 8 - 13 - read-write - - - AHO - Alarm Hours Compare Value - 16 - 20 - read-write - - - ADA - Alarm Days Compare Value - 24 - 28 - read-write - - - - - ATIM1 - RTC Alarm Time Register 1 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - AMO - Alarm Month Compare Value - 8 - 11 - read-write - - - AYE - Alarm Year Compare Value - 16 - 31 - read-write - - - - - TIM0 - RTC Time Register 0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SE - Seconds Time Value - 0 - 5 - read-write - - - MI - Minutes Time Value - 8 - 13 - read-write - - - HO - Hours Time Value - 16 - 20 - read-write - - - DA - Days Time Value - 24 - 28 - read-write - - - - - TIM1 - RTC Time Register 1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAWE - Days of Week Time Value - 0 - 2 - read-write - - - MO - Month Time Value - 8 - 11 - read-write - - - YE - Year Time Value - 16 - 31 - read-write - - - - - - - SCU_CLK - System Control Unit - SCU - 0x50004600 - - 0x0 - 0x100 - registers - - - - CLKSTAT - Clock Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBCST - USB Clock Status - 0 - 0 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - MMCCST - MMC Clock Status - 1 - 1 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - ETH0CST - Ethernet Clock Status - 2 - 2 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - EBUCST - EBU Clock Status - 3 - 3 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - CCUCST - CCU Clock Status - 4 - 4 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - WDTCST - WDT Clock Status - 5 - 5 - read-only - - - value1 - Clock disabled - 0b0 - - - value2 - Clock enabled - 0b1 - - - - - - - CLKSET - CLK Set Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBCEN - USB Clock Enable - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - MMCCEN - MMC Clock Enable - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - ETH0CEN - Ethernet Clock Enable - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - EBUCEN - EBU Clock Enable - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - CCUCEN - CCU Clock Enable - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - WDTCEN - WDT Clock Enable - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable - 0b1 - - - - - - - CLKCLR - CLK Clear Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBCDI - USB Clock Disable - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - MMCCDI - MMC Clock Disable - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - ETH0CDI - Ethernet Clock Disable - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - EBUCDI - EBU Clock Disable - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - CCUCDI - CCU Clock Disable - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - WDTCDI - WDT Clock Disable - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable clock - 0b1 - - - - - - - SYSCLKCR - System Clock Control Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSDIV - System Clock Division Value - 0 - 7 - read-write - - - SYSSEL - System Clock Selection Value - 16 - 16 - read-write - - - value1 - fOFI clock - 0b0 - - - value2 - fPLL clock - 0b1 - - - - - - - CPUCLKCR - CPU Clock Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CPUDIV - CPU Clock Divider Enable - 0 - 0 - read-write - - - value1 - fCPU = fSYS - 0b0 - - - value2 - fCPU = fSYS / 2 - 0b1 - - - - - - - PBCLKCR - Peripheral Bus Clock Control Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PBDIV - PB Clock Divider Enable - 0 - 0 - read-write - - - value1 - fPERIPH = fCPU - 0b0 - - - value2 - fPERIPH = fCPU / 2 - 0b1 - - - - - - - USBCLKCR - USB Clock Control Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - USBDIV - USB Clock Divider Value - 0 - 2 - read-write - - - USBSEL - USB Clock Selection Value - 16 - 16 - read-write - - - value1 - USB PLL Clock - 0b0 - - - value2 - PLL Clock - 0b1 - - - - - - - EBUCLKCR - EBU Clock Control Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - EBUDIV - EBU Clock Divider Value - 0 - 5 - read-write - - - - - CCUCLKCR - CCU Clock Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CCUDIV - CCU Clock Divider Enable - 0 - 0 - read-write - - - value1 - fCCU = fSYS - 0b0 - - - value2 - fCCU = fSYS / 2 - 0b1 - - - - - - - WDTCLKCR - WDT Clock Control Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDTDIV - WDT Clock Divider Value - 0 - 7 - read-write - - - WDTSEL - WDT Clock Selection Value - 16 - 17 - read-write - - - value1 - fOFI clock - 0b00 - - - value2 - fSTDBY clock - 0b01 - - - value3 - fPLL clock - 0b10 - - - value4 - Reserved - 0b11 - - - - - - - EXTCLKCR - External Clock Control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ECKSEL - External Clock Selection Value - 0 - 1 - read-write - - - value1 - fSYS clock - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - fUSB clock - 0b10 - - - value4 - fPLL clock divided according to ECKDIV bit field configuration - 0b11 - - - - - ECKDIV - External Clock Divider Value - 16 - 24 - read-write - - - - - SLEEPCR - Sleep Control Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSSEL - System Clock Selection Value - 0 - 0 - read-write - - - value1 - fOFI clock - 0b0 - - - value2 - fPLL clock - 0b1 - - - - - USBCR - USB Clock Control - 16 - 16 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - MMCCR - MMC Clock Control - 17 - 17 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ETH0CR - Ethernet Clock Control - 18 - 18 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - EBUCR - EBU Clock Control - 19 - 19 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - CCUCR - CCU Clock Control - 20 - 20 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WDTCR - WDT Clock Control - 21 - 21 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - DSLEEPCR - Deep Sleep Control Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSSEL - System Clock Selection Value - 0 - 1 - read-write - - - value1 - fOFI clock - 0b0 - - - value2 - fPLL clock - 0b1 - - - - - FPDN - Flash Power Down - 11 - 11 - read-write - - - value1 - Flash power down module - 0b1 - - - value2 - No effect - 0b0 - - - - - PLLPDN - PLL Power Down - 12 - 12 - read-write - - - value1 - Switch off main PLL - 0b1 - - - value2 - No effect - 0b0 - - - - - VCOPDN - VCO Power Down - 13 - 13 - read-write - - - value1 - Switch off VCO of main PLL - 0b1 - - - value2 - No effect - 0b0 - - - - - USBCR - USB Clock Control - 16 - 16 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - MMCCR - MMC Clock Control - 17 - 17 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ETH0CR - Ethernet Clock Control - 18 - 18 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - EBUCR - EBU Clock Control - 19 - 19 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - CCUCR - CCU Clock Control - 20 - 20 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WDTCR - WDT Clock Control - 21 - 21 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - - - SCU_OSC - System Control Unit - SCU - 0x50004700 - - 0x0 - 0x10 - registers - - - - OSCHPSTAT - OSC_HP Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - X1D - XTAL1 Data Value - 0 - 0 - read-only - - - - - OSCHPCTRL - OSC_HP Control Register - 0x04 - 32 - 0x0000003C - 0xFFFFFFFF - - - X1DEN - XTAL1 Data Enable - 0 - 0 - read-write - - - value1 - Bit X1D is not updated - 0b0 - - - value2 - Bit X1D can be updated - 0b1 - - - - - SHBY - Shaper Bypass - 1 - 1 - read-write - - - value1 - The shaper is not bypassed - 0b0 - - - value2 - The shaper is bypassed - 0b1 - - - - - MODE - Oscillator Mode - 4 - 5 - read-write - - - value1 - External Crystal Mode and External Input Clock Mode. The oscillator Power-Saving Mode is not entered. - 0b00 - - - value2 - OSC is disabled. The oscillator Power-Saving Mode is not entered. - 0b01 - - - value3 - External Input Clock Mode and the oscillator Power-Saving Mode is entered - 0b10 - - - value4 - OSC is disabled. The oscillator Power-Saving Mode is entered. - 0b11 - - - - - OSCVAL - OSC Frequency Value - 16 - 20 - read-write - - - - - CLKCALCONST - Clock Calibration Constant Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - CALIBCONST - Clock Calibration Constant Value - 0 - 3 - read-write - - - - - - - SCU_PLL - System Control Unit - SCU - 0x50004710 - - 0x0 - 0x2C - registers - - - - PLLSTAT - PLL Status Register - 0x00 - 32 - 0x00000002 - 0xFFFFFFFF - - - VCOBYST - VCO Bypass Status - 0 - 0 - read-only - - - value1 - Free-running / Normal Mode is entered - 0b0 - - - value2 - Prescaler Mode is entered - 0b1 - - - - - PWDSTAT - PLL Power-saving Mode Status - 1 - 1 - read-only - - - value1 - PLL Power-saving Mode was not entered - 0b0 - - - value2 - PLL Power-saving Mode was entered - 0b1 - - - - - VCOLOCK - PLL LOCK Status - 2 - 2 - read-only - - - value1 - PLL not locked - 0b0 - - - value2 - PLL locked - 0b1 - - - - - K1RDY - K1 Divider Ready Status - 4 - 4 - read-only - - - value1 - K1-Divider does not operate with the new value - 0b0 - - - value2 - K1-Divider operate with the new value - 0b1 - - - - - K2RDY - K2 Divider Ready Status - 5 - 5 - read-only - - - value1 - K2-Divider does not operate with the new value - 0b0 - - - value2 - K2-Divider operate with the new value - 0b1 - - - - - BY - Bypass Mode Status - 6 - 6 - read-only - - - value1 - Bypass Mode is not entered - 0b0 - - - value2 - Bypass Mode is entered. Input fOSC is selected as output fPLL. - 0b1 - - - - - PLLLV - Oscillator for PLL Valid Low Status Bit - 7 - 7 - read-only - - - value1 - The OSC frequency is not usable. Frequency fREF is too low. - 0b0 - - - value2 - The OSC frequency is usable - 0b1 - - - - - PLLHV - Oscillator for PLL Valid High Status Bit - 8 - 8 - read-only - - - value1 - The OSC frequency is not usable. Frequency fOSC is too high. - 0b0 - - - value2 - The OSC frequency is usable - 0b1 - - - - - PLLSP - Oscillator for PLL Valid Spike Status Bit - 9 - 9 - read-only - - - value1 - The OSC frequency is not usable. Spikes are detected that disturb a locked operation - 0b0 - - - value2 - The OSC frequency is usable - 0b1 - - - - - - - PLLCON0 - PLL Configuration 0 Register - 0x04 - 32 - 0x00030003 - 0xFFFFFFFF - - - VCOBYP - VCO Bypass - 0 - 0 - read-write - - - value1 - Normal operation, VCO is not bypassed - 0b0 - - - value2 - Prescaler Mode, VCO is bypassed - 0b1 - - - - - VCOPWD - VCO Power Saving Mode - 1 - 1 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The VCO is put into a Power Saving Mode and can no longer be used. Only the Bypass and Prescaler Mode are active if previously selected. - 0b1 - - - - - VCOTR - VCO Trim Control - 2 - 2 - read-write - - - value1 - VCO bandwidth is operation in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b0 - - - value2 - VCO bandwidth is operation in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b1 - - - - - FINDIS - Disconnect Oscillator from VCO - 4 - 4 - read-write - - - value1 - connect oscillator to the VCO part - 0b0 - - - value2 - disconnect oscillator from the VCO part. - 0b1 - - - - - OSCDISCDIS - Oscillator Disconnect Disable - 6 - 6 - read-write - - - value1 - In case of a PLL loss-of-lock bit FINDIS is set - 0b0 - - - value2 - In case of a PLL loss-of-lock bit FINDIS is cleared - 0b1 - - - - - PLLPWD - PLL Power Saving Mode - 16 - 16 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The complete PLL block is put into a Power Saving Mode and can no longer be used. Only the Bypass Mode is active if previously selected. - 0b1 - - - - - OSCRES - Oscillator Watchdog Reset - 17 - 17 - read-write - - - value1 - The Oscillator Watchdog of the PLL is not cleared and remains active - 0b0 - - - value2 - The Oscillator Watchdog of the PLL is cleared and restarted - 0b1 - - - - - RESLD - Restart VCO Lock Detection - 18 - 18 - write-only - - - AOTREN - Automatic Oscillator Calibration Enable - 19 - 19 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - FOTR - Factory Oscillator Calibration - 20 - 20 - read-write - - - value1 - No effect - 0b0 - - - value2 - Force fixed-value trimming - 0b1 - - - - - - - PLLCON1 - PLL Configuration 1 Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - K1DIV - K1-Divider Value - 0 - 6 - read-write - - - NDIV - N-Divider Value - 8 - 14 - read-write - - - K2DIV - K2-Divider Value - 16 - 22 - read-write - - - PDIV - P-Divider Value - 24 - 27 - read-write - - - - - PLLCON2 - PLL Configuration 2 Register - 0x0C - 32 - 0x00000001 - 0xFFFFFFFF - - - PINSEL - P-Divider Input Selection - 0 - 0 - read-write - - - value1 - PLL external oscillator selected - 0b0 - - - value2 - Backup clock fofi selected - 0b1 - - - - - K1INSEL - K1-Divider Input Selection - 8 - 8 - read-write - - - value1 - PLL external oscillator selected - 0b0 - - - value2 - Backup clock fofi selected - 0b1 - - - - - - - USBPLLSTAT - USB PLL Status Register - 0x10 - 32 - 0x00000002 - 0xFFFFFFFF - - - VCOBYST - VCO Bypass Status - 0 - 0 - read-only - - - value1 - Normal Mode is entered - 0b0 - - - value2 - Prescaler Mode is entered - 0b1 - - - - - PWDSTAT - PLL Power-saving Mode Status - 1 - 1 - read-only - - - value1 - PLL Power-saving Mode was not entered - 0b0 - - - value2 - PLL Power-saving Mode was entered - 0b1 - - - - - VCOLOCK - PLL VCO Lock Status - 2 - 2 - read-only - - - value1 - The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency. - 0b0 - - - value2 - The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation - 0b1 - - - - - BY - Bypass Mode Status - 6 - 6 - read-only - - - value1 - Bypass Mode is not entered - 0b0 - - - value2 - Bypass Mode is entered. Input fOSC is selected as output fPLL. - 0b1 - - - - - VCOLOCKED - PLL LOCK Status - 7 - 7 - read-only - - - value1 - PLL not locked - 0b0 - - - value2 - PLL locked - 0b1 - - - - - - - USBPLLCON - USB PLL Configuration Register - 0x14 - 32 - 0x00010003 - 0xFFFFFFFF - - - VCOBYP - VCO Bypass - 0 - 0 - read-write - - - value1 - Normal operation, VCO is not bypassed - 0b0 - - - value2 - Prescaler Mode, VCO is bypassed - 0b1 - - - - - VCOPWD - VCO Power Saving Mode - 1 - 1 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The VCO is put into a Power Saving Mode - 0b1 - - - - - VCOTR - VCO Trim Control - 2 - 2 - read-write - - - value1 - VCO bandwidth is operating in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b0 - - - value2 - VCO bandwidth is operating in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. - 0b1 - - - - - FINDIS - Disconnect Oscillator from VCO - 4 - 4 - read-write - - - value1 - Connect oscillator to the VCO part - 0b0 - - - value2 - Disconnect oscillator from the VCO part. - 0b1 - - - - - OSCDISCDIS - Oscillator Disconnect Disable - 6 - 6 - read-write - - - value1 - In case of a PLL loss-of-lock bit FINDIS is set - 0b0 - - - value2 - In case of a PLL loss-of-lock bit FINDIS is cleared - 0b1 - - - - - NDIV - N-Divider Value - 8 - 14 - read-write - - - PLLPWD - PLL Power Saving Mode - 16 - 16 - read-write - - - value1 - Normal behavior - 0b0 - - - value2 - The complete PLL block is put into a Power Saving Mode. Only the Bypass Mode is active if previously selected. - 0b1 - - - - - RESLD - Restart VCO Lock Detection - 18 - 18 - write-only - - - PDIV - P-Divider Value - 24 - 27 - read-write - - - - - CLKMXSTAT - Clock Multiplexing Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYSCLKMUX - Status of System Clock Multiplexing Upon Source Switching - 0 - 1 - read-only - - - value1 - fOFI clock active - 0b01 - - - value2 - fPLL clock active - 0b10 - - - - - - - - - SCU_GENERAL - System Control Unit - SCU - 0x50004000 - - 0x0 - 0x100 - registers - - - - ID - SCU Module ID Register - 0x0000 - 32 - 0x00A0C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - IDCHIP - Chip ID Register - 0x0004 - 32 - 0x00000000 - 0x00000000 - - - IDCHIP - Chip ID - 0 - 31 - read-only - - - - - IDMANUF - Manufactory ID Register - 0x0008 - 32 - 0x00001820 - 0xFFFFFFFF - - - DEPT - Department Identification Number - 0 - 4 - read-only - - - MANUF - Manufacturer Identification Number - 5 - 15 - read-only - - - - - STCON - Startup Configuration Register - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - HWCON - HW Configuration - 0 - 1 - read-only - - - value1 - Normal mode, JTAG - 0b00 - - - value2 - ASC BSL enabled - 0b01 - - - value3 - BMI customized boot enabled - 0b10 - - - value4 - CAN BSL enabled - 0b11 - - - - - SWCON - SW Configuration - 8 - 11 - read-write - - - value1 - Normal mode, boot from Boot ROM - 0b0000 - - - value2 - ASC BSL enabled - 0b0001 - - - value3 - BMI customized boot enabled - 0b0010 - - - value4 - CAN BSL enabled - 0b0011 - - - value5 - Boot from Code SRAM - 0b0100 - - - value6 - Boot from alternate Flash Address 0 - 0b1000 - - - value7 - Boot from alternate Flash Address 1 - 0b1100 - - - value8 - Enable fallback Alternate Boot Mode (ABM) - 0b1110 - - - - - - - GPR0 - General Purpose Register 0 - 0x002C - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - User Data - 0 - 31 - read-write - - - - - GPR1 - General Purpose Register 1 - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - User Data - 0 - 31 - read-write - - - - - CCUCON - CCU Control Register - 0x004C - 32 - 0x00000000 - 0xFFFFFFFF - - - GSC40 - Global Start Control CCU40 - 0 - 0 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC41 - Global Start Control CCU41 - 1 - 1 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC42 - Global Start Control CCU42 - 2 - 2 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC43 - Global Start Control CCU43 - 3 - 3 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC80 - Global Start Control CCU80 - 8 - 8 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - GSC81 - Global Start Control CCU81 - 9 - 9 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - DTSCON - Die Temperature Sensor Control Register - 0x008C - 32 - 0x00000001 - 0xFFFFFFFF - - - PWD - Sensor Power Down - 0 - 0 - read-write - - - value1 - The DTS is powered - 0b0 - - - value2 - The DTS is not powered - 0b1 - - - - - START - Sensor Measurement Start - 1 - 1 - write-only - - - value1 - No DTS measurement is started - 0b0 - - - value2 - A DTS measurement is started - 0b1 - - - - - OFFSET - Offset Calibration Value - 4 - 10 - read-write - - - GAIN - Gain Calibration Value - 11 - 16 - read-write - - - REFTRIM - Reference Trim Calibration Value - 17 - 19 - read-write - - - BGTRIM - Bandgap Trim Calibration Value - 20 - 23 - read-write - - - - - DTSSTAT - Die Temperature Sensor Status Register - 0x0090 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of the DTS Measurement - 0 - 9 - read-only - - - RDY - Sensor Ready Status - 14 - 14 - read-only - - - value1 - The DTS is not ready - 0b0 - - - value2 - The DTS is ready - 0b1 - - - - - BUSY - Sensor Busy Status - 15 - 15 - read-only - - - value1 - not busy - 0b0 - - - value2 - busy - 0b1 - - - - - - - SDMMCDEL - SD-MMC Delay Control Register - 0x009C - 32 - 0x00000000 - 0xFFFFFFFF - - - TAPEN - Enable delay on the CMD/DAT out lines - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - TAPDEL - Number of Delay Elements Select - 4 - 7 - read-write - - - - - G0ORCEN - Out of Range Comparator Enable Register 0 - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENORC6 - Enable Out of Range Comparator, Channel 6 - 6 - 6 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ENORC7 - Enable Out of Range Comparator, Channel 7 - 7 - 7 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - G1ORCEN - Out of Range Comparator Enable Register 1 - 0x00A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENORC6 - Enable Out of Range Comparator, Channel 6 - 6 - 6 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ENORC7 - Enable Out of Range Comparator, Channel 7 - 7 - 7 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - MIRRSTS - Mirror Write Status Register - 0x00C4 - 32 - 0x00000000 - 0xFFFFFFFF - - - HDCLR - HDCLR Mirror Register Write Status - 1 - 1 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - HDSET - HDSET Mirror Register Write Status - 2 - 2 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - HDCR - HDCR Mirror Register Write Status - 3 - 3 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Write Status - 5 - 5 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Write Status - 6 - 6 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Write Status - 7 - 7 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Write Status - 8 - 8 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Write Status - 9 - 9 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Write Status - 10 - 10 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Write Status - 11 - 11 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Write Status - 12 - 12 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RMX - Retention Memory Access Register Update Status - 13 - 13 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_MSKSR - RTC MSKSSR Mirror Register Write Status - 14 - 14 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - RTC_CLRSR - RTC CLRSR Mirror Register Write Status - 15 - 15 - read-only - - - value1 - Ready - 0b0 - - - value2 - Busy - 0b1 - - - - - - - RMACR - Retention Memory Access Control Register - 0x00C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDWR - Hibernate Retention Memory Register Update Control - 0 - 0 - read-write - - - value1 - transfer data from Retention Memory in Hibernate domain to RMDATA register - 0b0 - - - value2 - transfer data from RMDATA into Retention Memory in Hibernate domain - 0b1 - - - - - ADDR - Hibernate Retention Memory Register Address Select - 16 - 19 - read-write - - - - - RMDATA - Retention Memory Access Data Register - 0x00CC - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Hibernate Retention Memory Data - 0 - 31 - read-write - - - - - - - SCU_INTERRUPT - System Control Unit - SCU - 0x50004074 - - 0x0 - 0x18 - registers - - - - SRSTAT - SCU Service Request Status - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Status - 0 - 0 - read-only - - - value1 - Inactive - 0b0 - - - value2 - Active - 0b1 - - - - - PI - RTC Periodic Interrupt Status - 1 - 1 - read-only - - - AI - Alarm Interrupt Status - 2 - 2 - read-only - - - DLROVR - DLR Request Overrun Interrupt Status - 3 - 3 - read-only - - - HDSTAT - HDSTAT Mirror Register Update Status - 16 - 16 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Status - 17 - 17 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDSET - HDSET Mirror Register Update Status - 18 - 18 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCR - HDCR Mirror Register Update Status - 19 - 19 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Status - 21 - 21 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Status - 22 - 22 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Status - 23 - 23 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Status - 24 - 24 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Status - 25 - 25 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Status - 26 - 26 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Status - 27 - 27 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Status - 28 - 28 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Status - 29 - 29 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - - - SRRAW - SCU Raw Service Request Status - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Status Before Masking - 0 - 0 - read-only - - - value1 - Inactive - 0b0 - - - value2 - Active - 0b1 - - - - - PI - RTC Raw Periodic Interrupt Status Before Masking - 1 - 1 - read-only - - - AI - RTC Raw Alarm Interrupt Status Before Masking - 2 - 2 - read-only - - - DLROVR - DLR Request Overrun Interrupt Status Before Masking - 3 - 3 - read-only - - - HDSTAT - HDSTAT Mirror Register Update Status Before Masking - 16 - 16 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Status Before Masking - 17 - 17 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDSET - HDSET Mirror Register Update Status Before Masking - 18 - 18 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - HDCR - HDCR Mirror Register Update Status Before Masking - 19 - 19 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Status Before Masking - 21 - 21 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Status Before Masking - 22 - 22 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Status Before Masking - 23 - 23 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Status Before Masking - 24 - 24 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Status Before Masking - 25 - 25 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Status Before Masking - 26 - 26 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Before Masking Status - 27 - 27 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Status Before Masking - 28 - 28 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Status Before Masking - 29 - 29 - read-only - - - value1 - Not updated - 0b0 - - - value2 - Update completed - 0b1 - - - - - - - SRMSK - SCU Service Request Mask - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Mask - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PI - RTC Periodic Interrupt Mask - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - AI - RTC Alarm Interrupt Mask - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - DLROVR - DLR Request Overrun Interrupt Mask - 3 - 3 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDSTAT - HDSTAT Mirror Register Update Mask - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Mask - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDSET - HDSET Mirror Register Update Mask - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - HDCR - HDCR Mirror Register Update Mask - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Mask - 21 - 21 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Mask - 22 - 22 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Mask - 23 - 23 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Mask - 24 - 24 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Mask - 25 - 25 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Mask - 26 - 26 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Mask - 27 - 27 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Mask - 28 - 28 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Mask - 29 - 29 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - SRCLR - SCU Service Request Clear - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - PI - RTC Periodic Interrupt Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - AI - RTC Alarm Interrupt Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - DLROVR - DLR Request Overrun Interrupt clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDSTAT - HDCTAT Mirror Register Update Clear - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDCLR - HDCLR Mirror Register Update Clear - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDSET - HDSET Mirror Register Update Clear - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - HDCR - HDCR Mirror Register Update Clear - 19 - 19 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Clear - 21 - 21 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Clear - 22 - 22 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Clear - 23 - 23 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Clear - 24 - 24 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Clear - 25 - 25 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Clear - 26 - 26 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Clear - 27 - 27 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Clear - 28 - 28 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Clear - 29 - 29 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear the status bit - 0b1 - - - - - - - SRSET - SCU Service Request Set - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - WDT pre-warning Interrupt Set - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - PI - RTC Periodic Interrupt Set - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - AI - RTC Alarm Interrupt Set - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - DLROVR - DLR Request Overrun Interrupt Set - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDSTAT - HDSTAT Mirror Register Update Set - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDCRCLR - HDCRCLR Mirror Register Update Set - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDCRSET - HDCRSET Mirror Register Update Set - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - HDCR - HDCR Mirror Register Update Set - 19 - 19 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - OSCSICTRL - OSCSICTRL Mirror Register Update Set - 21 - 21 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - OSCULSTAT - OSCULSTAT Mirror Register Update Set - 22 - 22 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - OSCULCTRL - OSCULCTRL Mirror Register Update Set - 23 - 23 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_CTR - RTC CTR Mirror Register Update Set - 24 - 24 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_ATIM0 - RTC ATIM0 Mirror Register Update Set - 25 - 25 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_ATIM1 - RTC ATIM1 Mirror Register Update Set - 26 - 26 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_TIM0 - RTC TIM0 Mirror Register Update Set - 27 - 27 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RTC_TIM1 - RTC TIM1 Mirror Register Update Set - 28 - 28 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - RMX - Retention Memory Mirror Register Update Set - 29 - 29 - write-only - - - value1 - No effect - 0b0 - - - value2 - set the status bit - 0b1 - - - - - - - NMIREQEN - SCU Service Request Mask - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRWARN - Promote Pre-Warning Interrupt Request to NMI Request - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PI - Promote RTC Periodic Interrupt request to NMI Request - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - AI - Promote RTC Alarm Interrupt Request to NMI Request - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU00 - Promote Channel 0 Interrupt of ERU0 Request to NMI Request - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU01 - Promote Channel 1 Interrupt of ERU0 Request to NMI Request - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU02 - Promote Channel 2 Interrupt of ERU0 Request to NMI Request - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - ERU03 - Promote Channel 3 Interrupt of ERU0 Request to NMI Request - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - - - SCU_PARITY - System Control Unit - SCU - 0x5000413C - - 0x0 - 0x20 - registers - - - - PEEN - Parity Error Enable Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - PEENPS - Parity Error Enable for PSRAM - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENDS1 - Parity Error Enable for DSRAM1 - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENDS2 - Parity Error Enable for DSRAM2 - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENU0 - Parity Error Enable for USIC0 Memory - 8 - 8 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENU1 - Parity Error Enable for USIC1 Memory - 9 - 9 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENU2 - Parity Error Enable for USIC2 Memory - 10 - 10 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENMC - Parity Error Enable for MultiCAN Memory - 12 - 12 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENPPRF - Parity Error Enable for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENUSB - Parity Error Enable for USB Memory - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENETH0TX - Parity Error Enable for ETH TX Memory - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENETH0RX - Parity Error Enable for ETH RX Memory - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENSD0 - Parity Error Enable for SDMMC Memory 0 - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PEENSD1 - Parity Error Enable for SDMMC Memory 1 - 20 - 20 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - MCHKCON - Memory Checking Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - SELPS - Select Memory Check for PSRAM - 0 - 0 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELDS1 - Select Memory Check for DSRAM1 - 1 - 1 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELDS2 - Select Memory Check for DSRAM2 - 2 - 2 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - USIC0DRA - Select Memory Check for USIC0 - 8 - 8 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - USIC1DRA - Select Memory Check for USIC1 - 9 - 9 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - USIC2DRA - Select Memory Check for USIC2 - 10 - 10 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - MCANDRA - Select Memory Check for MultiCAN - 12 - 12 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - PPRFDRA - Select Memory Check for PMU - 13 - 13 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELUSB - Select Memory Check for USB SRAM - 16 - 16 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELETH0TX - Select Memory Check for ETH0 TX SRAM - 17 - 17 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELETH0RX - Select Memory Check for ETH0 RX SRAM - 18 - 18 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELSD0 - Select Memory Check for SDMMC SRAM 0 - 19 - 19 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - SELSD1 - Select Memory Check for SDMMC SRAM 1 - 20 - 20 - read-write - - - value1 - Not selected - 0b0 - - - value2 - Selected - 0b1 - - - - - - - PETE - Parity Error Trap Enable Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETEPS - Parity Error Trap Enable for PSRAM - 0 - 0 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEDS1 - Parity Error Trap Enable for DSRAM1 - 1 - 1 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEDS2 - Parity Error Trap Enable for DSRAM2 - 2 - 2 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEU0 - Parity Error Trap Enable for USIC0 Memory - 8 - 8 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEU1 - Parity Error Trap Enable for USIC1 Memory - 9 - 9 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEU2 - Parity Error Trap Enable for USIC2 Memory - 10 - 10 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEMC - Parity Error Trap Enable for MultiCAN Memory - 12 - 12 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEPPRF - Parity Error Trap Enable for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEUSB - Parity Error Trap Enable for USB Memory - 16 - 16 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEETH0TX - Parity Error Trap Enable for ETH 0TX Memory - 17 - 17 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETEETH0RX - Parity Error Trap Enable for ETH0 RX Memory - 18 - 18 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETESD0 - Parity Error Trap Enable for SDMMC SRAM 0 Memory - 19 - 19 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - PETESD1 - Parity Error Trap Enable for SDMMC SRAM 1 Memory - 20 - 20 - read-write - - - value1 - Disabled - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - PERSTEN - Parity Error Reset Enable Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - RSEN - System Reset Enable upon Parity Error Trap - 0 - 0 - read-write - - - value1 - Reset request disabled - 0b0 - - - value2 - Reset request enabled - 0b1 - - - - - - - PEFLAG - Parity Error Flag Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PEFPS - Parity Error Flag for PSRAM - 0 - 0 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFDS1 - Parity Error Flag for DSRAM1 - 1 - 1 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFDS2 - Parity Error Flag for DSRAM2 - 2 - 2 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFU0 - Parity Error Flag for USIC0 Memory - 8 - 8 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFU1 - Parity Error Flag for USIC1 Memory - 9 - 9 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFU2 - Parity Error Flag for USIC2 Memory - 10 - 10 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFMC - Parity Error Flag for MultiCAN Memory - 12 - 12 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEFPPRF - Parity Error Flag for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEUSB - Parity Error Flag for USB Memory - 16 - 16 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEETH0TX - Parity Error Flag for ETH TX Memory - 17 - 17 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PEETH0RX - Parity Error Flag for ETH RX Memory - 18 - 18 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PESD0 - Parity Error Flag for SDMMC Memory 0 - 19 - 19 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - PESD1 - Parity Error Flag for SDMMC Memory 1 - 20 - 20 - read-write - - - value1 - No parity error detected - 0b0 - - - value2 - Parity error detected - 0b1 - - - - - - - PMTPR - Parity Memory Test Pattern Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRD - Parity Read Values for Memory Test - 8 - 15 - read-only - - - PWR - Parity Write Values for Memory Test - 0 - 7 - read-write - - - - - PMTSR - Parity Memory Test Select Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - MTENPS - Test Enable Control for PSRAM - 0 - 0 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTENDS1 - Test Enable Control for DSRAM1 - 1 - 1 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTENDS2 - Test Enable Control for DSRAM2 - 2 - 2 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEU0 - Test Enable Control for USIC0 Memory - 8 - 8 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEU1 - Test Enable Control for USIC1 Memory - 9 - 9 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEU2 - Test Enable Control for USIC2 Memory - 10 - 10 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEMC - Test Enable Control for MultiCAN Memory - 12 - 12 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTEPPRF - Test Enable Control for PMU Prefetch Memory - 13 - 13 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTUSB - Test Enable Control for USB Memory - 16 - 16 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTETH0TX - Test Enable Control for ETH TX Memory - 17 - 17 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTETH0RX - Test Enable Control for ETH RX Memory - 18 - 18 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTSD0 - Test Enable Control for SDMMC Memory 0 - 19 - 19 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - MTSD1 - Test Enable Control for SDMMC Memory 1 - 20 - 20 - read-write - - - value1 - Standard operation - 0b0 - - - value2 - Parity bits under test - 0b1 - - - - - - - - - SCU_TRAP - System Control Unit - SCU - 0x50004160 - - 0x0 - 0x14 - registers - - - - TRAPSTAT - Trap Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Status - 0 - 0 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Status - 2 - 2 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Status - 3 - 3 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - PET - Parity Error Trap Status - 4 - 4 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BRWNT - Brown Out Trap Status - 5 - 5 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Status - 6 - 6 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Status - 7 - 7 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Status - 8 - 8 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - - - TRAPRAW - Trap Raw Status Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Raw Status - 0 - 0 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Raw Status - 2 - 2 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Raw Status - 3 - 3 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - PET - Parity Error Trap Raw Status - 4 - 4 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BRWNT - Brown Out Trap Raw Status - 5 - 5 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Raw Status - 6 - 6 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Raw Status - 7 - 7 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Raw Status - 8 - 8 - read-only - - - value1 - No pending trap request - 0b0 - - - value2 - Pending trap request - 0b1 - - - - - - - TRAPDIS - Trap Disable Register - 0x08 - 32 - 0x000001FF - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Disable - 0 - 0 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Disable - 2 - 2 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Disable - 3 - 3 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - PET - Parity Error Trap Disable - 4 - 4 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - BRWNT - Brown Out Trap Disable - 5 - 5 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Disable - 6 - 6 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Disable - 7 - 7 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Disable - 8 - 8 - read-write - - - value1 - Trap request enabled - 0b0 - - - value2 - Trap request disabled - 0b1 - - - - - - - TRAPCLR - Trap Clear Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - PET - Parity Error Trap Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - BRWNT - Brown Out Trap Clear - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - ULPWDGT - OSC_ULP Oscillator Watchdog Trap Clear - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Clear - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear trap request - 0b1 - - - - - - - TRAPSET - Trap Set Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SOSCWDGT - OSC_HP Oscillator Watchdog Trap Set - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - SVCOLCKT - System VCO Lock Trap Set - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - UVCOLCKT - USB VCO Lock Trap Set - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - PET - Parity Error Trap Set - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - BRWNT - Brown Out Trap Set - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - ULPWDT - OSC_ULP Oscillator Watchdog Trap Set - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - BWERR0T - Peripheral Bridge 0 Trap Set - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - BWERR1T - Peripheral Bridge 1 Trap Set - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set trap request - 0b1 - - - - - - - - - SCU_HIBERNATE - System Control Unit - SCU - 0x50004300 - - 0x0 - 0x100 - registers - - - - HDSTAT - Hibernate Domain Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPEV - Wake-up Pin Event Positive Edge - 0 - 0 - read-only - - - value1 - Wake-up on positive edge pin event inactive - 0b0 - - - value2 - Wake-up on positive edge pin event active - 0b1 - - - - - ENEV - Wake-up Pin Event Negative Edge - 1 - 1 - read-only - - - value1 - Wake-up on negative edge pin event inactive - 0b0 - - - value2 - Wake-up on negative edge pin event active - 0b1 - - - - - RTCEV - RTC Event - 2 - 2 - read-only - - - value1 - Wake-up on RTC event inactive - 0b0 - - - value2 - Wake-up on RTC event active - 0b1 - - - - - ULPWDG - ULP WDG Alarm Status - 3 - 3 - read-only - - - value1 - Watchdog alarm did not occur - 0b0 - - - value2 - Watchdog alarm occurred - 0b1 - - - - - HIBNOUT - Hibernate Control Status - 4 - 4 - read-only - - - value1 - Hibernate not driven active to pads - 0b0 - - - value2 - Hibernate driven active to pads - 0b1 - - - - - - - HDCLR - Hibernate Domain Status Clear Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPEV - Wake-up Pin Event Positive Edge Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear wake-up event - 0b1 - - - - - ENEV - Wake-up Pin Event Negative Edge Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear wake-up event - 0b1 - - - - - RTCEV - RTC Event Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear wake-up event - 0b1 - - - - - ULPWDG - ULP WDG Alarm Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clear watchdog alarm - 0b1 - - - - - - - HDSET - Hibernate Domain Status Set Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPEV - Wake-up Pin Event Positive Edge Set - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set wake-up event - 0b1 - - - - - ENEV - Wake-up Pin Event Negative Edge Set - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set wake-up event - 0b1 - - - - - RTCEV - RTC Event Set - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set wake-up event - 0b1 - - - - - ULPWDG - ULP WDG Alarm Set - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Set watchdog alarm - 0b1 - - - - - - - HDCR - Hibernate Domain Control Register - 0x0C - 32 - 0x000C2000 - 0xFFFFFFFF - - - WKPEP - Wake-Up on Pin Event Positive Edge Enable - 0 - 0 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - WKPEN - Wake-up on Pin Event Negative Edge Enable - 1 - 1 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - RTCE - Wake-up on RTC Event Enable - 2 - 2 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - ULPWDGEN - ULP WDG Alarm Enable - 3 - 3 - read-write - - - value1 - Wake-up event disabled - 0b0 - - - value2 - Wake-up event enabled - 0b1 - - - - - HIB - Hibernate Request Value Set - 4 - 4 - read-write - - - value1 - External hibernate request inactive - 0b0 - - - value2 - External hibernate request active - 0b1 - - - - - RCS - fRTC Clock Selection - 6 - 6 - read-write - - - value1 - fOSI selected - 0b0 - - - value2 - fULP selected - 0b1 - - - - - STDBYSEL - fSTDBY Clock Selection - 7 - 7 - read-write - - - value1 - fOSI selected - 0b0 - - - value2 - fULP selected - 0b1 - - - - - WKUPSEL - Wake-Up from Hibernate Trigger Input Selection - 8 - 8 - read-write - - - value1 - HIB_IO_1 pin selected - 0b0 - - - value2 - HIB_IO_0 pin selected - 0b1 - - - - - GPI0SEL - General Purpose Input 0 Selection - 10 - 10 - read-write - - - value1 - HIB_IO_1 pin selected - 0b0 - - - value2 - HIB_IO_0 pin selected - 0b1 - - - - - HIBIO0POL - HIBIO0 Polarity Set - 12 - 12 - read-write - - - value1 - Direct value - 0b0 - - - value2 - Inverted value - 0b1 - - - - - HIBIO1POL - HIBIO1 Polarity Set - 13 - 13 - read-write - - - value1 - Direct value - 0b0 - - - value2 - Inverted value - 0b1 - - - - - HIBIO0SEL - HIB_IO_0 Pin I/O Control (default HIBOUT) - 16 - 19 - read-write - - - value1 - Direct input, No input pull device connected - 0b0000 - - - value2 - Direct input, Input pull-down device connected - 0b0001 - - - value3 - Direct input, Input pull-up device connected - 0b0010 - - - value4 - Push-pull HIB Control output - 0b1000 - - - value5 - Push-pull WDT service output - 0b1001 - - - value6 - Push-pull GPIO output - 0b1010 - - - value7 - Open-drain HIB Control output - 0b1100 - - - value8 - Open-drain WDT service output - 0b1101 - - - value9 - Open-drain GPIO output - 0b1110 - - - - - HIBIO1SEL - HIB_IO_1 Pin I/O Control (Default WKUP) - 20 - 23 - read-write - - - value1 - Direct input, No input pull device connected - 0b0000 - - - value2 - Direct input, Input pull-down device connected - 0b0001 - - - value3 - Direct input, Input pull-up device connected - 0b0010 - - - value4 - Push-pull HIB Control output - 0b1000 - - - value5 - Push-pull WDT service output - 0b1001 - - - value6 - Push-pull GPIO output - 0b1010 - - - value7 - Open-drain HIB Control output - 0b1100 - - - value8 - Open-drain WDT service output - 0b1101 - - - value9 - Open-drain GPIO output - 0b1110 - - - - - - - OSCSICTRL - fOSI Control Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - PWD - Turn OFF the fOSI Clock Source - 0 - 0 - read-write - - - value1 - Enabled - 0b0 - - - value2 - Disabled - 0b1 - - - - - - - OSCULSTAT - OSC_ULP Status Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - X1D - XTAL1 Data Value - 0 - 0 - read-only - - - - - OSCULCTRL - OSC_ULP Control Register - 0x1C - 32 - 0x00000020 - 0xFFFFFFFF - - - X1DEN - XTAL1 Data General Purpose Input Enable - 0 - 0 - read-write - - - value1 - Data input inactivated, power down - 0b0 - - - value2 - Data input active - 0b1 - - - - - MODE - Oscillator Mode - 4 - 5 - read-write - - - value1 - Oscillator is enabled, in operation - 0b00 - - - value2 - Oscillator is enabled, in bypass mode - 0b01 - - - value3 - Oscillator in power down - 0b10 - - - value4 - Oscillator in power down, can be used as GPI - 0b11 - - - - - - - - - SCU_POWER - System Control Unit - SCU - 0x50004200 - - 0x0 - 0x100 - registers - - - - PWRSTAT - PCU Status Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIBEN - Hibernate Domain Enable Status - 0 - 0 - read-only - - - value1 - Inactive - 0b0 - - - value2 - Active - 0b1 - - - - - USBPHYPDQ - USB PHY Transceiver State - 16 - 16 - read-only - - - value1 - Power-down - 0b0 - - - value2 - Active - 0b1 - - - - - USBOTGEN - USB On-The-Go Comparators State - 17 - 17 - read-only - - - value1 - Power-down - 0b0 - - - value2 - Active - 0b1 - - - - - USBPUWQ - USB Weak Pull-Up at PADN State - 18 - 18 - read-only - - - value1 - Pull-up active - 0b0 - - - value2 - Pull-up not active - 0b1 - - - - - - - PWRSET - PCU Set Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIB - Set Hibernate Domain Enable - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable Hibernate domain - 0b1 - - - - - USBPHYPDQ - Set USB PHY Transceiver Disable - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Active - 0b1 - - - - - USBOTGEN - Set USB On-The-Go Comparators Enable - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - Active - 0b1 - - - - - USBPUWQ - Set USB Weak Pull-Up at PADN Enable - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - Pull-up not active - 0b1 - - - - - - - PWRCLR - PCU Clear Control Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIB - Clear Disable Hibernate Domain - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable Hibernate domain - 0b1 - - - - - USBPHYPDQ - Clear USB PHY Transceiver Disable - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Power-down - 0b1 - - - - - USBOTGEN - Clear USB On-The-Go Comparators Enable - 17 - 17 - write-only - - - value1 - No effect - 0b0 - - - value2 - Power-down - 0b1 - - - - - USBPUWQ - Clear USB Weak Pull-Up at PADN Enable - 18 - 18 - write-only - - - value1 - No effect - 0b0 - - - value2 - Pull-up active - 0b1 - - - - - - - EVRSTAT - EVR Status Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - OV13 - Regulator Overvoltage for 1.3 V - 1 - 1 - read-only - - - value1 - No overvoltage condition - 0b0 - - - value2 - Regulator is in overvoltage - 0b1 - - - - - - - EVRVADCSTAT - EVR VADC Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VADC13V - VADC 1.3 V Conversion Result - 0 - 7 - read-only - - - VADC33V - VADC 3.3 V Conversion Result - 8 - 15 - read-only - - - - - PWRMON - Power Monitor Control - 0x2C - 32 - 0x00000000 - 0xFFFFFFFF - - - THRS - Threshold - 0 - 7 - read-write - - - INTV - Interval - 8 - 15 - read-write - - - ENB - Enable - 16 - 16 - read-write - - - - - - - SCU_RESET - System Control Unit - SCU - 0x50004400 - - 0x0 - 0x100 - registers - - - - RSTSTAT - RCU Reset Status - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSTSTAT - Reset Status Information - 0 - 7 - read-only - - - value1 - PORST reset - 0b00000001 - - - value2 - SWD reset - 0b00000010 - - - value3 - PV reset - 0b00000100 - - - value4 - CPU system reset - 0b00001000 - - - value5 - CPU lockup reset - 0b00010000 - - - value6 - WDT reset - 0b00100000 - - - value7 - Reserved - 0b01000000 - - - value8 - Parity Error reset - 0b10000000 - - - - - HIBWK - Hibernate Wake-up Status - 8 - 8 - read-only - - - value1 - No Wake-up - 0b0 - - - value2 - Wake-up event - 0b1 - - - - - HIBRS - Hibernate Reset Status - 9 - 9 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - LCKEN - Enable Lockup Status - 10 - 10 - read-only - - - value1 - Reset by Lockup disabled - 0b0 - - - value2 - Reset by Lockup enabled - 0b1 - - - - - - - RSTSET - RCU Reset Set Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIBWK - Set Hibernate Wake-up Reset Status - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset status bit - 0b1 - - - - - HIBRS - Set Hibernate Reset - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - LCKEN - Enable Lockup Reset - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - Enable reset when Lockup gets asserted - 0b1 - - - - - - - RSTCLR - RCU Reset Clear Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSCLR - Clear Reset Status - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Clears field RSTSTAT.RSTSTAT - 0b1 - - - - - HIBWK - Clear Hibernate Wake-up Reset Status - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset status bit - 0b1 - - - - - HIBRS - Clear Hibernate Reset - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - LCKEN - Enable Lockup Reset - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - Disable reset when Lockup gets asserted - 0b1 - - - - - - - PRSTAT0 - RCU Peripheral 0 Reset Status - 0x0C - 32 - 0x00010F9F - 0xFFFFFFFF - - - VADCRS - VADC Reset Status - 0 - 0 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DSDRS - DSD Reset Status - 1 - 1 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU40RS - CCU40 Reset Status - 2 - 2 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU41RS - CCU41 Reset Status - 3 - 3 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU42RS - CCU42 Reset Status - 4 - 4 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU80RS - CCU80 Reset Status - 7 - 7 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - CCU81RS - CCU81 Reset Status - 8 - 8 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - POSIF0RS - POSIF0 Reset Status - 9 - 9 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - POSIF1RS - POSIF1 Reset Status - 10 - 10 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USIC0RS - USIC0 Reset Status - 11 - 11 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - ERU1RS - ERU1 Reset Status - 16 - 16 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET0 - RCU Peripheral 0 Reset Set - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VADCRS - VADC Reset Assert - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DSDRS - DSD Reset Assert - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU40RS - CCU40 Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU41RS - CCU41 Reset Assert - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU42RS - CCU42 Reset Assert - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU80RS - CCU80 Reset Assert - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - CCU81RS - CCU81 Reset Assert - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - POSIF0RS - POSIF0 Reset Assert - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - POSIF1RS - POSIF1 Reset Assert - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USIC0RS - USIC0 Reset Assert - 11 - 11 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - ERU1RS - ERU1 Reset Assert - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR0 - RCU Peripheral 0 Reset Clear - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VADCRS - VADC Reset Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DSDRS - DSD Reset Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU40RS - CCU40 Reset Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU41RS - CCU41 Reset Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU42RS - CCU42 Reset Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU80RS - CCU80 Reset Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - CCU81RS - CCU81 Reset Clear - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - POSIF0RS - POSIF0 Reset Clear - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - POSIF1RS - POSIF1 Reset Clear - 10 - 10 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USIC0RS - USIC0 Reset Clear - 11 - 11 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - ERU1RS - ERU1 Reset Clear - 16 - 16 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - PRSTAT1 - RCU Peripheral 1 Reset Status - 0x18 - 32 - 0x000001F9 - 0xFFFFFFFF - - - CCU43RS - CCU43 Reset Status - 0 - 0 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - LEDTSCU0RS - LEDTS Reset Status - 3 - 3 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - MCAN0RS - MultiCAN Reset Status - 4 - 4 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DACRS - DAC Reset Status - 5 - 5 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - MMCIRS - MMC Interface Reset Status - 6 - 6 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USIC1RS - USIC1 Reset Status - 7 - 7 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USIC2RS - USIC2 Reset Status - 8 - 8 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - PPORTSRS - PORTS Reset Status - 9 - 9 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET1 - RCU Peripheral 1 Reset Set - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - CCU43RS - CCU43 Reset Assert - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - LEDTSCU0RS - LEDTS Reset Assert - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - MCAN0RS - MultiCAN Reset Assert - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DACRS - DAC Reset Assert - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - MMCIRS - MMC Interface Reset Assert - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USIC1RS - USIC1 Reset Assert - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USIC2RS - USIC2 Reset Assert - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - PPORTSRS - PORTS Reset Assert - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR1 - RCU Peripheral 1 Reset Clear - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CCU43RS - CCU43 Reset Clear - 0 - 0 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - LEDTSCU0RS - LEDTS Reset Clear - 3 - 3 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - MCAN0RS - MultiCAN Reset Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DACRS - DAC Reset Clear - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - MMCIRS - MMC Interface Reset Clear - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USIC1RS - USIC1 Reset Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USIC2RS - USIC2 Reset Clear - 8 - 8 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - PPORTSRS - PORTS Reset Clear - 9 - 9 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - PRSTAT2 - RCU Peripheral 2 Reset Status - 0x24 - 32 - 0x000000F6 - 0xFFFFFFFF - - - WDTRS - WDT Reset Status - 1 - 1 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - ETH0RS - ETH0 Reset Status - 2 - 2 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DMA0RS - DMA0 Reset Status - 4 - 4 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - DMA1RS - DMA1 Reset Status - 5 - 5 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - FCERS - FCE Reset Status - 6 - 6 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - USBRS - USB Reset Status - 7 - 7 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET2 - RCU Peripheral 2 Reset Set - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDTRS - WDT Reset Assert - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - ETH0RS - ETH0 Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DMA0RS - DMA0 Reset Assert - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - DMA1RS - DMA1 Reset Assert - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - FCERS - FCE Reset Assert - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - USBRS - USB Reset Assert - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR2 - RCU Peripheral 2 Reset Clear - 0x2C - 32 - 0x00000000 - 0xFFFFFFFF - - - WDTRS - WDT Reset Clear - 1 - 1 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - ETH0RS - ETH0 Reset Clear - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DMA0RS - DMA0 Reset Clear - 4 - 4 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - DMA1RS - DMA1 Reset Clear - 5 - 5 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - FCERS - FCE Reset Clear - 6 - 6 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - USBRS - USB Reset Clear - 7 - 7 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - PRSTAT3 - RCU Peripheral 3 Reset Status - 0x30 - 32 - 0x00000004 - 0xFFFFFFFF - - - EBURS - EBU Reset Status - 2 - 2 - read-only - - - value1 - Reset de-asserted - 0b0 - - - value2 - Reset asserted - 0b1 - - - - - - - PRSET3 - RCU Peripheral 3 Reset Set - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - EBURS - EBU Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - Assert reset - 0b1 - - - - - - - PRCLR3 - RCU Peripheral 3 Reset Clear - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - EBURS - EBU Reset Assert - 2 - 2 - write-only - - - value1 - No effect - 0b0 - - - value2 - De-assert reset - 0b1 - - - - - - - - - LEDTS0 - LED and Touch Sense Unit 0 - LEDTS - 0x48010000 - - 0x0 - 0x0100 - registers - - - - ID - Module Identification Register - 0x0000 - 32 - 0x00ABC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - GLOBCTL - Global Control Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - TS_EN - Touch-Sense Function Enable - 0 - 0 - read-write - - - LD_EN - LED Function Enable - 1 - 1 - read-write - - - CMTR - Clock Master Disable - 2 - 2 - read-write - - - value1 - Kernel generates its own clock for LEDTS-counter based on SFR setting - 0b0 - - - value2 - LEDTS-counter takes its clock from another master kernel - 0b1 - - - - - ENSYNC - Enable Autoscan Time Period Synchronization - 3 - 3 - read-write - - - value1 - No synchronization - 0b0 - - - value2 - Synchronization enabled on Kernel0 autoscan time period - 0b1 - - - - - SUSCFG - Suspend Request Configuration - 8 - 8 - read-write - - - value1 - Ignore suspend request - 0b0 - - - value2 - Enable suspend according to request - 0b1 - - - - - MASKVAL - Mask Number of LSB Bits for Event Validation - 9 - 11 - read-write - - - value1 - Mask LSB bit - 0 - - - value2 - Mask 2 LSB bits - 1 - - - value3 - Mask 8 LSB bits - 7 - - - - - FENVAL - Enable (Extended) Time Frame Validation - 12 - 12 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ITS_EN - Enable Time Slice Interrupt - 13 - 13 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ITF_EN - Enable (Extended) Time Frame Interrupt - 14 - 14 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - ITP_EN - Enable Autoscan Time Period Interrupt - 15 - 15 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable (valid only for case of hardware-enabled pad turn control) - 0b1 - - - - - CLK_PS - LEDTS-Counter Clock Pre-Scale Factor - 16 - 31 - read-write - - - value1 - No clock - 0 - - - value2 - Divide by 1 - 1 - - - value3 - Divide by 65535 - 65535 - - - - - - - FNCTL - Function Control Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - PADT - Touch-Sense TSIN Pad Turn - 0 - 2 - read-write - - - value1 - TSIN0 - 0 - - - value2 - TSIN7 - 7 - - - - - PADTSW - Software Control for Touch-Sense Pad Turn - 3 - 3 - read-write - - - value1 - The hardware automatically enables the touch-sense inputs in sequence round-robin, starting from TSIN0. - 0b0 - - - value2 - Disable hardware control for software control only. The touch-sense input is configured in bit PADT. - 0b1 - - - - - EPULL - Enable External Pull-up Configuration on Pin COLA - 4 - 4 - read-write - - - value1 - HW over-rule to enable internal pull-up is active on TSIN[x] for set duration in touch-sense time slice. With this setting, it is not specified to assign the COLA to any pin. - 0b0 - - - value2 - Enable external pull-up: Output 1 on pin COLA for whole duration of touch-sense time slice. - 0b1 - - - - - FNCOL - Previous Active Function/LED Column Status - 5 - 7 - read-only - - - ACCCNT - Accumulate Count on Touch-Sense Input - 16 - 19 - read-write - - - value1 - 1 time - 0 - - - value2 - 2 times - 1 - - - value3 - 16 times - 15 - - - - - TSCCMP - Common Compare Enable for Touch-Sense - 20 - 20 - read-write - - - value1 - Disable common compare for touch-sense - 0b0 - - - value2 - Enable common compare for touch-sense - 0b1 - - - - - TSOEXT - Extension for Touch-Sense Output for Pin-Low-Level - 21 - 22 - read-write - - - value1 - Extend by 1 ledts_clk - 0b00 - - - value2 - Extend by 4 ledts_clk - 0b01 - - - value3 - Extend by 8 ledts_clk - 0b10 - - - value4 - Extend by 16 ledts_clk - 0b11 - - - - - TSCTRR - TS-Counter Auto Reset - 23 - 23 - read-write - - - value1 - Disable TS-counter automatic reset - 0b0 - - - value2 - Enable TS-counter automatic reset to 00H on the first pad turn of a new TSIN[x]. Triggered on compare match in time slice. - 0b1 - - - - - TSCTRSAT - Saturation of TS-Counter - 24 - 24 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable. TS-counter stops counting in the touch-sense time slice(s) of the same (extended) frame when it reaches FFH. Counter starts to count again on the first pad turn of a new TSIN[x], triggered on compare match. - 0b1 - - - - - NR_TSIN - Number of Touch-Sense Input - 25 - 27 - read-write - - - value1 - 1 - 0 - - - value2 - 8 - 7 - - - - - COLLEV - Active Level of LED Column - 28 - 28 - read-write - - - value1 - Active low - 0b0 - - - value2 - Active high - 0b1 - - - - - NR_LEDCOL - Number of LED Columns - 29 - 31 - read-write - - - value1 - 1 LED column - 0b000 - - - value2 - 2 LED columns - 0b001 - - - value3 - 3 LED columns - 0b010 - - - value4 - 4 LED columns - 0b011 - - - value5 - 5 LED columns - 0b100 - - - value6 - 6 LED columns - 0b101 - - - value7 - 7 LED columns - 0b110 - - - value8 - 8 LED columns (max. LED columns = 7 if bit TS_EN = 1) - 0b111 - - - - - - - EVFR - Event Flag Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - TSF - Time Slice Interrupt Flag - 0 - 0 - read-only - - - TFF - (Extended) Time Frame Interrupt Flag - 1 - 1 - read-only - - - TPF - Autoscan Time Period Interrupt Flag - 2 - 2 - read-only - - - TSCTROVF - TS-Counter Overflow Indication - 3 - 3 - read-only - - - value1 - No overflow has occurred. - 0b0 - - - value2 - The TS-counter has overflowed at least once. - 0b1 - - - - - CTSF - Clear Time Slice Interrupt Flag - 16 - 16 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TSF is cleared. - 0b1 - - - - - CTFF - Clear (Extended) Time Frame Interrupt Flag - 17 - 17 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TFF is cleared. - 0b1 - - - - - CTPF - Clear Autoscan Time Period Interrupt Flag - 18 - 18 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TPF is cleared. - 0b1 - - - - - - - TSVAL - Touch-sense TS-Counter Value - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSCTRVALR - Shadow TS-Counter (Read) - 0 - 15 - read-only - - - TSCTRVAL - TS-Counter Value - 16 - 31 - read-write - - - - - LINE0 - Line Pattern Register 0 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINE_0 - Output on LINE[x] - 0 - 7 - read-write - - - LINE_1 - Output on LINE[x] - 8 - 15 - read-write - - - LINE_2 - Output on LINE[x] - 16 - 23 - read-write - - - LINE_3 - Output on LINE[x] - 24 - 31 - read-write - - - - - LINE1 - Line Pattern Register 1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINE_4 - Output on LINE[x] - 0 - 7 - read-write - - - LINE_5 - Output on LINE[x] - 8 - 15 - read-write - - - LINE_6 - Output on LINE[x] - 16 - 23 - read-write - - - LINE_A - Output on LINE[x] - 24 - 31 - read-write - - - - - LDCMP0 - LED Compare Register 0 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_LD0 - Compare Value for LED COL[x] - 0 - 7 - read-write - - - CMP_LD1 - Compare Value for LED COL[x] - 8 - 15 - read-write - - - CMP_LD2 - Compare Value for LED COL[x] - 16 - 23 - read-write - - - CMP_LD3 - Compare Value for LED COL[x] - 24 - 31 - read-write - - - - - LDCMP1 - LED Compare Register 1 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_LD4 - Compare Value for LED COL[x] - 0 - 7 - read-write - - - CMP_LD5 - Compare Value for LED COL[x] - 8 - 15 - read-write - - - CMP_LD6 - Compare Value for LED COL[x] - 16 - 23 - read-write - - - CMP_LDA_TSCOM - Compare Value for LED COLA / Common Compare Value for Touch-sense Pad Turns - 24 - 31 - read-write - - - - - TSCMP0 - Touch-sense Compare Register 0 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_TS0 - Compare Value for Touch-Sense TSIN[x] - 0 - 7 - read-write - - - CMP_TS1 - Compare Value for Touch-Sense TSIN[x] - 8 - 15 - read-write - - - CMP_TS2 - Compare Value for Touch-Sense TSIN[x] - 16 - 23 - read-write - - - CMP_TS3 - Compare Value for Touch-Sense TSIN[x] - 24 - 31 - read-write - - - - - TSCMP1 - Touch-sense Compare Register 1 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_TS4 - Compare Value for Touch-Sense TSIN[x] - 0 - 7 - read-write - - - CMP_TS5 - Compare Value for Touch-Sense TSIN[x] - 8 - 15 - read-write - - - CMP_TS6 - Compare Value for Touch-Sense TSIN[x] - 16 - 23 - read-write - - - CMP_TS7 - Compare Value for Touch-Sense TSIN[x] - 24 - 31 - read-write - - - - - - - SDMMC - SD and Multimediacard Interface - 0x4801C000 - - 0x0 - 0x4000 - registers - - - - BLOCK_SIZE - Block Size Register - 0x0004 - 16 - 0x0000 - 0xFFFF - - - TX_BLOCK_SIZE_12 - Transfer Block Size 12th bit. - 15 - 15 - read-write - - - TX_BLOCK_SIZE - Transfer Block Size - 0 - 11 - read-write - - - value1 - No Data Transfer - 0x0000 - - - value2 - 1 Byte - 0x0001 - - - value3 - 2 Bytes - 0x0002 - - - value4 - 3 Bytes - 0x0003 - - - value5 - 4 Bytes - 0x0004 - - - value6 - 511 Bytes - 0x01FF - - - value7 - 512 Bytes (Maximum Block Size) - 0x0200 - - - - - - - BLOCK_COUNT - Block Count Register - 0x0006 - 16 - 0x0000 - 0xFFFF - - - BLOCK_COUNT - Blocks Count for Current Transfer - 0 - 15 - read-write - - - value1 - Stop Count - 0x0000 - - - value2 - 1 block - 0x0001 - - - value3 - 2 blocks - 0x0002 - - - value4 - 65535 blocks - 0xFFFF - - - - - - - ARGUMENT1 - Argument1 Register - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMENT1 - Command Argument - 0 - 31 - read-write - - - - - TRANSFER_MODE - Transfer Mode Register - 0x000C - 16 - 0x0000 - 0xFFFF - - - CMD_COMP_ATA - Command Completion Signal Enable for CE-ATA Device - 6 - 6 - read-write - - - value1 - Device will send command completion Signal - 0b1 - - - value2 - Device will not send command completion Signal - 0b0 - - - - - MULTI_BLOCK_SELECT - Multi / Single Block Select - 5 - 5 - read-write - - - value1 - Single Block - 0b0 - - - value2 - Multiple Block - 0b1 - - - - - TX_DIR_SELECT - Data Transfer Direction Select - 4 - 4 - read-write - - - value1 - Write (Host to Card) - 0b0 - - - value2 - Read (Card to Host) - 0b1 - - - - - ACMD_EN - Auto CMD Enable - 2 - 3 - read-write - - - value1 - Auto Command Disabled - 0b00 - - - value2 - Auto CMD12 Enable - 0b01 - - - - - BLOCK_COUNT_EN - Block Count Enable - 1 - 1 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - COMMAND - Command Register - 0x000E - 16 - 0x0000 - 0xFFFF - - - CMD_IND - Command Index - 8 - 13 - read-write - - - CMD_TYPE - Command Type - 6 - 7 - read-write - - - value1 - Normal - 0b00 - - - value2 - Suspend - 0b01 - - - value3 - Resume - 0b10 - - - value4 - Abort - 0b11 - - - - - DATA_PRESENT_SELECT - Data Present Select - 5 - 5 - read-write - - - value1 - No Data Present - 0b0 - - - value2 - Data Present - 0b1 - - - - - CMD_IND_CHECK_EN - Command Index Check Enable - 4 - 4 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - CMD_CRC_CHECK_EN - Command CRC Check Enable - 3 - 3 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - RESP_TYPE_SELECT - Response Type Select - 0 - 1 - read-write - - - value1 - No Response - 0b00 - - - value2 - Response length 136 - 0b01 - - - value3 - Response length 48 - 0b10 - - - value4 - Response length 48 check Busy after response - 0b11 - - - - - - - RESPONSE0 - Response 0 Register - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE1 - Response1 - 16 - 31 - read-only - - - RESPONSE0 - Response0 - 0 - 15 - read-only - - - - - RESPONSE2 - Response 2 Register - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE3 - Response3 - 16 - 31 - read-only - - - RESPONSE2 - Response2 - 0 - 15 - read-only - - - - - RESPONSE4 - Response 4 Register - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE5 - Response5 - 16 - 31 - read-only - - - RESPONSE4 - Response4 - 0 - 15 - read-only - - - - - RESPONSE6 - Response 6 Register - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - RESPONSE7 - Response7 - 16 - 31 - read-only - - - RESPONSE6 - Response6 - 0 - 15 - read-only - - - - - DATA_BUFFER - Data Buffer Register - 0x0020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_BUFFER - Data Buffer - 0 - 31 - read-write - - - - - PRESENT_STATE - Present State Register - 0x0024 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT_7_4_PIN_LEVEL - Line Signal Level - 25 - 28 - read-only - - - CMD_LINE_LEVEL - CMD Line Signal Level - 24 - 24 - read-only - - - DAT_3_0_PIN_LEVEL - Line Signal Level - 20 - 23 - read-only - - - WRITE_PROTECT_PIN_LEVEL - Write Protect Switch Pin Level - 19 - 19 - read-only - - - value1 - Write protected (SDWP = 1) - 0b0 - - - value2 - Write enabled (SDWP = 0) - 0b1 - - - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level - 18 - 18 - read-only - - - value1 - No Card present (SDCD = 1) - 0b0 - - - value2 - Card present (SDCD = 0) - 0b1 - - - - - CARD_STATE_STABLE - Card State Stable - 17 - 17 - read-only - - - value1 - Reset of Debouncing - 0b0 - - - value2 - No Card or Inserted - 0b1 - - - - - CARD_INSERTED - Card Inserted - 16 - 16 - read-only - - - value1 - Reset or Debouncing or No Card - 0b0 - - - value2 - Card Inserted - 0b1 - - - - - BUFFER_READ_ENABLE - Buffer Read Enable - 11 - 11 - read-only - - - value1 - Read Disable - 0b0 - - - value2 - Read Enable. - 0b1 - - - - - BUFFER_WRITE_ENABLE - Buffer Write Enable - 10 - 10 - read-only - - - value1 - Write Disable - 0b0 - - - value2 - Write Enable. - 0b1 - - - - - READ_TRANSFER_ACTIVE - Read Transfer Active - 9 - 9 - read-only - - - value1 - No valid data - 0b0 - - - value2 - Transferring data - 0b1 - - - - - WRITE_TRANSFER_ACTIVE - Write Transfer Active - 8 - 8 - read-only - - - value1 - No valid data - 0b0 - - - value2 - Transferring data - 0b1 - - - - - DAT_LINE_ACTIVE - DAT Line Active - 2 - 2 - read-only - - - value1 - DAT line inactive - 0b0 - - - value2 - DAT line active - 0b1 - - - - - COMMAND_INHIBIT_DAT - Command Inhibit (DAT) - 1 - 1 - read-only - - - value1 - Can issue command which uses the DAT line - 0b0 - - - value2 - Cannot issue command which uses the DAT line - 0b1 - - - - - COMMAND_INHIBIT_CMD - Command Inhibit (CMD) - 0 - 0 - read-only - - - - - HOST_CTRL - Host Control Register - 0x0028 - 8 - 0x00 - 0xFF - - - CARD_DET_SIGNAL_DETECT - Card detect signal detetction - 7 - 7 - read-write - - - value1 - SDCD is selected (for normal use) - 0b0 - - - value2 - The card detect test level is selected - 0b1 - - - - - CARD_DETECT_TEST_LEVEL - Card Detect Test Level - 6 - 6 - read-write - - - value1 - No Card - 0b0 - - - value2 - Card Inserted - 0b1 - - - - - HIGH_SPEED_EN - High Speed Enable - 2 - 2 - read-write - - - value1 - Normal Speed Mode - 0b0 - - - value2 - High Speed Mode - 0b1 - - - - - DATA_TX_WIDTH - Data Transfer Width (SD1 or SD4) - 1 - 1 - read-write - - - value1 - 1 bit mode - 0b0 - - - value2 - 4-bit mode - 0b1 - - - - - LED_CTRL - LED Control - 0 - 0 - read-write - - - value1 - LED off - 0b0 - - - value2 - LED on - 0b1 - - - - - - - POWER_CTRL - Power Control Register - 0x0029 - 8 - 0x00 - 0xFF - - - HARDWARE_RESET - Hardware reset - 4 - 4 - read-write - - - SD_BUS_VOLTAGE_SEL - SD Bus Voltage Select - 1 - 3 - read-write - - - value1 - 3.3V (Flattop.) - 0b111 - - - - - SD_BUS_POWER - SD Bus Power - 0 - 0 - read-write - - - value1 - Power off - 0b0 - - - value2 - Power on - 0b1 - - - - - - - BLOCK_GAP_CTRL - Block Gap Control Register - 0x002A - 8 - 0x00 - 0xFF - - - SPI_MODE - SPI_MODE - 4 - 4 - read-write - - - value1 - SD mode - 0b0 - - - value2 - SPI mode - 0b1 - - - - - INT_AT_BLOCK_GAP - Interrupt At Block Gap - 3 - 3 - read-write - - - READ_WAIT_CTRL - Read Wait Control - 2 - 2 - read-write - - - value1 - Disable Read Wait Control - 0b0 - - - value2 - Enable Read Wait Control - 0b1 - - - - - CONTINUE_REQ - Continue Request - 1 - 1 - read-write - - - value1 - Ignored - 0b0 - - - value2 - Restart - 0b1 - - - - - STOP_AT_BLOCK_GAP - Stop At Block Gap Request - 0 - 0 - read-write - - - value1 - Transfer - 0b0 - - - value2 - Stop - 0b1 - - - - - - - WAKEUP_CTRL - Wake-up Control Register - 0x002B - 8 - 0x00 - 0xFF - - - WAKEUP_EVENT_EN_REM - Wakeup Event Enable On SD Card Removal - 2 - 2 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WAKEUP_EVENT_EN_INS - Wakeup Event Enable On SD Card Insertion - 1 - 1 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - WAKEUP_EVENT_EN_INT - Wakeup Event Enable On Card Interrupt - 0 - 0 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - - - CLOCK_CTRL - Clock Control Register - 0x002C - 16 - 0x0000 - 0xFFFF - - - SDCLK_FREQ_SEL - SDCLK Frequency Select - 8 - 15 - read-write - - - value1 - base clock(10MHz-63MHz) - 0x00 - - - value2 - base clock divided by 2 - 0x01 - - - value3 - base clock divided by 32 - 0x10 - - - value4 - base clock divided by 4 - 0x02 - - - value5 - base clock divided by 8 - 0x04 - - - value6 - base clock divided by 16 - 0x08 - - - value7 - base clock divided by 64 - 0x20 - - - value8 - base clock divided by 128 - 0x40 - - - value9 - base clock divided by 256 - 0x80 - - - - - SDCLOCK_EN - SD Clock Enable - 2 - 2 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - INTERNAL_CLOCK_STABLE - Internal Clock Stable - 1 - 1 - read-only - - - value1 - Not Ready - 0b0 - - - value2 - Ready - 0b1 - - - - - INTERNAL_CLOCK_EN - Internal Clock Enable - 0 - 0 - read-write - - - value1 - Stop - 0b0 - - - value2 - Oscillate - 0b1 - - - - - - - TIMEOUT_CTRL - Timeout Control Register - 0x002E - 8 - 0x00 - 0xFF - - - DAT_TIMEOUT_CNT_VAL - Data Timeout Counter Value - 0 - 3 - read-write - - - value1 - TMCLK * 2^13 - 0b0000 - - - value2 - TMCLK * 2^14 - 0b0001 - - - value3 - TMCLK * 2^27 - 0b1110 - - - value4 - Reserved - 0b1111 - - - - - - - SW_RESET - Software Reset Register - 0x002F - 8 - 0x00 - 0xFF - - - SW_RST_DAT_LINE - Software Reset for DAT Line - 2 - 2 - read-write - - - value1 - Work - 0b0 - - - value2 - Reset - 0b1 - - - - - SW_RST_CMD_LINE - Software Reset for CMD Line - 1 - 1 - read-write - - - value1 - Work - 0b0 - - - value2 - Reset - 0b1 - - - - - SW_RST_ALL - Software Reset for All - 0 - 0 - read-write - - - - - INT_STATUS_NORM - Normal Interrupt Status Register - 0x0030 - 16 - 0x0000 - 0xFFFF - - - ERR_INT - Error Interrupt - 15 - 15 - read-only - - - value1 - No Error. - 0b0 - - - value2 - Error. - 0b1 - - - - - CARD_INT - Card Interrupt - 8 - 8 - read-only - - - value1 - No Card Interrupt - 0b0 - - - value2 - Generate Card Interrupt - 0b1 - - - - - CARD_REMOVAL - Card Removal - 7 - 7 - read-write - - - value1 - Card State Stable or Debouncing - 0b0 - - - value2 - Card Removed - 0b1 - - - - - CARD_INS - Card Insertion - 6 - 6 - read-write - - - value1 - Card State Stable or Debouncing - 0b0 - - - value2 - Card Inserted - 0b1 - - - - - BUFF_READ_READY - Buffer Read Ready - 5 - 5 - read-write - - - value1 - Not Ready to read Buffer. - 0b0 - - - value2 - Ready to read Buffer. - 0b1 - - - - - BUFF_WRITE_READY - Buffer Write Ready - 4 - 4 - read-write - - - value1 - Not Ready to Write Buffer. - 0b0 - - - value2 - Ready to Write Buffer. - 0b1 - - - - - BLOCK_GAP_EVENT - Block Gap Event - 2 - 2 - read-write - - - value1 - No Block Gap Event - 0b0 - - - value2 - Transaction stopped at Block Gap - 0b1 - - - - - TX_COMPLETE - Transfer Complete - 1 - 1 - read-write - - - value1 - No Data Transfer Complete - 0b0 - - - value2 - Data Transfer Complete - 0b1 - - - - - CMD_COMPLETE - Command Complete - 0 - 0 - read-write - - - value1 - No Command Complete - 0b0 - - - value2 - Command Complete - 0b1 - - - - - - - INT_STATUS_ERR - Error Interrupt Status Register - 0x0032 - 16 - 0x0000 - 0xFFFF - - - CEATA_ERR - Ceata Error Status - 13 - 13 - read-write - - - value1 - no error - 0b0 - - - value2 - error - 0b1 - - - - - ACMD_ERR - Auto CMD Error - 8 - 8 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - CURRENT_LIMIT_ERR - Current Limit Error - 7 - 7 - read-write - - - value1 - No Error - 0b0 - - - value2 - Power Fail - 0b1 - - - - - DATA_END_BIT_ERR - Data End Bit Error - 6 - 6 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - DATA_CRC_ERR - Data CRC Error - 5 - 5 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - DATA_TIMEOUT_ERR - Data Timeout Error - 4 - 4 - read-write - - - value1 - No Error - 0b0 - - - value2 - Timeout - 0b1 - - - - - CMD_IND_ERR - Command Index Error - 3 - 3 - read-write - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - CMD_END_BIT_ERR - Command End Bit Error - 2 - 2 - read-write - - - value1 - No Error - 0b0 - - - value2 - End Bit Error Generated - 0b1 - - - - - CMD_CRC_ERR - Command CRC Error - 1 - 1 - read-write - - - value1 - No Error - 0b0 - - - value2 - CRC Error Generated - 0b1 - - - - - CMD_TIMEOUT_ERR - Command Timeout Error - 0 - 0 - read-write - - - value1 - No Error - 0b0 - - - value2 - Timeout - 0b1 - - - - - - - EN_INT_STATUS_NORM - Normal Interrupt Status Enable Register - 0x0034 - 16 - 0x0000 - 0xFFFF - - - FIXED_TO_0 - Fixed to 0 - 15 - 15 - read-only - - - CARD_INT_EN - Card Interrupt Status Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_REMOVAL_EN - Card Removal Status Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_INS_EN - Card Insertion Status Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_READ_READY_EN - Buffer Read Ready Status Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_WRITE_READY_EN - Buffer Write Ready Status Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BLOCK_GAP_EVENT_EN - Block Gap Event Status Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TX_COMPLETE_EN - Transfer Complete Status Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_COMPLETE_EN - Command Complete Status Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - EN_INT_STATUS_ERR - Error Interrupt Status Enable Register - 0x0036 - 16 - 0x0000 - 0xFFFF - - - CEATA_ERR_EN - Ceata Error Status Enable - 13 - 13 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TARGET_RESP_ERR_EN - Target Response Error Status Enable - 12 - 12 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - ACMD_ERR_EN - Auto CMD12 Error Status Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CURRENT_LIMIT_ERR_EN - Current Limit Error Status Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_END_BIT_ERR_EN - Data End Bit Error Status Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_CRC_ERR_EN - Data CRC Error Status Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_TIMEOUT_ERR_EN - Data Timeout Error Status Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_IND_ERR_EN - Command Index Error Status Enable - 3 - 3 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_END_BIT_ERR_EN - Command End Bit Error Status Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_CRC_ERR_EN - Command CRC Error Status Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_TIMEOUT_ERR_EN - Command Timeout Error Status Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - EN_INT_SIGNAL_NORM - Normal Interrupt Signal Enable Register - 0x0038 - 16 - 0x0000 - 0xFFFF - - - FIXED_TO_0 - Fixed to 0 - 15 - 15 - read-only - - - CARD_INT_EN - Card Interrupt Signal Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_REMOVAL_EN - Card Removal Signal Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CARD_INS_EN - Card Insertion Signal Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_READ_READY_EN - Buffer Read Ready Signal Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BUFF_WRITE_READY_EN - Buffer Write Ready Signal Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - BLOCK_GAP_EVENT_EN - Block Gap Event Signal Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TX_COMPLETE_EN - Transfer Complete Signal Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_COMPLETE_EN - Command Complete Signal Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - EN_INT_SIGNAL_ERR - Error Interrupt Signal Enable Register - 0x003A - 16 - 0x0000 - 0xFFFF - - - CEATA_ERR_EN - Ceata Error Signal Enable - 13 - 13 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - TARGET_RESP_ERR_EN - Target Response Error Signal Enable - 12 - 12 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - ACMD_ERR_EN - Auto CMD12 Error Signal Enable - 8 - 8 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CURRENT_LIMIT_ERR_EN - Current Limit Error Signal Enable - 7 - 7 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_END_BIT_ERR_EN - Data End Bit Error Signal Enable - 6 - 6 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_CRC_ERR_EN - Data CRC Error Signal Enable - 5 - 5 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - DATA_TIMEOUT_ERR_EN - Data Timeout Error Signal Enable - 4 - 4 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_IND_ERR_EN - Command Index Error Signal Enable - 3 - 3 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_END_BIT_ERR_EN - Command End Bit Error Signal Enable - 2 - 2 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_CRC_ERR_EN - Command CRC Error Signal Enable - 1 - 1 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - CMD_TIMEOUT_ERR_EN - Command Timeout Error Signal Enable - 0 - 0 - read-write - - - value1 - Masked - 0b0 - - - value2 - Enabled - 0b1 - - - - - - - ACMD_ERR_STATUS - Auto CMD Error Status Register - 0x003C - 16 - 0x0000 - 0xFFFF - - - CMD_NOT_ISSUED_BY_ACMD12_ERR - Command Not Issued By Auto CMD12 Error - 7 - 7 - read-only - - - value1 - No Error - 0b0 - - - value2 - Not Issued - 0b1 - - - - - ACMD_IND_ERR - Auto CMD Index Error - 4 - 4 - read-only - - - value1 - No Error - 0b0 - - - value2 - Error - 0b1 - - - - - ACMD_END_BIT_ERR - Auto CMD End Bit Error - 3 - 3 - read-only - - - value1 - No Error - 0b0 - - - value2 - End Bit Error Generated - 0b1 - - - - - ACMD_CRC_ERR - Auto CMD CRC Error - 2 - 2 - read-only - - - value1 - No Error - 0b0 - - - value2 - CRC Error Generated - 0b1 - - - - - ACMD_TIMEOUT_ERR - Auto CMD Timeout Error - 1 - 1 - read-only - - - value1 - No Error - 0b0 - - - value2 - Timeout - 0b1 - - - - - ACMD12_NOT_EXEC_ERR - Auto CMD12 Not Executed - 0 - 0 - read-only - - - value1 - Executed - 0b0 - - - value2 - Not Executed - 0b1 - - - - - - - FORCE_EVENT_ACMD_ERR_STATUS - Force Event Register for Auto CMD Error Status - 0x0050 - 16 - 0x0000 - 0xFFFF - - - FE_CMD_NOT_ISSUED_ACMD12_ERR - Force Event for CMD not issued by Auto CMD12 Error - 7 - 7 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_IND_ERR - Force Event for Auto CMD Index Error - 4 - 4 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_END_BIT_ERR - Force Event for Auto CMD End bit Error - 3 - 3 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_CRC_ERR - Force Event for Auto CMD CRC Error - 2 - 2 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_TIMEOUT_ERR - Force Event for Auto CMD timeout Error - 1 - 1 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD_NOT_EXEC - Force Event for Auto CMD12 NOT Executed - 0 - 0 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - - - FORCE_EVENT_ERR_STATUS - Force Event Register for Error Interrupt Status - 0x0052 - 16 - 0x0000 - 0xFFFF - - - FE_CEATA_ERR - Force Event for Ceata Error - 13 - 13 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_TARGET_RESPONSE_ERR - Force event for Target Response Error - 12 - 12 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_ACMD12_ERR - Force Event for Auto CMD Error - 8 - 8 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CURRENT_LIMIT_ERR - Force Event for Current Limit Error - 7 - 7 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_DATA_END_BIT_ERR - Force Event for Data End Bit Error - 6 - 6 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_DATA_CRC_ERR - Force Event for Data CRC Error - 5 - 5 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_DATA_TIMEOUT_ERR - Force Event for Data Timeout Error - 4 - 4 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_IND_ERR - Force Event for Command Index Error - 3 - 3 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_END_BIT_ERR - Force Event for Command End Bit Error - 2 - 2 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_CRC_ERR - Force Event for Command CRC Error - 1 - 1 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - FE_CMD_TIMEOUT_ERR - Force Event for Command Timeout Error - 0 - 0 - write-only - - - value1 - No interrupt - 0b0 - - - value2 - Interrupt is generated - 0b1 - - - - - - - DEBUG_SEL - Debug Selection Register - 0x0074 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_SEL - Debug_sel - 0 - 0 - write-only - - - value1 - receiver module and fifo_ctrl module signals are probed out - 0b0 - - - value2 - cmd register, Interrupt status, transmitter module and clk sdcard signals are probed out. - 0b1 - - - - - - - SPI - SPI Interrupt Support Register - 0x00F0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPI_INT_SUPPORT - SPI INT SUPPORT - 0 - 7 - read-write - - - - - SLOT_INT_STATUS - Slot Interrupt Status Register - 0x00FC - 16 - 0x0000 - 0xFFFF - - - SLOT_INT_STATUS - Interrupt Signal for Card Slot - 0 - 7 - read-only - - - value1 - Slot 1 - 0x00 - - - - - - - - - EBU - External Bus Unit - 0x58008000 - - 0x0 - 0x4000 - registers - - - - CLC - EBU Clock Control Register - 0x00 - 32 - 0x00110000 - 0xFFFFFFFF - - - DISR - EBU Disable Request Bit - 0 - 0 - read-write - - - value1 - EBU disable is not requested - 0b0 - - - value2 - EBU disable is requested - 0b1 - - - - - DISS - EBU Disable Status Bit - 1 - 1 - read-only - - - value1 - EBU is enabled (default after reset) - 0b0 - - - value2 - EBU is disabled - 0b1 - - - - - SYNC - EBU Clocking Mode - 16 - 16 - read-write - - - value1 - request EBU to run asynchronously to AHB bus clock and use separate clock source - 0b0 - - - value2 - request EBU to run synchronously to ARM processor (default after reset) - 0b1 - - - - - DIV2 - DIV2 Clocking Mode - 17 - 17 - read-write - - - value1 - standard clocking mode. clock input selected by SYNC bitfield (default after reset). - 0b0 - - - value2 - request EBU to run off AHB bus clock divided by 2. - 0b1 - - - - - EBUDIV - EBU Clock Divide Ratio - 18 - 19 - read-write - - - value1 - request EBU to run off input clock (default after reset) - 0b00 - - - value2 - request EBU to run off input clock divided by 2 - 0b01 - - - value3 - request EBU to run off input clock divided by 3 - 0b10 - - - value4 - request EBU to run off input clock divided by 4 - 0b11 - - - - - SYNCACK - EBU Clocking Mode Status - 20 - 20 - read-only - - - value1 - the EBU is asynchronous to the AHB bus clock and is using a separate clock source - 0b0 - - - value2 - EBU is synchronous to the AHB bus clock (default after reset) - 0b1 - - - - - DIV2ACK - DIV2 Clocking Mode Status - 21 - 21 - read-only - - - value1 - EBU is using standard clocking mode. clock input selected by SYNC bitfield (default after reset). - 0b0 - - - value2 - EBU is running off AHB bus clock divided by 2. - 0b1 - - - - - EBUDIVACK - EBU Clock Divide Ratio Status - 22 - 23 - read-only - - - value1 - EBU is running off input clock (default after reset) - 0b00 - - - value2 - EBU is running off input clock divided by 2 - 0b01 - - - value3 - EBU is running off input clock divided by 3 - 0b10 - - - value4 - EBU is running off input clock divided by 4 - 0b11 - - - - - - - MODCON - EBU Configuration Register - 0x04 - 32 - 0x00000020 - 0xFFFFFFFF - - - STS - Memory Status Bit - 0 - 0 - read-only - - - LCKABRT - Lock Abort - 1 - 1 - read-only - - - SDTRI - SDRAM Tristate - 2 - 2 - read-write - - - value1 - SDRAM control signals are driven by the EBU when the EBU does not own the external bus. SDRAM cannot be shared. - 0b0 - - - value2 - SDRAM control signals are tri-stated by the EBU when the EBU does not own the external bus. The SDRAM can be shared. - 0b1 - - - - - EXTLOCK - External Bus Lock Control - 4 - 4 - read-write - - - value1 - External bus is not locked after the EBU gains ownership - 0b0 - - - value2 - External bus is locked after the EBU gains ownership - 0b1 - - - - - ARBSYNC - Arbitration Signal Synchronization Control - 5 - 5 - read-write - - - value1 - Arbitration inputs are synchronous - 0b0 - - - value2 - Arbitration inputs are asynchronous - 0b1 - - - - - ARBMODE - Arbitration Mode Selection - 6 - 7 - read-write - - - value1 - No Bus arbitration mode selected - 0b00 - - - value2 - Arbiter Mode arbitration mode selected - 0b01 - - - value3 - Participant arbitration mode selected - 0b10 - - - value4 - Sole Master arbitration mode selected - 0b11 - - - - - TIMEOUTC - Bus Time-out Control - 8 - 15 - read-write - - - value1 - Time-out is disabled. - 0x00 - - - value2 - Time-out is generated after 1 8 clock cycles. - 0x01 - - - value3 - Time-out is generated after 255 8 clock cycles. - 0xFF - - - - - LOCKTIMEOUT - Lock Timeout Counter Preload - 16 - 23 - read-write - - - GLOBALCS - Global Chip Select Enable - 24 - 27 - read-write - - - ACCSINH - Access Inhibit request - 28 - 28 - read-write - - - ACCSINHACK - Access inhibit acknowledge - 29 - 29 - read-only - - - ALE - ALE Mode - 31 - 31 - read-write - - - value1 - Output is ADV - 0b0 - - - value2 - Output is ALE - 0b1 - - - - - - - ID - EBU Module Identification Register - 0x08 - 32 - 0x0014C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - USERCON - EBU Test/Control Configuration Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - DIP - Disable Internal Pipelining - 0 - 0 - read-write - - - ADDIO - Address Pins to GPIO Mode - 16 - 24 - read-write - - - value1 - Address Bit is required for addressing memory - 0b0 - - - value2 - Address Bit is available for GPIO function - 0b1 - - - - - ADVIO - ADV Pin to GPIO Mode - 25 - 25 - read-write - - - value1 - ADV pin is required for controlling memory - 0b0 - - - value2 - ADV pin is available for GPIO function - 0b1 - - - - - - - ADDRSEL0 - EBU Address Select Register 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - ADDRSEL1 - EBU Address Select Register 1 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - ADDRSEL2 - EBU Address Select Register 2 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - ADDRSEL3 - EBU Address Select Register 3 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - REGENAB - Memory Region Enable - 0 - 0 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - ALTENAB - Alternate Region Enable - 1 - 1 - read-write - - - value1 - Memory region is disabled (default after reset). - 0b0 - - - value2 - Memory region is enabled. - 0b1 - - - - - WPROT - Memory Region Write Protect - 2 - 2 - read-write - - - value1 - Region is enabled for write accesses - 0b0 - - - value2 - Region is write protected. - 0b1 - - - - - - - BUSRCON0 - EBU Bus Configuration Register - 0x28 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP0 - EBU Bus Read Access Parameter Register - 0x2C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON0 - EBU Bus Write Configuration Register - 0x30 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP0 - EBU Bus Write Access Parameter Register - 0x34 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSRCON1 - EBU Bus Configuration Register - 0x38 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP1 - EBU Bus Read Access Parameter Register - 0x3C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON1 - EBU Bus Write Configuration Register - 0x40 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP1 - EBU Bus Write Access Parameter Register - 0x44 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSRCON2 - EBU Bus Configuration Register - 0x48 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP2 - EBU Bus Read Access Parameter Register - 0x4C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON2 - EBU Bus Write Configuration Register - 0x50 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP2 - EBU Bus Write Access Parameter Register - 0x54 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSRCON3 - EBU Bus Configuration Register - 0x58 - 32 - 0x00D30040 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction is transferred in a single burst. - 0b1 - - - - - BFSSS - Read Single Stage Synchronization: - 4 - 4 - read-write - - - value1 - Two stages of synchronization used. (maximum margin) - 0b0 - - - value2 - One stage of synchronization used. (minimum latency) - 0b1 - - - - - FDBKEN - Burst FLASH Clock Feedback Enable - 5 - 5 - read-write - - - value1 - BFCLK feedback not used. - 0b0 - - - value2 - Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. - 0b1 - - - - - BFCMSEL - Burst Flash Clock Mode Select - 6 - 6 - read-write - - - value1 - Burst Flash Clock runs continuously with values selected by this register - 0b0 - - - value2 - Burst Flash Clock is disabled between accesses - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-write - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - DBA - Disable Burst Address Wrapping - 18 - 18 - read-write - - - value1 - Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. - 0b0 - - - value2 - Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-write - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSRAP3 - EBU Bus Read Access Parameter Register - 0x5C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RDDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - RDRECOVC - Recovery Cycles after Read Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITRDC - Programmed Wait States for read accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Read Accesses - 12 - 15 - read-write - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - BUSWCON3 - EBU Bus Write Configuration Register - 0x60 - 32 - 0x00D30000 - 0xFFFFFFFF - - - FETBLEN - Burst Length for Synchronous Burst - 0 - 2 - read-write - - - value1 - 1 data access (default after reset). - 0b000 - - - value2 - 2 data accesses. - 0b001 - - - value3 - 4 data accesses. - 0b010 - - - value4 - 8 data accesses. - 0b011 - - - - - FBBMSEL - Synchronous burst buffer mode select - 3 - 3 - read-write - - - value1 - Burst buffer length defined by value in FETBLEN (default after reset). - 0b0 - - - value2 - Continuous mode. All data required for transaction transferred in single burst - 0b1 - - - - - NAA - Enable flash non-array access workaround - 7 - 7 - read-only - - - ECSE - Early Chip Select for Synchronous Burst - 16 - 16 - read-write - - - value1 - CS is delayed. - 0b0 - - - value2 - CS is not delayed. - 0b1 - - - - - EBSE - Early Burst Signal Enable for Synchronous Burst - 17 - 17 - read-write - - - value1 - ADV is delayed. - 0b0 - - - value2 - ADV is not delayed. - 0b1 - - - - - WAITINV - Reversed polarity at WAIT - 19 - 19 - read-write - - - value1 - input at WAIT pin is active low (default after reset). - 0b0 - - - value2 - input at WAIT pin is active high. - 0b1 - - - - - BCGEN - Byte Control Signal Control - 20 - 21 - read-write - - - value1 - Byte control signals follow chip select timing. - 0b00 - - - value2 - Byte control signals follow control signal timing (RD, RD/WR) (default after reset). - 0b01 - - - value3 - Byte control signals follow write enable signal timing (RD/WR only). - 0b10 - - - value4 - Reserved. - 0b11 - - - - - PORTW - Device Addressing Mode - 22 - 23 - read-only - - - WAIT - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., - 24 - 25 - read-write - - - AAP - Asynchronous Address phase: - 26 - 26 - read-write - - - value1 - Clock is enabled at beginning of access. - 0b0 - - - value2 - Clock is enabled at after address phase. - 0b1 - - - - - LOCKCS - Lock Chip Select - 27 - 27 - read-write - - - value1 - Chip Select cannot be locked (default after reset). - 0b0 - - - value2 - Chip Select will be automatically locked when written to from the processor data port. - 0b1 - - - - - AGEN - Device Type for Region - 28 - 31 - read-write - - - - - BUSWAP3 - EBU Bus Write Access Parameter Register - 0x64 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - WRDTACS - Recovery Cycles between Different Regions - 0 - 3 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - WRRECOVC - Recovery Cycles after Write Accesses - 4 - 6 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b000 - - - value2 - 1 clock cycle selected. - 0b001 - - - value3 - 6 clock cycles selected. - 0b110 - - - value4 - 7 clock cycles selected. - 0b111 - - - - - WAITWRC - Programmed Wait States for write accesses - 7 - 11 - read-write - - - value1 - 1 wait state. - 0b00000 - - - value2 - 1 wait states. - 0b00001 - - - value3 - 2 wait state. - 0b00010 - - - value4 - 30 wait states. - 0b11110 - - - value5 - 31 wait states. - 0b11111 - - - - - DATAC - Data Hold Cycles for Write Accesses - 12 - 15 - read-write - - - value1 - No Recovery Phase clock cycles available. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - EXTCLOCK - Frequency of external clock at pin BFCLKO - 16 - 17 - read-write - - - value1 - Equal to INT_CLK frequency. - 0b00 - - - value2 - 1/2 of INT_CLK frequency. - 0b01 - - - value3 - 1/3 of INT_CLK frequency. - 0b10 - - - value4 - 1/4 of INT_CLK frequency (default after reset). - 0b11 - - - - - EXTDATA - Extended data - 18 - 19 - read-write - - - value1 - external memory outputs data every BFCLK cycle - 0b00 - - - value2 - external memory outputs data every two BFCLK cycles - 0b01 - - - value3 - external memory outputs data every four BFCLK cycles - 0b10 - - - value4 - external memory outputs data every eight BFCLK cycles - 0b11 - - - - - CMDDELAY - Command Delay Cycles - 20 - 23 - read-write - - - value1 - 0 clock cycle selected. - 0b0000 - - - value2 - 1 clock cycle selected. - 0b0001 - - - value3 - 14 clock cycles selected. - 0b1110 - - - value4 - 15 clock cycles selected. - 0b1111 - - - - - AHOLDC - Address Hold Cycles - 24 - 27 - read-write - - - value1 - 0 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - ADDRC - Address Cycles - 28 - 31 - read-write - - - value1 - 1 clock cycle selected - 0b0000 - - - value2 - 1 clock cycle selected - 0b0001 - - - value3 - 14 clock cycles selected - 0b1110 - - - value4 - 15 clock cycles selected - 0b1111 - - - - - - - SDRMCON - EBU SDRAM Control Register - 0x68 - 32 - 0x80000000 - 0xFFFFFFFF - - - SDCMSEL - SDRAM clock mode select - 31 - 31 - read-write - - - value1 - clock disabled between accesses - 0b1 - - - value2 - clock continuously runs - 0b0 - - - - - PWR_MODE - Power Save Mode used for gated clock mode - 29 - 30 - read-write - - - value1 - precharge before clock stop (default after reset) - 0x0 - - - value2 - auto-precharge before clock stop - 0x1 - - - value3 - active power down (stop clock without precharge) - 0x2 - - - value4 - clock stop power down - 0x3 - - - - - CLKDIS - Disable SDRAM clock output - 28 - 28 - read-write - - - value1 - clock enabled - 0b0 - - - value2 - clock disabled - 0b1 - - - - - CRCE - Row cycle time counter extension - 25 - 27 - read-write - - - BANKM - Mask for bank tag - 22 - 24 - read-write - - - value1 - Reserved; (default after reset) - 0x0 - - - value2 - Address bit 21 to 20 - 0x1 - - - value3 - Address bit 22 to 21 - 0x2 - - - value4 - Address bit 23 to 22 - 0x3 - - - value5 - Address bit 24 to 23 - 0x4 - - - value6 - Address bit 25 to 24 - 0x5 - - - value7 - Address bit 26 to 25 - 0x6 - - - value8 - Address bit 26 - 0x7 - - - - - ROWM - Mask for row tag - 19 - 21 - read-write - - - value1 - reserved; (default after reset) - 0x0 - - - value2 - Address bit 26 to 9 - 0x1 - - - value3 - Address bit 26 to 10 - 0x2 - - - value4 - Address bit 26 to 11 - 0x3 - - - value5 - Address bit 26 to 12 - 0x4 - - - value6 - Address bit 26 to 13 - 0x5 - - - value7 - reserved - 0x6 - - - value8 - reserved - 0x7 - - - - - CRC - Row cycle time counter - 16 - 18 - read-write - - - CRCD - Row to column delay counter - 14 - 15 - read-write - - - AWIDTH - Width of column address - 12 - 13 - read-write - - - value1 - do not use - 0x0 - - - value2 - Address(8:0) - 0x1 - - - value3 - Address(9:0) - 0x2 - - - value4 - Address(10:0) - 0x3 - - - - - CRP - Row precharge time counter - 10 - 11 - read-write - - - CRSC - Mode register set-up time - 8 - 9 - read-write - - - CRFSH - Initialization refresh commands counter - 4 - 7 - read-write - - - CRAS - Row to precharge delay counter - 0 - 3 - read-write - - - - - SDRMOD - EBU SDRAM Mode Register - 0x6C - 32 - 0x00000020 - 0xFFFFFFFF - - - XBA - Extended Operation Bank Select - 28 - 31 - read-write - - - XOPM - Extended Operation Mode - 16 - 27 - read-write - - - COLDSTART - SDRAM coldstart - 15 - 15 - write-only - - - OPMODE - Operation Mode - 7 - 13 - read-write - - - value1 - Only this value must be written (default after reset) - 0b000000 - - - - - CASLAT - CAS latency - 4 - 6 - read-write - - - value1 - Two clocks (default after reset) - 2 - - - value2 - Three clocks - 3 - - - - - BTYP - Burst type - 3 - 3 - read-write - - - value1 - Only this value should be written (default after reset) - 0b0 - - - value2 - Reserved - 0b1 - - - - - BURSTL - Burst length - 0 - 2 - read-write - - - value1 - 1 (default after reset) - 0 - - - value2 - 2 - 1 - - - value3 - 4 - 2 - - - value4 - 8 - 3 - - - value5 - 16 - 4 - - - - - - - SDRMREF - EBU SDRAM Refresh Control Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - RES_DLY - Delay on Power Down Exit - 25 - 27 - read-write - - - ARFSH - Auto Refresh on Self refresh Exit - 24 - 24 - read-write - - - SELFREX_DLY - Self Refresh Exit Delay - 16 - 23 - read-write - - - ERFSHC - Extended Refresh Counter Period - 14 - 15 - read-write - - - AUTOSELFR - Automatic Self Refresh - 13 - 13 - read-write - - - SELFREN - Self Refresh Entry - 12 - 12 - read-write - - - SELFRENST - Self Refresh Entry Status. - 11 - 11 - read-only - - - SELFREX - Self Refresh Exit (Power Up). - 10 - 10 - read-write - - - SELFREXST - Self Refresh Exit Status. - 9 - 9 - read-only - - - REFRESHR - Number of refresh commands - 6 - 8 - read-write - - - REFRESHC - Refresh counter period - 0 - 5 - read-write - - - - - SDRSTAT - EBU SDRAM Status Register - 0x74 - 32 - 0x00010000 - 0xFFFFFFFF - - - SDERR - SDRAM read error - 2 - 2 - read-only - - - value1 - Reads running successfully - 0b0 - - - value2 - Read error condition has been detected - 0b1 - - - - - SDRMBUSY - SDRAM Busy - 1 - 1 - read-only - - - value1 - Power-up initialization sequence is not running - 0b0 - - - value2 - Power-up initialization sequence is running - 0b1 - - - - - REFERR - SDRAM Refresh Error - 0 - 0 - read-only - - - value1 - No refresh error. - 0b0 - - - value2 - Refresh error occurred. - 0b1 - - - - - - - - - ETH0_CON - Ethernet Control Register - ETH - 0x50004040 - - 0 - 4 - registers - - - - ETH0_CON - Ethernet 0 Port Control Register - 0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXD0 - MAC Receive Input 0 - 0 - 1 - read-write - - - value1 - Data input RXD0A is selected - 0b00 - - - value2 - Data input RXD0B is selected - 0b01 - - - value3 - Data input RXD0C is selected - 0b10 - - - value4 - Data input RXD0D is selected - 0b11 - - - - - RXD1 - MAC Receive Input 1 - 2 - 3 - read-write - - - value1 - Data input RXD1A is selected - 0b00 - - - value2 - Data input RXD1B is selected - 0b01 - - - value3 - Data input RXD1C is selected - 0b10 - - - value4 - Data input RXD1D is selected - 0b11 - - - - - RXD2 - MAC Receive Input 2 - 4 - 5 - read-write - - - value1 - Data input RXD2A is selected - 0b00 - - - value2 - Data input RXD2B is selected - 0b01 - - - value3 - Data input RXD2C is selected - 0b10 - - - value4 - Data input RXD2D is selected - 0b11 - - - - - RXD3 - MAC Receive Input 3 - 6 - 7 - read-write - - - value1 - Data input RXD3A is selected - 0b00 - - - value2 - Data input RXD3B is selected - 0b01 - - - value3 - Data input RXD3C is selected - 0b10 - - - value4 - Data input RXD3D is selected - 0b11 - - - - - CLK_RMII - RMII clock input - 8 - 9 - read-write - - - value1 - Data input RMIIA is selected - 0b00 - - - value2 - Data input RMIIB is selected - 0b01 - - - value3 - Data input RMIIC is selected - 0b10 - - - value4 - Data input RMIID is selected - 0b11 - - - - - CRS_DV - CRS_DV input - 10 - 11 - read-write - - - value1 - Data input CRS_DVA is selected - 0b00 - - - value2 - Data input CRS_DVB is selected - 0b01 - - - value3 - Data input CRS_DVC is selected - 0b10 - - - value4 - Data input CRS_DVD is selected - 0b11 - - - - - CRS - CRS input - 12 - 13 - read-write - - - value1 - Data input CRSA - 0b00 - - - value2 - Data input CRSB - 0b01 - - - value3 - Data input CRSC - 0b10 - - - value4 - Data input CRSD - 0b11 - - - - - RXER - RXER Input - 14 - 15 - read-write - - - value1 - Data input RXERA is selected - 0b00 - - - value2 - Data input RXERB is selected - 0b01 - - - value3 - Data input RXERC is selected - 0b10 - - - value4 - Data input RXERD is selected - 0b11 - - - - - COL - COL input - 16 - 17 - read-write - - - value1 - Data input COLA is selected - 0b00 - - - value2 - Data input COLB is selected - 0b01 - - - value3 - Data input COLC is selected - 0b10 - - - value4 - Data input COLD is selected - 0b11 - - - - - CLK_TX - CLK_TX input - 18 - 19 - read-write - - - value1 - Data input CLK_TXA is selected - 0b00 - - - value2 - Data input CLK_TXB is selected - 0b01 - - - value3 - Data input CLK_TXC is selected - 0b10 - - - value4 - Data input CLK_TXD is selected - 0b11 - - - - - MDIO - MDIO Input Select - 22 - 23 - read-write - - - value1 - Data input MDIA is selected - 0b00 - - - value2 - Data input MDIB is selected - 0b01 - - - value3 - Data input MDIC is selected - 0b10 - - - value4 - Data input MDID is selected - 0b11 - - - - - INFSEL - Ethernet MAC Interface Selection - 26 - 26 - read-write - - - value1 - MII - 0b0 - - - value2 - RMII - 0b1 - - - - - - - - - ETH0 - Ethernet Unit 0 - ETH - ETH - 0x5000C000 - - 0x0 - 0x4000 - registers - - - - MAC_CONFIGURATION - MAC Configuration Register - 0x0000 - 32 - 0x00008000 - 0xFFFFFFFF - - - PRELEN - Preamble Length for Transmit Frames - 0 - 1 - read-write - - - RE - Receiver Enable - 2 - 2 - read-write - - - TE - Transmitter Enable - 3 - 3 - read-write - - - DC - Deferral Check - 4 - 4 - read-write - - - BL - Back-Off Limit - 5 - 6 - read-write - - - ACS - Automatic Pad or CRC Stripping - 7 - 7 - read-write - - - Reserved_8 - Reserved - 8 - 8 - read-only - - - DR - Disable Retry - 9 - 9 - read-write - - - IPC - Checksum Offload - 10 - 10 - read-write - - - DM - Duplex Mode - 11 - 11 - read-write - - - LM - Loopback Mode - 12 - 12 - read-write - - - DO - Disable Receive Own - 13 - 13 - read-write - - - FES - Speed - 14 - 14 - read-write - - - Reserved - Reserved - 15 - 15 - read-only - - - DCRS - Disable Carrier Sense During Transmission - 16 - 16 - read-write - - - IFG - Inter-Frame Gap - 17 - 19 - read-write - - - JE - Jumbo Frame Enable - 20 - 20 - read-write - - - BE - Frame Burst Enable - 21 - 21 - read-only - - - JD - Jabber Disable - 22 - 22 - read-write - - - WD - Watchdog Disable - 23 - 23 - read-write - - - TC - Transmit Configuration in RMII - 24 - 24 - read-only - - - CST - CRC Stripping of Type Frames - 25 - 25 - read-write - - - Reserved_26 - Reserved - 26 - 26 - read-only - - - TWOKPE - IEEE 802.3as support for 2K packets Enable - 27 - 27 - read-write - - - SARC - Source Address Insertion or Replacement Control - 28 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - MAC_FRAME_FILTER - MAC Frame Filter - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - PR - Promiscuous Mode - 0 - 0 - read-write - - - HUC - Hash Unicast - 1 - 1 - read-write - - - HMC - Hash Multicast - 2 - 2 - read-write - - - DAIF - DA Inverse Filtering - 3 - 3 - read-write - - - PM - Pass All Multicast - 4 - 4 - read-write - - - DBF - Disable Broadcast Frames - 5 - 5 - read-write - - - PCF - Pass Control Frames - 6 - 7 - read-write - - - SAIF - SA Inverse Filtering - 8 - 8 - read-write - - - SAF - Source Address Filter Enable - 9 - 9 - read-write - - - HPF - Hash or Perfect Filter - 10 - 10 - read-write - - - Reserved_15_11 - Reserved - 11 - 15 - read-only - - - VTFE - VLAN Tag Filter Enable - 16 - 16 - read-write - - - Reserved_19_17 - Reserved - 17 - 19 - read-only - - - IPFE - Layer 3 and Layer 4 Filter Enable - 20 - 20 - read-only - - - DNTU - Drop non-TCP/UDP over IP Frames - 21 - 21 - read-only - - - Reserved_30_22 - Reserved - 22 - 30 - read-only - - - RA - Receive All - 31 - 31 - read-write - - - - - HASH_TABLE_HIGH - Hash Table High Register - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - 0 - 31 - read-write - - - - - HASH_TABLE_LOW - Hash Table Low Register - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - 0 - 31 - read-write - - - - - GMII_ADDRESS - MII Address Register - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - MB - MII Busy - 0 - 0 - read-write - - - MW - MII Write - 1 - 1 - read-write - - - CR - CSR Clock Range - 2 - 5 - read-write - - - MR - MII Register - 6 - 10 - read-write - - - PA - Physical Layer Address - 11 - 15 - read-write - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - GMII_DATA - MII Data Register - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - MD - MII Data - 0 - 15 - read-write - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - FLOW_CONTROL - Flow Control Register - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - FCA_BPA - Flow Control Busy or Backpressure Activate - 0 - 0 - read-write - - - TFE - Transmit Flow Control Enable - 1 - 1 - read-write - - - RFE - Receive Flow Control Enable - 2 - 2 - read-write - - - UP - Unicast Pause Frame Detect - 3 - 3 - read-write - - - PLT - Pause Low Threshold - 4 - 5 - read-write - - - Reserved_6 - Reserved - 6 - 6 - read-only - - - DZPQ - Disable Zero-Quanta Pause - 7 - 7 - read-write - - - Reserved_15_8 - Reserved - 8 - 15 - read-only - - - PT - Pause Time - 16 - 31 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - VL - VLAN Tag Identifier for Receive Frames - 0 - 15 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - 16 - 16 - read-write - - - VTIM - VLAN Tag Inverse Match Enable - 17 - 17 - read-write - - - ESVL - Enable S-VLAN - 18 - 18 - read-write - - - VTHM - VLAN Tag Hash Table Match Enable - 19 - 19 - read-only - - - Reserved_31_20 - Reserved - 20 - 31 - read-only - - - - - VERSION - Version Register - 0x0020 - 32 - 0x00001037 - 0xFFFFFFFF - - - SNPSVER - Synopsys-defined Version (3.7) - 0 - 7 - read-only - - - USERVER - User-defined Version (Configured with the coreConsultant) - 8 - 15 - read-only - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - DEBUG - Debug Register - 0x0024 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPESTS - MAC MII Receive Protocol Engine Status - 0 - 0 - read-only - - - RFCFCSTS - MAC Receive Frame Controller FIFO Status - 1 - 2 - read-only - - - Reserved_3 - Reserved - 3 - 3 - read-only - - - RWCSTS - MTL Rx FIFO Write Controller Active Status - 4 - 4 - read-only - - - RRCSTS - MTL Rx FIFO Read Controller State - 5 - 6 - read-only - - - Reserved_7 - Reserved - 7 - 7 - read-only - - - RXFSTS - MTL Rx FIFO Fill-level Status - 8 - 9 - read-only - - - Reserved_15_10 - Reserved - 10 - 15 - read-only - - - TPESTS - MAC MII Transmit Protocol Engine Status - 16 - 16 - read-only - - - TFCSTS - MAC Transmit Frame Controller Status - 17 - 18 - read-only - - - TXPAUSED - MAC transmitter in PAUSE - 19 - 19 - read-only - - - TRCSTS - MTL Tx FIFO Read Controller Status - 20 - 21 - read-only - - - TWCSTS - MTL Tx FIFO Write Controller Active Status - 22 - 22 - read-only - - - Reserved_23 - Reserved - 23 - 23 - read-only - - - TXFSTS - MTL Tx FIFO Not Empty Status - 24 - 24 - read-only - - - TXSTSFSTS - MTL TxStatus FIFO Full Status - 25 - 25 - read-only - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - REMOTE_WAKE_UP_FRAME_FILTER - Remote Wake Up Frame Filter Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFTR - Remote Wake-Up Frame Filter - 0 - 31 - read-write - - - - - PMT_CONTROL_STATUS - PMT Control and Status Register - 0x002C - 32 - 0x00000000 - 0xFFFFFFFF - - - PWRDWN - Power Down - 0 - 0 - read-write - - - MGKPKTEN - Magic Packet Enable - 1 - 1 - read-write - - - RWKPKTEN - Wake-Up Frame Enable - 2 - 2 - read-write - - - Reserved_4_3 - Reserved - 3 - 4 - read-only - - - MGKPRCVD - Magic Packet Received - 5 - 5 - read-only - - - RWKPRCVD - Wake-Up Frame Received - 6 - 6 - read-only - - - Reserved_8_7 - Reserved - 7 - 8 - read-only - - - GLBLUCAST - Global Unicast - 9 - 9 - read-write - - - Reserved_30_10 - Reserved - 10 - 30 - read-only - - - RWKFILTRST - Wake-Up Frame Filter Register Pointer Reset - 31 - 31 - read-write - - - - - INTERRUPT_STATUS - Interrupt Register - 0x0038 - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_2_0 - Reserved - 0 - 2 - read-only - - - PMTIS - PMT Interrupt Status - 3 - 3 - read-only - - - MMCIS - MMC Interrupt Status - 4 - 4 - read-only - - - MMCRXIS - MMC Receive Interrupt Status - 5 - 5 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status - 6 - 6 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status - 7 - 7 - read-only - - - Reserved_8 - Reserved - 8 - 8 - read-only - - - TSIS - Timestamp Interrupt Status - 9 - 9 - read-only - - - Reserved_10 - Reserved - 10 - 10 - read-only - - - Reserved_31_11 - Reserved - 11 - 31 - read-only - - - - - INTERRUPT_MASK - Interrupt Mask Register - 0x003C - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_2_0 - Reserved - 0 - 2 - read-only - - - PMTIM - PMT Interrupt Mask - 3 - 3 - read-write - - - Reserved_8_4 - Reserved - 4 - 8 - read-only - - - TSIM - Timestamp Interrupt Mask - 9 - 9 - read-write - - - Reserved_31_10 - Reserved - 10 - 31 - read-only - - - - - MAC_ADDRESS0_HIGH - MAC Address0 High Register - 0x0040 - 32 - 0x8000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address0 [47:32] - 0 - 15 - read-write - - - Reserved_30_16 - Reserved - 16 - 30 - read-only - - - AE - Address Enable - 31 - 31 - read-only - - - - - MAC_ADDRESS0_LOW - MAC Address0 Low Register - 0x0044 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - 0 - 31 - read-write - - - - - MAC_ADDRESS1_HIGH - MAC Address1 High Register - 0x0048 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address1 [47:32] - 0 - 15 - read-write - - - Reserved_23_16 - Reserved - 16 - 23 - read-only - - - MBC - Mask Byte Control - 24 - 29 - read-write - - - SA - Source Address - 30 - 30 - read-write - - - AE - Address Enable - 31 - 31 - read-write - - - - - MAC_ADDRESS1_LOW - MAC Address1 Low Register - 0x004C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] - 0 - 31 - read-write - - - - - MAC_ADDRESS2_HIGH - MAC Address2 High Register - 0x0050 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address2 [47:32] - 0 - 15 - read-write - - - Reserved_23_16 - Reserved - 16 - 23 - read-only - - - MBC - Mask Byte Control - 24 - 29 - read-write - - - SA - Source Address - 30 - 30 - read-write - - - AE - Address Enable - 31 - 31 - read-write - - - - - MAC_ADDRESS2_LOW - MAC Address2 Low Register - 0x0054 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address2 [31:0] - 0 - 31 - read-write - - - - - MAC_ADDRESS3_HIGH - MAC Address3 High Register - 0x0058 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - ADDRHI - MAC Address3 [47:32] - 0 - 15 - read-write - - - Reserved_23_16 - Reserved - 16 - 23 - read-only - - - MBC - Mask Byte Control - 24 - 29 - read-write - - - SA - Source Address - 30 - 30 - read-write - - - AE - Address Enable - 31 - 31 - read-write - - - - - MAC_ADDRESS3_LOW - MAC Address3 Low Register - 0x005C - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ADDRLO - MAC Address3 [31:0] - 0 - 31 - read-write - - - - - MMC_CONTROL - MMC Control Register - 0x0100 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTRST - Counters Reset - 0 - 0 - read-write - - - CNTSTOPRO - Counters Stop Rollover - 1 - 1 - read-write - - - RSTONRD - Reset on Read - 2 - 2 - read-write - - - CNTFREEZ - MMC Counter Freeze - 3 - 3 - read-write - - - CNTPRST - Counters Preset - 4 - 4 - read-write - - - CNTPRSTLVL - Full-Half Preset - 5 - 5 - read-write - - - Reserved_7_6 - Reserved - 6 - 7 - read-only - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames - 8 - 8 - read-write - - - Reserved_31_9 - Reserved - 9 - 31 - read-only - - - - - MMC_RECEIVE_INTERRUPT - MMC Receive Interrupt Register - 0x0104 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status - 0 - 0 - read-only - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status - 1 - 1 - read-only - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status. - 2 - 2 - read-only - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status. - 3 - 3 - read-only - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status - 4 - 4 - read-only - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status - 5 - 5 - read-only - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status - 6 - 6 - read-only - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status - 7 - 7 - read-only - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status - 8 - 8 - read-only - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status - 9 - 9 - read-only - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status - 10 - 10 - read-only - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - 11 - 11 - read-only - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - 12 - 12 - read-only - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - 13 - 13 - read-only - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - 14 - 14 - read-only - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - 15 - 15 - read-only - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - 16 - 16 - read-only - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status - 17 - 17 - read-only - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status - 18 - 18 - read-only - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status - 19 - 19 - read-only - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status - 20 - 20 - read-only - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status - 21 - 21 - read-only - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status - 22 - 22 - read-only - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status - 23 - 23 - read-only - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status - 24 - 24 - read-only - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status - 25 - 25 - read-only - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - MMC_TRANSMIT_INTERRUPT - MMC Transmit Interrupt Register - 0x0108 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status - 0 - 0 - read-only - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status - 1 - 1 - read-only - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status - 2 - 2 - read-only - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status - 3 - 3 - read-only - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. - 4 - 4 - read-only - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - 5 - 5 - read-only - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - 6 - 6 - read-only - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - 7 - 7 - read-only - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - 8 - 8 - read-only - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - 9 - 9 - read-only - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - 10 - 10 - read-only - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - 11 - 11 - read-only - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - 12 - 12 - read-only - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status - 13 - 13 - read-only - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status - 14 - 14 - read-only - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - 15 - 15 - read-only - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status - 16 - 16 - read-only - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status - 17 - 17 - read-only - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status - 18 - 18 - read-only - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status - 19 - 19 - read-only - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status - 20 - 20 - read-only - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status - 21 - 21 - read-only - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status - 22 - 22 - read-only - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status - 23 - 23 - read-only - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status - 24 - 24 - read-only - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status - 25 - 25 - read-only - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - MMC_RECEIVE_INTERRUPT_MASK - MMC Reveive Interrupt Mask Register - 0x010C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXGBFRMIM - MMC Receive Good Bad Frame Counter Interrupt Mask - 0 - 0 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask - 1 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask - 2 - 2 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask - 3 - 3 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask - 4 - 4 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask - 5 - 5 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask - 6 - 6 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask - 7 - 7 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask - 8 - 8 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask - 9 - 9 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask - 10 - 10 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - 11 - 11 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - 12 - 12 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - 13 - 13 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - 14 - 14 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - 15 - 15 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - 16 - 16 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask - 17 - 17 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask - 18 - 18 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask - 19 - 19 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask - 20 - 20 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask - 21 - 21 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - 22 - 22 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask - 23 - 23 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask - 24 - 24 - read-write - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask - 25 - 25 - read-write - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - MMC_TRANSMIT_INTERRUPT_MASK - MMC Transmit Interrupt Mask Register - 0x0110 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask - 0 - 0 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask - 1 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask - 2 - 2 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask - 3 - 3 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - 4 - 4 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - 5 - 5 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - 6 - 6 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - 7 - 7 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - 8 - 8 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - 9 - 9 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - 10 - 10 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - 11 - 11 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - 12 - 12 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask - 13 - 13 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask - 14 - 14 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - 15 - 15 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask - 16 - 16 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask - 17 - 17 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask - 18 - 18 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask - 19 - 19 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask - 20 - 20 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask - 21 - 21 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - 22 - 22 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask - 23 - 23 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask - 24 - 24 - read-write - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask - 25 - 25 - read-write - - - Reserved_31_26 - Reserved - 26 - 31 - read-only - - - - - TX_OCTET_COUNT_GOOD_BAD - Transmit Octet Count for Good and Bad Frames Register - 0x0114 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXOCTGB - This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes. - 0 - 31 - read-only - - - - - TX_FRAME_COUNT_GOOD_BAD - Transmit Frame Count for Goodand Bad Frames Register - 0x0118 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFRMGB - This field indicates the number of good and bad frames transmitted, exclusive of retried frames - 0 - 31 - read-only - - - - - TX_BROADCAST_FRAMES_GOOD - Transmit Frame Count for Good Broadcast Frames - 0x011C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBCASTG - This field indicates the number of transmitted good broadcast frames. - 0 - 31 - read-only - - - - - TX_MULTICAST_FRAMES_GOOD - Transmit Frame Count for Good Multicast Frames - 0x0120 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXMCASTG - This field indicates the number of transmitted good multicast frames. - 0 - 31 - read-only - - - - - TX_64OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 64 Byte Frames - 0x0124 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX64OCTGB - This field indicates the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_65TO127OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames - 0x0128 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX65_127OCTGB - This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_128TO255OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames - 0x012C - 32 - 0x00000000 - 0xFFFFFFFF - - - TX128_255OCTGB - This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_256TO511OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames - 0x0130 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX256_511OCTGB - This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_512TO1023OCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames - 0x0134 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX512_1023OCTGB - This field indicates the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD - Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames - 0x0138 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX1024_MAXOCTGB - This field indicates the number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - TX_UNICAST_FRAMES_GOOD_BAD - Transmit Frame Count for Good and Bad Unicast Frames - 0x013C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXUCASTGB - This field indicates the number of transmitted good and bad unicast frames. - 0 - 31 - read-only - - - - - TX_MULTICAST_FRAMES_GOOD_BAD - Transmit Frame Count for Good and Bad Multicast Frames - 0x0140 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXMCASTGB - This field indicates the number of transmitted good and bad multicast frames. - 0 - 31 - read-only - - - - - TX_BROADCAST_FRAMES_GOOD_BAD - Transmit Frame Count for Good and Bad Broadcast Frames - 0x0144 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBCASTGB - This field indicates the number of transmitted good and bad broadcast frames. - 0 - 31 - read-only - - - - - TX_UNDERFLOW_ERROR_FRAMES - Transmit Frame Count for Underflow Error Frames - 0x0148 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXUNDRFLW - This field indicates the number of frames aborted because of frame underflow error. - 0 - 31 - read-only - - - - - TX_SINGLE_COLLISION_GOOD_FRAMES - Transmit Frame Count for Frames Transmitted after Single Collision - 0x014C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXSNGLCOLG - This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode. - 0 - 31 - read-only - - - - - TX_MULTIPLE_COLLISION_GOOD_FRAMES - Transmit Frame Count for Frames Transmitted after Multiple Collision - 0x0150 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXMULTCOLG - This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode. - 0 - 31 - read-only - - - - - TX_DEFERRED_FRAMES - Tx Deferred Frames Register - 0x0154 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXDEFRD - This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode. - 0 - 31 - read-only - - - - - TX_LATE_COLLISION_FRAMES - Transmit Frame Count for Late Collision Error Frames - 0x0158 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXLATECOL - This field indicates the number of frames aborted because of late collision error. - 0 - 31 - read-only - - - - - TX_EXCESSIVE_COLLISION_FRAMES - Transmit Frame Count for Excessive Collision Error Frames - 0x015C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXEXSCOL - This field indicates the number of frames aborted because of excessive (16) collision error. - 0 - 31 - read-only - - - - - TX_CARRIER_ERROR_FRAMES - Transmit Frame Count for Carrier Sense Error Frames - 0x0160 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXCARR - This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier). - 0 - 31 - read-only - - - - - TX_OCTET_COUNT_GOOD - Tx Octet Count Good Register - 0x0164 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXOCTG - This field indicates the number of bytes transmitted, exclusive of preamble, in good frames. - 0 - 31 - read-only - - - - - TX_FRAME_COUNT_GOOD - Tx Frame Count Good Register - 0x0168 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFRMG - This field indicates the number of transmitted good frames, exclusive of preamble. - 0 - 31 - read-only - - - - - TX_EXCESSIVE_DEFERRAL_ERROR - Transmit Frame Count for Excessive Deferral Error Frames - 0x016C - 32 - 0x00000000 - 0xFFFFFFFF - - - TXEXSDEF - This field indicates the number of frames aborted because of excessive deferral error, that is, frames deferred for more than two max-sized frame times. - 0 - 31 - read-only - - - - - TX_PAUSE_FRAMES - Transmit Frame Count for Good PAUSE Frames - 0x0170 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXPAUSE - This field indicates the number of transmitted good PAUSE frames. - 0 - 31 - read-only - - - - - TX_VLAN_FRAMES_GOOD - Transmit Frame Count for Good VLAN Frames - 0x0174 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXVLANG - This register maintains the number of transmitted good VLAN frames, exclusive of retried frames. - 0 - 31 - read-only - - - - - TX_OSIZE_FRAMES_GOOD - Transmit Frame Count for Good Oversize Frames - 0x0178 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXOSIZG - This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled by setting MAC Configuration.2KPE). - 0 - 31 - read-only - - - - - RX_FRAMES_COUNT_GOOD_BAD - Receive Frame Count for Good and Bad Frames - 0x0180 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFRMGB - This field indicates the number of received good and bad frames. - 0 - 31 - read-only - - - - - RX_OCTET_COUNT_GOOD_BAD - Receive Octet Count for Good and Bad Frames - 0x0184 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOCTGB - This field indicates the number of bytes received, exclusive of preamble, in good and bad frames. - 0 - 31 - read-only - - - - - RX_OCTET_COUNT_GOOD - Rx Octet Count Good Register - 0x0188 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOCTG - This field indicates the number of bytes received, exclusive of preamble, only in good frames. - 0 - 31 - read-only - - - - - RX_BROADCAST_FRAMES_GOOD - Receive Frame Count for Good Broadcast Frames - 0x018C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXBCASTG - This field indicates the number of received good broadcast frames. - 0 - 31 - read-only - - - - - RX_MULTICAST_FRAMES_GOOD - Receive Frame Count for Good Multicast Frames - 0x0190 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXMCASTG - This field indicates the number of received good multicast frames. - 0 - 31 - read-only - - - - - RX_CRC_ERROR_FRAMES - Receive Frame Count for CRC Error Frames - 0x0194 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXCRCERR - This field indicates the number of frames received with CRC error. - 0 - 31 - read-only - - - - - RX_ALIGNMENT_ERROR_FRAMES - Receive Frame Count for Alignment Error Frames - 0x0198 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXALGNERR - This field indicates the number of frames received with alignment (dribble) error. - 0 - 31 - read-only - - - - - RX_RUNT_ERROR_FRAMES - Receive Frame Count for Runt Error Frames - 0x019C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXRUNTERR - This field indicates the number of frames received with runt error(<64 bytes and CRC error). - 0 - 31 - read-only - - - - - RX_JABBER_ERROR_FRAMES - Receive Frame Count for Jabber Error Frames - 0x01A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXJABERR - This field indicates the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - 0 - 31 - read-only - - - - - RX_UNDERSIZE_FRAMES_GOOD - Receive Frame Count for Undersize Frames - 0x01A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUNDERSZG - This field indicates the number of frames received with length less than 64 bytes and without errors. - 0 - 31 - read-only - - - - - RX_OVERSIZE_FRAMES_GOOD - Rx Oversize Frames Good Register - 0x01A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOVERSZG - This field indicates the number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled by setting MAC Configuration.2KPE). - 0 - 31 - read-only - - - - - RX_64OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 64 Byte Frames - 0x01AC - 32 - 0x00000000 - 0xFFFFFFFF - - - RX64OCTGB - This field indicates the number of received good and bad frames with length 64 bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_65TO127OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 65 to 127 Bytes Frames - 0x01B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX65_127OCTGB - This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_128TO255OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 128 to 255 Bytes Frames - 0x01B4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX128_255OCTGB - This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_256TO511OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 256 to 511 Bytes Frames - 0x01B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX256_511OCTGB - This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_512TO1023OCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames - 0x01BC - 32 - 0x00000000 - 0xFFFFFFFF - - - RX512_1023OCTGB - This field indicates the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - 0 - 31 - read-only - - - - - RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX1024_MAXOCTGB - This field indicates the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 31 - read-only - - - - - RX_UNICAST_FRAMES_GOOD - Receive Frame Count for Good Unicast Frames - 0x01C4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUCASTG - This field indicates the number of received good unicast frames. - 0 - 31 - read-only - - - - - RX_LENGTH_ERROR_FRAMES - Receive Frame Count for Length Error Frames - 0x01C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXLENERR - This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field. - 0 - 31 - read-only - - - - - RX_OUT_OF_RANGE_TYPE_FRAMES - Receive Frame Count for Out of Range Frames - 0x01CC - 32 - 0x00000000 - 0xFFFFFFFF - - - RXOUTOFRNG - This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - 0 - 31 - read-only - - - - - RX_PAUSE_FRAMES - Receive Frame Count for PAUSE Frames - 0x01D0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXPAUSEFRM - This field indicates the number of received good and valid PAUSE frames. - 0 - 31 - read-only - - - - - RX_FIFO_OVERFLOW_FRAMES - Receive Frame Count for FIFO Overflow Frames - 0x01D4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFOOVFL - This field indicates the number of received frames missed because of FIFO overflow. - 0 - 31 - read-only - - - - - RX_VLAN_FRAMES_GOOD_BAD - Receive Frame Count for Good and Bad VLAN Frames - 0x01D8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXVLANFRGB - This field indicates the number of received good and bad VLAN frames. - 0 - 31 - read-only - - - - - RX_WATCHDOG_ERROR_FRAMES - Receive Frame Count for Watchdog Error Frames - 0x01DC - 32 - 0x00000000 - 0xFFFFFFFF - - - RXWDGERR - This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). - 0 - 31 - read-only - - - - - RX_RECEIVE_ERROR_FRAMES - Receive Frame Count for Receive Error Frames - 0x01E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXRCVERR - This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). - 0 - 31 - read-only - - - - - RX_CONTROL_FRAMES_GOOD - Receive Frame Count for Good Control Frames Frames - 0x01E4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXCTRLG - This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). - 0 - 31 - read-only - - - - - MMC_IPC_RECEIVE_INTERRUPT_MASK - MMC Receive Checksum Offload Interrupt Mask Register - 0x0200 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask - 0 - 0 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - 1 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - 2 - 2 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - 3 - 3 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - 4 - 4 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask - 5 - 5 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - 6 - 6 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - 7 - 7 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask - 8 - 8 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask - 9 - 9 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask - 10 - 10 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask - 11 - 11 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask - 12 - 12 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask - 13 - 13 - read-write - - - Reserved_15_14 - Reserved - 14 - 15 - read-only - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask - 16 - 16 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - 17 - 17 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - 18 - 18 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - 19 - 19 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - 20 - 20 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask - 21 - 21 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - 22 - 22 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - 23 - 23 - read-write - - - RXUDPGOIM - MMC Receive UDP Good Octet Counter Interrupt Mask - 24 - 24 - read-write - - - RXUDPEROIM - MMC Receive UDP Error Octet Counter Interrupt Mask - 25 - 25 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask - 26 - 26 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask - 27 - 27 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask - 28 - 28 - read-write - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask - 29 - 29 - read-write - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - MMC_IPC_RECEIVE_INTERRUPT - MMC Receive Checksum Offload Interrupt Register - 0x0208 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status - 0 - 0 - read-only - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status - 1 - 1 - read-only - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status - 2 - 2 - read-only - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - 3 - 3 - read-only - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - 4 - 4 - read-only - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status - 5 - 5 - read-only - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status - 6 - 6 - read-only - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status - 7 - 7 - read-only - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status - 8 - 8 - read-only - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status - 9 - 9 - read-only - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status - 10 - 10 - read-only - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status - 11 - 11 - read-only - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status - 12 - 12 - read-only - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status - 13 - 13 - read-only - - - Reserved_15_14 - Reserved - 14 - 15 - read-only - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status - 16 - 16 - read-only - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status - 17 - 17 - read-only - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status - 18 - 18 - read-only - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - 19 - 19 - read-only - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - 20 - 20 - read-only - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status - 21 - 21 - read-only - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status - 22 - 22 - read-only - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status - 23 - 23 - read-only - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status - 24 - 24 - read-only - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status - 25 - 25 - read-only - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status - 26 - 26 - read-only - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status - 27 - 27 - read-only - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status - 28 - 28 - read-only - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status - 29 - 29 - read-only - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - RXIPV4_GOOD_FRAMES - RxIPv4 Good Frames Register - 0x0210 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GDFRM - This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. - 0 - 31 - read-only - - - - - RXIPV4_HEADER_ERROR_FRAMES - Receive IPV4 Header Error Frame Counter Register - 0x0214 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4HDRERRFRM - This field indicates the number of IPv4 datagrams received with header errors (checksum, length, or version mismatch). - 0 - 31 - read-only - - - - - RXIPV4_NO_PAYLOAD_FRAMES - Receive IPV4 No Payload Frame Counter Register - 0x0218 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4NOPAYFRM - This field indicates the number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine. - 0 - 31 - read-only - - - - - RXIPV4_FRAGMENTED_FRAMES - Receive IPV4 Fragmented Frame Counter Register - 0x021C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4FRAGFRM - This field indicates the number of good IPv4 datagrams received with fragmentation. - 0 - 31 - read-only - - - - - RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES - Receive IPV4 UDP Checksum Disabled Frame Counter Register - 0x0220 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4UDSBLFRM - This field indicates the number of received good IPv4 datagrams which have the UDP payload with checksum disabled. - 0 - 31 - read-only - - - - - RXIPV6_GOOD_FRAMES - RxIPv6 Good Frames Register - 0x0224 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6GDFRM - This field indicates the number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads. - 0 - 31 - read-only - - - - - RXIPV6_HEADER_ERROR_FRAMES - Receive IPV6 Header Error Frame Counter Register - 0x0228 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6HDRERRFRM - This field indicates the number of IPv6 datagrams received with header errors (length or version mismatch). - 0 - 31 - read-only - - - - - RXIPV6_NO_PAYLOAD_FRAMES - Receive IPV6 No Payload Frame Counter Register - 0x022C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6NOPAYFRM - This field indicates the number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers. - 0 - 31 - read-only - - - - - RXUDP_GOOD_FRAMES - RxUDP Good Frames Register - 0x0230 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPGDFRM - This field indicates the number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented. - 0 - 31 - read-only - - - - - RXUDP_ERROR_FRAMES - RxUDP Error Frames Register - 0x0234 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPERRFRM - This field indicates the number of good IP datagrams whose UDP payload has a checksum error. - 0 - 31 - read-only - - - - - RXTCP_GOOD_FRAMES - RxTCP Good Frames Register - 0x0238 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPGDFRM - This field indicates the number of good IP datagrams with a good TCP payload. - 0 - 31 - read-only - - - - - RXTCP_ERROR_FRAMES - RxTCP Error Frames Register - 0x023C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPERRFRM - This field indicates the number of good IP datagrams whose TCP payload has a checksum error. - 0 - 31 - read-only - - - - - RXICMP_GOOD_FRAMES - RxICMP Good Frames Register - 0x0240 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPGDFRM - This field indicates the number of good IP datagrams with a good ICMP payload. - 0 - 31 - read-only - - - - - RXICMP_ERROR_FRAMES - RxICMP Error Frames Register - 0x0244 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPERRFRM - This field indicates the number of good IP datagrams whose ICMP payload has a checksum error. - 0 - 31 - read-only - - - - - RXIPV4_GOOD_OCTETS - RxIPv4 Good Octets Register - 0x0250 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4GDOCT - This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. The Ethernet header, FCS, pad, or IP pad - 0 - 31 - read-only - - - - - RXIPV4_HEADER_ERROR_OCTETS - Receive IPV4 Header Error Octet Counter Register - 0x0254 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4HDRERROCT - This field indicates the number of bytes received in the IPv4 datagrams with header errors (checksum, length, or version mismatch). The value in the Length field of IPv4 header is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV4_NO_PAYLOAD_OCTETS - Receive IPV4 No Payload Octet Counter Register - 0x0258 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4NOPAYOCT - This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV4_FRAGMENTED_OCTETS - Receive IPV4 Fragmented Octet Counter Register - 0x025C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4FRAGOCT - This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Receive IPV4 Fragmented Octet Counter Register - 0x0260 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV4UDSBLOCT - This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXIPV6_GOOD_OCTETS - RxIPv6 Good Octets Register - 0x0264 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6GDOCT - Thsi field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data. - 0 - 31 - read-only - - - - - RXIPV6_HEADER_ERROR_OCTETS - Receive IPV6 Header Error Octet Counter Register - 0x0268 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6HDRERROCT - This field indicates the number of bytes received in IPv6 datagrams with header errors (length or version mismatch). The value in the IPv6 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXIPV6_NO_PAYLOAD_OCTETS - Receive IPV6 No Payload Octet Counter Register - 0x026C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXIPV6NOPAYOCT - This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter. - 0 - 31 - read-only - - - - - RXUDP_GOOD_OCTETS - Receive UDP Good Octets Register - 0x0270 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPGDOCT - This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXUDP_ERROR_OCTETS - Receive UDP Error Octets Register - 0x0274 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXUDPERROCT - This field indicates the number of bytes received in a UDP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXTCP_GOOD_OCTETS - Receive TCP Good Octets Register - 0x0278 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPGDOCT - This field indicates the number of bytes received in a good TCP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXTCP_ERROR_OCTETS - Receive TCP Error Octets Register - 0x027C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXTCPERROCT - Thsi field indicates the number of bytes received in a TCP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXICMP_GOOD_OCTETS - Receive ICMP Good Octets Register - 0x0280 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPGDOCT - This field indicates the number of bytes received in a good ICMP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. - 0 - 31 - read-only - - - - - RXICMP_ERROR_OCTETS - Receive ICMP Error Octets Register - 0x0284 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXICMPERROCT - Number of bytes received in an ICMP segment with checksum errors - 0 - 31 - read-only - - - - - TIMESTAMP_CONTROL - Timestamp Control Register - 0x0700 - 32 - 0x00002000 - 0xFFFFFFFF - - - TSENA - Timestamp Enable - 0 - 0 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update - 1 - 1 - read-write - - - TSINIT - Timestamp Initialize - 2 - 2 - read-write - - - TSUPDT - Timestamp Update - 3 - 3 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable - 4 - 4 - read-write - - - TSADDREG - Addend Reg Update - 5 - 5 - read-write - - - Reserved_7_6 - Reserved - 6 - 7 - read-only - - - TSENALL - Enable Timestamp for All Frames - 8 - 8 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control - 9 - 9 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format - 10 - 10 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames - 11 - 11 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent Over IPv6-UDP - 12 - 12 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - 13 - 13 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages - 14 - 14 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master - 15 - 15 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - 16 - 17 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering - 18 - 18 - read-write - - - Reserved_23_19 - Reserved - 19 - 31 - read-only - - - - - SUB_SECOND_INCREMENT - Sub-Second Increment Register - 0x0704 - 32 - 0x00000000 - 0xFFFFFFFF - - - SSINC - Sub-second Increment Value - 0 - 7 - read-write - - - Reserved_31_8 - Reserved - 8 - 31 - read-only - - - - - SYSTEM_TIME_SECONDS - System Time - Seconds Register - 0x0708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - 0 - 31 - read-only - - - - - SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds Register - 0x070C - 32 - 0x00000000 - 0xFFFFFFFF - - - TSSS - Timestamp Sub Seconds - 0 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - SYSTEM_TIME_SECONDS_UPDATE - System Time - Seconds Update Register - 0x0710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - 0 - 31 - read-write - - - - - SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update Register - 0x0714 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSSS - Timestamp Sub Second - 0 - 30 - read-write - - - ADDSUB - Add or subtract time - 31 - 31 - read-write - - - - - TIMESTAMP_ADDEND - Timestamp Addend Register - 0x0718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register - 0 - 31 - read-write - - - - - TARGET_TIME_SECONDS - Target Time Seconds Register - 0x071C - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - 0 - 31 - read-write - - - - - TARGET_TIME_NANOSECONDS - Target Time Nanoseconds Register - 0x0720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTSLO - Target Timestamp Low Register - 0 - 30 - read-write - - - TRGTBUSY - Target Time Register Busy - 31 - 31 - read-only - - - - - SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds Register - 0x0724 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSHWR - Timestamp Higher Word Register - 0 - 15 - read-write - - - Reserved_31_16 - Reserved - 16 - 31 - read-only - - - - - TIMESTAMP_STATUS - Timestamp Status Register - 0x0728 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSSOVF - Timestamp Seconds Overflow - 0 - 0 - read-only - - - TSTARGT - Timestamp Target Time Reached - 1 - 1 - read-only - - - Reserved_2 - Reserved - 2 - 2 - read-only - - - TSTRGTERR - Timestamp Target Time Error - 3 - 3 - read-only - - - TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 - 4 - 4 - read-only - - - TSTRGTERR1 - Timestamp Target Time Error - 5 - 5 - read-only - - - TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 - 6 - 6 - read-only - - - TSTRGTERR2 - Timestamp Target Time Error - 7 - 7 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 - 8 - 8 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error - 9 - 9 - read-only - - - Reserved_15_10 - Reserved - 10 - 15 - read-only - - - Reserved_19_16 - Reserved - 16 - 19 - read-only - - - Reserved_23_20 - Reserved - 20 - 23 - read-only - - - Reserved_24 - Reserved - 24 - 24 - read-only - - - Reserved_29_25 - Reserved - 25 - 29 - read-only - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - PPS_CONTROL - PPS Control Register - 0x072C - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSCTRL_PPSCMD - PPSCTRL0 or PPSCMD0 - 0 - 3 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable - 4 - 4 - read-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - 5 - 6 - read-only - - - Reserved_7 - Reserved - 7 - 7 - read-only - - - PPSCMD1 - Flexible PPS1 Output Control - 8 - 10 - read-only - - - Reserved_12_11 - Reserved - 11 - 12 - read-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output - 13 - 14 - read-only - - - Reserved_15 - Reserved - 15 - 15 - read-only - - - PPSCMD2 - Flexible PPS2 Output Control - 16 - 18 - read-only - - - Reserved_20_19 - Reserved - 19 - 20 - read-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output - 21 - 22 - read-only - - - Reserved_23 - Reserved - 23 - 23 - read-only - - - PPSCMD3 - Flexible PPS3 Output Control - 24 - 26 - read-only - - - Reserved_28_27 - Reserved - 27 - 28 - read-only - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output - 29 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00020101 - 0xFFFFFFFF - - - SWR - Software Reset - 0 - 0 - read-write - - - DA - DMA Arbitration Scheme - 1 - 1 - read-write - - - DSL - Descriptor Skip Length - 2 - 6 - read-write - - - Reserved_7 - Reserved - 7 - 7 - read-write - - - PBL - Programmable Burst Length - 8 - 13 - read-write - - - PR - Priority Ratio - 14 - 15 - read-write - - - FB - Fixed Burst - 16 - 16 - read-write - - - RPBL - Rx DMA PBL - 17 - 22 - read-write - - - USP - Use Seperate PBL - 23 - 23 - read-write - - - EIGHTxPBL - 8xPBL Mode - 24 - 24 - read-write - - - AAL - Address Aligned Beats - 25 - 25 - read-write - - - MB - Mixed Burst - 26 - 26 - read-write - - - TXPR - Transmit Priority - 27 - 27 - read-write - - - PRWG - Channel Priority Weights - 28 - 29 - read-only - - - Reserved_31_30 - Reserved - 30 - 31 - read-only - - - - - TRANSMIT_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand - 0 - 31 - read-write - - - - - RECEIVE_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand - 0 - 31 - read-write - - - - - RECEIVE_DESCRIPTOR_LIST_ADDRESS - Receive Descriptor Address Register - 0x100C - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_1_0 - Reserved - 0 - 1 - read-only - - - RDESLA_32bit - Start of Receive List - 2 - 31 - read-write - - - - - TRANSMIT_DESCRIPTOR_LIST_ADDRESS - Transmit descripter Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_1_0 - Reserved - 0 - 1 - read-only - - - TDESLA_32bit - Start of Transmit List - 2 - 31 - read-write - - - - - STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0xFFFFFFFF - - - TI - Transmit Interrupt - 0 - 0 - read-write - - - TPS - Transmit Process Stopped - 1 - 1 - read-write - - - TU - Transmit Buffer Unavailable - 2 - 2 - read-write - - - TJT - Transmit Jabber Timeout - 3 - 3 - read-write - - - OVF - Receive Overflow - 4 - 4 - read-write - - - UNF - Transmit Underflow - 5 - 5 - read-write - - - RI - Receive Interrupt - 6 - 6 - read-write - - - RU - Receive Buffer Unavailable - 7 - 7 - read-write - - - RPS - Receive Process Stopped - 8 - 8 - read-write - - - RWT - Receive Watchdog Timeout - 9 - 9 - read-write - - - ETI - Early Transmit Interrupt - 10 - 10 - read-write - - - Reserved_12_11 - Reserved - 11 - 12 - read-only - - - FBI - Fatal Bus Error Interrupt - 13 - 13 - read-write - - - ERI - Early Receive Interrupt - 14 - 14 - read-write - - - AIS - Abnormal Interrupt Summary - 15 - 15 - read-write - - - NIS - Normal Interrupt Summary - 16 - 16 - read-write - - - RS - Received Process State - 17 - 19 - read-only - - - TS - Transmit Process State - 20 - 22 - read-only - - - EB - Error Bits - 23 - 25 - read-only - - - Reserved_26 - Reserved - 26 - 26 - read-only - - - EMI - ETH MMC Interrupt - 27 - 27 - read-only - - - EPI - ETH PMT Interrupt - 28 - 28 - read-only - - - TTI - Timestamp Trigger Interrupt - 29 - 29 - read-only - - - Reserved_30 - Reserved - 30 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - OPERATION_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0xFFFFFFFF - - - Reserved_0 - Reserved - 0 - 0 - read-only - - - SR - Start or Stop Receive - 1 - 1 - read-write - - - OSF - Operate on Second Frame - 2 - 2 - read-write - - - RTC - Receive Threshold Control - 3 - 4 - read-write - - - Reserved_5 - Reserved - 5 - 5 - read-only - - - FUF - Forward Undersized Good Frames - 6 - 6 - read-write - - - FEF - Forward Error Frames - 7 - 7 - read-write - - - Reserved_12_8 - Reserved - 8 - 12 - read-only - - - ST - Start or Stop Transmission Command - 13 - 13 - read-write - - - TTC - Transmit Threshold Control - 14 - 16 - read-write - - - Reserved_19_17 - Reserved - 17 - 19 - read-only - - - FTF - Flush Transmit FIFO - 20 - 20 - read-write - - - TSF - Transmit Store and Forward - 21 - 21 - read-write - - - Reserved_23_22 - Reserved - 22 - 23 - read-only - - - DFF - Disable Flushing of Received Frames - 24 - 24 - read-write - - - RSF - Receive Store and Forward - 25 - 25 - read-write - - - DT - Disable Dropping of TCP/IP Checksum Error Frames - 26 - 26 - read-write - - - Reserved_31_27 - Reserved - 27 - 31 - read-only - - - - - INTERRUPT_ENABLE - Interrupt Enable Register - 0x101C - 32 - 0x00000000 - 0xFFFFFFFF - - - TIE - Transmit Interrupt Enable - 0 - 0 - read-write - - - TSE - Transmit Stopped Enable - 1 - 1 - read-write - - - TUE - Transmit Buffer Unvailable Enable - 2 - 2 - read-write - - - TJE - Transmit Jabber Timeout Enable - 3 - 3 - read-write - - - OVE - Overflow Interrupt Enable - 4 - 4 - read-write - - - UNE - Underflow Interrupt Enable - 5 - 5 - read-write - - - RIE - Receive Interrupt Enable - 6 - 6 - read-write - - - RUE - Receive Buffer Unavailable Enable - 7 - 7 - read-write - - - RSE - Receive Stopped Enable - 8 - 8 - read-write - - - RWE - Receive Watchdog Timeout Enable - 9 - 9 - read-write - - - ETE - Early Transmit Interrupt Enable - 10 - 10 - read-write - - - Reserved_12_11 - Reserved - 11 - 12 - read-only - - - FBE - Fatal Bus Error Enable - 13 - 13 - read-write - - - ERE - Early Receive Interrupt Enable - 14 - 14 - read-write - - - AIE - Abnormal Interrupt Summary Enable - 15 - 15 - read-write - - - NIE - Normal Interrupt Summary Enable - 16 - 16 - read-write - - - Reserved_31_17 - Reserved - 17 - 31 - read-only - - - - - MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER - Missed Frame and Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0xFFFFFFFF - - - MISFRMCNT - This field indicates the number of frames missed by the controller because of the RAM Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read. - 0 - 15 - read-only - - - MISCNTOVF - Overflow bit for Missed Frame Counter - 16 - 16 - read-only - - - OVFFRMCNT - This field indicates the number of frames missed by the application. The counter is cleared when this register is read. - 17 - 27 - read-only - - - OVFCNTOVF - Overflow bit for FIFO Overflow Counter - 28 - 28 - read-only - - - Reserved_31_29 - Reserved - 29 - 31 - read-only - - - - - RECEIVE_INTERRUPT_WATCHDOG_TIMER - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0xFFFFFFFF - - - RIWT - RI Watchdog Timer Count - 0 - 7 - read-write - - - Reserved_31_8 - Reserved - 8 - 31 - read-only - - - - - AHB_STATUS - AHB Status Register - 0x102C - 32 - 0x00000000 - 0xFFFFFFFF - - - AHBMS - AHB Master Status - 0 - 0 - read-only - - - Reserved_1 - Reserved - 1 - 1 - read-only - - - Reserved_31_2 - Reserved - 2 - 31 - read-only - - - - - CURRENT_HOST_TRANSMIT_DESCRIPTOR - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer - 0 - 31 - read-only - - - - - CURRENT_HOST_RECEIVE_DESCRIPTOR - Current Host Receive Descriptor Register - 0x104C - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer - 0 - 31 - read-only - - - - - CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer - 0 - 31 - read-only - - - - - CURRENT_HOST_RECEIVE_BUFFER_ADDRESS - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer - 0 - 31 - read-only - - - - - HW_FEATURE - HW Feature Register - 0x1058 - 32 - 0x03052F35 - 0xFFFFFFFF - - - MIISEL - 10 or 100 Mbps support - 0 - 0 - read-only - - - GMIISEL - 1000 Mbps support - 1 - 1 - read-only - - - HDSEL - Half-Duplex support - 2 - 2 - read-only - - - EXTHASHEN - Expanded DA Hash Filter - 3 - 3 - read-only - - - HASHSEL - HASH Filter - 4 - 4 - read-only - - - ADDMACADRSEL - Multiple MAC Address Registers - 5 - 5 - read-only - - - PCSSEL - PCS registers (TBI, SGMII, or RTBI PHY interface) - 6 - 6 - read-only - - - L3L4FLTREN - Layer 3 and Layer 4 Filter Feature - 7 - 7 - read-only - - - SMASEL - SMA (MDIO) Interface - 8 - 8 - read-only - - - RWKSEL - PMT Remote Wakeup - 9 - 9 - read-only - - - MGKSEL - PMT Magic Packet - 10 - 10 - read-only - - - MMCSEL - RMON Module - 11 - 11 - read-only - - - TSVER1SEL - Only IEEE 1588-2002 Timestamp - 12 - 12 - read-only - - - TSVER2SEL - IEEE 1588-2008 Advanced Timestamp - 13 - 13 - read-only - - - EEESEL - Energy Efficient Ethernet - 14 - 14 - read-only - - - AVSEL - AV Feature - 15 - 15 - read-only - - - TXCOESEL - Checksum Offload in Tx - 16 - 16 - read-only - - - RXTYP1COE - IP Checksum Offload (Type 1) in Rx - 17 - 17 - read-only - - - RXTYP2COE - IP Checksum Offload (Type 2) in Rx - 18 - 18 - read-only - - - RXFIFOSIZE - Rx FIFO > 2,048 Bytes - 19 - 19 - read-write - - - RXCHCNT - Number of additional Rx channels - 20 - 21 - read-only - - - TXCHCNT - Number of additional Tx channels - 22 - 23 - read-only - - - ENHDESSEL - Alternate (Enhanced Descriptor) - 24 - 24 - read-only - - - INTTSEN - Timestamping with Internal System Time - 25 - 25 - read-only - - - FLEXIPPSEN - Flexible Pulse-Per-Second Output - 26 - 26 - read-only - - - SAVLANINS - Source Address or VLAN Insertion - 27 - 27 - read-only - - - ACTPHYIF - Active or Selected PHY interface - 28 - 30 - read-only - - - Reserved_31 - Reserved - 31 - 31 - read-only - - - - - - - USB0 - Universal Serial Bus - USB - USB - 0x50040000 - - 0x0 - 0x040000 - registers - - - - GOTGCTL - Control and Status Register - 0x000 - 32 - 0x00010000 - 0xFFFFFFFF - - - SesReqScs - Session Request Success - 0 - 0 - read-only - - - value1 - Session request failure - 0b0 - - - value2 - Session request success - 0b1 - - - - - SesReq - Session Request - 1 - 1 - read-write - - - value1 - No session request - 0b0 - - - value2 - Session request - 0b1 - - - - - VbvalidOvEn - VBUS Valid Override Enable - 2 - 2 - read-write - - - value1 - Override is disabled and vbus valid signal from the PHY is used internally by the core. - 0b0 - - - value2 - Internally vbus valid received from the PHY is overridden with GOTGCTL.VbvalidOvVal. - 0b1 - - - - - VbvalidOvVal - VBUS Valid Override Value - 3 - 3 - read-write - - - value1 - vbusvalid value is 0# when GOTGCTL.VbvalidOvEn = 1 - 0b0 - - - value2 - vbusvalid value is 1# when GOTGCTL.VbvalidOvEn = 1 - 0b1 - - - - - AvalidOvEn - A-Peripheral Session Valid Override Enable - 4 - 4 - read-write - - - value1 - Override is disabled and Avalid signal from the PHY is used internally by the core. - 0b0 - - - value2 - Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal. - 0b1 - - - - - AvalidOvVal - A-Peripheral Session Valid Override Value - 5 - 5 - read-write - - - value1 - Avalid value is 0# when GOTGCTL.AvalidOvEn = 1 - 0b0 - - - value2 - Avalid value is 1# when GOTGCTL.AvalidOvEn = 1 - 0b1 - - - - - BvalidOvEn - B-Peripheral Session Valid Override Enable - 6 - 6 - read-write - - - value1 - Override is disabled and Bvalid signal from the PHY is used internally by the core. - 0b0 - - - value2 - Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal. - 0b1 - - - - - BvalidOvVal - B-Peripheral Session Valid Override Value - 7 - 7 - read-write - - - value1 - Bvalid value is 0# when GOTGCTL.BvalidOvEn = 1 - 0b0 - - - value2 - Bvalid value is 1# when GOTGCTL.BvalidOvEn = 1 - 0b1 - - - - - HstNegScs - Host Negotiation Success - 8 - 8 - read-only - - - value1 - Host negotiation failure - 0b0 - - - value2 - Host negotiation success - 0b1 - - - - - HNPReq - HNP Request - 9 - 9 - read-write - - - value1 - No HNP request - 0b0 - - - value2 - HNP request - 0b1 - - - - - HstSetHNPEn - Host Set HNP Enable - 10 - 10 - read-write - - - value1 - Host Set HNP is not enabled - 0b0 - - - value2 - Host Set HNP is enabled - 0b1 - - - - - DevHNPEn - Device HNP Enabled - 11 - 11 - read-write - - - value1 - HNP is not enabled in the application - 0b0 - - - value2 - HNP is enabled in the application - 0b1 - - - - - ConlDSts - Connector ID Status - 16 - 16 - read-only - - - value1 - The USB core is in A-Device mode - 0b0 - - - value2 - The USB core is in B-Device mode - 0b1 - - - - - DbncTime - Long/Short Debounce Time - 17 - 17 - read-only - - - value1 - Long debounce time, used for physical connections (100 ms + 2.5 us) - 0b0 - - - value2 - Short debounce time, used for soft connections (2.5 us) - 0b1 - - - - - ASesVId - A-Session Valid - 18 - 18 - read-only - - - value1 - A-session is not valid - 0b0 - - - value2 - A-session is valid - 0b1 - - - - - BSesVld - B-Session Valid - 19 - 19 - read-only - - - value1 - B-session is not valid. - 0b0 - - - value2 - B-session is valid. - 0b1 - - - - - OTGVer - OTG Version - 20 - 20 - read-write - - - value1 - OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP. - 0b0 - - - value2 - OTG Version 2.0. In this version the core supports only Data line pulsing for SRP. - 0b1 - - - - - - - GOTGINT - OTG Interrupt Register - 0x004 - 32 - 0x00000000 - 0xFFFFFFFF - - - SesEndDet - Session End Detected - 2 - 2 - read-write - - - SesReqSucStsChng - Session Request Success Status Change - 8 - 8 - read-write - - - HstNegSucStsChng - Host Negotiation Success Status Change - 9 - 9 - read-write - - - HstNegDet - Host Negotiation Detected - 17 - 17 - read-write - - - ADevTOUTChg - A-Device Timeout Change - 18 - 18 - read-write - - - DbnceDone - Debounce Done - 19 - 19 - read-write - - - - - GAHBCFG - AHB Configuration Register - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - GlblIntrMsk - Global Interrupt Mask - 0 - 0 - read-write - - - value1 - Mask the interrupt assertion to the application. - 0b0 - - - value2 - Unmask the interrupt assertion to the application. - 0b1 - - - - - HBstLen - Burst Length/Type - 1 - 4 - read-write - - - value1 - Single - 0b0000 - - - value2 - INCR - 0b0001 - - - value3 - INCR4 - 0b0011 - - - value4 - INCR8 - 0b0101 - - - value5 - INCR16 - 0b0111 - - - - - DMAEn - DMA Enable - 5 - 5 - read-write - - - value1 - Core operates in Slave mode - 0b0 - - - value2 - Core operates in a DMA mode - 0b1 - - - - - NPTxFEmpLvl - Non-Periodic TxFIFO Empty Level - 7 - 7 - read-write - - - value1 - DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty - 0b0 - - - value2 - DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty - 0b1 - - - - - PTxFEmpLvl - Periodic TxFIFO Empty Level - 8 - 8 - read-write - - - value1 - GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty - 0b0 - - - value2 - GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty - 0b1 - - - - - - - GUSBCFG - USB Configuration Register - 0x00C - 32 - 0x00001440 - 0xFFFFFFFF - - - TOutCal - FS Timeout Calibration - 0 - 2 - read-write - - - PHYSel - USB 1.1 Full-Speed Serial Transceiver Select - 6 - 6 - read-only - - - value1 - Reserved - 0b0 - - - value2 - USB 1.1 full-speed serial transceiver - 0b1 - - - - - SRPCap - SRP-Capable - 8 - 8 - read-write - - - value1 - SRP capability is not enabled. - 0b0 - - - value2 - SRP capability is enabled. - 0b1 - - - - - HNPCap - HNP-Capable - 9 - 9 - read-write - - - value1 - HNP capability is not enabled. - 0b0 - - - value2 - HNP capability is enabled. - 0b1 - - - - - USBTrdTim - USB Turnaround Time - 10 - 13 - read-write - - - OtgI2CSel - UTMIFS Interface Select - 16 - 16 - read-write - - - value1 - UTMI USB 1.1 Full-Speed interface for OTG signals - 0b0 - - - value2 - Reserved - 0b1 - - - - - TxEndDelay - Tx End Delay - 28 - 28 - read-write - - - value1 - Normal mode - 0b0 - - - value2 - Introduce Tx end delay timers - 0b1 - - - - - ForceHstMode - Force Host Mode - 29 - 29 - read-write - - - value1 - Normal Mode - 0b0 - - - value2 - Force Host Mode - 0b1 - - - - - ForceDevMode - Force Device Mode - 30 - 30 - read-write - - - value1 - Normal Mode - 0b0 - - - value2 - Force Device Mode - 0b1 - - - - - CTP - Corrupt Tx packet - 31 - 31 - read-write - - - - - GRSTCTL - Reset Register - 0x010 - 32 - 0x10000000 - 0xFFFFFFFF - - - CSftRst - Core Soft Reset - 0 - 0 - read-write - - - FrmCntrRst - Host Frame Counter Reset - 2 - 2 - read-write - - - RxFFlsh - RxFIFO Flush - 4 - 4 - read-write - - - TxFFlsh - TxFIFO Flush - 5 - 5 - read-write - - - TxFNum - TxFIFO Number - 6 - 10 - read-write - - - value1 - Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode - 0x00 - - - value2 - Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode - 0x01 - - - value3 - Tx FIFO 2 flush in device mode - 0x02 - - - value4 - Tx FIFO 15 flush in device mode - 0x0F - - - value5 - Flush all the transmit FIFOs in device or host mode. - 0x10 - - - - - DMAReq - DMA Request Signal - 30 - 30 - read-only - - - AHBIdle - AHB Master Idle - 31 - 31 - read-only - - - - - GINTSTS_HOSTMODE - Interrupt Register [HOSTMODE] - 0x014 - 32 - 0x14000020 - 0xFFFFFFFF - - - CurMod - Current Mode of Operation - 0 - 0 - read-only - - - value1 - Device mode - 0b0 - - - value2 - Host mode - 0b1 - - - - - ModeMis - Mode Mismatch Interrupt - 1 - 1 - read-write - - - OTGInt - OTG Interrupt - 2 - 2 - read-only - - - Sof - Start of Frame - 3 - 3 - read-write - - - RxFLvl - RxFIFO Non-Empty - 4 - 4 - read-only - - - incomplP - Incomplete Periodic Transfer - 21 - 21 - read-write - - - PrtInt - Host Port Interrupt - 24 - 24 - read-only - - - HChInt - Host Channels Interrupt - 25 - 25 - read-only - - - PTxFEmp - Periodic TxFIFO Empty - 26 - 26 - read-only - - - ConIDStsChng - Connector ID Status Change - 28 - 28 - read-write - - - DisconnInt - Disconnect Detected Interrupt - 29 - 29 - read-write - - - SessReqInt - Session Request/New Session Detected Interrupt - 30 - 30 - read-write - - - WkUpInt - Resume/Remote Wakeup Detected Interrupt - 31 - 31 - read-write - - - - - GINTSTS_DEVICEMODE - Interrupt Register [DEVICEMODE] - GINTSTS_HOSTMODE - 0x014 - 32 - 0x14000020 - 0xFFFFFFFF - - - CurMod - Current Mode of Operation - 0 - 0 - read-only - - - value1 - Device mode - 0b0 - - - value2 - Host mode - 0b1 - - - - - ModeMis - Mode Mismatch Interrupt - 1 - 1 - read-write - - - OTGInt - OTG Interrupt - 2 - 2 - read-only - - - Sof - Start of Frame - 3 - 3 - read-write - - - RxFLvl - RxFIFO Non-Empty - 4 - 4 - read-only - - - GINNakEff - Global IN Non-Periodic NAK Effective - 6 - 6 - read-only - - - GOUTNakEff - Global OUT NAK Effective - 7 - 7 - read-only - - - ErlySusp - Early Suspend - 10 - 10 - read-write - - - USBSusp - USB Suspend - 11 - 11 - read-write - - - USBRst - USB Reset - 12 - 12 - read-write - - - EnumDone - Enumeration Done - 13 - 13 - read-write - - - ISOOutDrop - Isochronous OUT Packet Dropped Interrupt - 14 - 14 - read-write - - - EOPF - End of Periodic Frame Interrupt - 15 - 15 - read-write - - - IEPInt - IN Endpoints Interrupt - 18 - 18 - read-only - - - OEPInt - OUT Endpoints Interrupt - 19 - 19 - read-only - - - incompISOIN - Incomplete Isochronous IN Transfer - 20 - 20 - read-write - - - incomplSOOUT - Incomplete Isochronous OUT Transfer - 21 - 21 - read-write - - - ConIDStsChng - Connector ID Status Change - 28 - 28 - read-write - - - SessReqInt - Session Request/New Session Detected Interrupt - 30 - 30 - read-write - - - WkUpInt - Resume/Remote Wakeup Detected Interrupt - 31 - 31 - read-write - - - - - GINTMSK_HOSTMODE - Interrupt Mask Register [HOSTMODE] - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - ModeMisMsk - Mode Mismatch Interrupt Mask - 1 - 1 - read-write - - - OTGIntMsk - OTG Interrupt Mask - 2 - 2 - read-write - - - SofMsk - Start of Frame Mask - 3 - 3 - read-write - - - RxFLvlMsk - Receive FIFO Non-Empty Mask - 4 - 4 - read-write - - - incomplPMsk - Incomplete Periodic Transfer Mask - 21 - 21 - read-write - - - PrtIntMsk - Host Port Interrupt Mask - 24 - 24 - read-write - - - HChIntMsk - Host Channels Interrupt Mask - 25 - 25 - read-write - - - PTxFEmpMsk - Periodic TxFIFO Empty Mask - 26 - 26 - read-write - - - ConIDStsChngMsk - Connector ID Status Change Mask - 28 - 28 - read-write - - - DisconnIntMsk - Disconnect Detected Interrupt Mask - 29 - 29 - read-write - - - SessReqIntMsk - Session Request/New Session Detected Interrupt Mask - 30 - 30 - read-write - - - WkUpIntMsk - Resume/Remote Wakeup Detected Interrupt Mask - 31 - 31 - read-write - - - - - GINTMSK_DEVICEMODE - Interrupt Mask Register [DEVICEMODE] - GINTMSK_HOSTMODE - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - ModeMisMsk - Mode Mismatch Interrupt Mask - 1 - 1 - read-write - - - OTGIntMsk - OTG Interrupt Mask - 2 - 2 - read-write - - - SofMsk - Start of Frame Mask - 3 - 3 - read-write - - - RxFLvlMsk - Receive FIFO Non-Empty Mask - 4 - 4 - read-write - - - GINNakEffMsk - Global Non-periodic IN NAK Effective Mask - 6 - 6 - read-write - - - GOUTNakEffMsk - Global OUT NAK Effective Mask - 7 - 7 - read-write - - - ErlySuspMsk - Early Suspend Mask - 10 - 10 - read-write - - - USBSuspMsk - USB Suspend Mask - 11 - 11 - read-write - - - USBRstMsk - USB Reset Mask - 12 - 12 - read-write - - - EnumDoneMsk - Enumeration Done Mask - 13 - 13 - read-write - - - ISOOutDropMsk - Isochronous OUT Packet Dropped Interrupt Mask - 14 - 14 - read-write - - - EOPFMsk - End of Periodic Frame Interrupt Mask - 15 - 15 - read-write - - - IEPIntMsk - IN Endpoints Interrupt Mask - 18 - 18 - read-write - - - OEPIntMsk - OUT Endpoints Interrupt Mask - 19 - 19 - read-write - - - incompISOINMsk - Incomplete Isochronous IN Transfer Mask - 20 - 20 - read-write - - - incomplSOOUTMsk - Incomplete Isochronous OUT Transfer Mask - 21 - 21 - read-write - - - ConIDStsChngMsk - Connector ID Status Change Mask - 28 - 28 - read-write - - - SessReqIntMsk - Session Request/New Session Detected Interrupt Mask - 30 - 30 - read-write - - - WkUpIntMsk - Resume/Remote Wakeup Detected Interrupt Mask - 31 - 31 - read-write - - - - - GRXSTSR_HOSTMODE - Receive Status Debug Read Register [HOSTMODE] - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - ChNum - Channel Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - IN data packet received - 0b0010 - - - value2 - IN transfer completed (triggers an interrupt) - 0b0011 - - - value3 - Data toggle error (triggers an interrupt) - 0b0101 - - - value4 - Channel halted (triggers an interrupt) - 0b0111 - - - - - - - GRXSTSR_DEVICEMODE - Receive Status Debug Read Register [DEVICEMODE] - GRXSTSR_HOSTMODE - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - EPNum - Endpoint Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - Global OUT NAK (triggers an interrupt) - 0b0001 - - - value2 - OUT data packet received - 0b0010 - - - value3 - OUT transfer completed (triggers an interrupt) - 0b0011 - - - value4 - SETUP transaction completed (triggers an interrupt) - 0b0100 - - - value5 - SETUP data packet received - 0b0110 - - - - - FN - Frame Number - 21 - 24 - read-only - - - - - GRXSTSP_HOSTMODE - Receive Status Read and Pop Register [HOSTMODE] - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - ChNum - Channel Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - IN data packet received - 0b0010 - - - value2 - IN transfer completed (triggers an interrupt) - 0b0011 - - - value3 - Data toggle error (triggers an interrupt) - 0b0101 - - - value4 - Channel halted (triggers an interrupt) - 0b0111 - - - - - - - GRXSTSP_DEVICEMODE - Receive Status Read and Pop Register [DEVICEMODE] - GRXSTSP_HOSTMODE - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPNum - Endpoint Number - 0 - 3 - read-only - - - BCnt - Byte Count - 4 - 14 - read-only - - - DPID - Data PID - 15 - 16 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA1 - 0b10 - - - value3 - DATA2 - 0b01 - - - value4 - MDATA - 0b11 - - - - - PktSts - Packet Status - 17 - 20 - read-only - - - value1 - Global OUT NAK (triggers an interrupt) - 0b0001 - - - value2 - OUT data packet received - 0b0010 - - - value3 - OUT transfer completed (triggers an interrupt) - 0b0011 - - - value4 - SETUP transaction completed (triggers an interrupt) - 0b0100 - - - value5 - SETUP data packet received - 0b0110 - - - - - FN - Frame Number - 21 - 24 - read-only - - - - - GRXFSIZ - Receive FIFO Size Register - 0x024 - 32 - 0x0000011A - 0xFFFFFFFF - - - RxFDep - RxFIFO Depth - 0 - 15 - read-write - - - - - GNPTXFSIZ_HOSTMODE - Non-Periodic Transmit FIFO Size Register [HOSTMODE] - 0x028 - 32 - 0x0010011A - 0xFFFFFFFF - - - NPTxFStAddr - Non-periodic Transmit RAM Start Address - 0 - 15 - read-write - - - NPTxFDep - Non-periodic TxFIFO Depth - 16 - 31 - read-write - - - - - GNPTXFSIZ_DEVICEMODE - Non-Periodic Transmit FIFO Size Register [DEVICEMODE] - GNPTXFSIZ_HOSTMODE - 0x028 - 32 - 0x00100000 - 0xFFFFFFFF - - - INEPTxF0StAddr - IN Endpoint FIFO0 Transmit RAM Start Address - 0 - 15 - read-write - - - INEPTxF0Dep - IN Endpoint TxFIFO 0 Depth - 16 - 31 - read-write - - - - - GNPTXSTS - Non-Periodic Transmit FIFO/Queue Status Register - 0x02C - 32 - 0x00080010 - 0xFFFFFFFF - - - NPTxFSpcAvail - Non-periodic TxFIFO Space Avail - 0 - 15 - read-only - - - value1 - Non-periodic TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - NPTxQSpcAvail - Non-periodic Transmit Request Queue Space Available - 16 - 23 - read-only - - - value1 - Non-periodic Transmit Request Queue is full - 0x0 - - - value2 - 1 location available - 0x1 - - - value3 - 2 locations available - 0x2 - - - - - NPTxQTop - Top of the Non-periodic Transmit Request Queue - 24 - 30 - read-only - - - value1 - IN/OUT token - 0b00 - - - value2 - Zero-length transmit packet (device IN/host OUT) - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Channel halt command - 0b11 - - - - - - - GUID - USB Module Identification Register - 0x03C - 32 - 0x00AEC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-write - - - MOD_TYPE - Module Type - 8 - 15 - read-write - - - MOD_NUMBER - Module Number - 16 - 31 - read-write - - - - - GDFIFOCFG - Global DFIFO Software Config Register - 0x05C - 32 - 0x027A02B2 - 0xFFFFFFFF - - - GDFIFOCfg - GDFIFOCfg - 0 - 15 - read-write - - - EPInfoBaseAddr - EPInfoBaseAddr - 16 - 31 - read-write - - - - - HPTXFSIZ - Host Periodic Transmit FIFO Size Register - 0x100 - 32 - 0x0100012A - 0xFFFFFFFF - - - PTxFStAddr - Host Periodic TxFIFO Start Address - 0 - 15 - read-write - - - PTxFSize - Host Periodic TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF1 - Device IN Endpoint 1 Transmit FIFO Size Register - 0x104 - 32 - 0x0100012A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF2 - Device IN Endpoint 2 Transmit FIFO Size Register - 0x108 - 32 - 0x0100022A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF3 - Device IN Endpoint 3 Transmit FIFO Size Register - 0x10C - 32 - 0x0100032A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF4 - Device IN Endpoint 4 Transmit FIFO Size Register - 0x110 - 32 - 0x0100042A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF5 - Device IN Endpoint 5 Transmit FIFO Size Register - 0x114 - 32 - 0x0100052A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - DIEPTXF6 - Device IN Endpoint 6 Transmit FIFO Size Register - 0x118 - 32 - 0x0100062A - 0xFFFFFFFF - - - INEPnTxFStAddr - IN Endpoint FIFOn Transmit RAM Start Address - 0 - 15 - read-write - - - INEPnTxFDep - IN Endpoint TxFIFO Depth - 16 - 31 - read-write - - - - - HCFG - Host Configuration Register - 0x400 - 32 - 0x00000200 - 0xFFFFFFFF - - - FSLSPclkSel - FS PHY Clock Select - 0 - 1 - read-write - - - value1 - PHY clock is running at 48 MHz - 0b01 - - - - - FSLSSupp - FS-Only Support - 2 - 2 - read-write - - - value1 - FS-only, connected device can supports also only FS. - 0b0 - - - value2 - FS-only, even if the connected device can support HS - 0b1 - - - - - DescDMA - Enable Scatter/gather DMA in Host mode - 23 - 23 - read-write - - - FrListEn - Frame List Entries - 24 - 25 - read-write - - - value1 - 8 Entries - 0b00 - - - value2 - 16 Entries - 0b01 - - - value3 - 32 Entries - 0b10 - - - value4 - 64 Entries - 0b11 - - - - - PerSchedEna - Enable Periodic Scheduling - 26 - 26 - read-write - - - - - HFIR - Host Frame Interval Register - 0x404 - 32 - 0x0000EA60 - 0xFFFFFFFF - - - FrInt - Frame Interval - 0 - 15 - read-write - - - HFIRRldCtrl - Reload Control - 16 - 16 - read-write - - - value1 - HFIR cannot be reloaded dynamically - 0b0 - - - value2 - HFIR can be dynamically reloaded during runtime - 0b1 - - - - - - - HFNUM - Host Frame Number/Frame Time Remaining Register - 0x408 - 32 - 0x00003FFF - 0xFFFFFFFF - - - FrNum - Frame Number - 0 - 15 - read-write - - - FrRem - Frame Time Remaining - 16 - 31 - read-only - - - - - HPTXSTS - Host Periodic Transmit FIFO/ Queue Status Register - 0x410 - 32 - 0x00080100 - 0xFFFFFFFF - - - PTxFSpcAvail - Periodic Transmit Data FIFO Space Available - 0 - 15 - read-write - - - value1 - Periodic TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - PTxQSpcAvail - Periodic Transmit Request Queue Space Available - 16 - 23 - read-only - - - value1 - Periodic Transmit Request Queue is full - 0x0 - - - value2 - 1 location available - 0x1 - - - value3 - 2 locations available - 0x2 - - - - - PTxQTop - Top of the Periodic Transmit Request Queue - 24 - 31 - read-only - - - - - HAINT - Host All Channels Interrupt Register - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - HAINT - Channel Interrupts - 0 - 13 - read-only - - - - - HAINTMSK - Host All Channels Interrupt Mask Register - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - HAINTMsk - Channel Interrupt Mask - 0 - 13 - read-write - - - - - HFLBADDR - Host Frame List Base Address Register - 0x41C - 32 - 0x00000000 - 0xFFFFFFFF - - - Starting_Address - Starting Address - 0 - 31 - read-write - - - - - HPRT - Host Port Control and Status Register - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - PrtConnSts - Port Connect Status - 0 - 0 - read-only - - - value1 - No device is attached to the port. - 0b0 - - - value2 - A device is attached to the port. - 0b1 - - - - - PrtConnDet - Port Connect Detected - 1 - 1 - read-write - - - PrtEna - Port Enable - 2 - 2 - read-write - - - value1 - Port disabled - 0b0 - - - value2 - Port enabled - 0b1 - - - - - PrtEnChng - Port Enable/Disable Change - 3 - 3 - read-write - - - PrtOvrCurrAct - Port Overcurrent Active - 4 - 4 - read-only - - - value1 - No overcurrent condition - 0b0 - - - value2 - Overcurrent condition - 0b1 - - - - - PrtOvrCurrChng - Port Overcurrent Change - 5 - 5 - read-write - - - PrtRes - Port Resume - 6 - 6 - read-write - - - value1 - No resume driven - 0b0 - - - value2 - Resume driven - 0b1 - - - - - PrtSusp - Port Suspend - 7 - 7 - read-write - - - value1 - Port not in Suspend mode - 0b0 - - - value2 - Port in Suspend mode - 0b1 - - - - - PrtRst - Port Reset - 8 - 8 - read-write - - - value1 - Port not in reset - 0b0 - - - value2 - Port in reset - 0b1 - - - - - PrtLnSts - Port Line Status - 10 - 11 - read-only - - - PrtPwr - Port Power - 12 - 12 - read-write - - - value1 - Power off - 0b0 - - - value2 - Power on - 0b1 - - - - - PrtSpd - Port Speed - 17 - 18 - read-only - - - value1 - Full speed - 0b01 - - - - - - - DCFG - Device Configuration Register - 0x800 - 32 - 0x08200000 - 0xFFFFFFFF - - - DevSpd - Device Speed - 0 - 1 - read-write - - - value1 - Reserved - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Full speed (USB 1.1 transceiver clock is 48 MHz) - 0b11 - - - - - NZStsOUTHShk - Non-Zero-Length Status OUT Handshake - 2 - 2 - read-write - - - value1 - Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. - 0b1 - - - value2 - Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register. - 0b0 - - - - - DevAddr - Device Address - 4 - 10 - read-write - - - PerFrInt - Periodic Frame Interval - 11 - 12 - read-write - - - value1 - 80% of the frame interval - 0b00 - - - value2 - 85% - 0b01 - - - value3 - 90% - 0b10 - - - value4 - 95% - 0b11 - - - - - DescDMA - Enable Scatter/Gather DMA in Device mode. - 23 - 23 - read-write - - - PerSchIntvl - Periodic Scheduling Interval - 24 - 25 - read-write - - - value1 - 25% of frame. - 0b00 - - - value2 - 50% of frame. - 0b01 - - - value3 - 75% of frame. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - DCTL - Device Control Register - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - RmtWkUpSig - Remote Wakeup Signaling - 0 - 0 - read-write - - - SftDiscon - Soft Disconnect - 1 - 1 - read-write - - - value1 - Normal operation. When this bit is cleared after a soft disconnect, the core drives a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. - 0b0 - - - value2 - The core drives a device disconnect event to the USB host. - 0b1 - - - - - GNPINNakSts - Global Non-periodic IN NAK Status - 2 - 2 - read-only - - - value1 - A handshake is sent out based on the data availability in the transmit FIFO. - 0b0 - - - value2 - A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. - 0b1 - - - - - GOUTNakSts - Global OUT NAK Status - 3 - 3 - read-only - - - value1 - A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. - 0b0 - - - value2 - No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. - 0b1 - - - - - SGNPInNak - Set Global Non-periodic IN NAK - 7 - 7 - write-only - - - CGNPInNak - Clear Global Non-periodic IN NAK - 8 - 8 - write-only - - - SGOUTNak - Set Global OUT NAK - 9 - 9 - write-only - - - CGOUTNak - Clear Global OUT NAK - 10 - 10 - write-only - - - GMC - Global Multi Count - 13 - 14 - read-write - - - value1 - Invalid. - 0b00 - - - value2 - 1 packet. - 0b01 - - - value3 - 2 packets. - 0b10 - - - value4 - 3 packets. - 0b11 - - - - - IgnrFrmNum - Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA - 15 - 15 - read-write - - - value1 - Scatter/Gather enabled: The core transmits the packets only in the frame number in which they are intended to be transmitted. Scatter/Gather disabled: Periodic transfer interrupt feature is disabled; the application must program transfers for periodic endpoints every frame - 0b0 - - - value2 - Scatter/Gather enabled: The core ignores the frame number, sending packets immediately as the packets are ready. Scatter/Gather disabled: Periodic transfer interrupt feature is enabled; the application can program transfers for multiple frames for periodic endpoints. - 0b1 - - - - - NakOnBble - Set NAK automatically on babble - 16 - 16 - read-write - - - - - DSTS - Device Status Register - 0x808 - 32 - 0x00000002 - 0xFFFFFFFF - - - SuspSts - Suspend Status - 0 - 0 - read-only - - - EnumSpd - Enumerated Speed - 1 - 2 - read-only - - - value1 - Reserved - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Full speed (PHY clock is running at 48 MHz) - 0b11 - - - - - ErrticErr - Erratic Error - 3 - 3 - read-only - - - SOFFN - Frame Number of the Received SOF - 8 - 21 - read-only - - - - - DIEPMSK - Device IN Endpoint Common Interrupt Mask Register - 0x810 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferComplMsk - Transfer Completed Interrupt Mask - 0 - 0 - read-write - - - EPDisbldMsk - Endpoint Disabled Interrupt Mask - 1 - 1 - read-write - - - AHBErrMsk - AHB Error Mask - 2 - 2 - read-write - - - TimeOUTMsk - Timeout Condition Mask - 3 - 3 - read-write - - - INTknTXFEmpMsk - IN Token Received When TxFIFO Empty Mask - 4 - 4 - read-write - - - INEPNakEffMsk - IN Endpoint NAK Effective Mask - 6 - 6 - read-write - - - TxfifoUndrnMsk - Fifo Underrun Mask - 8 - 8 - read-write - - - BNAInIntrMsk - BNA Interrupt Mask - 9 - 9 - read-write - - - NAKMsk - NAK interrupt Mask - 13 - 13 - read-write - - - - - DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register - 0x814 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferComplMsk - Transfer Completed Interrupt Mask - 0 - 0 - read-write - - - EPDisbldMsk - Endpoint Disabled Interrupt Mask - 1 - 1 - read-write - - - AHBErrMsk - AHB Error - 2 - 2 - read-write - - - SetUPMsk - SETUP Phase Done Mask - 3 - 3 - read-write - - - OUTTknEPdisMsk - OUT Token Received when Endpoint Disabled Mask - 4 - 4 - read-write - - - Back2BackSETup - Back-to-Back SETUP Packets Received Mask - 6 - 6 - read-write - - - OutPktErrMsk - OUT Packet Error Mask - 8 - 8 - read-write - - - BnaOutIntrMsk - BNA interrupt Mask - 9 - 9 - read-write - - - BbleErrMsk - Babble Interrupt Mask - 12 - 12 - read-write - - - NAKMsk - NAK Interrupt Mask - 13 - 13 - read-write - - - NYETMsk - NYET Interrupt Mask - 14 - 14 - read-write - - - - - DAINT - Device All Endpoints Interrupt Register - 0x818 - 32 - 0x00000000 - 0xFFFFFFFF - - - InEpInt - IN Endpoint Interrupt Bits - 0 - 15 - read-only - - - OutEPInt - OUT Endpoint Interrupt Bits - 16 - 31 - read-only - - - - - DAINTMSK - Device All Endpoints Interrupt Mask Register - 0x81C - 32 - 0x00000000 - 0xFFFFFFFF - - - InEpMsk - IN EP Interrupt Mask Bits - 0 - 15 - read-write - - - OutEpMsk - OUT EP Interrupt Mask Bits - 16 - 31 - read-write - - - - - DVBUSDIS - Device VBUS Discharge Time Register - 0x828 - 32 - 0x000017D7 - 0xFFFFFFFF - - - DVBUSDis - Device Vbus Discharge Time - 0 - 15 - read-write - - - - - DVBUSPULSE - Device VBUS Pulsing Time Register - 0x82C - 32 - 0x000005B8 - 0xFFFFFFFF - - - DVBUSPulse - Device Vbus Pulsing Time - 0 - 11 - read-write - - - - - DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register - 0x834 - 32 - 0x00000000 - 0xFFFFFFFF - - - InEpTxfEmpMsk - IN EP Tx FIFO Empty Interrupt Mask Bits - 0 - 15 - read-write - - - - - PCGCCTL - Power and Clock Gating Control Register - 0xE00 - 32 - 0x00000100 - 0xFFFFFFFF - - - StopPclk - Stop Pclk - 0 - 0 - read-write - - - GateHclk - Gate Hclk - 1 - 1 - read-write - - - - - - - USB0_EP0 - Universal Serial Bus - USB - 0x50040900 - - 0x0 - 0x0400 - registers - - - - DIEPCTL0 - Device Control IN Endpoint 0 Control Register - 0x000 - 32 - 0x00008000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 1 - read-write - - - value1 - 64 bytes - 0b00 - - - value2 - 32 bytes - 0b01 - - - value3 - 16 bytes - 0b10 - - - value4 - 8 bytes - 0b11 - - - - - USBActEP - USB Active Endpoint - 15 - 15 - read-only - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-only - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DIEPINT0 - Device Endpoint-0 Interrupt Register - 0x008 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - TimeOUT - Timeout Condition - 3 - 3 - read-write - - - INTknTXFEmp - IN Token Received When TxFIFO is Empty - 4 - 4 - read-write - - - INEPNakEff - IN Endpoint NAK Effective - 6 - 6 - read-write - - - TxFEmp - Transmit FIFO Empty - 7 - 7 - read-only - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - - - DIEPTSIZ0 - Device IN Endpoint 0 Transfer Size Register - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 6 - read-write - - - PktCnt - Packet Count - 19 - 20 - read-write - - - - - DIEPDMA0 - Device Endpoint-0 DMA Address Register - 0x014 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DTXFSTS0 - Device IN Endpoint Transmit FIFO Status Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - INEPTxFSpcAvail - IN Endpoint TxFIFO Space Avail - 0 - 15 - read-only - - - value1 - Endpoint TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - - - DIEPDMAB0 - Device Endpoint-0 DMA Buffer Address Register - 0x01C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - DOEPCTL0 - Device Control OUT Endpoint 0 Control Register - 0x200 - 32 - 0x00008000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 1 - read-only - - - value1 - 64 bytes - 0b00 - - - value2 - 32 bytes - 0b01 - - - value3 - 16 bytes - 0b10 - - - value4 - 8 bytes - 0b11 - - - - - USBActEP - USB Active Endpoint - 15 - 15 - read-only - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-only - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-only - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DOEPINT0 - Device Endpoint-0 Interrupt Register - 0x208 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - SetUp - SETUP Phase Done - 3 - 3 - read-write - - - OUTTknEPdis - OUT Token Received When Endpoint Disabled - 4 - 4 - read-write - - - StsPhseRcvd - Status Phase Received For Control Write - 5 - 5 - read-write - - - Back2BackSETup - Back-to-Back SETUP Packets Received - 6 - 6 - read-write - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - PktDrpSts - Packet Dropped Status - 11 - 11 - read-write - - - BbleErrIntrpt - BbleErr (Babble Error) interrupt - 12 - 12 - read-write - - - NAKIntrpt - NAK interrupt - 13 - 13 - read-write - - - NYETIntrpt - NYET interrupt - 14 - 14 - read-write - - - - - DOEPTSIZ0 - Device OUT Endpoint 0 Transfer Size Register - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 6 - read-write - - - PktCnt - Packet Count - 19 - 20 - read-write - - - SUPCnt - SETUP Packet Count - 29 - 30 - read-write - - - value1 - 1 packet - 0b01 - - - value2 - 2 packets - 0b10 - - - value3 - 3 packets - 0b11 - - - - - - - DOEPDMA0 - Device Endpoint-0 DMA Address Register - 0x214 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DOEPDMAB0 - Device Endpoint-0 DMA Buffer Address Register - 0x21C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - - - USB0_EP1 - Universal Serial Bus - USB - USB_EP - 0x50040920 - - 0x0 - 0x0400 - registers - - - - DIEPCTL_ISOCONT - Device Endpoint Control Register [ISOCONT] - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - EO_FrNum - Even/Odd Frame - 16 - 16 - read-only - - - value1 - Even frame - 0b0 - - - value2 - Odd rame - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetEvenFr - In non-Scatter/Gather DMA mode: Set Even frame - 28 - 28 - write-only - - - SetOddFr - Set Odd frame - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DIEPCTL_INTBULK - Device Endpoint Control Register [INTBULK] - DIEPCTL_ISOCONT - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - DPID - Endpoint Data PID - 16 - 16 - read-only - - - value1 - DATA0 - 0b0 - - - value2 - DATA1 - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetD0PID - Set DATA0 PID - 28 - 28 - write-only - - - SetD1PID - 29 Set DATA1 PID - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DIEPINT - Device Endpoint Interrupt Register - 0x008 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - TimeOUT - Timeout Condition - 3 - 3 - read-write - - - INTknTXFEmp - IN Token Received When TxFIFO is Empty - 4 - 4 - read-write - - - INEPNakEff - IN Endpoint NAK Effective - 6 - 6 - read-write - - - TxFEmp - Transmit FIFO Empty - 7 - 7 - read-only - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - - - DIEPTSIZ - Device Endpoint Transfer Size Register - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - - - DIEPDMA - Device Endpoint DMA Address Register - 0x014 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DTXFSTS - Device IN Endpoint Transmit FIFO Status Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - INEPTxFSpcAvail - IN Endpoint TxFIFO Space Avail - 0 - 15 - read-only - - - value1 - Endpoint TxFIFO is full - 0x0 - - - value2 - 1 word available - 0x1 - - - value3 - 2 words available - 0x2 - - - - - - - DIEPDMAB - Device Endpoint DMA Buffer Address Register - 0x01C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - DOEPCTL_ISOCONT - Device Endpoint Control Register [ISOCONT] - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - EO_FrNum - Even/Odd Frame - 16 - 16 - read-only - - - value1 - Even frame - 0b0 - - - value2 - Odd rame - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetEvenFr - In non-Scatter/Gather DMA mode: Set Even frame - 28 - 28 - write-only - - - SetOddFr - Set Odd frame - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DOEPCTL_INTBULK - Device Endpoint Control Register [INTBULK] - DOEPCTL_ISOCONT - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - USBActEP - USB Active Endpoint - 15 - 15 - read-write - - - DPID - Endpoint Data PID - 16 - 16 - read-only - - - value1 - DATA0 - 0b0 - - - value2 - DATA1 - 0b1 - - - - - NAKSts - NAK Status - 17 - 17 - read-only - - - value1 - The core is transmitting non-NAK handshakes based on the FIFO status. - 0b0 - - - value2 - The core is transmitting NAK handshakes on this endpoint. - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - Snp - Snoop Mode - 20 - 20 - read-write - - - Stall - STALL Handshake - 21 - 21 - read-write - - - TxFNum - TxFIFO Number - 22 - 25 - read-write - - - CNAK - Clear NAK - 26 - 26 - write-only - - - SNAK - Set NAK - 27 - 27 - write-only - - - SetD0PID - Set DATA0 PID - 28 - 28 - write-only - - - SetD1PID - 29 Set DATA1 PID - 29 - 29 - write-only - - - EPDis - Endpoint Disable - 30 - 30 - read-write - - - EPEna - Endpoint Enable - 31 - 31 - read-write - - - - - DOEPINT - Device Endpoint Interrupt Register - 0x208 - 32 - 0x00000080 - 0xFFFFFFFF - - - XferCompl - Transfer Completed Interrupt - 0 - 0 - read-write - - - EPDisbld - Endpoint Disabled Interrupt - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - SetUp - SETUP Phase Done - 3 - 3 - read-write - - - OUTTknEPdis - OUT Token Received When Endpoint Disabled - 4 - 4 - read-write - - - StsPhseRcvd - Status Phase Received For Control Write - 5 - 5 - read-write - - - Back2BackSETup - Back-to-Back SETUP Packets Received - 6 - 6 - read-write - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 9 - 9 - read-write - - - PktDrpSts - Packet Dropped Status - 11 - 11 - read-write - - - BbleErrIntrpt - BbleErr (Babble Error) interrupt - 12 - 12 - read-write - - - NAKIntrpt - NAK interrupt - 13 - 13 - read-write - - - NYETIntrpt - NYET interrupt - 14 - 14 - read-write - - - - - DOEPTSIZ_ISO - Device Endpoint Transfer Size Register [ISO] - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - RxDPID - Received Data PID - 29 - 30 - read-only - - - value1 - DATA0 - 0b00 - - - value2 - DATA2 - 0b01 - - - value3 - DATA1 - 0b10 - - - value4 - MDATA - 0b11 - - - - - - - DOEPTSIZ_CONTROL - Device Endpoint Transfer Size Register [CONT] - DOEPTSIZ_ISO - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - SUPCnt - SETUP Packet Count - 29 - 30 - read-write - - - value1 - 1 packet - 0b01 - - - value2 - 2 packets - 0b10 - - - value3 - 3 packets - 0b11 - - - - - - - DOEPDMA - Device Endpoint DMA Address Register - 0x214 - 32 - 0x00000000 - 0x00000000 - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - DOEPDMAB - Device Endpoint DMA Buffer Address Register - 0x21C - 32 - 0x00000000 - 0x00000000 - - - DMABufferAddr - DMA Buffer Address - 0 - 31 - read-only - - - - - - - USB0_EP2 - Universal Serial Bus - USB - 0x50040940 - - 0x0 - 0x0400 - registers - - - - USB0_EP3 - Universal Serial Bus - USB - 0x50040960 - - 0x0 - 0x0400 - registers - - - - USB0_EP4 - Universal Serial Bus - USB - 0x50040980 - - 0x0 - 0x0400 - registers - - - - USB0_EP5 - Universal Serial Bus - USB - 0x500409A0 - - 0x0 - 0x0400 - registers - - - - USB0_EP6 - Universal Serial Bus - USB - 0x500409C0 - - 0x0 - 0x0400 - registers - - - - USB0_CH0 - Universal Serial Bus - USB - USB_CH - 0x50040500 - - 0x0 - 0x20 - registers - - - - HCCHAR - Host Channel Characteristics Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPS - Maximum Packet Size - 0 - 10 - read-write - - - EPNum - Endpoint Number - 11 - 14 - read-write - - - EPDir - Endpoint Direction - 15 - 15 - read-write - - - value1 - OUT - 0b0 - - - value2 - IN - 0b1 - - - - - EPType - Endpoint Type - 18 - 19 - read-write - - - value1 - Control - 0b00 - - - value2 - Isochronous - 0b01 - - - value3 - Bulk - 0b10 - - - value4 - Interrupt - 0b11 - - - - - MC_EC - Multi Count / Error Count - 20 - 21 - read-write - - - value1 - Reserved. This field yields undefined results. - 0b00 - - - value2 - 1 transaction - 0b01 - - - value3 - 2 transactions to be issued for this endpoint per frame - 0b10 - - - value4 - 3 transactions to be issued for this endpoint per frame - 0b11 - - - - - DevAddr - Device Address - 22 - 28 - read-write - - - OddFrm - Odd Frame - 29 - 29 - read-write - - - value1 - Even frame - 0b0 - - - value2 - Odd frame - 0b1 - - - - - ChDis - Channel Disable - 30 - 30 - read-write - - - ChEna - Channel Enable - 31 - 31 - read-write - - - value1 - Scatter/Gather mode enabled: Indicates that the descriptor structure is not yet ready. Scatter/Gather mode disabled: Channel disabled - 0b0 - - - value2 - Scatter/Gather mode enabled: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor. Scatter/Gather mode disabled: Channel enabled - 0b1 - - - - - - - HCINT - Host Channel Interrupt Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferCompl - Transfer Completed - 0 - 0 - read-write - - - ChHltd - Channel Halted - 1 - 1 - read-write - - - AHBErr - AHB Error - 2 - 2 - read-write - - - STALL - STALL Response Received Interrupt - 3 - 3 - read-write - - - NAK - NAK Response Received Interrupt - 4 - 4 - read-write - - - ACK - ACK Response Received/Transmitted Interrupt - 5 - 5 - read-write - - - NYET - NYET Response Received Interrupt - 6 - 6 - read-write - - - XactErr - Transaction Error - 7 - 7 - read-write - - - BblErr - Babble Error - 8 - 8 - read-write - - - FrmOvrun - Frame Overrun - 9 - 9 - read-write - - - DataTglErr - Data Toggle Error - 10 - 10 - read-write - - - BNAIntr - BNA (Buffer Not Available) Interrupt - 11 - 11 - read-write - - - XCS_XACT_ERR - Excessive Transaction Error - 12 - 12 - read-write - - - DESC_LST_ROLLIntr - Descriptor rollover interrupt - 13 - 13 - read-write - - - - - HCINTMSK - Host Channel Interrupt Mask Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - XferComplMsk - Transfer Completed Mask - 0 - 0 - read-write - - - ChHltdMsk - Channel Halted Mask - 1 - 1 - read-write - - - AHBErrMsk - AHB Error Mask - 2 - 2 - read-write - - - StallMsk - STALL Response Received Interrupt Mask - 3 - 3 - read-write - - - NakMsk - NAK Response Received Interrupt Mask - 4 - 4 - read-write - - - AckMsk - ACK Response Received/Transmitted Interrupt Mask - 5 - 5 - read-write - - - NyetMsk - NYET Response Received Interrupt Mask - 6 - 6 - read-write - - - XactErrMsk - Transaction Error Mask - 7 - 7 - read-write - - - BblErrMsk - Babble Error Mask - 8 - 8 - read-write - - - FrmOvrunMsk - Frame Overrun Mask - 9 - 9 - read-write - - - DataTglErrMsk - Data Toggle Error Mask - 10 - 10 - read-write - - - BNAIntrMsk - BNA (Buffer Not Available) Interrupt mask register - 11 - 11 - read-write - - - DESC_LST_ROLLIntrMsk - Descriptor rollover interrupt Mask register - 13 - 13 - read-write - - - - - HCTSIZ_BUFFERMODE - Host Channel Transfer Size Register [BUFFERMODE] - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XferSize - Transfer Size - 0 - 18 - read-write - - - PktCnt - Packet Count - 19 - 28 - read-write - - - Pid - PID - 29 - 30 - read-write - - - value1 - DATA0 - 0b00 - - - value2 - DATA2 - 0b01 - - - value3 - DATA1 - 0b10 - - - value4 - MDATA (non-control)/SETUP (control) - 0b11 - - - - - - - HCTSIZ_SCATGATHER - Host Channel Transfer Size Register [SCATGATHER] - HCTSIZ_BUFFERMODE - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCHED_INFO - Schedule information - 0 - 7 - read-write - - - NTD - Number of Transfer Descriptors - 8 - 15 - read-write - - - Pid - PID - 29 - 30 - read-write - - - value1 - DATA0 - 0b00 - - - value2 - DATA2 - 0b01 - - - value3 - DATA1 - 0b10 - - - value4 - MDATA (non-control) - 0b11 - - - - - - - HCDMA_BUFFERMODE - Host Channel DMA Address Register [BUFFERMODE] - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMAAddr - DMA Address - 0 - 31 - read-write - - - - - HCDMA_SCATGATHER - Host Channel DMA Address Register [SCATGATHER] - HCDMA_BUFFERMODE - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CTD - Current Transfer Desc: - 3 - 8 - read-write - - - value1 - 1 descriptor - 0 - - - value2 - 64 descriptors - 63 - - - - - DMAAddr - DMA Address - 9 - 31 - read-write - - - - - HCDMAB - Host Channel DMA Buffer Address Register - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - Buffer_Address - Buffer Address - 0 - 31 - read-only - - - - - - - USB0_CH1 - Universal Serial Bus - USB - 0x50040520 - - 0x0 - 0x20 - registers - - - - USB0_CH2 - Universal Serial Bus - USB - 0x50040540 - - 0x0 - 0x20 - registers - - - - USB0_CH3 - Universal Serial Bus - USB - 0x50040560 - - 0x0 - 0x20 - registers - - - - USB0_CH4 - Universal Serial Bus - USB - 0x50040580 - - 0x0 - 0x20 - registers - - - - USB0_CH5 - Universal Serial Bus - USB - 0x500405A0 - - 0x0 - 0x20 - registers - - - - USB0_CH6 - Universal Serial Bus - USB - 0x500405C0 - - 0x0 - 0x20 - registers - - - - USB0_CH7 - Universal Serial Bus - USB - 0x500405E0 - - 0x0 - 0x20 - registers - - - - USB0_CH8 - Universal Serial Bus - USB - 0x50040600 - - 0x0 - 0x20 - registers - - - - USB0_CH9 - Universal Serial Bus - USB - 0x50040620 - - 0x0 - 0x20 - registers - - - - USB0_CH10 - Universal Serial Bus - USB - 0x50040640 - - 0x0 - 0x20 - registers - - - - USB0_CH11 - Universal Serial Bus - USB - 0x50040660 - - 0x0 - 0x20 - registers - - - - USB0_CH12 - Universal Serial Bus - USB - 0x50040680 - - 0x0 - 0x20 - registers - - - - USB0_CH13 - Universal Serial Bus - USB - 0x500406A0 - - 0x0 - 0x20 - registers - - - - USIC0 - Universal Serial Interface Controller 0 - USIC - USIC - 0x40030008 - - 0 - 4 - registers - - - - ID - Module Identification Register - 0 - 32 - 0x00AAC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - - - USIC1 - Universal Serial Interface Controller 1 - USIC - 0x48020008 - - 0 - 4 - registers - - - - USIC2 - Universal Serial Interface Controller 2 - USIC - 0x48024008 - - 0 - 4 - registers - - - - USIC0_CH0 - Universal Serial Interface Controller 0 - USIC - USIC_CH - 0x40030000 - - 0x0 - 0x0200 - registers - - - - CCFG - Channel Configuration Register - 0x004 - 32 - 0x000000CF - 0xFFFFFFFF - - - SSC - SSC Protocol Available - 0 - 0 - read-only - - - value1 - The SSC protocol is not available. - 0b0 - - - value2 - The SSC protocol is available. - 0b1 - - - - - ASC - ASC Protocol Available - 1 - 1 - read-only - - - value1 - The ASC protocol is not available. - 0b0 - - - value2 - The ASC protocol is available. - 0b1 - - - - - IIC - IIC Protocol Available - 2 - 2 - read-only - - - value1 - The IIC protocol is not available. - 0b0 - - - value2 - The IIC protocol is available. - 0b1 - - - - - IIS - IIS Protocol Available - 3 - 3 - read-only - - - value1 - The IIS protocol is not available. - 0b0 - - - value2 - The IIS protocol is available. - 0b1 - - - - - RB - Receive FIFO Buffer Available - 6 - 6 - read-only - - - value1 - A receive FIFO buffer is not available. - 0b0 - - - value2 - A receive FIFO buffer is available. - 0b1 - - - - - TB - Transmit FIFO Buffer Available - 7 - 7 - read-only - - - value1 - A transmit FIFO buffer is not available. - 0b0 - - - value2 - A transmit FIFO buffer is available. - 0b1 - - - - - - - KSCFG - Kernel State Configuration Register - 0x00C - 32 - 0x00000000 - 0xFFFFFFFF - - - MODEN - Module Enable - 0 - 0 - read-write - - - value1 - The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). - 0b0 - - - value2 - The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other GPDMA registers. - 0b1 - - - - - BPMODEN - Bit Protection for MODEN - 1 - 1 - write-only - - - value1 - MODEN is not changed. - 0b0 - - - value2 - MODEN is updated with the written value. - 0b1 - - - - - NOMCFG - Normal Operation Mode Configuration - 4 - 5 - read-write - - - value1 - Run mode 0 is selected. - 0b00 - - - value2 - Run mode 1 is selected. - 0b01 - - - value3 - Stop mode 0 is selected. - 0b10 - - - value4 - Stop mode 1 is selected. - 0b11 - - - - - BPNOM - Bit Protection for NOMCFG - 7 - 7 - write-only - - - value1 - NOMCFG is not changed. - 0b0 - - - value2 - NOMCFG is updated with the written value. - 0b1 - - - - - SUMCFG - Suspend Mode Configuration - 8 - 9 - read-write - - - BPSUM - Bit Protection for SUMCFG - 11 - 11 - write-only - - - value1 - SUMCFG is not changed. - 0b0 - - - value2 - SUMCFG is updated with the written value. - 0b1 - - - - - - - FDR - Fractional Divider Register - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - STEP - Step Value - 0 - 9 - read-write - - - DM - Divider Mode - 14 - 15 - read-write - - - value1 - The divider is switched off, fFD = 0. - 0b00 - - - value2 - Normal divider mode selected. - 0b01 - - - value3 - Fractional divider mode selected. - 0b10 - - - value4 - The divider is switched off, fFD = 0. - 0b11 - - - - - RESULT - Result Value - 16 - 25 - read-only - - - - - BRG - Baud Rate Generator Register - 0x014 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLKSEL - Clock Selection - 0 - 1 - read-write - - - value1 - The fractional divider frequency fFD is selected. - 0b00 - - - value2 - Reserved, no action - 0b01 - - - value3 - The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. - 0b10 - - - value4 - Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. - 0b11 - - - - - TMEN - Timing Measurement Enable - 3 - 3 - read-write - - - value1 - Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored. - 0b0 - - - value2 - Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. - 0b1 - - - - - PPPEN - Enable 2:1 Divider for fPPP - 4 - 4 - read-write - - - value1 - The 2:1 divider for fPPP is disabled. fPPP = fPIN - 0b0 - - - value2 - The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. - 0b1 - - - - - CTQSEL - Input Selection for CTQ - 6 - 7 - read-write - - - value1 - fCTQIN = fPDIV - 0b00 - - - value2 - fCTQIN = fPPP - 0b01 - - - value3 - fCTQIN = fSCLK - 0b10 - - - value4 - fCTQIN = fMCLK - 0b11 - - - - - PCTQ - Pre-Divider for Time Quanta Counter - 8 - 9 - read-write - - - DCTQ - Denominator for Time Quanta Counter - 10 - 14 - read-write - - - PDIV - Divider Mode: Divider Factor to Generate fPDIV - 16 - 25 - read-write - - - SCLKOSEL - Shift Clock Output Select - 28 - 28 - read-write - - - value1 - SCLK from the baud rate generator is selected as the SCLKOUT input source. - 0b0 - - - value2 - The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. - 0b1 - - - - - MCLKCFG - Master Clock Configuration - 29 - 29 - read-write - - - value1 - The passive level is 0. - 0b0 - - - value2 - The passive level is 1. - 0b1 - - - - - SCLKCFG - Shift Clock Output Configuration - 30 - 31 - read-write - - - value1 - The passive level is 0 and the delay is disabled. - 0b00 - - - value2 - The passive level is 1 and the delay is disabled. - 0b01 - - - value3 - The passive level is 0 and the delay is enabled. - 0b10 - - - value4 - The passive level is 1 and the delay is enabled. - 0b11 - - - - - - - INPR - Interrupt Node Pointer Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSINP - Transmit Shift Interrupt Node Pointer - 0 - 2 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - TBINP - Transmit Buffer Interrupt Node Pointer - 4 - 6 - read-write - - - RINP - Receive Interrupt Node Pointer - 8 - 10 - read-write - - - AINP - Alternative Receive Interrupt Node Pointer - 12 - 14 - read-write - - - PINP - Protocol Interrupt Node Pointer - 16 - 18 - read-write - - - - - DX0CR - Input Control Register 0 - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX1CR - Input Control Register 1 - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DX1A is selected. - 0b000 - - - value2 - The data input DX1B is selected. - 0b001 - - - value3 - The data input DX1C is selected. - 0b010 - - - value4 - The data input DX1D is selected. - 0b011 - - - value5 - The data input DX1E is selected. - 0b100 - - - value6 - The data input DX1F is selected. - 0b101 - - - value7 - The data input DX1G is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - DCEN - Delay Compensation Enable - 3 - 3 - read-write - - - value1 - The receive shift clock is dependent on INSW selection. - 0b0 - - - value2 - The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. - 0b1 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DX1T. - 0b01 - - - value3 - A falling edge activates DX1T. - 0b10 - - - value4 - Both edges activate DX1T. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DX1S is 0. - 0b0 - - - value2 - The current value of DX1S is 1. - 0b1 - - - - - - - DX2CR - Input Control Register 2 - 0x024 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX3CR - Input Control Register 3 - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX4CR - Input Control Register 4 - 0x02C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - DX5CR - Input Control Register 5 - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSEL - Data Selection for Input Signal - 0 - 2 - read-write - - - value1 - The data input DXnA is selected. - 0b000 - - - value2 - The data input DXnB is selected. - 0b001 - - - value3 - The data input DXnC is selected. - 0b010 - - - value4 - The data input DXnD is selected. - 0b011 - - - value5 - The data input DXnE is selected. - 0b100 - - - value6 - The data input DXnF is selected. - 0b101 - - - value7 - The data input DXnG is selected. - 0b110 - - - value8 - The data input is always 1. - 0b111 - - - - - INSW - Input Switch - 4 - 4 - read-write - - - value1 - The input of the data shift unit is controlled by the protocol pre-processor. - 0b0 - - - value2 - The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. - 0b1 - - - - - DFEN - Digital Filter Enable - 5 - 5 - read-write - - - value1 - The input signal is not digitally filtered. - 0b0 - - - value2 - The input signal is digitally filtered. - 0b1 - - - - - DSEN - Data Synchronization Enable - 6 - 6 - read-write - - - value1 - The un-synchronized signal can be taken as input for the data shift unit. - 0b0 - - - value2 - The synchronized signal can be taken as input for the data shift unit. - 0b1 - - - - - DPOL - Data Polarity for DXn - 8 - 8 - read-write - - - value1 - The input signal is not inverted. - 0b0 - - - value2 - The input signal is inverted. - 0b1 - - - - - SFSEL - Sampling Frequency Selection - 9 - 9 - read-write - - - value1 - The sampling frequency is fPB. - 0b0 - - - value2 - The sampling frequency is fFD. - 0b1 - - - - - CM - Combination Mode - 10 - 11 - read-write - - - value1 - The trigger activation is disabled. - 0b00 - - - value2 - A rising edge activates DXnT. - 0b01 - - - value3 - A falling edge activates DXnT. - 0b10 - - - value4 - Both edges activate DXnT. - 0b11 - - - - - DXS - Synchronized Data Value - 15 - 15 - read-only - - - value1 - The current value of DXnS is 0. - 0b0 - - - value2 - The current value of DXnS is 1. - 0b1 - - - - - - - SCTR - Shift Control Register - 0x034 - 32 - 0x00000000 - 0xFFFFFFFF - - - SDIR - Shift Direction - 0 - 0 - read-write - - - value1 - Shift LSB first. The first data bit of a data word is located at bit position 0. - 0b0 - - - value2 - Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE. - 0b1 - - - - - PDL - Passive Data Level - 1 - 1 - read-write - - - value1 - The passive data level is 0. - 0b0 - - - value2 - The passive data level is 1. - 0b1 - - - - - DSM - Data Shift Mode - 2 - 3 - read-write - - - value1 - Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0. - 0b00 - - - value2 - Reserved. - 0b01 - - - value3 - Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively. - 0b10 - - - value4 - Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively. - 0b11 - - - - - HPCDIR - Port Control Direction - 4 - 4 - read-write - - - value1 - The pin(s) with hardware pin control enabled are selected to be in input mode. - 0b0 - - - value2 - The pin(s) with hardware pin control enabled are selected to be in output mode. - 0b1 - - - - - DOCFG - Data Output Configuration - 6 - 7 - read-write - - - value1 - DOUTx = shift data value - 0b00 - - - value2 - DOUTx = inverted shift data value - 0b01 - - - - - TRM - Transmission Mode - 8 - 9 - read-write - - - value1 - The shift control signal is considered as inactive and data frame transfers are not possible. - 0b00 - - - value2 - The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. - 0b01 - - - value3 - The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. - 0b10 - - - value4 - The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. - 0b11 - - - - - FLE - Frame Length - 16 - 21 - read-write - - - WLE - Word Length - 24 - 27 - read-write - - - value1 - The data word contains 1 data bit located at bit position 0. - 0x0 - - - value2 - The data word contains 2 data bits located at bit positions [1:0]. - 0x1 - - - value3 - The data word contains 15 data bits located at bit positions [14:0]. - 0xE - - - value4 - The data word contains 16 data bits located at bit positions [15:0]. - 0xF - - - - - - - TCSR - Transmit Control/Status Register - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLEMD - WLE Mode - 0 - 0 - read-write - - - value1 - The automatic update of SCTR.WLE and TCSR.EOF is disabled. - 0b0 - - - value2 - The automatic update of SCTR.WLE and TCSR.EOF is enabled. - 0b1 - - - - - SELMD - Select Mode - 1 - 1 - read-write - - - value1 - The automatic update of PCR.CTR[23:16] is disabled. - 0b0 - - - value2 - The automatic update of PCR.CTR[23:16] is disabled. - 0b1 - - - - - FLEMD - FLE Mode - 2 - 2 - read-write - - - value1 - The automatic update of FLE is disabled. - 0b0 - - - value2 - The automatic update of FLE is enabled. - 0b1 - - - - - WAMD - WA Mode - 3 - 3 - read-write - - - value1 - The automatic update of bit WA is disabled. - 0b0 - - - value2 - The automatic update of bit WA is enabled. - 0b1 - - - - - HPCMD - Hardware Port Control Mode - 4 - 4 - read-write - - - value1 - The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled. - 0b0 - - - value2 - The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled. - 0b1 - - - - - SOF - Start Of Frame - 5 - 5 - read-write - - - value1 - The data word in TBUF is not considered as first word of a frame. - 0b0 - - - value2 - The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). - 0b1 - - - - - EOF - End Of Frame - 6 - 6 - read-write - - - value1 - The data word in TBUF is not considered as last word of an SSC frame. - 0b0 - - - value2 - The data word in TBUF is considered as last word of an SSC frame. - 0b1 - - - - - TDV - Transmit Data Valid - 7 - 7 - read-only - - - value1 - The data word in TBUF is not valid for transmission. - 0b0 - - - value2 - The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. - 0b1 - - - - - TDSSM - TBUF Data Single Shot Mode - 8 - 8 - read-write - - - value1 - The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. - 0b0 - - - value2 - The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. - 0b1 - - - - - TDEN - TBUF Data Enable - 10 - 11 - read-write - - - value1 - A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. - 0b00 - - - value2 - A transmission of the data word in TBUF can be started if TDV = 1. - 0b01 - - - value3 - A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. - 0b10 - - - value4 - A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. - 0b11 - - - - - TDVTR - TBUF Data Valid Trigger - 12 - 12 - read-write - - - value1 - Bit TCSR.TE is permanently set. - 0b0 - - - value2 - Bit TCSR.TE is set if DX2T becomes active while TDV = 1. - 0b1 - - - - - WA - Word Address - 13 - 13 - read-write - - - value1 - The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA). - 0b0 - - - value2 - The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA). - 0b1 - - - - - TSOF - Transmitted Start Of Frame - 24 - 24 - read-only - - - value1 - The latest data word transmission has not been started for the first word of a data frame. - 0b0 - - - value2 - The latest data word transmission has been started for the first word of a data frame. - 0b1 - - - - - TV - Transmission Valid - 26 - 26 - read-only - - - value1 - The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started. - 0b0 - - - value2 - The latest start of a data word transmission has taken place with valid data from TBUF. - 0b1 - - - - - TVC - Transmission Valid Cumulated - 27 - 27 - read-only - - - value1 - Since TVC has been set, at least one data buffer underflow condition has occurred. - 0b0 - - - value2 - Since TVC has been set, no data buffer underflow condition has occurred. - 0b1 - - - - - TE - Trigger Event - 28 - 28 - read-only - - - value1 - The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started. - 0b0 - - - value2 - The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can be started. - 0b1 - - - - - - - PCR - Protocol Control Register - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - CTR0 - Protocol Control Bit 0 - 0 - 0 - read-write - - - CTR1 - Protocol Control Bit 1 - 1 - 1 - read-write - - - CTR2 - Protocol Control Bit 2 - 2 - 2 - read-write - - - CTR3 - Protocol Control Bit 3 - 3 - 3 - read-write - - - CTR4 - Protocol Control Bit 4 - 4 - 4 - read-write - - - CTR5 - Protocol Control Bit 5 - 5 - 5 - read-write - - - CTR6 - Protocol Control Bit 6 - 6 - 6 - read-write - - - CTR7 - Protocol Control Bit 7 - 7 - 7 - read-write - - - CTR8 - Protocol Control Bit 8 - 8 - 8 - read-write - - - CTR9 - Protocol Control Bit 9 - 9 - 9 - read-write - - - CTR10 - Protocol Control Bit 10 - 10 - 10 - read-write - - - CTR11 - Protocol Control Bit 11 - 11 - 11 - read-write - - - CTR12 - Protocol Control Bit 12 - 12 - 12 - read-write - - - CTR13 - Protocol Control Bit 13 - 13 - 13 - read-write - - - CTR14 - Protocol Control Bit 14 - 14 - 14 - read-write - - - CTR15 - Protocol Control Bit 15 - 15 - 15 - read-write - - - CTR16 - Protocol Control Bit 16 - 16 - 16 - read-write - - - CTR17 - Protocol Control Bit 17 - 17 - 17 - read-write - - - CTR18 - Protocol Control Bit 18 - 18 - 18 - read-write - - - CTR19 - Protocol Control Bit 19 - 19 - 19 - read-write - - - CTR20 - Protocol Control Bit 20 - 20 - 20 - read-write - - - CTR21 - Protocol Control Bit 21 - 21 - 21 - read-write - - - CTR22 - Protocol Control Bit 22 - 22 - 22 - read-write - - - CTR23 - Protocol Control Bit 23 - 23 - 23 - read-write - - - CTR24 - Protocol Control Bit 24 - 24 - 24 - read-write - - - CTR25 - Protocol Control Bit 25 - 25 - 25 - read-write - - - CTR26 - Protocol Control Bit 26 - 26 - 26 - read-write - - - CTR27 - Protocol Control Bit 27 - 27 - 27 - read-write - - - CTR28 - Protocol Control Bit 28 - 28 - 28 - read-write - - - CTR29 - Protocol Control Bit 29 - 29 - 29 - read-write - - - CTR30 - Protocol Control Bit 30 - 30 - 30 - read-write - - - CTR31 - Protocol Control Bit 31 - 31 - 31 - read-write - - - - - PCR_ASCMode - Protocol Control Register [ASC Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - SMD - Sample Mode - 0 - 0 - read-write - - - value1 - Only one sample is taken per bit time. The current input value is sampled. - 0b0 - - - value2 - Three samples are taken per bit time and a majority decision is made. - 0b1 - - - - - STPB - Stop Bits - 1 - 1 - read-write - - - value1 - The number of stop bits is 1. - 0b0 - - - value2 - The number of stop bits is 2. - 0b1 - - - - - IDM - Idle Detection Mode - 2 - 2 - read-write - - - value1 - The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. - 0b0 - - - value2 - The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). - 0b1 - - - - - SBIEN - Synchronization Break Interrupt Enable - 3 - 3 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - CDEN - Collision Detection Enable - 4 - 4 - read-write - - - value1 - The collision detection is disabled. - 0b0 - - - value2 - If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software. - 0b1 - - - - - RNIEN - Receiver Noise Detection Interrupt Enable - 5 - 5 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - FEIEN - Format Error Interrupt Enable - 6 - 6 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - FFIEN - Frame Finished Interrupt Enable - 7 - 7 - read-write - - - value1 - The interrupt generation is disabled. - 0b0 - - - value2 - The interrupt generation is enabled. - 0b1 - - - - - SP - Sample Point - 8 - 12 - read-write - - - PL - Pulse Length - 13 - 15 - read-write - - - value1 - The pulse length is equal to the bit length (no shortened 0). - 0b000 - - - value2 - The pulse length of a 0 bit is 2 time quanta. - 0b001 - - - value3 - The pulse length of a 0 bit is 3 time quanta. - 0b010 - - - value4 - The pulse length of a 0 bit is 8 time quanta. - 0b111 - - - - - RSTEN - Receiver Status Enable - 16 - 16 - read-write - - - value1 - Flag PSR[9] is not modified depending on the receiver status. - 0b0 - - - value2 - Flag PSR[9] is set during the complete reception of a frame. - 0b1 - - - - - TSTEN - Transmitter Status Enable - 17 - 17 - read-write - - - value1 - Flag PSR[9] is not modified depending on the transmitter status. - 0b0 - - - value2 - Flag PSR[9] is set during the complete transmission of a frame. - 0b1 - - - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and the MCLK signal is 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - PCR_SSCMode - Protocol Control Register [SSC Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - MSLSEN - MSLS Enable - 0 - 0 - read-write - - - value1 - The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. - 0b0 - - - value2 - The MSLS generation is enabled. This is the setting for SSC master mode. - 0b1 - - - - - SELCTR - Select Control - 1 - 1 - read-write - - - value1 - The coded select mode is enabled. - 0b0 - - - value2 - The direct select mode is enabled. - 0b1 - - - - - SELINV - Select Inversion - 2 - 2 - read-write - - - value1 - The SELO outputs have the same polarity as the MSLS signal (active high). - 0b0 - - - value2 - The SELO outputs have the inverted polarity to the MSLS signal (active low). - 0b1 - - - - - FEM - Frame End Mode - 3 - 3 - read-write - - - value1 - The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). - 0b0 - - - value2 - The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. - 0b1 - - - - - CTQSEL1 - Input Frequency Selection - 4 - 5 - read-write - - - value1 - fCTQIN = fPDIV - 0b00 - - - value2 - fCTQIN = fPPP - 0b01 - - - value3 - fCTQIN = fSCLK - 0b10 - - - value4 - fCTQIN = fMCLK - 0b11 - - - - - PCTQ1 - Divider Factor PCTQ1 for Tiw and Tnf - 6 - 7 - read-write - - - DCTQ1 - Divider Factor DCTQ1 for Tiw and Tnf - 8 - 12 - read-write - - - PARIEN - Parity Error Interrupt Enable - 13 - 13 - read-write - - - value1 - A protocol interrupt is not generated with the detection of a parity error. - 0b0 - - - value2 - A protocol interrupt is generated with the detection of a parity error. - 0b1 - - - - - MSLSIEN - MSLS Interrupt Enable - 14 - 14 - read-write - - - value1 - A protocol interrupt is not generated if a change of signal MSLS is detected. - 0b0 - - - value2 - A protocol interrupt is generated if a change of signal MSLS is detected. - 0b1 - - - - - DX2TIEN - DX2T Interrupt Enable - 15 - 15 - read-write - - - value1 - A protocol interrupt is not generated if DX2T is activated. - 0b0 - - - value2 - A protocol interrupt is generated if DX2T is activated. - 0b1 - - - - - SELO - Select Output - 16 - 23 - read-write - - - value1 - The corresponding SELOx line cannot be activated. - 0b0 - - - value2 - The corresponding SELOx line can be activated (according to the mode selected by SELCTR). - 0b1 - - - - - TIWEN - Enable Inter-Word Delay Tiw - 24 - 24 - read-write - - - value1 - No delay between data words of the same frame. - 0b0 - - - value2 - The inter-word delay Tiw is enabled and introduced between data words of the same frame. - 0b1 - - - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and output MCLK = 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - PCR_IICMode - Protocol Control Register [IIC Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - SLAD - Slave Address - 0 - 15 - read-write - - - ACK00 - Acknowledge 00H - 16 - 16 - read-write - - - value1 - The slave device is not sensitive to this address. - 0b0 - - - value2 - The slave device is sensitive to this address. - 0b1 - - - - - STIM - Symbol Timing - 17 - 17 - read-write - - - value1 - A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud). - 0b0 - - - value2 - A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud). - 0b1 - - - - - SCRIEN - Start Condition Received Interrupt Enable - 18 - 18 - read-write - - - value1 - The start condition interrupt is disabled. - 0b0 - - - value2 - The start condition interrupt is enabled. - 0b1 - - - - - RSCRIEN - Repeated Start Condition Received Interrupt Enable - 19 - 19 - read-write - - - value1 - The repeated start condition interrupt is disabled. - 0b0 - - - value2 - The repeated start condition interrupt is enabled. - 0b1 - - - - - PCRIEN - Stop Condition Received Interrupt Enable - 20 - 20 - read-write - - - value1 - The stop condition interrupt is disabled. - 0b0 - - - value2 - The stop condition interrupt is enabled. - 0b1 - - - - - NACKIEN - Non-Acknowledge Interrupt Enable - 21 - 21 - read-write - - - value1 - The non-acknowledge interrupt is disabled. - 0b0 - - - value2 - The non-acknowledge interrupt is enabled. - 0b1 - - - - - ARLIEN - Arbitration Lost Interrupt Enable - 22 - 22 - read-write - - - value1 - The arbitration lost interrupt is disabled. - 0b0 - - - value2 - The arbitration lost interrupt is enabled. - 0b1 - - - - - SRRIEN - Slave Read Request Interrupt Enable - 23 - 23 - read-write - - - value1 - The slave read request interrupt is disabled. - 0b0 - - - value2 - The slave read request interrupt is enabled. - 0b1 - - - - - ERRIEN - Error Interrupt Enable - 24 - 24 - read-write - - - value1 - The error interrupt is disabled. - 0b0 - - - value2 - The error interrupt is enabled. - 0b1 - - - - - SACKDIS - Slave Acknowledge Disable - 25 - 25 - read-write - - - value1 - The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received). - 0b0 - - - value2 - The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped). - 0b1 - - - - - HDEL - Hardware Delay - 26 - 29 - read-write - - - ACKIEN - Acknowledge Interrupt Enable - 30 - 30 - read-write - - - value1 - The acknowledge interrupt is disabled. - 0b0 - - - value2 - The acknowledge interrupt is enabled. - 0b1 - - - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and MCLK is 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - PCR_IISMode - Protocol Control Register [IIS Mode] - PCR - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - WAGEN - WA Generation Enable - 0 - 0 - read-write - - - value1 - The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. - 0b0 - - - value2 - The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. - 0b1 - - - - - DTEN - Data Transfers Enable - 1 - 1 - read-write - - - value1 - The changes of the WA input signal are ignored and no transfers take place. - 0b0 - - - value2 - Transfers are enabled. - 0b1 - - - - - SELINV - Select Inversion - 2 - 2 - read-write - - - value1 - The SELOx outputs have the same polarity as the WA signal. - 0b0 - - - value2 - The SELOx outputs have the inverted polarity to the WA signal. - 0b1 - - - - - WAFEIEN - WA Falling Edge Interrupt Enable - 4 - 4 - read-write - - - value1 - A protocol interrupt is not activated if a falling edge of WA is generated. - 0b0 - - - value2 - A protocol interrupt is activated if a falling edge of WA is generated. - 0b1 - - - - - WAREIEN - WA Rising Edge Interrupt Enable - 5 - 5 - read-write - - - value1 - A protocol interrupt is not activated if a rising edge of WA is generated. - 0b0 - - - value2 - A protocol interrupt is activated if a rising edge of WA is generated. - 0b1 - - - - - ENDIEN - END Interrupt Enable - 6 - 6 - read-write - - - value1 - A protocol interrupt is not activated. - 0b0 - - - value2 - A protocol interrupt is activated. - 0b1 - - - - - DX2TIEN - DX2T Interrupt Enable - 15 - 15 - read-write - - - value1 - A protocol interrupt is not generated if DX2T is active. - 0b0 - - - value2 - A protocol interrupt is generated if DX2T is active. - 0b1 - - - - - TDEL - Transfer Delay - 16 - 21 - read-write - - - MCLK - Master Clock Enable - 31 - 31 - read-write - - - value1 - The MCLK generation is disabled and MCLK is 0. - 0b0 - - - value2 - The MCLK generation is enabled. - 0b1 - - - - - - - CCR - Channel Control Register - 0x040 - 32 - 0x00000000 - 0xFFFFFFFF - - - MODE - Operating Mode - 0 - 3 - read-write - - - value1 - The USIC channel is disabled. All protocol-related state machines are set to an idle state. - 0x0 - - - value2 - The SSC (SPI) protocol is selected. - 0x1 - - - value3 - The ASC (SCI, UART) protocol is selected. - 0x2 - - - value4 - The IIS protocol is selected. - 0x3 - - - value5 - The IIC protocol is selected. - 0x4 - - - - - HPCEN - Hardware Port Control Enable - 6 - 7 - read-write - - - value1 - The hardware port control is disabled. - 0b00 - - - value2 - The hardware port control is enabled for DX0 and DOUT0. - 0b01 - - - value3 - The hardware port control is enabled for DX3, DX0 and DOUT[1:0]. - 0b10 - - - value4 - The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0]. - 0b11 - - - - - PM - Parity Mode - 8 - 9 - read-write - - - value1 - The parity generation is disabled. - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). - 0b10 - - - value4 - Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). - 0b11 - - - - - RSIEN - Receiver Start Interrupt Enable - 10 - 10 - read-write - - - value1 - The receiver start interrupt is disabled. - 0b0 - - - value2 - The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated. - 0b1 - - - - - DLIEN - Data Lost Interrupt Enable - 11 - 11 - read-write - - - value1 - The data lost interrupt is disabled. - 0b0 - - - value2 - The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated. - 0b1 - - - - - TSIEN - Transmit Shift Interrupt Enable - 12 - 12 - read-write - - - value1 - The transmit shift interrupt is disabled. - 0b0 - - - value2 - The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated. - 0b1 - - - - - TBIEN - Transmit Buffer Interrupt Enable - 13 - 13 - read-write - - - value1 - The transmit buffer interrupt is disabled. - 0b0 - - - value2 - The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated. - 0b1 - - - - - RIEN - Receive Interrupt Enable - 14 - 14 - read-write - - - value1 - The receive interrupt is disabled. - 0b0 - - - value2 - The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated. - 0b1 - - - - - AIEN - Alternative Receive Interrupt Enable - 15 - 15 - read-write - - - value1 - The alternative receive interrupt is disabled. - 0b0 - - - value2 - The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated. - 0b1 - - - - - BRGIEN - Baud Rate Generator Interrupt Enable - 16 - 16 - read-write - - - value1 - The baud rate generator interrupt is disabled. - 0b0 - - - value2 - The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated. - 0b1 - - - - - - - CMTR - Capture Mode Timer Register - 0x044 - 32 - 0x00000000 - 0xFFFFFFFF - - - CTV - Captured Timer Value - 0 - 9 - read-write - - - - - PSR - Protocol Status Register - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - ST0 - Protocol Status Flag 0 - 0 - 0 - read-write - - - ST1 - Protocol Status Flag 1 - 1 - 1 - read-write - - - ST2 - Protocol Status Flag 2 - 2 - 2 - read-write - - - ST3 - Protocol Status Flag 3 - 3 - 3 - read-write - - - ST4 - Protocol Status Flag 4 - 4 - 4 - read-write - - - ST5 - Protocol Status Flag 5 - 5 - 5 - read-write - - - ST6 - Protocol Status Flag 6 - 6 - 6 - read-write - - - ST7 - Protocol Status Flag 7 - 7 - 7 - read-write - - - ST8 - Protocol Status Flag 8 - 8 - 8 - read-write - - - ST9 - Protocol Status Flag 9 - 9 - 9 - read-write - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_ASCMode - Protocol Status Register [ASC Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXIDLE - Transmission Idle - 0 - 0 - read-write - - - value1 - The transmitter line has not yet been idle. - 0b0 - - - value2 - The transmitter line has been idle and frame transmission is possible. - 0b1 - - - - - RXIDLE - Reception Idle - 1 - 1 - read-write - - - value1 - The receiver line has not yet been idle. - 0b0 - - - value2 - The receiver line has been idle and frame reception is possible. - 0b1 - - - - - SBD - Synchronization Break Detected - 2 - 2 - read-write - - - value1 - A synchronization break has not yet been detected. - 0b0 - - - value2 - A synchronization break has been detected. - 0b1 - - - - - COL - Collision Detected - 3 - 3 - read-write - - - value1 - A collision has not yet been detected and frame transmission is possible. - 0b0 - - - value2 - A collision has been detected and frame transmission is not possible. - 0b1 - - - - - RNS - Receiver Noise Detected - 4 - 4 - read-write - - - value1 - Receiver noise has not been detected. - 0b0 - - - value2 - Receiver noise has been detected. - 0b1 - - - - - FER0 - Format Error in Stop Bit 0 - 5 - 5 - read-write - - - value1 - A format error 0 has not been detected. - 0b0 - - - value2 - A format error 0 has been detected. - 0b1 - - - - - FER1 - Format Error in Stop Bit 1 - 6 - 6 - read-write - - - value1 - A format error 1 has not been detected. - 0b0 - - - value2 - A format error 1 has been detected. - 0b1 - - - - - RFF - Receive Frame Finished - 7 - 7 - read-write - - - value1 - The received frame is not yet finished. - 0b0 - - - value2 - The received frame is finished. - 0b1 - - - - - TFF - Transmitter Frame Finished - 8 - 8 - read-write - - - value1 - The transmitter frame is not yet finished. - 0b0 - - - value2 - The transmitter frame is finished. - 0b1 - - - - - BUSY - Transfer Status BUSY - 9 - 9 - read-only - - - value1 - A data transfer does not take place. - 0b0 - - - value2 - A data transfer currently takes place. - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_SSCMode - Protocol Status Register [SSC Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - MSLS - MSLS Status - 0 - 0 - read-write - - - value1 - The internal signal MSLS is inactive (0). - 0b0 - - - value2 - The internal signal MSLS is active (1). - 0b1 - - - - - DX2S - DX2S Status - 1 - 1 - read-write - - - value1 - DX2S is 0. - 0b0 - - - value2 - DX2S is 1. - 0b1 - - - - - MSLSEV - MSLS Event Detected - 2 - 2 - read-write - - - value1 - The MSLS signal has not changed its state. - 0b0 - - - value2 - The MSLS signal has changed its state. - 0b1 - - - - - DX2TEV - DX2T Event Detected - 3 - 3 - read-write - - - value1 - The DX2T signal has not been activated. - 0b0 - - - value2 - The DX2T signal has been activated. - 0b1 - - - - - PARERR - Parity Error Event Detected - 4 - 4 - read-write - - - value1 - A parity error event has not been activated. - 0b0 - - - value2 - A parity error event has been activated. - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_IICMode - Protocol Status Register [IIC Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLSEL - Slave Select - 0 - 0 - read-write - - - value1 - The device is not selected as slave. - 0b0 - - - value2 - The device is selected as slave. - 0b1 - - - - - WTDF - Wrong TDF Code Found - 1 - 1 - read-write - - - value1 - A wrong TDF code has not been found. - 0b0 - - - value2 - A wrong TDF code has been found. - 0b1 - - - - - SCR - Start Condition Received - 2 - 2 - read-write - - - value1 - A start condition has not yet been detected. - 0b0 - - - value2 - A start condition has been detected. - 0b1 - - - - - RSCR - Repeated Start Condition Received - 3 - 3 - read-write - - - value1 - A repeated start condition has not yet been detected. - 0b0 - - - value2 - A repeated start condition has been detected. - 0b1 - - - - - PCR - Stop Condition Received - 4 - 4 - read-write - - - value1 - A stop condition has not yet been detected. - 0b0 - - - value2 - A stop condition has been detected. - 0b1 - - - - - NACK - Non-Acknowledge Received - 5 - 5 - read-write - - - value1 - A non-acknowledge has not been received. - 0b0 - - - value2 - A non-acknowledge has been received. - 0b1 - - - - - ARL - Arbitration Lost - 6 - 6 - read-write - - - value1 - An arbitration has not been lost. - 0b0 - - - value2 - An arbitration has been lost. - 0b1 - - - - - SRR - Slave Read Request - 7 - 7 - read-write - - - value1 - A slave read request has not been detected. - 0b0 - - - value2 - A slave read request has been detected. - 0b1 - - - - - ERR - Error - 8 - 8 - read-write - - - value1 - An IIC error has not been detected. - 0b0 - - - value2 - An IIC error has been detected. - 0b1 - - - - - ACK - Acknowledge Received - 9 - 9 - read-write - - - value1 - An acknowledge has not been received. - 0b0 - - - value2 - An acknowledge has been received. - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSR_IISMode - Protocol Status Register [IIS Mode] - PSR - 0x048 - 32 - 0x00000000 - 0xFFFFFFFF - - - WA - Word Address - 0 - 0 - read-write - - - value1 - WA has been sampled 0. - 0b0 - - - value2 - WA has been sampled 1. - 0b1 - - - - - DX2S - DX2S Status - 1 - 1 - read-write - - - value1 - DX2S is 0. - 0b0 - - - value2 - DX2S is 1. - 0b1 - - - - - DX2TEV - DX2T Event Detected - 3 - 3 - read-write - - - value1 - The DX2T signal has not been activated. - 0b0 - - - value2 - The DX2T signal has been activated. - 0b1 - - - - - WAFE - WA Falling Edge Event - 4 - 4 - read-write - - - value1 - A WA falling edge has not been generated. - 0b0 - - - value2 - A WA falling edge has been generated. - 0b1 - - - - - WARE - WA Rising Edge Event - 5 - 5 - read-write - - - value1 - A WA rising edge has not been generated. - 0b0 - - - value2 - A WA rising edge has been generated. - 0b1 - - - - - END - WA Generation End - 6 - 6 - read-write - - - value1 - The WA generation has not yet ended (if it is running and WAGEN has been cleared). - 0b0 - - - value2 - The WA generation has ended (if it has been running). - 0b1 - - - - - RSIF - Receiver Start Indication Flag - 10 - 10 - read-write - - - value1 - A receiver start event has not occurred. - 0b0 - - - value2 - A receiver start event has occurred. - 0b1 - - - - - DLIF - Data Lost Indication Flag - 11 - 11 - read-write - - - value1 - A data lost event has not occurred. - 0b0 - - - value2 - A data lost event has occurred. - 0b1 - - - - - TSIF - Transmit Shift Indication Flag - 12 - 12 - read-write - - - value1 - A transmit shift event has not occurred. - 0b0 - - - value2 - A transmit shift event has occurred. - 0b1 - - - - - TBIF - Transmit Buffer Indication Flag - 13 - 13 - read-write - - - value1 - A transmit buffer event has not occurred. - 0b0 - - - value2 - A transmit buffer event has occurred. - 0b1 - - - - - RIF - Receive Indication Flag - 14 - 14 - read-write - - - value1 - A receive event has not occurred. - 0b0 - - - value2 - A receive event has occurred. - 0b1 - - - - - AIF - Alternative Receive Indication Flag - 15 - 15 - read-write - - - value1 - An alternative receive event has not occurred. - 0b0 - - - value2 - An alternative receive event has occurred. - 0b1 - - - - - BRGIF - Baud Rate Generator Indication Flag - 16 - 16 - read-write - - - value1 - A baud rate generator event has not occurred. - 0b0 - - - value2 - A baud rate generator event has occurred. - 0b1 - - - - - - - PSCR - Protocol Status Clear Register - 0x04C - 32 - 0x00000000 - 0xFFFFFFFF - - - CST0 - Clear Status Flag 0 in PSR - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST1 - Clear Status Flag 1 in PSR - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST2 - Clear Status Flag 2 in PSR - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST3 - Clear Status Flag 3 in PSR - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST4 - Clear Status Flag 4 in PSR - 4 - 4 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST5 - Clear Status Flag 5 in PSR - 5 - 5 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST6 - Clear Status Flag 6 in PSR - 6 - 6 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST7 - Clear Status Flag 7 in PSR - 7 - 7 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST8 - Clear Status Flag 8 in PSR - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CST9 - Clear Status Flag 9 in PSR - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.STx is cleared. - 0b1 - - - - - CRSIF - Clear Receiver Start Indication Flag - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.RSIF is cleared. - 0b1 - - - - - CDLIF - Clear Data Lost Indication Flag - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.DLIF is cleared. - 0b1 - - - - - CTSIF - Clear Transmit Shift Indication Flag - 12 - 12 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.TSIF is cleared. - 0b1 - - - - - CTBIF - Clear Transmit Buffer Indication Flag - 13 - 13 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.TBIF is cleared. - 0b1 - - - - - CRIF - Clear Receive Indication Flag - 14 - 14 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.RIF is cleared. - 0b1 - - - - - CAIF - Clear Alternative Receive Indication Flag - 15 - 15 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.AIF is cleared. - 0b1 - - - - - CBRGIF - Clear Baud Rate Generator Indication Flag - 16 - 16 - write-only - - - value1 - No action - 0b0 - - - value2 - Flag PSR.BRGIF is cleared. - 0b1 - - - - - - - RBUFSR - Receiver Buffer Status Register - 0x050 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLEN - Received Data Word Length in RBUF or RBUFD - 0 - 3 - read-only - - - SOF - Start of Frame in RBUF or RBUFD - 6 - 6 - read-only - - - PAR - Protocol-Related Argument in RBUF or RBUFD - 8 - 8 - read-only - - - PERR - Protocol-related Error in RBUF or RBUFD - 9 - 9 - read-only - - - RDV0 - Receive Data Valid in RBUF or RBUFD - 13 - 13 - read-only - - - RDV1 - Receive Data Valid in RBUF or RBUFD - 14 - 14 - read-only - - - DS - Data Source of RBUF or RBUFD - 15 - 15 - read-only - - - - - RBUF - Receiver Buffer Register - 0x054 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Received Data - 0 - 15 - read-only - - - - - RBUFD - Receiver Buffer Register for Debugger - 0x058 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Data from Shift Register - 0 - 15 - read-only - - - - - RBUF0 - Receiver Buffer Register 0 - 0x05C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR0 - Data of Shift Registers 0[3:0] - 0 - 15 - read-only - - - - - RBUF1 - Receiver Buffer Register 1 - 0x060 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR1 - Data of Shift Registers 1[3:0] - 0 - 15 - read-only - - - - - RBUF01SR - Receiver Buffer 01 Status Register - 0x064 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLEN0 - Received Data Word Length in RBUF0 - 0 - 3 - read-only - - - SOF0 - Start of Frame in RBUF0 - 6 - 6 - read-only - - - value1 - The data in RBUF0 has not been the first data word of a data frame. - 0b0 - - - value2 - The data in RBUF0 has been the first data word of a data frame. - 0b1 - - - - - PAR0 - Protocol-Related Argument in RBUF0 - 8 - 8 - read-only - - - PERR0 - Protocol-related Error in RBUF0 - 9 - 9 - read-only - - - value1 - The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. - 0b0 - - - value2 - The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. - 0b1 - - - - - RDV00 - Receive Data Valid in RBUF0 - 13 - 13 - read-only - - - value1 - Register RBUF0 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF0 contains data that has not yet been read out. - 0b1 - - - - - RDV01 - Receive Data Valid in RBUF1 - 14 - 14 - read-only - - - value1 - Register RBUF1 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF1 contains data that has not yet been read out. - 0b1 - - - - - DS0 - Data Source - 15 - 15 - read-only - - - value1 - The register RBUF contains the data of RBUF0 (same for associated status information). - 0b0 - - - value2 - The register RBUF contains the data of RBUF1 (same for associated status information). - 0b1 - - - - - WLEN1 - Received Data Word Length in RBUF1 - 16 - 19 - read-only - - - SOF1 - Start of Frame in RBUF1 - 22 - 22 - read-only - - - value1 - The data in RBUF1 has not been the first data word of a data frame. - 0b0 - - - value2 - The data in RBUF1 has been the first data word of a data frame. - 0b1 - - - - - PAR1 - Protocol-Related Argument in RBUF1 - 24 - 24 - read-only - - - PERR1 - Protocol-related Error in RBUF1 - 25 - 25 - read-only - - - value1 - The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. - 0b0 - - - value2 - The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. - 0b1 - - - - - RDV10 - Receive Data Valid in RBUF0 - 29 - 29 - read-only - - - value1 - Register RBUF0 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF0 contains data that has not yet been read out. - 0b1 - - - - - RDV11 - Receive Data Valid in RBUF1 - 30 - 30 - read-only - - - value1 - Register RBUF1 does not contain data that has not yet been read out. - 0b0 - - - value2 - Register RBUF1 contains data that has not yet been read out. - 0b1 - - - - - DS1 - Data Source - 31 - 31 - read-only - - - value1 - The register RBUF contains the data of RBUF0 (same for associated status information). - 0b0 - - - value2 - The register RBUF contains the data of RBUF1 (same for associated status information). - 0b1 - - - - - - - FMR - Flag Modification Register - 0x068 - 32 - 0x00000000 - 0xFFFFFFFF - - - MTDV - Modify Transmit Data Valid - 0 - 1 - write-only - - - value1 - No action. - 0b00 - - - value2 - Bit TDV is set, TE is unchanged. - 0b01 - - - value3 - Bits TDV and TE are cleared. - 0b10 - - - value4 - Reserved - 0b11 - - - - - ATVC - Activate Bit TVC - 4 - 4 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bit TCSR.TVC is set. - 0b1 - - - - - CRDV0 - Clear Bits RDV for RBUF0 - 14 - 14 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared. - 0b1 - - - - - CRDV1 - Clear Bit RDV for RBUF1 - 15 - 15 - write-only - - - value1 - No action. - 0b0 - - - value2 - Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared. - 0b1 - - - - - SIO0 - Set Interrupt Output SRx - 16 - 16 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO1 - Set Interrupt Output SRx - 17 - 17 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO2 - Set Interrupt Output SRx - 18 - 18 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO3 - Set Interrupt Output SRx - 19 - 19 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO4 - Set Interrupt Output SRx - 20 - 20 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - SIO5 - Set Interrupt Output SRx - 21 - 21 - write-only - - - value1 - No action. - 0b0 - - - value2 - The service request output SRx is activated. - 0b1 - - - - - - - 32 - 4 - TBUF[%s] - Transmit Buffer - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDATA - Transmit Data - 0 - 15 - read-write - - - - - BYP - Bypass Data Register - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - BDATA - Bypass Data - 0 - 15 - read-write - - - - - BYPCR - Bypass Control Register - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - BWLE - Bypass Word Length - 0 - 3 - read-write - - - BDSSM - Bypass Data Single Shot Mode - 8 - 8 - read-write - - - value1 - The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. - 0b0 - - - value2 - The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV. - 0b1 - - - - - BDEN - Bypass Data Enable - 10 - 11 - read-write - - - value1 - The transfer of bypass data is disabled. - 0b00 - - - value2 - The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. - 0b01 - - - value3 - Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. - 0b10 - - - value4 - Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. - 0b11 - - - - - BDVTR - Bypass Data Valid Trigger - 12 - 12 - read-write - - - value1 - Bit BDV is not influenced by DX2T. - 0b0 - - - value2 - Bit BDV is set if DX2T is active. - 0b1 - - - - - BPRIO - Bypass Priority - 13 - 13 - read-write - - - value1 - The transmit FIFO data has a higher priority than the bypass data. - 0b0 - - - value2 - The bypass data has a higher priority than the transmit FIFO data. - 0b1 - - - - - BDV - Bypass Data Valid - 15 - 15 - read-only - - - value1 - The bypass data is not valid. - 0b0 - - - value2 - The bypass data is valid. - 0b1 - - - - - BSELO - Bypass Select Outputs - 16 - 20 - read-write - - - BHPC - Bypass Hardware Port Control - 21 - 23 - read-write - - - - - TBCTR - Transmitter Buffer Control Register - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPTR - Data Pointer - 0 - 5 - write-only - - - LIMIT - Limit For Interrupt Generation - 8 - 13 - read-write - - - STBTM - Standard Transmit Buffer Trigger Mode - 14 - 14 - read-write - - - value1 - Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT. - 0b0 - - - value2 - Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE. - 0b1 - - - - - STBTEN - Standard Transmit Buffer Trigger Enable - 15 - 15 - read-write - - - value1 - The standard transmit buffer event trigger through bit TRBSR.STBT is disabled. - 0b0 - - - value2 - The standard transmit buffer event trigger through bit TRBSR.STBT is enabled. - 0b1 - - - - - STBINP - Standard Transmit Buffer Interrupt Node Pointer - 16 - 18 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - ATBINP - Alternative Transmit Buffer Interrupt Node Pointer - 19 - 21 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - SIZE - Buffer Size - 24 - 26 - read-write - - - value1 - The FIFO mechanism is disabled. The buffer does not accept any request for data. - 0b000 - - - value2 - The FIFO buffer contains 2 entries. - 0b001 - - - value3 - The FIFO buffer contains 4 entries. - 0b010 - - - value4 - The FIFO buffer contains 8 entries. - 0b011 - - - value5 - The FIFO buffer contains 16 entries. - 0b100 - - - value6 - The FIFO buffer contains 32 entries. - 0b101 - - - value7 - The FIFO buffer contains 64 entries. - 0b110 - - - value8 - Reserved - 0b111 - - - - - LOF - Buffer Event on Limit Overflow - 28 - 28 - read-write - - - value1 - A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word. - 0b0 - - - value2 - A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. - 0b1 - - - - - STBIEN - Standard Transmit Buffer Interrupt Enable - 30 - 30 - read-write - - - value1 - The standard transmit buffer interrupt generation is disabled. - 0b0 - - - value2 - The standard transmit buffer interrupt generation is enabled. - 0b1 - - - - - TBERIEN - Transmit Buffer Error Interrupt Enable - 31 - 31 - read-write - - - value1 - The transmit buffer error interrupt generation is disabled. - 0b0 - - - value2 - The transmit buffer error interrupt generation is enabled. - 0b1 - - - - - - - RBCTR - Receiver Buffer Control Register - 0x10C - 32 - 0x00000000 - 0xFFFFFFFF - - - DPTR - Data Pointer - 0 - 5 - write-only - - - LIMIT - Limit For Interrupt Generation - 8 - 13 - read-write - - - SRBTM - Standard Receive Buffer Trigger Mode - 14 - 14 - read-write - - - value1 - Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. - 0b0 - - - value2 - Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. - 0b1 - - - - - SRBTEN - Standard Receive Buffer Trigger Enable - 15 - 15 - read-write - - - value1 - The standard receive buffer event trigger through bit TRBSR.SRBT is disabled. - 0b0 - - - value2 - The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. - 0b1 - - - - - SRBINP - Standard Receive Buffer Interrupt Node Pointer - 16 - 18 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - ARBINP - Alternative Receive Buffer Interrupt Node Pointer - 19 - 21 - read-write - - - value1 - Output SR0 becomes activated. - 0b000 - - - value2 - Output SR1 becomes activated. - 0b001 - - - value3 - Output SR2 becomes activated. - 0b010 - - - value4 - Output SR3 becomes activated. - 0b011 - - - value5 - Output SR4 becomes activated. - 0b100 - - - value6 - Output SR5 becomes activated. - 0b101 - - - - - RCIM - Receiver Control Information Mode - 22 - 23 - read-write - - - value1 - RCI[4] = PERR, RCI[3:0] = WLEN - 0b00 - - - value2 - RCI[4] = SOF, RCI[3:0] = WLEN - 0b01 - - - value3 - RCI[4] = 0, RCI[3:0] = WLEN - 0b10 - - - value4 - RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF - 0b11 - - - - - SIZE - Buffer Size - 24 - 26 - read-write - - - value1 - The FIFO mechanism is disabled. The buffer does not accept any request for data. - 0b000 - - - value2 - The FIFO buffer contains 2 entries. - 0b001 - - - value3 - The FIFO buffer contains 4 entries. - 0b010 - - - value4 - The FIFO buffer contains 8 entries. - 0b011 - - - value5 - The FIFO buffer contains 16 entries. - 0b100 - - - value6 - The FIFO buffer contains 32 entries. - 0b101 - - - value7 - The FIFO buffer contains 64 entries. - 0b110 - - - value8 - Reserved - 0b111 - - - - - RNM - Receiver Notification Mode - 27 - 27 - read-write - - - value1 - Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). - 0b0 - - - value2 - RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. - 0b1 - - - - - LOF - Buffer Event on Limit Overflow - 28 - 28 - read-write - - - value1 - A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR. - 0b0 - - - value2 - A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. - 0b1 - - - - - ARBIEN - Alternative Receive Buffer Interrupt Enable - 29 - 29 - read-write - - - value1 - The alternative receive buffer interrupt generation is disabled. - 0b0 - - - value2 - The alternative receive buffer interrupt generation is enabled. - 0b1 - - - - - SRBIEN - Standard Receive Buffer Interrupt Enable - 30 - 30 - read-write - - - value1 - The standard receive buffer interrupt generation is disabled. - 0b0 - - - value2 - The standard receive buffer interrupt generation is enabled. - 0b1 - - - - - RBERIEN - Receive Buffer Error Interrupt Enable - 31 - 31 - read-write - - - value1 - The receive buffer error interrupt generation is disabled. - 0b0 - - - value2 - The receive buffer error interrupt generation is enabled. - 0b1 - - - - - - - TRBPTR - Transmit/Receive Buffer Pointer Register - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDIPTR - Transmitter Data Input Pointer - 0 - 5 - read-only - - - TDOPTR - Transmitter Data Output Pointer - 8 - 13 - read-only - - - RDIPTR - Receiver Data Input Pointer - 16 - 21 - read-only - - - RDOPTR - Receiver Data Output Pointer - 24 - 29 - read-only - - - - - TRBSR - Transmit/Receive Buffer Status Register - 0x114 - 32 - 0x00000808 - 0xFFFFFFFF - - - SRBI - Standard Receive Buffer Event - 0 - 0 - read-write - - - value1 - A standard receive buffer event has not been detected. - 0b0 - - - value2 - A standard receive buffer event has been detected. - 0b1 - - - - - RBERI - Receive Buffer Error Event - 1 - 1 - read-write - - - value1 - A receive buffer error event has not been detected. - 0b0 - - - value2 - A receive buffer error event has been detected. - 0b1 - - - - - ARBI - Alternative Receive Buffer Event - 2 - 2 - read-write - - - value1 - An alternative receive buffer event has not been detected. - 0b0 - - - value2 - An alternative receive buffer event has been detected. - 0b1 - - - - - REMPTY - Receive Buffer Empty - 3 - 3 - read-only - - - value1 - The receive buffer is not empty. - 0b0 - - - value2 - The receive buffer is empty. - 0b1 - - - - - RFULL - Receive Buffer Full - 4 - 4 - read-only - - - value1 - The receive buffer is not full. - 0b0 - - - value2 - The receive buffer is full. - 0b1 - - - - - RBUS - Receive Buffer Busy - 5 - 5 - read-only - - - value1 - The receive buffer information has been completely updated. - 0b0 - - - value2 - The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. - 0b1 - - - - - SRBT - Standard Receive Buffer Event Trigger - 6 - 6 - read-only - - - value1 - A standard receive buffer event is not triggered using this bit. - 0b0 - - - value2 - A standard receive buffer event is triggered using this bit. - 0b1 - - - - - STBI - Standard Transmit Buffer Event - 8 - 8 - read-write - - - value1 - A standard transmit buffer event has not been detected. - 0b0 - - - value2 - A standard transmit buffer event has been detected. - 0b1 - - - - - TBERI - Transmit Buffer Error Event - 9 - 9 - read-write - - - value1 - A transmit buffer error event has not been detected. - 0b0 - - - value2 - A transmit buffer error event has been detected. - 0b1 - - - - - TEMPTY - Transmit Buffer Empty - 11 - 11 - read-only - - - value1 - The transmit buffer is not empty. - 0b0 - - - value2 - The transmit buffer is empty. - 0b1 - - - - - TFULL - Transmit Buffer Full - 12 - 12 - read-only - - - value1 - The transmit buffer is not full. - 0b0 - - - value2 - The transmit buffer is full. - 0b1 - - - - - TBUS - Transmit Buffer Busy - 13 - 13 - read-only - - - value1 - The transmit buffer information has been completely updated. - 0b0 - - - value2 - The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. - 0b1 - - - - - STBT - Standard Transmit Buffer Event Trigger - 14 - 14 - read-only - - - value1 - A standard transmit buffer event is not triggered using this bit. - 0b0 - - - value2 - A standard transmit buffer event is triggered using this bit. - 0b1 - - - - - RBFLVL - Receive Buffer Filling Level - 16 - 22 - read-only - - - TBFLVL - Transmit Buffer Filling Level - 24 - 30 - read-only - - - - - TRBSCR - Transmit/Receive Buffer Status Clear Register - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - CSRBI - Clear Standard Receive Buffer Event - 0 - 0 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.SRBI. - 0b1 - - - - - CRBERI - Clear Receive Buffer Error Event - 1 - 1 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.RBERI. - 0b1 - - - - - CARBI - Clear Alternative Receive Buffer Event - 2 - 2 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.ARBI. - 0b1 - - - - - CSTBI - Clear Standard Transmit Buffer Event - 8 - 8 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.STBI. - 0b1 - - - - - CTBERI - Clear Transmit Buffer Error Event - 9 - 9 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear TRBSR.TBERI. - 0b1 - - - - - CBDV - Clear Bypass Data Valid - 10 - 10 - write-only - - - value1 - No effect. - 0b0 - - - value2 - Clear BYPCR.BDV. - 0b1 - - - - - FLUSHRB - Flush Receive Buffer - 14 - 14 - write-only - - - value1 - No effect. - 0b0 - - - value2 - The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. - 0b1 - - - - - FLUSHTB - Flush Transmit Buffer - 15 - 15 - write-only - - - value1 - No effect. - 0b0 - - - value2 - The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. - 0b1 - - - - - - - OUTR - Receiver Buffer Output Register - 0x11C - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Received Data - 0 - 15 - read-only - - - RCI - Receiver Control Information - 16 - 20 - read-only - - - - - OUTDR - Receiver Buffer Output Register L for Debugger - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSR - Data from Shift Register - 0 - 15 - read-only - - - RCI - Receive Control Information from Shift Register - 16 - 20 - read-only - - - - - 32 - 4 - IN[%s] - Transmit FIFO Buffer - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDATA - Transmit Data - 0 - 15 - write-only - - - - - - - USIC0_CH1 - Universal Serial Interface Controller 0 - USIC - 0x40030200 - - 0x0 - 0x0200 - registers - - - - USIC1_CH0 - Universal Serial Interface Controller 0 - USIC - 0x48020000 - - 0x0 - 0x0200 - registers - - - - USIC1_CH1 - Universal Serial Interface Controller 0 - USIC - 0x48020200 - - 0x0 - 0x0200 - registers - - - - USIC2_CH0 - Universal Serial Interface Controller 0 - USIC - 0x48024000 - - 0x0 - 0x0200 - registers - - - - USIC2_CH1 - Universal Serial Interface Controller 0 - USIC - 0x48024200 - - 0x0 - 0x0200 - registers - - - - CAN - Controller Area Networks - CAN - 0x48014000 - - 0x0 - 0x4000 - registers - - - - CLC - CAN Clock Control Register - 0x0000 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - EDIS - Sleep Mode Enable Control - 3 - 3 - read-write - - - SBWE - Module Suspend Bit Write Enable for OCDS - 4 - 4 - write-only - - - - - ID - Module Identification Register - 0x0008 - 32 - 0x002BC000 - 0xFFFFFF00 - - - MOD_REV - Module Revision Number - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - value1 - Define the module as a 32-bit module. - 0xC0 - - - - - MOD_NUMBER - Module Number Value - 16 - 31 - read-only - - - - - FDR - CAN Fractional Divider Register - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - STEP - Step Value - 0 - 9 - read-write - - - SM - Suspend Mode - 11 - 11 - read-write - - - SC - Suspend Control - 12 - 13 - read-write - - - DM - Divider Mode - 14 - 15 - read-write - - - RESULT - Result Value - 16 - 25 - read-only - - - SUSACK - Suspend Mode Acknowledge - 28 - 28 - read-only - - - SUSREQ - Suspend Mode Request - 29 - 29 - read-only - - - ENHW - Enable Hardware Clock Control - 30 - 30 - read-write - - - DISCLK - Disable Clock - 31 - 31 - read-write - - - - - 8 - 4 - LIST[%s] - List Register - 0x0100 - 32 - 0x00000000 - 0x00000000 - - - BEGIN - List Begin - 0 - 7 - read-only - - - END - List End - 8 - 15 - read-only - - - SIZE - List Size - 16 - 23 - read-only - - - EMPTY - List Empty Indication - 24 - 24 - read-only - - - value1 - At least one message object is allocated to list i. - 0b0 - - - value2 - No message object is allocated to the list x. List x is empty. - 0b1 - - - - - - - 8 - 4 - MSPND[%s] - Message Pending Register - 0x0140 - 32 - 0x00000000 - 0xFFFFFFFF - - - PND - Message Pending - 0 - 31 - read-write - - - - - 8 - 4 - MSID[%s] - Message Index Register - 0x0180 - 32 - 0x00000020 - 0xFFFFFFFF - - - INDEX - Message Pending Index - 0 - 5 - read-only - - - - - MSIMASK - Message Index Mask Register - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IM - Message Index Mask - 0 - 31 - read-write - - - - - PANCTR - Panel Control Register - 0x01C4 - 32 - 0x00000301 - 0xFFFFFFFF - - - PANCMD - Panel Command - 0 - 7 - read-write - - - BUSY - Panel Busy Flag - 8 - 8 - read-only - - - value1 - Panel has finished command and is ready to accept a new command. - 0b0 - - - value2 - Panel operation is in progress. - 0b1 - - - - - RBUSY - Result Busy Flag - 9 - 9 - read-only - - - value1 - No update of PANAR1 and PANAR2 is scheduled by the list controller. - 0b0 - - - value2 - A list command is running (BUSY = 1) that will write results to PANAR1 and PANAR2, but the results are not yet available. - 0b1 - - - - - PANAR1 - Panel Argument 1 - 16 - 23 - read-write - - - PANAR2 - Panel Argument 2 - 24 - 31 - read-write - - - - - MCR - Module Control Register - 0x01C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPSEL - Message Pending Selector - 12 - 15 - read-write - - - - - MITR - Module Interrupt Trigger Register - 0x01CC - 32 - 0x00000000 - 0xFFFFFFFF - - - IT - Interrupt Trigger - 0 - 7 - write-only - - - - - - - CAN_NODE0 - Controller Area Networks - CAN - CAN_NODE - 0x48014200 - - 0x0 - 0x4000 - registers - - - - NCR - Node Control Register - 0x00 - 32 - 0x00000001 - 0xFFFFFFFF - - - INIT - Node Initialization - 0 - 0 - read-write - - - value1 - Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic. - 0b0 - - - value2 - Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set. - 0b1 - - - - - TRIE - Transfer Interrupt Enable - 1 - 1 - read-write - - - value1 - Transfer interrupt is disabled. - 0b0 - - - value2 - Transfer interrupt is enabled. - 0b1 - - - - - LECIE - LEC Indicated Error Interrupt Enable - 2 - 2 - read-write - - - value1 - Last error code interrupt is disabled. - 0b0 - - - value2 - Last error code interrupt is enabled. - 0b1 - - - - - ALIE - Alert Interrupt Enable - 3 - 3 - read-write - - - value1 - Alert interrupt is disabled. - 0b0 - - - value2 - Alert interrupt is enabled. - 0b1 - - - - - CANDIS - CAN Disable - 4 - 4 - read-write - - - CCE - Configuration Change Enable - 6 - 6 - read-write - - - value1 - The Bit Timing Register, the Port Control Register, and the Error Counter Register may only be read. All attempts to modify them are ignored. - 0b0 - - - value2 - The Bit Timing Register, the Port Control Register, and the Error Counter Register may be read and written. - 0b1 - - - - - CALM - CAN Analyzer Mode - 7 - 7 - read-write - - - SUSEN - Suspend Enable - 8 - 8 - read-write - - - value1 - An OCDS suspend trigger is ignored by the CAN node. - 0b0 - - - value2 - An OCDS suspend trigger disables the CAN node: As soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. The actual value of bit INIT remains unchanged. - 0b1 - - - - - - - NSR - Node Status Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - LEC - Last Error Code - 0 - 2 - read-write - - - TXOK - Message Transmitted Successfully - 3 - 3 - read-write - - - value1 - No successful transmission since last (most recent) flag reset. - 0b0 - - - value2 - A message has been transmitted successfully (error-free and acknowledged by at least another node). - 0b1 - - - - - RXOK - Message Received Successfully - 4 - 4 - read-write - - - value1 - No successful reception since last (most recent) flag reset. - 0b0 - - - value2 - A message has been received successfully. - 0b1 - - - - - ALERT - Alert Warning - 5 - 5 - read-write - - - EWRN - Error Warning Status - 6 - 6 - read-only - - - value1 - No warning limit exceeded. - 0b0 - - - value2 - One of the error counters REC or TEC reached the warning limit EWRNLVL. - 0b1 - - - - - BOFF - Bus-off Status - 7 - 7 - read-only - - - value1 - CAN controller is not in the bus-off state. - 0b0 - - - value2 - CAN controller is in the bus-off state. - 0b1 - - - - - LLE - List Length Error - 8 - 8 - read-write - - - value1 - No List Length Error since last (most recent) flag reset. - 0b0 - - - value2 - A List Length Error has been detected during message acceptance filtering. The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list termination pointer. - 0b1 - - - - - LOE - List Object Error - 9 - 9 - read-write - - - value1 - No List Object Error since last (most recent) flag reset. - 0b0 - - - value2 - A List Object Error has been detected during message acceptance filtering. A message object with wrong LIST index entry in the Message Object Control Register has been detected. - 0b1 - - - - - SUSACK - Suspend Acknowledge - 10 - 10 - read-only - - - value1 - The CAN node is not in Suspend Mode or a suspend request is pending, but the CAN node has not yet reached bus-idle or bus-off. - 0b0 - - - value2 - The CAN node is in Suspend Mode: The CAN node is inactive (bit NCR.INIT internally forced to 1) due to an OCDS suspend request. - 0b1 - - - - - - - NIPR - Node Interrupt Pointer Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALINP - Alert Interrupt Node Pointer - 0 - 2 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - LECINP - Last Error Code Interrupt Node Pointer - 4 - 6 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - TRINP - Transfer OK Interrupt Node Pointer - 8 - 10 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - CFCINP - Frame Counter Interrupt Node Pointer - 12 - 14 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - - - NPCR - Node Port Control Register - 0x0C - 32 - 0x00000000 - 0xFFFFFFFF - - - RXSEL - Receive Select - 0 - 2 - read-write - - - LBM - Loop-Back Mode - 8 - 8 - read-write - - - value1 - Loop-Back Mode is disabled. - 0b0 - - - value2 - Loop-Back Mode is enabled. This node is connected to an internal (virtual) loop-back CAN bus. All CAN nodes which are in Loop-Back Mode are connected to this virtual CAN bus so that they can communicate with each other internally. The external transmit line is forced recessive in Loop-Back Mode. - 0b1 - - - - - - - NBTR - Node Bit Timing Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - BRP - Baud Rate Prescaler - 0 - 5 - read-write - - - SJW - (Re) Synchronization Jump Width - 6 - 7 - read-write - - - TSEG1 - Time Segment Before Sample Point - 8 - 11 - read-write - - - TSEG2 - Time Segment After Sample Point - 12 - 14 - read-write - - - DIV8 - Divide Prescaler Clock by 8 - 15 - 15 - read-write - - - value1 - A time quantum lasts (BRP+1) clock cycles. - 0b0 - - - value2 - A time quantum lasts 8 (BRP+1) clock cycles. - 0b1 - - - - - - - NECNT - Node Error Counter Register - 0x14 - 32 - 0x00600000 - 0xFFFFFFFF - - - REC - Receive Error Counter - 0 - 7 - read-write - - - TEC - Transmit Error Counter - 8 - 15 - read-write - - - EWRNLVL - Error Warning Level - 16 - 23 - read-write - - - LETD - Last Error Transfer Direction - 24 - 24 - read-only - - - value1 - The last error occurred while the CAN node x was receiver (REC has been incremented). - 0b0 - - - value2 - The last error occurred while the CAN node x was transmitter (TEC has been incremented). - 0b1 - - - - - LEINC - Last Error Increment - 25 - 25 - read-only - - - value1 - The last error led to an error counter increment of 1. - 0b0 - - - value2 - The last error led to an error counter increment of 8. - 0b1 - - - - - - - NFCR - Node Frame Counter Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFC - CAN Frame Counter - 0 - 15 - read-write - - - CFSEL - CAN Frame Count Selection - 16 - 18 - read-write - - - value1 - The frame counter is incremented (internally) at the beginning of a new bit time. The value is sampled during the SOF bit of a new frame. The sampled value is visible in the CFC field. - 0b000 - - - - - CFMOD - CAN Frame Counter Mode - 19 - 20 - read-write - - - value1 - Frame Count Mode: The frame counter is incremented upon the reception and transmission of frames. - 0b00 - - - value2 - Time Stamp Mode: The frame counter is used to count bit times. - 0b01 - - - value3 - Bit Timing Mode: The frame counter is used for analysis of the bit timing. - 0b10 - - - - - CFCIE - CAN Frame Count Interrupt Enable - 22 - 22 - read-write - - - value1 - CAN frame counter overflow interrupt is disabled. - 0b0 - - - value2 - CAN frame counter overflow interrupt is enabled. - 0b1 - - - - - CFCOV - CAN Frame Counter Overflow Flag - 23 - 23 - read-write - - - value1 - No overflow has occurred since last flag reset. - 0b0 - - - value2 - An overflow has occurred since last flag reset. - 0b1 - - - - - - - - - CAN_NODE1 - Controller Area Networks - CAN - 0x48014300 - - 0x0 - 0x4000 - registers - - - - CAN_NODE2 - Controller Area Networks - CAN - 0x48014400 - - 0x0 - 0x4000 - registers - - - - CAN_MO0 - Controller Area Networks - CAN - CAN_MO - 0x48015000 - - 0x0 - 0x20 - registers - - - - MOFCR - Message Object Function Control Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - MMC - Message Mode Control - 0 - 3 - read-write - - - value1 - Standard Message Object - 0b0000 - - - value2 - Receive FIFO Base Object - 0b0001 - - - value3 - Transmit FIFO Base Object - 0b0010 - - - value4 - Transmit FIFO Slave Object - 0b0011 - - - value5 - Gateway Source Object - 0b0100 - - - - - GDFS - Gateway Data Frame Send - 8 - 8 - read-write - - - value1 - TXRQ is unchanged in the destination object. - 0b0 - - - value2 - TXRQ is set in the gateway destination object after the internal transfer from the gateway source to the gateway destination object. - 0b1 - - - - - IDC - Identifier Copy - 9 - 9 - read-write - - - value1 - The identifier of the gateway source object is not copied. - 0b0 - - - value2 - The identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. - 0b1 - - - - - DLCC - Data Length Code Copy - 10 - 10 - read-write - - - value1 - Data length code is not copied. - 0b0 - - - value2 - Data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. - 0b1 - - - - - DATC - Data Copy - 11 - 11 - read-write - - - value1 - Data fields are not copied. - 0b0 - - - value2 - Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) are copied to the gateway destination. - 0b1 - - - - - RXIE - Receive Interrupt Enable - 16 - 16 - read-write - - - value1 - Message receive interrupt is disabled. - 0b0 - - - value2 - Message receive interrupt is enabled. - 0b1 - - - - - TXIE - Transmit Interrupt Enable - 17 - 17 - read-write - - - value1 - Message transmit interrupt is disabled. - 0b0 - - - value2 - Message transmit interrupt is enabled. - 0b1 - - - - - OVIE - Overflow Interrupt Enable - 18 - 18 - read-write - - - value1 - FIFO full interrupt is disabled. - 0b0 - - - value2 - FIFO full interrupt is enabled. - 0b1 - - - - - FRREN - Foreign Remote Request Enable - 20 - 20 - read-write - - - value1 - TXRQ of message object n is set on reception of a matching Remote Frame. - 0b0 - - - value2 - TXRQ of the message object referenced by the pointer CUR is set on reception of a matching Remote Frame. - 0b1 - - - - - RMM - Transmit Object Remote Monitoring - 21 - 21 - read-write - - - value1 - Remote monitoring is disabled: Identifier, IDE bit, and DLC of message object n remain unchanged upon the reception of a matching Remote Frame. - 0b0 - - - value2 - Remote monitoring is enabled: Identifier, IDE bit, and DLC of a matching Remote Frame are copied to transmit object n in order to monitor incoming Remote Frames. - 0b1 - - - - - SDT - Single Data Transfer - 22 - 22 - read-write - - - STT - Single Transmit Trial - 23 - 23 - read-write - - - DLC - Data Length Code - 24 - 27 - read-write - - - - - MOFGPR - Message Object FIFO/Gateway Pointer Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOT - Bottom Pointer - 0 - 7 - read-write - - - TOP - Top Pointer - 8 - 15 - read-write - - - CUR - Current Object Pointer - 16 - 23 - read-write - - - SEL - Object Select Pointer - 24 - 31 - read-write - - - - - MOIPR - Message Object Interrupt Pointer Register - 0x08 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXINP - Receive Interrupt Node Pointer - 0 - 2 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - TXINP - Transmit Interrupt Node Pointer - 4 - 6 - read-write - - - value1 - Interrupt output line INT_O0 is selected. - 0b000 - - - value2 - Interrupt output line INT_O1 is selected. - 0b001 - - - value3 - Interrupt output line INT_O7 is selected. - 0b111 - - - - - MPN - Message Pending Number - 8 - 15 - read-write - - - CFCVAL - CAN Frame Counter Value - 16 - 31 - read-write - - - - - MOAMR - Message Object Acceptance Mask Register - 0x0C - 32 - 0x3FFFFFFF - 0xFFFFFFFF - - - AM - Acceptance Mask for Message Identifier - 0 - 28 - read-write - - - MIDE - Acceptance Mask Bit for Message IDE Bit - 29 - 29 - read-write - - - value1 - Message object n accepts the reception of both, standard and extended frames. - 0b0 - - - value2 - Message object n receives frames only with matching IDE bit. - 0b1 - - - - - - - MODATAL - Message Object Data Register Low - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DB0 - Data Byte 0 of Message Object n - 0 - 7 - read-write - - - DB1 - Data Byte 1 of Message Object n - 8 - 15 - read-write - - - DB2 - Data Byte 2 of Message Object n - 16 - 23 - read-write - - - DB3 - Data Byte 3 of Message Object n - 24 - 31 - read-write - - - - - MODATAH - Message Object Data Register High - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DB4 - Data Byte 4 of Message Object n - 0 - 7 - read-write - - - DB5 - Data Byte 5 of Message Object n - 8 - 15 - read-write - - - DB6 - Data Byte 6 of Message Object n - 16 - 23 - read-write - - - DB7 - Data Byte 7 of Message Object n - 24 - 31 - read-write - - - - - MOAR - Message Object Arbitration Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ID - CAN Identifier of Message Object n - 0 - 28 - read-write - - - IDE - Identifier Extension Bit of Message Object n - 29 - 29 - read-write - - - value1 - Message object n handles standard frames with 11-bit identifier. - 0b0 - - - value2 - Message object n handles extended frames with 29-bit identifier. - 0b1 - - - - - PRI - Priority Class - 30 - 31 - read-write - - - value1 - Applicable only if TTCAN is available. - 0b00 - - - value2 - Transmit acceptance filtering is based on the list order. This means that message object n is considered for transmission only if there is no other message object with valid transmit request (MSGVAL & TXEN0 & TXEN1 = 1) somewhere before this object in the list. - 0b01 - - - value3 - Transmit acceptance filtering is based on the CAN identifier. This means, message object n is considered for transmission only if there is no other message object with higher priority identifier + IDE + DIR (with respect to CAN arbitration rules) somewhere in the list (see ). - 0b10 - - - value4 - Transmit acceptance filtering is based on the list order (as PRI = 01B). - 0b11 - - - - - - - MOCTR - Message Object Control Register - 0x1C - 32 - 0x00000000 - 0x0000FFFF - - - RESRXPND - Reset/Set Receive Pending - 0 - 0 - write-only - - - SETRXPND - Reset/Set Receive Pending - 16 - 16 - write-only - - - RESTXPND - Reset/Set Transmit Pending - 1 - 1 - write-only - - - SETTXPND - Reset/Set Transmit Pending - 17 - 17 - write-only - - - RESRXUPD - Reset/Set Receive Updating - 2 - 2 - write-only - - - SETRXUPD - Reset/Set Receive Updating - 18 - 18 - write-only - - - RESNEWDAT - Reset/Set New Data - 3 - 3 - write-only - - - SETNEWDAT - Reset/Set New Data - 19 - 19 - write-only - - - RESMSGLST - Reset/Set Message Lost - 4 - 4 - write-only - - - SETMSGLST - Reset/Set Message Lost - 20 - 20 - write-only - - - RESMSGVAL - Reset/Set Message Valid - 5 - 5 - write-only - - - SETMSGVAL - Reset/Set Message Valid - 21 - 21 - write-only - - - RESRTSEL - Reset/Set Receive/Transmit Selected - 6 - 6 - write-only - - - SETRTSEL - Reset/Set Receive/Transmit Selected - 22 - 22 - write-only - - - RESRXEN - Reset/Set Receive Enable - 7 - 7 - write-only - - - SETRXEN - Reset/Set Receive Enable - 23 - 23 - write-only - - - RESTXRQ - Reset/Set Transmit Request - 8 - 8 - write-only - - - SETTXRQ - Reset/Set Transmit Request - 24 - 24 - write-only - - - RESTXEN0 - Reset/Set Transmit Enable 0 - 9 - 9 - write-only - - - SETTXEN0 - Reset/Set Transmit Enable 0 - 25 - 25 - write-only - - - RESTXEN1 - Reset/Set Transmit Enable 1 - 10 - 10 - write-only - - - SETTXEN1 - Reset/Set Transmit Enable 1 - 26 - 26 - write-only - - - RESDIR - Reset/Set Message Direction - 11 - 11 - write-only - - - SETDIR - Reset/Set Message Direction - 27 - 27 - write-only - - - - - MOSTAT - Message Object Status Register - MOCTR - 0x1C - 32 - 0x00000000 - 0x0000FFFF - - - RXPND - Receive Pending - 0 - 0 - read-only - - - value1 - No CAN message has been received. - 0b0 - - - value2 - A CAN message has been received by the message object n, either directly or via gateway copy action. - 0b1 - - - - - TXPND - Transmit Pending - 1 - 1 - read-only - - - value1 - No CAN message has been transmitted. - 0b0 - - - value2 - A CAN message from message object n has been transmitted successfully over the CAN bus. - 0b1 - - - - - RXUPD - Receive Updating - 2 - 2 - read-only - - - value1 - No receive update ongoing. - 0b0 - - - value2 - Message identifier, DLC, and data of the message object are currently updated. - 0b1 - - - - - NEWDAT - New Data - 3 - 3 - read-only - - - value1 - No update of the message object n since last flag reset. - 0b0 - - - value2 - Message object n has been updated. - 0b1 - - - - - MSGLST - Message Lost - 4 - 4 - read-only - - - value1 - No CAN message is lost. - 0b0 - - - value2 - A CAN message is lost because NEWDAT has become set again when it has already been set. - 0b1 - - - - - MSGVAL - Message Valid - 5 - 5 - read-only - - - value1 - Message object n is not valid. - 0b0 - - - value2 - Message object n is valid. - 0b1 - - - - - RTSEL - Receive/Transmit Selected - 6 - 6 - read-only - - - value1 - Message object n is not selected for receive or transmit operation. - 0b0 - - - value2 - Message object n is selected for receive or transmit operation. - 0b1 - - - - - RXEN - Receive Enable - 7 - 7 - read-only - - - value1 - Message object n is not enabled for frame reception. - 0b0 - - - value2 - Message object n is enabled for frame reception. - 0b1 - - - - - TXRQ - Transmit Request - 8 - 8 - read-only - - - value1 - No transmission of message object n is requested. - 0b0 - - - value2 - Transmission of message object n on the CAN bus is requested. - 0b1 - - - - - TXEN0 - Transmit Enable 0 - 9 - 9 - read-only - - - value1 - Message object n is not enabled for frame transmission. - 0b0 - - - value2 - Message object n is enabled for frame transmission. - 0b1 - - - - - TXEN1 - Transmit Enable 1 - 10 - 10 - read-only - - - value1 - Message object n is not enabled for frame transmission. - 0b0 - - - value2 - Message object n is enabled for frame transmission. - 0b1 - - - - - DIR - Message Direction - 11 - 11 - read-only - - - value1 - Receive Object selected: With TXRQ = 1, a Remote Frame with the identifier of message object n is scheduled for transmission. On reception of a Data Frame with matching identifier, the message is stored in message object n. - 0b0 - - - value2 - Transmit Object selected: If TXRQ = 1, message object n is scheduled for transmission of a Data Frame. On reception of a Remote Frame with matching identifier, bit TXRQ is set. - 0b1 - - - - - LIST - List Allocation - 12 - 15 - read-only - - - PPREV - Pointer to Previous Message Object - 16 - 23 - read-only - - - PNEXT - Pointer to Next Message Object - 24 - 31 - read-only - - - - - - - CAN_MO1 - Controller Area Networks - CAN - 0x48015020 - - 0x0 - 0x20 - registers - - - - CAN_MO2 - Controller Area Networks - CAN - 0x48015040 - - 0x0 - 0x20 - registers - - - - CAN_MO3 - Controller Area Networks - CAN - 0x48015060 - - 0x0 - 0x20 - registers - - - - CAN_MO4 - Controller Area Networks - CAN - 0x48015080 - - 0x0 - 0x20 - registers - - - - CAN_MO5 - Controller Area Networks - CAN - 0x480150A0 - - 0x0 - 0x20 - registers - - - - CAN_MO6 - Controller Area Networks - CAN - 0x480150C0 - - 0x0 - 0x20 - registers - - - - CAN_MO7 - Controller Area Networks - CAN - 0x480150E0 - - 0x0 - 0x20 - registers - - - - CAN_MO8 - Controller Area Networks - CAN - 0x48015100 - - 0x0 - 0x20 - registers - - - - CAN_MO9 - Controller Area Networks - CAN - 0x48015120 - - 0x0 - 0x20 - registers - - - - CAN_MO10 - Controller Area Networks - CAN - 0x48015140 - - 0x0 - 0x20 - registers - - - - CAN_MO11 - Controller Area Networks - CAN - 0x48015160 - - 0x0 - 0x20 - registers - - - - CAN_MO12 - Controller Area Networks - CAN - 0x48015180 - - 0x0 - 0x20 - registers - - - - CAN_MO13 - Controller Area Networks - CAN - 0x480151A0 - - 0x0 - 0x20 - registers - - - - CAN_MO14 - Controller Area Networks - CAN - 0x480151C0 - - 0x0 - 0x20 - registers - - - - CAN_MO15 - Controller Area Networks - CAN - 0x480151E0 - - 0x0 - 0x20 - registers - - - - CAN_MO16 - Controller Area Networks - CAN - 0x48015200 - - 0x0 - 0x20 - registers - - - - CAN_MO17 - Controller Area Networks - CAN - 0x48015220 - - 0x0 - 0x20 - registers - - - - CAN_MO18 - Controller Area Networks - CAN - 0x48015240 - - 0x0 - 0x20 - registers - - - - CAN_MO19 - Controller Area Networks - CAN - 0x48015260 - - 0x0 - 0x20 - registers - - - - CAN_MO20 - Controller Area Networks - CAN - 0x48015280 - - 0x0 - 0x20 - registers - - - - CAN_MO21 - Controller Area Networks - CAN - 0x480152A0 - - 0x0 - 0x20 - registers - - - - CAN_MO22 - Controller Area Networks - CAN - 0x480152C0 - - 0x0 - 0x20 - registers - - - - CAN_MO23 - Controller Area Networks - CAN - 0x480152E0 - - 0x0 - 0x20 - registers - - - - CAN_MO24 - Controller Area Networks - CAN - 0x48015300 - - 0x0 - 0x20 - registers - - - - CAN_MO25 - Controller Area Networks - CAN - 0x48015320 - - 0x0 - 0x20 - registers - - - - CAN_MO26 - Controller Area Networks - CAN - 0x48015340 - - 0x0 - 0x20 - registers - - - - CAN_MO27 - Controller Area Networks - CAN - 0x48015360 - - 0x0 - 0x20 - registers - - - - CAN_MO28 - Controller Area Networks - CAN - 0x48015380 - - 0x0 - 0x20 - registers - - - - CAN_MO29 - Controller Area Networks - CAN - 0x480153A0 - - 0x0 - 0x20 - registers - - - - CAN_MO30 - Controller Area Networks - CAN - 0x480153C0 - - 0x0 - 0x20 - registers - - - - CAN_MO31 - Controller Area Networks - CAN - 0x480153E0 - - 0x0 - 0x20 - registers - - - - CAN_MO32 - Controller Area Networks - CAN - 0x48015400 - - 0x0 - 0x20 - registers - - - - CAN_MO33 - Controller Area Networks - CAN - 0x48015420 - - 0x0 - 0x20 - registers - - - - CAN_MO34 - Controller Area Networks - CAN - 0x48015440 - - 0x0 - 0x20 - registers - - - - CAN_MO35 - Controller Area Networks - CAN - 0x48015460 - - 0x0 - 0x20 - registers - - - - CAN_MO36 - Controller Area Networks - CAN - 0x48015480 - - 0x0 - 0x20 - registers - - - - CAN_MO37 - Controller Area Networks - CAN - 0x480154A0 - - 0x0 - 0x20 - registers - - - - CAN_MO38 - Controller Area Networks - CAN - 0x480154C0 - - 0x0 - 0x20 - registers - - - - CAN_MO39 - Controller Area Networks - CAN - 0x480154E0 - - 0x0 - 0x20 - registers - - - - CAN_MO40 - Controller Area Networks - CAN - 0x48015500 - - 0x0 - 0x20 - registers - - - - CAN_MO41 - Controller Area Networks - CAN - 0x48015520 - - 0x0 - 0x20 - registers - - - - CAN_MO42 - Controller Area Networks - CAN - 0x48015540 - - 0x0 - 0x20 - registers - - - - CAN_MO43 - Controller Area Networks - CAN - 0x48015560 - - 0x0 - 0x20 - registers - - - - CAN_MO44 - Controller Area Networks - CAN - 0x48015580 - - 0x0 - 0x20 - registers - - - - CAN_MO45 - Controller Area Networks - CAN - 0x480155A0 - - 0x0 - 0x20 - registers - - - - CAN_MO46 - Controller Area Networks - CAN - 0x480155C0 - - 0x0 - 0x20 - registers - - - - CAN_MO47 - Controller Area Networks - CAN - 0x480155E0 - - 0x0 - 0x20 - registers - - - - CAN_MO48 - Controller Area Networks - CAN - 0x48015600 - - 0x0 - 0x20 - registers - - - - CAN_MO49 - Controller Area Networks - CAN - 0x48015620 - - 0x0 - 0x20 - registers - - - - CAN_MO50 - Controller Area Networks - CAN - 0x48015640 - - 0x0 - 0x20 - registers - - - - CAN_MO51 - Controller Area Networks - CAN - 0x48015660 - - 0x0 - 0x20 - registers - - - - CAN_MO52 - Controller Area Networks - CAN - 0x48015680 - - 0x0 - 0x20 - registers - - - - CAN_MO53 - Controller Area Networks - CAN - 0x480156A0 - - 0x0 - 0x20 - registers - - - - CAN_MO54 - Controller Area Networks - CAN - 0x480156C0 - - 0x0 - 0x20 - registers - - - - CAN_MO55 - Controller Area Networks - CAN - 0x480156E0 - - 0x0 - 0x20 - registers - - - - CAN_MO56 - Controller Area Networks - CAN - 0x48015700 - - 0x0 - 0x20 - registers - - - - CAN_MO57 - Controller Area Networks - CAN - 0x48015720 - - 0x0 - 0x20 - registers - - - - CAN_MO58 - Controller Area Networks - CAN - 0x48015740 - - 0x0 - 0x20 - registers - - - - CAN_MO59 - Controller Area Networks - CAN - 0x48015760 - - 0x0 - 0x20 - registers - - - - CAN_MO60 - Controller Area Networks - CAN - 0x48015780 - - 0x0 - 0x20 - registers - - - - CAN_MO61 - Controller Area Networks - CAN - 0x480157A0 - - 0x0 - 0x20 - registers - - - - CAN_MO62 - Controller Area Networks - CAN - 0x480157C0 - - 0x0 - 0x20 - registers - - - - CAN_MO63 - Controller Area Networks - CAN - 0x480157E0 - - 0x0 - 0x20 - registers - - - - VADC - Analog to Digital Converter - VADC - 0x40004000 - - 0x0 - 0x4000 - registers - - - - CLC - Clock Control Register - 0x0000 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - value1 - On request: enable the module clock - 0b0 - - - value2 - Off request: stop the module clock - 0b1 - - - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - value1 - Module clock is enabled - 0b0 - - - value2 - Off: module is not clocked - 0b1 - - - - - EDIS - Sleep Mode Enable Control - 3 - 3 - read-write - - - value1 - Sleep mode request is enabled and functional - 0b0 - - - value2 - Module disregards the sleep mode control signal - 0b1 - - - - - - - ID - Module Identification Register - 0x0008 - 32 - 0x00C5C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - OCS - OCDS Control and Status Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - TGS - Trigger Set for OTGB0/1 - 0 - 1 - read-write - - - value1 - No Trigger Set output - 0b00 - - - value2 - Trigger Set 1: TS16_SSIG, input sample signals - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Reserved - 0b11 - - - - - TGB - OTGB0/1 Bus Select - 2 - 2 - read-write - - - value1 - Trigger Set is output on OTGB0 - 0b0 - - - value2 - Trigger Set is output on OTGB1 - 0b1 - - - - - TG_P - TGS, TGB Write Protection - 3 - 3 - write-only - - - SUS - OCDS Suspend Control - 24 - 27 - read-write - - - value1 - Will not suspend - 0b0000 - - - value2 - Hard suspend: Clock is switched off immediately. - 0b0001 - - - value3 - Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter. - 0b0010 - - - value4 - Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round. - 0b0011 - - - - - SUS_P - SUS Write Protection - 28 - 28 - write-only - - - SUSSTA - Suspend State - 29 - 29 - read-only - - - value1 - Module is not (yet) suspended - 0b0 - - - value2 - Module is suspended - 0b1 - - - - - - - GLOBCFG - Global Configuration Register - 0x0080 - 32 - 0x0000000F - 0xFFFFFFFF - - - DIVA - Divider Factor for the Analog Internal Clock - 0 - 4 - read-write - - - value1 - fADCI = fADC / 2 - 0x00 - - - value2 - fADCI = fADC / 2 - 0x01 - - - value3 - fADCI = fADC / 3 - 0x02 - - - value4 - fADCI = fADC / 32 - 0x1F - - - - - DCMSB - Double Clock for the MSB Conversion - 7 - 7 - read-write - - - value1 - 1 clock cycles for the MSB (standard) - 0b0 - - - value2 - 2 clock cycles for the MSB (fADCI > 20 MHz) - 0b1 - - - - - DIVD - Divider Factor for the Arbiter Clock - 8 - 9 - read-write - - - value1 - fADCD = fADC - 0b00 - - - value2 - fADCD = fADC / 2 - 0b01 - - - value3 - fADCD = fADC / 3 - 0b10 - - - value4 - fADCD = fADC / 4 - 0b11 - - - - - DIVWC - Write Control for Divider Parameters - 15 - 15 - write-only - - - value1 - No write access to divider parameters - 0b0 - - - value2 - Bitfields DIVA, DCMSB, DIVD can be written - 0b1 - - - - - DPCAL0 - Disable Post-Calibration - 16 - 16 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - DPCAL1 - Disable Post-Calibration - 17 - 17 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - DPCAL2 - Disable Post-Calibration - 18 - 18 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - DPCAL3 - Disable Post-Calibration - 19 - 19 - read-write - - - value1 - Automatic post-calibration after each conversion of group x - 0b0 - - - value2 - No post-calibration - 0b1 - - - - - SUCAL - Start-Up Calibration - 31 - 31 - write-only - - - value1 - No action - 0b0 - - - value2 - Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL) - 0b1 - - - - - - - 2 - 4 - GLOBICLASS[%s] - Input Class Register, Global - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STCS - Sample Time Control for Standard Conversions - 0 - 4 - read-write - - - CMS - Conversion Mode for Standard Conversions - 8 - 10 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - STCE - Sample Time Control for EMUX Conversions - 16 - 20 - read-write - - - CME - Conversion Mode for EMUX Conversions - 24 - 26 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - - - GLOBBOUND - Global Boundary Select Register - 0x00B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOUNDARY0 - Boundary Value 0 for Limit Checking - 0 - 11 - read-write - - - BOUNDARY1 - Boundary Value 1 for Limit Checking - 16 - 27 - read-write - - - - - GLOBEFLAG - Global Event Flag Register - 0x00E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEVGLB - Source Event (Background) - 0 - 0 - read-write - - - value1 - No source event - 0b0 - - - value2 - A source event has occurred - 0b1 - - - - - REVGLB - Global Result Event - 8 - 8 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GLOBRES - 0b1 - - - - - SEVGLBCLR - Clear Source Event (Background) - 16 - 16 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the source event flag SEVGLB - 0b1 - - - - - REVGLBCLR - Clear Global Result Event - 24 - 24 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag REVGLB - 0b1 - - - - - - - GLOBEVNP - Global Event Node Pointer Register - 0x0140 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0NP - Service Request Node Pointer Backgr. Source - 0 - 3 - read-write - - - value1 - Select shared service request line 0 of common service request group 0 - 0b0000 - - - value2 - Select shared service request line 3 of common service request group 0 - 0b0011 - - - value3 - Select shared service request line 0 of common service request group 1 - 0b0100 - - - value4 - Select shared service request line 3 of common service request group 1 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV0NP - Service Request Node Pointer Backgr. Result - 16 - 19 - read-write - - - value1 - Select shared service request line 0 of common service request group 0 - 0b0000 - - - value2 - Select shared service request line 3 of common service request group 0 - 0b0011 - - - value3 - Select shared service request line 0 of common service request group 1 - 0b0100 - - - value4 - Select shared service request line 3 of common service request group 1 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - GLOBTF - Global Test Functions Register - 0x0160 - 32 - 0x00000000 - 0xFFFFFFFF - - - CDGR - Converter Diagnostics Group - 4 - 7 - read-write - - - CDEN - Converter Diagnostics Enable - 8 - 8 - read-write - - - value1 - All diagnostic pull devices are disconnected - 0b0 - - - value2 - Diagnostic pull devices connected as selected by bitfield CDSEL - 0b1 - - - - - CDSEL - Converter Diagnostics Pull-Devices Select - 9 - 10 - read-write - - - value1 - Connected to VAREF - 0b00 - - - value2 - Connected to VAGND - 0b01 - - - value3 - Connected to 1/3rd VAREF - 0b10 - - - value4 - Connected to 2/3rd VAREF - 0b11 - - - - - CDWC - Write Control for Conversion Diagnostics - 15 - 15 - write-only - - - value1 - No write access to parameters - 0b0 - - - value2 - Bitfields CDSEL, CDEN, CDGR can be written - 0b1 - - - - - PDD - Pull-Down Diagnostics Enable - 16 - 16 - read-write - - - value1 - Disconnected - 0b0 - - - value2 - The pull-down diagnostics device is active - 0b1 - - - - - MDWC - Write Control for Multiplexer Diagnostics - 23 - 23 - write-only - - - value1 - No write access to parameters - 0b0 - - - value2 - Bitfield PDD can be written - 0b1 - - - - - - - 4 - 4 - BRSSEL[%s] - Background Request Source Channel Select Register - 0x0180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHSELG0 - Channel Selection Group x - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG1 - Channel Selection Group x - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG2 - Channel Selection Group x - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG3 - Channel Selection Group x - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG4 - Channel Selection Group x - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG5 - Channel Selection Group x - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG6 - Channel Selection Group x - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSELG7 - Channel Selection Group x - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - - - 4 - 4 - BRSPND[%s] - Background Request Source Pending Register - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHPNDG0 - Channels Pending Group x - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG1 - Channels Pending Group x - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG2 - Channels Pending Group x - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG3 - Channels Pending Group x - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG4 - Channels Pending Group x - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG5 - Channels Pending Group x - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG6 - Channels Pending Group x - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPNDG7 - Channels Pending Group x - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - - - BRSCTRL - Background Request Source Control Register - 0x0200 - 32 - 0x00000000 - 0xFFFFFFFF - - - XTSEL - External Trigger Input Selection - 8 - 11 - read-write - - - XTLVL - External Trigger Level - 12 - 12 - read-only - - - XTMODE - Trigger Operating Mode - 13 - 14 - read-write - - - value1 - No external trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon any edge - 0b11 - - - - - XTWC - Write Control for Trigger Configuration - 15 - 15 - write-only - - - value1 - No write access to trigger configuration - 0b0 - - - value2 - Bitfields XTMODE and XTSEL can be written - 0b1 - - - - - GTSEL - Gate Input Selection - 16 - 19 - read-write - - - GTLVL - Gate Input Level - 20 - 20 - read-only - - - GTWC - Write Control for Gate Configuration - 23 - 23 - write-only - - - value1 - No write access to gate configuration - 0b0 - - - value2 - Bitfield GTSEL can be written - 0b1 - - - - - - - BRSMR - Background Request Source Mode Register - 0x0204 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENGT - Enable Gate - 0 - 1 - read-write - - - value1 - No conversion requests are issued - 0b00 - - - value2 - Conversion requests are issued if at least one pending bit is set - 0b01 - - - value3 - Conversion requests are issued if at least one pending bit is set and REQGTx = 1. - 0b10 - - - value4 - Conversion requests are issued if at least one pending bit is set and REQGTx = 0. - 0b11 - - - - - ENTR - Enable External Trigger - 2 - 2 - read-write - - - value1 - External trigger disabled - 0b0 - - - value2 - The selected edge at the selected trigger input signal REQTR generates the load event - 0b1 - - - - - ENSI - Enable Source Interrupt - 3 - 3 - read-write - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source interrupt is generated upon a request source event (last pending conversion is finished) - 0b1 - - - - - SCAN - Autoscan Enable - 4 - 4 - read-write - - - value1 - No autoscan - 0b0 - - - value2 - Autoscan functionality enabled: a request source event automatically generates a load event - 0b1 - - - - - LDM - Autoscan Source Load Event Mode - 5 - 5 - read-write - - - value1 - Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event - 0b0 - - - value2 - Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) - 0b1 - - - - - REQGT - Request Gate Level - 7 - 7 - read-only - - - value1 - The gate input is low - 0b0 - - - value2 - The gate input is high - 0b1 - - - - - CLRPND - Clear Pending Bits - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - The bits in registers BRSPNDx are cleared - 0b1 - - - - - LDEV - Generate Load Event - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - A load event is generated - 0b1 - - - - - RPTDIS - Repeat Disable - 16 - 16 - read-write - - - value1 - A cancelled conversion is repeated - 0b0 - - - value2 - A cancelled conversion is discarded - 0b1 - - - - - - - GLOBRCR - Global Result Control Register - 0x0280 - 32 - 0x00000000 - 0xFFFFFFFF - - - DRCTR - Data Reduction Control - 16 - 19 - read-write - - - value1 - Data reduction disabled - 0b0000 - - - - - WFR - Wait-for-Read Mode Enable - 24 - 24 - read-write - - - value1 - Overwrite mode - 0b0 - - - value2 - Wait-for-read mode enabled for this register - 0b1 - - - - - SRGEN - Service Request Generation Enable - 31 - 31 - read-write - - - value1 - No service request - 0b0 - - - value2 - Service request after a result event - 0b1 - - - - - - - GLOBRES - Global Result Register - 0x0300 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-write - - - GNR - Group Number - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) - 0b1 - - - - - - - GLOBRESD - Global Result Register, Debug - 0x0380 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-write - - - GNR - Group Number - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) - 0b1 - - - - - - - EMUXSEL - External Multiplexer Select Register - 0x03F0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EMUXGRP0 - External Multiplexer Group for Interface x - 0 - 3 - read-write - - - EMUXGRP1 - External Multiplexer Group for Interface x - 4 - 7 - read-write - - - - - - - VADC_G0 - Analog to Digital Converter - VADC - VADC_G - 0x40004400 - - 0x0 - 0x400 - registers - - - - ARBCFG - Arbitration Configuration Register - 0x0080 - 32 - 0x00000000 - 0xFFFFFFFF - - - ANONC - Analog Converter Control - 0 - 1 - read-write - - - ARBRND - Arbitration Round Length - 4 - 5 - read-write - - - value1 - 4 arbitration slots per round (tARB = 4 / fADCD) - 0b00 - - - value2 - 8 arbitration slots per round (tARB = 8 / fADCD) - 0b01 - - - value3 - 16 arbitration slots per round (tARB = 16 / fADCD) - 0b10 - - - value4 - 20 arbitration slots per round (tARB = 20 / fADCD) - 0b11 - - - - - ARBM - Arbitration Mode - 7 - 7 - read-write - - - value1 - The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ). - 0b0 - - - value2 - The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported. - 0b1 - - - - - ANONS - Analog Converter Control Status - 16 - 17 - read-only - - - value1 - Analog converter off - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Normal operation (permanently on) - 0b11 - - - - - CAL - Start-Up Calibration Active Indication - 28 - 28 - read-only - - - value1 - Completed or not yet started - 0b0 - - - value2 - Start-up calibration phase is active - 0b1 - - - - - BUSY - Converter Busy Flag - 30 - 30 - read-only - - - value1 - Not busy - 0b0 - - - value2 - Converter is busy with a conversion - 0b1 - - - - - SAMPLE - Sample Phase Flag - 31 - 31 - read-only - - - value1 - Converting or idle - 0b0 - - - value2 - Input signal is currently sampled - 0b1 - - - - - - - ARBPR - Arbitration Priority Register - 0x0084 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIO0 - Priority of Request Source x - 0 - 1 - read-write - - - value1 - Lowest priority is selected. - 0b00 - - - value2 - Highest priority is selected. - 0b11 - - - - - PRIO1 - Priority of Request Source x - 4 - 5 - read-write - - - value1 - Lowest priority is selected. - 0b00 - - - value2 - Highest priority is selected. - 0b11 - - - - - PRIO2 - Priority of Request Source x - 8 - 9 - read-write - - - value1 - Lowest priority is selected. - 0b00 - - - value2 - Highest priority is selected. - 0b11 - - - - - CSM0 - Conversion Start Mode of Request Source x - 3 - 3 - read-write - - - value1 - Wait-for-start mode - 0b0 - - - value2 - Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. - 0b1 - - - - - CSM1 - Conversion Start Mode of Request Source x - 7 - 7 - read-write - - - value1 - Wait-for-start mode - 0b0 - - - value2 - Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. - 0b1 - - - - - CSM2 - Conversion Start Mode of Request Source x - 11 - 11 - read-write - - - value1 - Wait-for-start mode - 0b0 - - - value2 - Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. - 0b1 - - - - - ASEN0 - Arbitration Slot 0 Enable - 24 - 24 - read-write - - - value1 - The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. - 0b0 - - - value2 - The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. - 0b1 - - - - - ASEN1 - Arbitration Slot 1 Enable - 25 - 25 - read-write - - - value1 - The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. - 0b0 - - - value2 - The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. - 0b1 - - - - - ASEN2 - Arbitration Slot 2 Enable - 26 - 26 - read-write - - - value1 - The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. - 0b0 - - - value2 - The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. - 0b1 - - - - - - - CHASS - Channel Assignment Register - 0x0088 - 32 - 0x00000000 - 0xFFFFFFFF - - - ASSCH0 - Assignment for Channel 0 - 0 - 0 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH1 - Assignment for Channel 1 - 1 - 1 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH2 - Assignment for Channel 2 - 2 - 2 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH3 - Assignment for Channel 3 - 3 - 3 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH4 - Assignment for Channel 4 - 4 - 4 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH5 - Assignment for Channel 5 - 5 - 5 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH6 - Assignment for Channel 6 - 6 - 6 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - ASSCH7 - Assignment for Channel 7 - 7 - 7 - read-write - - - value1 - Channel y can be a background channel converted with lowest priority - 0b0 - - - value2 - Channel y is a priority channel within group x - 0b1 - - - - - - - 2 - 4 - ICLASS[%s] - Input Class Register - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STCS - Sample Time Control for Standard Conversions - 0 - 4 - read-write - - - CMS - Conversion Mode for Standard Conversions - 8 - 10 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - STCE - Sample Time Control for EMUX Conversions - 16 - 20 - read-write - - - CME - Conversion Mode for EMUX Conversions - 24 - 26 - read-write - - - value1 - 12-bit conversion - 0b000 - - - value2 - 10-bit conversion - 0b001 - - - value3 - 8-bit conversion - 0b010 - - - value4 - Reserved - 0b011 - - - value5 - Reserved - 0b100 - - - value6 - 10-bit fast compare mode - 0b101 - - - value7 - Reserved - 0b110 - - - value8 - Reserved - 0b111 - - - - - - - ALIAS - Alias Register - 0x00B0 - 32 - 0x00000100 - 0xFFFFFFFF - - - ALIAS0 - Alias Value for CH0 Conversion Requests - 0 - 4 - read-write - - - ALIAS1 - Alias Value for CH1 Conversion Requests - 8 - 12 - read-write - - - - - BOUND - Boundary Select Register - 0x00B8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOUNDARY0 - Boundary Value 0 for Limit Checking - 0 - 11 - read-write - - - BOUNDARY1 - Boundary Value 1 for Limit Checking - 16 - 27 - read-write - - - - - SYNCTR - Synchronization Control Register - 0x00C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STSEL - Start Selection - 0 - 1 - read-write - - - value1 - Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC - 0b00 - - - value2 - Kernel is synchronization slave: Control information from input CI1 - 0b01 - - - value3 - Kernel is synchronization slave: Control information from input CI2 - 0b10 - - - value4 - Kernel is synchronization slave: Control information from input CI3 - 0b11 - - - - - EVALR1 - Evaluate Ready Input Rx - 4 - 4 - read-write - - - value1 - No ready input control - 0b0 - - - value2 - Ready input Rx is considered for the start of a parallel conversion of this conversion group - 0b1 - - - - - EVALR2 - Evaluate Ready Input Rx - 5 - 5 - read-write - - - value1 - No ready input control - 0b0 - - - value2 - Ready input Rx is considered for the start of a parallel conversion of this conversion group - 0b1 - - - - - EVALR3 - Evaluate Ready Input Rx - 6 - 6 - read-write - - - value1 - No ready input control - 0b0 - - - value2 - Ready input Rx is considered for the start of a parallel conversion of this conversion group - 0b1 - - - - - - - BFL - Boundary Flag Register - 0x00C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BFL0 - Boundar0 Flag y - 0 - 0 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFL1 - Boundar1 Flag y - 1 - 1 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFL2 - Boundar2 Flag y - 2 - 2 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFL3 - Boundar3 Flag y - 3 - 3 - read-only - - - value1 - Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled - 0b0 - - - value2 - Active state: result has crossed the activation boundary - 0b1 - - - - - BFE0 - Enable Bit for Boundar0 Flag y - 16 - 16 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - BFE1 - Enable Bit for Boundar1 Flag y - 17 - 17 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - BFE2 - Enable Bit for Boundar2 Flag y - 18 - 18 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - BFE3 - Enable Bit for Boundar3 Flag y - 19 - 19 - read-write - - - value1 - Output 0 on this channel - 0b0 - - - value2 - Output BFLy on this channel - 0b1 - - - - - - - QCTRL0 - Queue 0 Source Control Register - 0x0100 - 32 - 0x00000000 - 0xFFFFFFFF - - - XTSEL - External Trigger Input Selection - 8 - 11 - read-write - - - XTLVL - External Trigger Level - 12 - 12 - read-only - - - XTMODE - Trigger Operating Mode - 13 - 14 - read-write - - - value1 - No external trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon any edge - 0b11 - - - - - XTWC - Write Control for Trigger Configuration - 15 - 15 - write-only - - - value1 - No write access to trigger configuration - 0b0 - - - value2 - Bitfields XTMODE and XTSEL can be written - 0b1 - - - - - GTSEL - Gate Input Selection - 16 - 19 - read-write - - - GTLVL - Gate Input Level - 20 - 20 - read-only - - - GTWC - Write Control for Gate Configuration - 23 - 23 - write-only - - - value1 - No write access to gate configuration - 0b0 - - - value2 - Bitfield GTSEL can be written - 0b1 - - - - - TMEN - Timer Mode Enable - 28 - 28 - read-write - - - value1 - No timer mode: standard gating mechanism can be used - 0b0 - - - value2 - Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled - 0b1 - - - - - TMWC - Write Control for Timer Mode - 31 - 31 - write-only - - - value1 - No write access to timer mode - 0b0 - - - value2 - Bitfield TMEN can be written - 0b1 - - - - - - - QMR0 - Queue 0 Mode Register - 0x0104 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENGT - Enable Gate - 0 - 1 - read-write - - - value1 - No conversion requests are issued - 0b00 - - - value2 - Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register - 0b01 - - - value3 - Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1 - 0b10 - - - value4 - Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0 - 0b11 - - - - - ENTR - Enable External Trigger - 2 - 2 - read-write - - - value1 - External trigger disabled - 0b0 - - - value2 - The selected edge at the selected trigger input signal REQTR generates the trigger event - 0b1 - - - - - CLRV - Clear Valid Bit - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. - 0b1 - - - - - TREV - Trigger Event - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Generate a trigger event by software - 0b1 - - - - - FLUSH - Flush Queue - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry. - 0b1 - - - - - CEV - Clear Event Flag - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit EV - 0b1 - - - - - RPTDIS - Repeat Disable - 16 - 16 - read-write - - - value1 - A cancelled conversion is repeated - 0b0 - - - value2 - A cancelled conversion is discarded - 0b1 - - - - - - - QSR0 - Queue 0 Status Register - 0x0108 - 32 - 0x00000020 - 0xFFFFFFFF - - - FILL - Filling Level for Queue 2 - 0 - 3 - read-only - - - value1 - There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue - 0b0000 - - - value2 - There are 2 valid entries in the queue - 0b0001 - - - value3 - There are 3 valid entries in the queue - 0b0010 - - - value4 - There are 8 valid entries in the queue - 0b0111 - - - - - EMPTY - Queue Empty - 5 - 5 - read-only - - - value1 - There are valid entries in the queue (see FILL) - 0b0 - - - value2 - No valid entries (queue is empty) - 0b1 - - - - - REQGT - Request Gate Level - 7 - 7 - read-only - - - value1 - The gate input is low - 0b0 - - - value2 - The gate input is high - 0b1 - - - - - EV - Event Detected - 8 - 8 - read-only - - - value1 - No trigger event - 0b0 - - - value2 - A trigger event has been detected - 0b1 - - - - - - - Q0R0 - Queue 0 Register 0 - 0x010C - 32 - 0x00000000 - 0xFFFFFFFF - - - REQCHNR - Request Channel Number - 0 - 4 - read-only - - - RF - Refill - 5 - 5 - read-only - - - value1 - The request is discarded after the conversion start. - 0b0 - - - value2 - The request is automatically refilled into the queue after the conversion start. - 0b1 - - - - - ENSI - Enable Source Interrupt - 6 - 6 - read-only - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source event interrupt is generated upon a request source event (related conversion is finished) - 0b1 - - - - - EXTR - External Trigger - 7 - 7 - read-only - - - value1 - A valid queue entry immediately leads to a conversion request - 0b0 - - - value2 - The request handler waits for a trigger event - 0b1 - - - - - V - Request Channel Number Valid - 8 - 8 - read-only - - - value1 - No valid queue entry - 0b0 - - - value2 - The queue entry is valid and leads to a conversion request - 0b1 - - - - - - - QINR0 - Queue 0 Input Register - 0x0110 - 32 - 0x00000000 - 0xFFFFFFFF - - - REQCHNR - Request Channel Number - 0 - 4 - write-only - - - RF - Refill - 5 - 5 - write-only - - - value1 - No refill: this queue entry is converted once and then invalidated - 0b0 - - - value2 - Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started - 0b1 - - - - - ENSI - Enable Source Interrupt - 6 - 6 - write-only - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source event interrupt is generated upon a request source event (related conversion is finished) - 0b1 - - - - - EXTR - External Trigger - 7 - 7 - write-only - - - value1 - A valid queue entry immediately leads to a conversion request. - 0b0 - - - value2 - A valid queue entry waits for a trigger event to occur before issuing a conversion request. - 0b1 - - - - - - - QBUR0 - Queue 0 Backup Register - QINR0 - 0x0110 - 32 - 0x00000000 - 0xFFFFFFFF - - - REQCHNR - Request Channel Number - 0 - 4 - read-only - - - RF - Refill - 5 - 5 - read-only - - - ENSI - Enable Source Interrupt - 6 - 6 - read-only - - - EXTR - External Trigger - 7 - 7 - read-only - - - V - Request Channel Number Valid - 8 - 8 - read-only - - - value1 - Backup register not valid - 0b0 - - - value2 - Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested. - 0b1 - - - - - - - ASCTRL - Autoscan Source Control Register - 0x0120 - 32 - 0x00000000 - 0xFFFFFFFF - - - XTSEL - External Trigger Input Selection - 8 - 11 - read-write - - - XTLVL - External Trigger Level - 12 - 12 - read-only - - - XTMODE - Trigger Operating Mode - 13 - 14 - read-write - - - value1 - No external trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon any edge - 0b11 - - - - - XTWC - Write Control for Trigger Configuration - 15 - 15 - write-only - - - value1 - No write access to trigger configuration - 0b0 - - - value2 - Bitfields XTMODE and XTSEL can be written - 0b1 - - - - - GTSEL - Gate Input Selection - 16 - 19 - read-write - - - GTLVL - Gate Input Level - 20 - 20 - read-only - - - GTWC - Write Control for Gate Configuration - 23 - 23 - write-only - - - value1 - No write access to gate configuration - 0b0 - - - value2 - Bitfield GTSEL can be written - 0b1 - - - - - TMEN - Timer Mode Enable - 28 - 28 - read-write - - - value1 - No timer mode: standard gating mechanism can be used - 0b0 - - - value2 - Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled - 0b1 - - - - - TMWC - Write Control for Timer Mode - 31 - 31 - write-only - - - value1 - No write access to timer mode - 0b0 - - - value2 - Bitfield TMEN can be written - 0b1 - - - - - - - ASMR - Autoscan Source Mode Register - 0x0124 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENGT - Enable Gate - 0 - 1 - read-write - - - value1 - No conversion requests are issued - 0b00 - - - value2 - Conversion requests are issued if at least one pending bit is set - 0b01 - - - value3 - Conversion requests are issued if at least one pending bit is set and REQGTx = 1. - 0b10 - - - value4 - Conversion requests are issued if at least one pending bit is set and REQGTx = 0. - 0b11 - - - - - ENTR - Enable External Trigger - 2 - 2 - read-write - - - value1 - External trigger disabled - 0b0 - - - value2 - The selected edge at the selected trigger input signal REQTR generates the load event - 0b1 - - - - - ENSI - Enable Source Interrupt - 3 - 3 - read-write - - - value1 - No request source interrupt - 0b0 - - - value2 - A request source interrupt is generated upon a request source event (last pending conversion is finished) - 0b1 - - - - - SCAN - Autoscan Enable - 4 - 4 - read-write - - - value1 - No autoscan - 0b0 - - - value2 - Autoscan functionality enabled: a request source event automatically generates a load event - 0b1 - - - - - LDM - Autoscan Source Load Event Mode - 5 - 5 - read-write - - - value1 - Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event - 0b0 - - - value2 - Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) - 0b1 - - - - - REQGT - Request Gate Level - 7 - 7 - read-only - - - value1 - The gate input is low - 0b0 - - - value2 - The gate input is high - 0b1 - - - - - CLRPND - Clear Pending Bits - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - The bits in register GxASPNDx are cleared - 0b1 - - - - - LDEV - Generate Load Event - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - A load event is generated - 0b1 - - - - - RPTDIS - Repeat Disable - 16 - 16 - read-write - - - value1 - A cancelled conversion is repeated - 0b0 - - - value2 - A cancelled conversion is discarded - 0b1 - - - - - - - ASSEL - Autoscan Source Channel Select Register - 0x0128 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHSEL0 - Channel Selection - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL1 - Channel Selection - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL2 - Channel Selection - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL3 - Channel Selection - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL4 - Channel Selection - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL5 - Channel Selection - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL6 - Channel Selection - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - CHSEL7 - Channel Selection - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - This channel is part of the scan sequence - 0b1 - - - - - - - ASPND - Autoscan Source Pending Register - 0x012C - 32 - 0x00000000 - 0xFFFFFFFF - - - CHPND0 - Channels Pending - 0 - 0 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND1 - Channels Pending - 1 - 1 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND2 - Channels Pending - 2 - 2 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND3 - Channels Pending - 3 - 3 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND4 - Channels Pending - 4 - 4 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND5 - Channels Pending - 5 - 5 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND6 - Channels Pending - 6 - 6 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - CHPND7 - Channels Pending - 7 - 7 - read-write - - - value1 - Ignore this channel - 0b0 - - - value2 - Request conversion of this channel - 0b1 - - - - - - - CEFLAG - Channel Event Flag Register - 0x0180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CEV0 - Channel Event for Channel 0 - 0 - 0 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV1 - Channel Event for Channel 1 - 1 - 1 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV2 - Channel Event for Channel 2 - 2 - 2 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV3 - Channel Event for Channel 3 - 3 - 3 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV4 - Channel Event for Channel 4 - 4 - 4 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV5 - Channel Event for Channel 5 - 5 - 5 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV6 - Channel Event for Channel 6 - 6 - 6 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - CEV7 - Channel Event for Channel 7 - 7 - 7 - read-write - - - value1 - No channel event - 0b0 - - - value2 - A channel event has occurred - 0b1 - - - - - - - REFLAG - Result Event Flag Register - 0x0184 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV0 - Result Event for Result Register 0 - 0 - 0 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV1 - Result Event for Result Register 1 - 1 - 1 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV2 - Result Event for Result Register 2 - 2 - 2 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV3 - Result Event for Result Register 3 - 3 - 3 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV4 - Result Event for Result Register 4 - 4 - 4 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV5 - Result Event for Result Register 5 - 5 - 5 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV6 - Result Event for Result Register 6 - 6 - 6 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV7 - Result Event for Result Register 7 - 7 - 7 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV8 - Result Event for Result Register 8 - 8 - 8 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV9 - Result Event for Result Register 9 - 9 - 9 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV10 - Result Event for Result Register 10 - 10 - 10 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV11 - Result Event for Result Register 11 - 11 - 11 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV12 - Result Event for Result Register 12 - 12 - 12 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV13 - Result Event for Result Register 13 - 13 - 13 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV14 - Result Event for Result Register 14 - 14 - 14 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - REV15 - Result Event for Result Register 15 - 15 - 15 - read-write - - - value1 - No result event - 0b0 - - - value2 - New result was stored in register GxRESy - 0b1 - - - - - - - SEFLAG - Source Event Flag Register - 0x0188 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0 - Source Event 0/1 - 0 - 0 - read-write - - - value1 - No source event - 0b0 - - - value2 - A source event has occurred - 0b1 - - - - - SEV1 - Source Event 0/1 - 1 - 1 - read-write - - - value1 - No source event - 0b0 - - - value2 - A source event has occurred - 0b1 - - - - - - - CEFCLR - Channel Event Flag Clear Register - 0x0190 - 32 - 0x00000000 - 0xFFFFFFFF - - - CEV0 - Clear Channel Event for Channel 0 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV1 - Clear Channel Event for Channel 1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV2 - Clear Channel Event for Channel 2 - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV3 - Clear Channel Event for Channel 3 - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV4 - Clear Channel Event for Channel 4 - 4 - 4 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV5 - Clear Channel Event for Channel 5 - 5 - 5 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV6 - Clear Channel Event for Channel 6 - 6 - 6 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - CEV7 - Clear Channel Event for Channel 7 - 7 - 7 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the channel event flag in GxCEFLAG - 0b1 - - - - - - - REFCLR - Result Event Flag Clear Register - 0x0194 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV0 - Clear Result Event for Result Register 0 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV1 - Clear Result Event for Result Register 1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV2 - Clear Result Event for Result Register 2 - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV3 - Clear Result Event for Result Register 3 - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV4 - Clear Result Event for Result Register 4 - 4 - 4 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV5 - Clear Result Event for Result Register 5 - 5 - 5 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV6 - Clear Result Event for Result Register 6 - 6 - 6 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV7 - Clear Result Event for Result Register 7 - 7 - 7 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV8 - Clear Result Event for Result Register 8 - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV9 - Clear Result Event for Result Register 9 - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV10 - Clear Result Event for Result Register 10 - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV11 - Clear Result Event for Result Register 11 - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV12 - Clear Result Event for Result Register 12 - 12 - 12 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV13 - Clear Result Event for Result Register 13 - 13 - 13 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV14 - Clear Result Event for Result Register 14 - 14 - 14 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - REV15 - Clear Result Event for Result Register 15 - 15 - 15 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the result event flag in GxREFLAG - 0b1 - - - - - - - SEFCLR - Source Event Flag Clear Register - 0x0198 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0 - Clear Source Event 0/1 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the source event flag in GxSEFLAG - 0b1 - - - - - SEV1 - Clear Source Event 0/1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear the source event flag in GxSEFLAG - 0b1 - - - - - - - CEVNP0 - Channel Event Node Pointer Register 0 - 0x01A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CEV0NP - Service Request Node Pointer Channel Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV1NP - Service Request Node Pointer Channel Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV2NP - Service Request Node Pointer Channel Event i - 8 - 11 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV3NP - Service Request Node Pointer Channel Event i - 12 - 15 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV4NP - Service Request Node Pointer Channel Event i - 16 - 19 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV5NP - Service Request Node Pointer Channel Event i - 20 - 23 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV6NP - Service Request Node Pointer Channel Event i - 24 - 27 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - CEV7NP - Service Request Node Pointer Channel Event i - 28 - 31 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - REVNP0 - Result Event Node Pointer Register 0 - 0x01B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV0NP - Service Request Node Pointer Result Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV1NP - Service Request Node Pointer Result Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV2NP - Service Request Node Pointer Result Event i - 8 - 11 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV3NP - Service Request Node Pointer Result Event i - 12 - 15 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV4NP - Service Request Node Pointer Result Event i - 16 - 19 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV5NP - Service Request Node Pointer Result Event i - 20 - 23 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV6NP - Service Request Node Pointer Result Event i - 24 - 27 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV7NP - Service Request Node Pointer Result Event i - 28 - 31 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - REVNP1 - Result Event Node Pointer Register 1 - 0x01B4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV8NP - Service Request Node Pointer Result Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV9NP - Service Request Node Pointer Result Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV10NP - Service Request Node Pointer Result Event i - 8 - 11 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV11NP - Service Request Node Pointer Result Event i - 12 - 15 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV12NP - Service Request Node Pointer Result Event i - 16 - 19 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV13NP - Service Request Node Pointer Result Event i - 20 - 23 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV14NP - Service Request Node Pointer Result Event i - 24 - 27 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - REV15NP - Service Request Node Pointer Result Event i - 28 - 31 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - SEVNP - Source Event Node Pointer Register - 0x01C0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEV0NP - Service Request Node Pointer Source Event i - 0 - 3 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - SEV1NP - Service Request Node Pointer Source Event i - 4 - 7 - read-write - - - value1 - Select service request line 0 of group x - 0b0000 - - - value2 - Select service request line 3 of group x - 0b0011 - - - value3 - Select shared service request line 0 - 0b0100 - - - value4 - Select shared service request line 3 - 0b0111 - - - value5 - Reserved - 0b1xxx - - - - - - - SRACT - Service Request Software Activation Trigger - 0x01C8 - 32 - 0x00000000 - 0xFFFFFFFF - - - AGSR0 - Activate Group Service Request Node 0 - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - AGSR1 - Activate Group Service Request Node 1 - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - AGSR2 - Activate Group Service Request Node 2 - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - AGSR3 - Activate Group Service Request Node 3 - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR0 - Activate Shared Service Request Node 0 - 8 - 8 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR1 - Activate Shared Service Request Node 1 - 9 - 9 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR2 - Activate Shared Service Request Node 2 - 10 - 10 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - ASSR3 - Activate Shared Service Request Node 3 - 11 - 11 - write-only - - - value1 - No action - 0b0 - - - value2 - Activate the associated service request line - 0b1 - - - - - - - EMUXCTR - External Multiplexer Control Register - 0x01F0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EMUXSET - External Multiplexer Start Selection - 0 - 2 - read-write - - - EMUXACT - External Multiplexer Actual Selection - 8 - 10 - read-only - - - EMUXCH - External Multiplexer Channel Select - 16 - 20 - read-write - - - EMUXMODE - External Multiplexer Mode - 26 - 27 - read-write - - - value1 - Software control (no hardware action) - 0b00 - - - value2 - Steady mode (use EMUXSET value) - 0b01 - - - value3 - Single-step mode - 0b10 - - - value4 - Sequence mode - 0b11 - - - - - EMXCOD - External Multiplexer Coding Scheme - 28 - 28 - read-write - - - value1 - Output the channel number in binary code - 0b0 - - - value2 - Output the channel number in Gray code - 0b1 - - - - - EMXST - External Multiplexer Sample Time Control - 29 - 29 - read-write - - - value1 - Use STCE whenever the setting changes - 0b0 - - - value2 - Use STCE for each conversion of an external channel - 0b1 - - - - - EMXWC - Write Control for EMUX Configuration - 31 - 31 - write-only - - - value1 - No write access to EMUX cfg. - 0b0 - - - value2 - Bitfields EMXMODE, EMXCOD, EMXST can be written - 0b1 - - - - - - - VFR - Valid Flag Register - 0x01F8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VF0 - Valid Flag of Result Register x - 0 - 0 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF1 - Valid Flag of Result Register x - 1 - 1 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF2 - Valid Flag of Result Register x - 2 - 2 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF3 - Valid Flag of Result Register x - 3 - 3 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF4 - Valid Flag of Result Register x - 4 - 4 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF5 - Valid Flag of Result Register x - 5 - 5 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF6 - Valid Flag of Result Register x - 6 - 6 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF7 - Valid Flag of Result Register x - 7 - 7 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF8 - Valid Flag of Result Register x - 8 - 8 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF9 - Valid Flag of Result Register x - 9 - 9 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF10 - Valid Flag of Result Register x - 10 - 10 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF11 - Valid Flag of Result Register x - 11 - 11 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF12 - Valid Flag of Result Register x - 12 - 12 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF13 - Valid Flag of Result Register x - 13 - 13 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF14 - Valid Flag of Result Register x - 14 - 14 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - VF15 - Valid Flag of Result Register x - 15 - 15 - read-write - - - value1 - Read access: No new valid data available Write access: No effect - 0b0 - - - value2 - Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) - 0b1 - - - - - - - 8 - 4 - CHCTR[%s] - Channel Ctrl. Reg. - 0x0200 - 32 - 0x00000000 - 0xFFFFFFFF - - - ICLSEL - Input Class Select - 0 - 1 - read-write - - - value1 - Use group-specific class 0 - 0b00 - - - value2 - Use group-specific class 1 - 0b01 - - - value3 - Use global class 0 - 0b10 - - - value4 - Use global class 1 - 0b11 - - - - - BNDSELL - Lower Boundary Select - 4 - 5 - read-write - - - value1 - Use group-specific boundary 0 - 0b00 - - - value2 - Use group-specific boundary 1 - 0b01 - - - value3 - Use global boundary 0 - 0b10 - - - value4 - Use global boundary 1 - 0b11 - - - - - BNDSELU - Upper Boundary Select - 6 - 7 - read-write - - - value1 - Use group-specific boundary 0 - 0b00 - - - value2 - Use group-specific boundary 1 - 0b01 - - - value3 - Use global boundary 0 - 0b10 - - - value4 - Use global boundary 1 - 0b11 - - - - - CHEVMODE - Channel Event Mode - 8 - 9 - read-write - - - value1 - Never - 0b00 - - - value2 - NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) - 0b01 - - - value3 - NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) - 0b10 - - - value4 - NCM: Always (ignore band) FCM: If result switches to either level - 0b11 - - - - - SYNC - Synchronization Request - 10 - 10 - read-write - - - value1 - No synchroniz. request, standalone operation - 0b0 - - - value2 - Request a synchronized conversion of this channel (only taken into account for a master) - 0b1 - - - - - REFSEL - Reference Input Selection - 11 - 11 - read-write - - - value1 - Standard reference input VAREF - 0b0 - - - value2 - Alternate reference input from CH0 - 0b1 - - - - - RESREG - Result Register - 16 - 19 - read-write - - - value1 - Store result in group result register GxRES0 - 0b0000 - - - value2 - Store result in group result register GxRES15 - 0b1111 - - - - - RESTBS - Result Target for Background Source - 20 - 20 - read-write - - - value1 - Store results in the selected group result register - 0b0 - - - value2 - Store results in the global result register - 0b1 - - - - - RESPOS - Result Position - 21 - 21 - read-write - - - value1 - Store results left-aligned - 0b0 - - - value2 - Store results right-aligned - 0b1 - - - - - BWDCH - Broken Wire Detection Channel - 28 - 29 - read-write - - - value1 - Select VAGND - 0b00 - - - value2 - Select VAREF - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Reserved - 0b11 - - - - - BWDEN - Broken Wire Detection Enable - 30 - 30 - read-write - - - value1 - Normal operation - 0b0 - - - value2 - Additional preparation phase is enabled - 0b1 - - - - - - - 16 - 4 - RCR[%s] - Result Control Register - 0x0280 - 32 - 0x00000000 - 0xFFFFFFFF - - - DRCTR - Data Reduction Control - 16 - 19 - read-write - - - DMM - Data Modification Mode - 20 - 21 - read-write - - - value1 - Standard data reduction (accumulation) - 0b00 - - - value2 - Result filtering mode - 0b01 - - - value3 - Difference mode - 0b10 - - - value4 - Reserved - 0b11 - - - - - WFR - Wait-for-Read Mode Enable - 24 - 24 - read-write - - - value1 - Overwrite mode - 0b0 - - - value2 - Wait-for-read mode enabled for this register - 0b1 - - - - - FEN - FIFO Mode Enable - 25 - 26 - read-write - - - value1 - Separate result register - 0b00 - - - value2 - Part of a FIFO structure: copy each new valid result - 0b01 - - - value3 - Reserved - 0b10 - - - - - SRGEN - Service Request Generation Enable - 31 - 31 - read-write - - - value1 - No service request - 0b0 - - - value2 - Service request after a result event - 0b1 - - - - - - - 16 - 4 - RES[%s] - Result Register - 0x0300 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of Most Recent Conversion - 0 - 15 - read-write - - - DRC - Data Reduction Counter - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - value1 - Request source 0 - 0b00 - - - value2 - Request source 1 - 0b01 - - - value3 - Request source 2 - 0b10 - - - value4 - Reserved - 0b11 - - - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-only - - - value1 - No new result available - 0b0 - - - value2 - Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated - 0b1 - - - - - - - 16 - 4 - RESD[%s] - Result Register, Debug - 0x0380 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of Most Recent Conversion - 0 - 15 - read-only - - - DRC - Data Reduction Counter - 16 - 19 - read-only - - - CHNR - Channel Number - 20 - 24 - read-only - - - EMUX - External Multiplexer Setting - 25 - 27 - read-only - - - CRS - Converted Request Source - 28 - 29 - read-only - - - value1 - Request source 0 - 0b00 - - - value2 - Request source 1 - 0b01 - - - value3 - Request source 2 - 0b10 - - - value4 - Reserved - 0b11 - - - - - FCR - Fast Compare Result - 30 - 30 - read-only - - - value1 - Signal level was below compare value - 0b0 - - - value2 - Signal level was above compare value - 0b1 - - - - - VF - Valid Flag - 31 - 31 - read-only - - - value1 - No new result available - 0b0 - - - value2 - Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated - 0b1 - - - - - - - - - VADC_G1 - Analog to Digital Converter - VADC - 0x40004800 - - 0x0 - 0x400 - registers - - - - VADC_G2 - Analog to Digital Converter - VADC - 0x40004C00 - - 0x0 - 0x400 - registers - - - - VADC_G3 - Analog to Digital Converter - VADC - 0x40005000 - - 0x0 - 0x400 - registers - - - - DSD - Delta Sigma Demodulator - DSD - 0x40008000 - - 0x0 - 0x4000 - registers - - - - CLC - Clock Control Register - 0x0000 - 32 - 0x00000003 - 0xFFFFFFFF - - - DISR - Module Disable Request Bit - 0 - 0 - read-write - - - value1 - On request: enable the module clock - 0b0 - - - value2 - Off request: stop the module clock - 0b1 - - - - - DISS - Module Disable Status Bit - 1 - 1 - read-only - - - value1 - Module clock is enabled - 0b0 - - - value2 - Off: module is not clocked - 0b1 - - - - - EDIS - Sleep Mode Enable Control - 3 - 3 - read-write - - - value1 - Sleep mode request is enabled and functional - 0b0 - - - value2 - Module disregards the sleep mode control signal - 0b1 - - - - - - - ID - Module Identification Register - 0x0008 - 32 - 0x00A4C000 - 0xFFFFFF00 - - - MOD_REV - Module Revision - 0 - 7 - read-only - - - MOD_TYPE - Module Type - 8 - 15 - read-only - - - MOD_NUMBER - Module Number - 16 - 31 - read-only - - - - - OCS - OCDS Control and Status Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUS - OCDS Suspend Control - 24 - 27 - read-write - - - value1 - Will not suspend - 0b0000 - - - value2 - Hard suspend: Clock is switched off immediately. - 0b0001 - - - value3 - Soft suspend channel 0 - 0b0010 - - - value4 - Soft suspend channel 1 - 0b0011 - - - value5 - Soft suspend channel 3 - 0b0101 - - - - - SUS_P - SUS Write Protection - 28 - 28 - write-only - - - SUSSTA - Suspend State - 29 - 29 - read-only - - - value1 - Module is not (yet) suspended - 0b0 - - - value2 - Module is suspended - 0b1 - - - - - - - GLOBCFG - Global Configuration Register - 0x0080 - 32 - 0x00000000 - 0xFFFFFFFF - - - MCSEL - Modulator Clock Select - 0 - 2 - read-write - - - value1 - Internal clock off, no source selected - 0b000 - - - value2 - fDSD - 0b001 - - - - - - - GLOBRC - Global Run Control Register - 0x0088 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH0RUN - Channel 0 Run Control - 0 - 0 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - CH1RUN - Channel 1 Run Control - 1 - 1 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - CH2RUN - Channel 2 Run Control - 2 - 2 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - CH3RUN - Channel 3 Run Control - 3 - 3 - read-write - - - value1 - Stop channel x - 0b0 - - - value2 - Demodulator channel x is enabled and runs - 0b1 - - - - - - - CGCFG - Carrier Generator Configuration Register - 0x00A0 - 32 - 0x07100000 - 0xFFFFFFFF - - - CGMOD - Carrier Generator Operating Mode - 0 - 1 - read-write - - - value1 - Stopped - 0b00 - - - value2 - Square wave - 0b01 - - - value3 - Triangle - 0b10 - - - value4 - Sine wave - 0b11 - - - - - BREV - Bit-Reverse PWM Generation - 2 - 2 - read-write - - - value1 - Normal mode - 0b0 - - - value2 - Bit-reverse mode - 0b1 - - - - - SIGPOL - Signal Polarity - 3 - 3 - read-write - - - value1 - Normal: carrier signal begins with +1 - 0b0 - - - value2 - Inverted: carrier signal begins with -1 - 0b1 - - - - - DIVCG - Divider Factor for the PWM Pattern Signal Generator - 4 - 7 - read-write - - - value1 - fCG = fCLK / 2 - 0x0 - - - value2 - fCG = fCLK / 4 - 0x1 - - - value3 - fCG = fCLK / 6 - 0x2 - - - value4 - fCG = fCLK / 32 - 0xF - - - - - RUN - Run Indicator - 15 - 15 - read-only - - - value1 - Stopped (cleared at the end of a period) - 0b0 - - - value2 - Running - 0b1 - - - - - BITCOUNT - Bit Counter - 16 - 20 - read-only - - - STEPCOUNT - Step Counter - 24 - 27 - read-only - - - STEPS - Step Counter Sign - 28 - 28 - read-only - - - value1 - Step counter value is positive - 0b0 - - - value2 - Step counter value is negative - 0b1 - - - - - STEPD - Step Counter Direction - 29 - 29 - read-only - - - value1 - Step counter is counting up - 0b0 - - - value2 - Step counter is counting down - 0b1 - - - - - SGNCG - Sign Signal from Carrier Generator - 30 - 30 - read-only - - - value1 - Positive values - 0b0 - - - value2 - Negative values - 0b1 - - - - - - - EVFLAG - Event Flag Register - 0x00E0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESEV0 - Result Event - 0 - 0 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - RESEV1 - Result Event - 1 - 1 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - RESEV2 - Result Event - 2 - 2 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - RESEV3 - Result Event - 3 - 3 - read-write - - - value1 - No result event - 0b0 - - - value2 - A new result has been stored in register RESMx - 0b1 - - - - - ALEV0 - Alarm Event - 16 - 16 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV1 - Alarm Event - 17 - 17 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV2 - Alarm Event - 18 - 18 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV3 - Alarm Event - 19 - 19 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV4 - Alarm Event - 20 - 20 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV5 - Alarm Event - 21 - 21 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV6 - Alarm Event - 22 - 22 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV7 - Alarm Event - 23 - 23 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV8 - Alarm Event - 24 - 24 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - ALEV9 - Alarm Event - 25 - 25 - read-write - - - value1 - No alarm event - 0b0 - - - value2 - An alarm event has occurred - 0b1 - - - - - - - EVFLAGCLR - Event Flag Clear Register - 0x00E4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESEC0 - Result Event Clear - 0 - 0 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - RESEC1 - Result Event Clear - 1 - 1 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - RESEC2 - Result Event Clear - 2 - 2 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - RESEC3 - Result Event Clear - 3 - 3 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit RESEVx - 0b1 - - - - - ALEC0 - Alarm Event Clear - 16 - 16 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - ALEC1 - Alarm Event Clear - 17 - 17 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - ALEC2 - Alarm Event Clear - 18 - 18 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - ALEC3 - Alarm Event Clear - 19 - 19 - write-only - - - value1 - No action - 0b0 - - - value2 - Clear bit ALEVx - 0b1 - - - - - - - - - DSD_CH0 - Delta Sigma Demodulator - DSD - DSD_CH - 0x40008100 - - 0x0 - 0x100 - registers - - - - MODCFG - Modulator Configuration Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIVM - Divider Factor for Modulator Clock - 16 - 19 - read-write - - - value1 - fMOD = fCLK / 2 - 0x0 - - - value2 - fMOD = fCLK / 4 - 0x1 - - - value3 - fMOD = fCLK / 6 - 0x2 - - - value4 - fMOD = fCLK / 32 - 0xF - - - - - DWC - Write Control for Divider Factor - 23 - 23 - write-only - - - value1 - No write access to divider factor - 0b0 - - - value2 - Bitfield DIVM can be written - 0b1 - - - - - - - DICFG - Demodulator Input Configuration Register - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSRC - Input Data Source Select - 0 - 3 - read-write - - - value1 - Disconnected - 0b000X - - - value2 - External, from input A, direct - 0b0010 - - - value3 - External, from input A, inverted - 0b0011 - - - value4 - External, from input B, direct - 0b0100 - - - value5 - External, from input B, inverted - 0b0101 - - - - - DSWC - Write Control for Data Selection - 7 - 7 - write-only - - - value1 - No write access to data parameters - 0b0 - - - value2 - Bitfield DSRC can be written - 0b1 - - - - - ITRMODE - Integrator Trigger Mode - 8 - 9 - read-write - - - value1 - No integration trigger, integrator bypassed - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - No trigger, integrator active all the time - 0b11 - - - - - TSTRMODE - Timestamp Trigger Mode - 10 - 11 - read-write - - - value1 - No timestamp trigger - 0b00 - - - value2 - Trigger event upon a falling edge - 0b01 - - - value3 - Trigger event upon a rising edge - 0b10 - - - value4 - Trigger event upon each edge - 0b11 - - - - - TRSEL - Trigger Select - 12 - 14 - read-write - - - TRWC - Write Control for Trigger Parameters - 15 - 15 - write-only - - - value1 - No write access to trigger parameters - 0b0 - - - value2 - Bitfields TRSEL, TSTRMODE, ITRMODE can be written - 0b1 - - - - - CSRC - Sample Clock Source Select - 16 - 19 - read-write - - - value1 - Reserved - 0b0000 - - - value2 - External, from input A - 0b0001 - - - value3 - External, from input B - 0b0010 - - - value4 - Internal clock - 0b1111 - - - - - STROBE - Data Strobe Generatoion Mode - 20 - 23 - read-write - - - value1 - No data strobe - 0b0000 - - - value2 - Direct clock, a sample trigger is generated at each rising clock edge - 0b0001 - - - value3 - Direct clock, a sample trigger is generated at each falling clock edge - 0b0010 - - - value4 - Double data, a sample trigger is generated at each rising and falling clock edge - 0b0011 - - - value5 - Reserved - 0b0100 - - - value6 - Double clock, a sample trigger is generated at every 2nd rising clock edge - 0b0101 - - - value7 - Double clock, a sample trigger is generated at every 2nd falling clock edge - 0b0110 - - - value8 - Reserved - 0b0111 - - - - - SCWC - Write Control for Strobe/Clock Selection - 31 - 31 - write-only - - - value1 - No write access to strobe/clock parameters - 0b0 - - - value2 - Bitfields STROBE, CSRC can be written - 0b1 - - - - - - - FCFGC - Filter Configuration Register, Main Comb Filter - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFMDF - CIC Filter (Main Chain) Decimation Factor - 0 - 7 - read-write - - - CFMC - CIC Filter (Main Chain) Configuration - 8 - 9 - read-write - - - value1 - CIC1 - 0b00 - - - value2 - CIC2 - 0b01 - - - value3 - CIC3 - 0b10 - - - value4 - CICF - 0b11 - - - - - CFEN - CIC Filter Enable - 10 - 10 - read-write - - - value1 - CIC filter disabled and bypassed - 0b0 - - - value2 - Enable CIC filter - 0b1 - - - - - SRGM - Service Request Generation Main Chain - 14 - 15 - read-write - - - value1 - Never, service requests disabled - 0b00 - - - value2 - Reserved - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Always, for each new result value - 0b11 - - - - - CFMSV - CIC Filter (Main Chain) Start Value - 16 - 23 - read-write - - - CFMDCNT - CIC Filter (Main Chain) Decimation Counter - 24 - 31 - read-only - - - - - FCFGA - Filter Configuration Register, Auxiliary Filter - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFADF - CIC Filter (Auxiliary) Decimation Factor - 0 - 7 - read-write - - - CFAC - CIC Filter (Auxiliary) Configuration - 8 - 9 - read-write - - - value1 - CIC1 - 0b00 - - - value2 - CIC2 - 0b01 - - - value3 - CIC3 - 0b10 - - - value4 - CICF - 0b11 - - - - - SRGA - Service Request Generation Auxiliary Filter - 10 - 11 - read-write - - - value1 - Never, service requests disabled - 0b00 - - - value2 - Auxiliary filter: As selected by bitfield ESEL - 0b01 - - - value3 - Alternate source: Capturing of a sign delay value to register CGSYNCx (x = 0 - 3) - 0b10 - - - value4 - Reserved - 0b11 - - - - - ESEL - Event Select - 12 - 13 - read-write - - - value1 - Always, for each new result value - 0b00 - - - value2 - If result is inside the boundary band - 0b01 - - - value3 - If result is outside the boundary band - 0b10 - - - value4 - Reserved - 0b11 - - - - - EGT - Event Gating - 14 - 14 - read-write - - - value1 - Separate: generate events according to ESEL - 0b0 - - - value2 - Coupled: generate events only when the integrator is enabled and after the discard phase defined by bitfield NVALDIS - 0b1 - - - - - CFADCNT - CIC Filter (Auxiliary) Decimation Counter - 24 - 31 - read-only - - - - - IWCTR - Integration Window Control Register - 0x0020 - 32 - 0x00000000 - 0xFFFFFFFF - - - NVALCNT - Number of Values Counted - 0 - 5 - read-only - - - INTEN - Integration Enable - 7 - 7 - read-only - - - value1 - Integration stopped. INTEN is cleared at the end of the integration window, i.e. upon the inverse trigger event transition of the external trigger signal. - 0b0 - - - value2 - Integration enabled. INTEN is set upon the defined trigger event. - 0b1 - - - - - REPCNT - Integration Cycle Counter - 8 - 11 - read-only - - - REPVAL - Number of Integration Cycles - 12 - 15 - read-write - - - NVALDIS - Number of Values Discarded - 16 - 21 - read-write - - - IWS - Integration Window SIze - 23 - 23 - read-write - - - value1 - Internal control: stop integrator after REPVAL+1 integration cycles - 0b0 - - - value2 - External control: stop integrator when bit INTEN becomes 0 - 0b1 - - - - - NVALINT - Number of Values Integrated - 24 - 29 - read-write - - - - - BOUNDSEL - Boundary Select Register - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - BOUNDARYL - Lower Boundary Value for Limit Checking - 0 - 15 - read-write - - - BOUNDARYU - Upper Boundary Value for Limit Checking - 16 - 31 - read-write - - - - - RESM - Result Register, Main Filter - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-only - - - - - OFFM - Offset Register, Main Filter - 0x0038 - 32 - 0x00000000 - 0xFFFFFFFF - - - OFFSET - Offset Value - 0 - 15 - read-write - - - - - RESA - Result Register, Auxiliary Filter - 0x0040 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-only - - - - - TSTMP - Time-Stamp Register - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - Result of most recent conversion - 0 - 15 - read-only - - - CFMDCNT - CIC Filter (Main Chain) Decimation Counter - 16 - 23 - read-only - - - NVALCNT - Number of Values Counted - 24 - 29 - read-only - - - - - CGSYNC - Carrier Generator Synchronization Register - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SDCOUNT - Sign Delay Counter - 0 - 7 - read-only - - - SDCAP - Sign Delay Capture Value - 8 - 15 - read-only - - - SDPOS - Sign Delay Value for Positive Halfwave - 16 - 23 - read-write - - - SDNEG - Sign Delay Value for Negative Halfwave - 24 - 31 - read-write - - - - - RECTCFG - Rectification Configuration Register - 0x00A8 - 32 - 0x80000000 - 0xFFFFFFFF - - - RFEN - Rectification Enable - 0 - 0 - read-write - - - value1 - No rectification, data not altered - 0b0 - - - value2 - Data are rectified according to SGND - 0b1 - - - - - SSRC - Sign Source - 4 - 5 - read-write - - - value1 - On-chip carrier generator - 0b00 - - - value2 - Sign of result of next channel - 0b01 - - - value3 - External sign signal A - 0b10 - - - value4 - External sign signal B - 0b11 - - - - - SDVAL - Valid Flag - 15 - 15 - read-only - - - value1 - No new result available - 0b0 - - - value2 - Bitfield SDCAP has been updated with a new captured value and has not yet been read - 0b1 - - - - - SGNCS - Selected Carrier Sign Signal - 30 - 30 - read-only - - - value1 - Positive values - 0b0 - - - value2 - Negative values - 0b1 - - - - - SGND - Sign Signal Delayed - 31 - 31 - read-only - - - value1 - Positive values - 0b0 - - - value2 - Negative values - 0b1 - - - - - - - - - DSD_CH1 - Delta Sigma Demodulator - DSD - 0x40008200 - - 0x0 - 0x100 - registers - - - - DSD_CH2 - Delta Sigma Demodulator - DSD - 0x40008300 - - 0x0 - 0x100 - registers - - - - DSD_CH3 - Delta Sigma Demodulator - DSD - 0x40008400 - - 0x0 - 0x100 - registers - - - - DAC - Digital to Analog Converter - 0x48018000 - - 0x0 - 0x4000 - registers - - - - ID - Module Identification Register - 0x000 - 32 - 0x00A5C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - DAC0CFG0 - DAC0 Configuration Register 0 - 0x004 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQ - Integer Frequency Divider Value - 0 - 19 - read-write - - - MODE - Enables and Sets the Mode for DAC0 - 20 - 22 - read-write - - - value1 - disable/switch-off DAC - 0b000 - - - value2 - Single Value Mode - 0b001 - - - value3 - Data Mode - 0b010 - - - value4 - Patgen Mode - 0b011 - - - value5 - Noise Mode - 0b100 - - - value6 - Ramp Mode - 0b101 - - - value7 - na - 0b110 - - - value8 - na - 0b111 - - - - - SIGN - Selects Between Signed and Unsigned DAC0 Mode - 23 - 23 - read-write - - - value1 - DAC expects unsigned input data - 0b0 - - - value2 - DAC expects signed input data - 0b1 - - - - - FIFOIND - Current write position inside the data FIFO - 24 - 25 - read-only - - - FIFOEMP - Indicate if the FIFO is empty - 26 - 26 - read-only - - - value1 - FIFO not empty - 0b0 - - - value2 - FIFO empty - 0b1 - - - - - FIFOFUL - Indicate if the FIFO is full - 27 - 27 - read-only - - - value1 - FIFO not full - 0b0 - - - value2 - FIFO full - 0b1 - - - - - SIGNEN - Enable Sign Output of DAC0 Pattern Generator - 29 - 29 - read-write - - - value1 - Disable - 0b0 - - - value2 - Enable - 0b1 - - - - - SREN - Enable DAC0 service request interrupt generation - 30 - 30 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - RUN - RUN indicates the current DAC0 operation status - 31 - 31 - read-only - - - value1 - DAC0 channel disabled - 0b0 - - - value2 - DAC0 channel in operation - 0b1 - - - - - - - DAC0CFG1 - DAC0 Configuration Register 1 - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCALE - Scale value for up- or downscale of the DAC0 input data in steps by the power of 2 (=shift operation) - 0 - 2 - read-write - - - value1 - no shift = multiplication/division by 1 - 0b000 - - - value2 - shift by 1 = multiplication/division by 2 - 0b001 - - - value3 - shift by 2 = multiplication/division by 4 - 0b010 - - - value4 - shift left by 3 = multiplication/division by 8 - 0b011 - - - value5 - shift left by 4 = multiplication/division by 16 - 0b100 - - - value6 - shift left by 5 = multiplication/division by 32 - 0b101 - - - value7 - shift left by 6 = multiplication/division by 64 - 0b110 - - - value8 - shift left by 7 = multiplication/division by 128 - 0b111 - - - - - MULDIV - Switch between up- and downscale of the DAC0 input data values - 3 - 3 - read-write - - - value1 - downscale = division (shift SCALE positions to the right) - 0b0 - - - value2 - upscale = multiplication (shift SCALE positions to the left) - 0b1 - - - - - OFFS - 8-bit offset value addition - 4 - 11 - read-write - - - TRIGSEL - Selects one of the eight external trigger sources for DAC0 - 12 - 14 - read-write - - - DATMOD - Switch between independent or simultaneous DAC mode and select the input data register for DAC0 and DAC1 - 15 - 15 - read-write - - - value1 - independent data handling - process data from DATA0 register (bits 11:0) to DAC0 and data from DATA1 register (bits 11:0) to DAC1 - 0b0 - - - value2 - simultaneous data handling - process data from DAC01 register to both DACs (bits 11:0 to DAC0 and bits 23:12 to DAC1). - 0b1 - - - - - SWTRIG - Software Trigger - 16 - 16 - read-write - - - TRIGMOD - Select the trigger source for channel 0 - 17 - 18 - read-write - - - value1 - internal Trigger (integer divided clock - see FREQ parameter) - 0b00 - - - value2 - external Trigger (preselected trigger by TRIGSEL parameter) - 0b01 - - - value3 - software Trigger (see SWTRIG parameter) - 0b10 - - - value4 - reserved - 0b11 - - - - - ANACFG - DAC0 analog configuration/calibration parameters - 19 - 23 - read-write - - - ANAEN - Enable analog DAC for channel 0 - 24 - 24 - read-write - - - value1 - DAC0 is set to standby (analog output only) - 0b0 - - - value2 - enable DAC0 (analog output only) - 0b1 - - - - - REFCFGL - Lower 4 band-gap configuration/calibration parameters - 28 - 31 - read-write - - - - - DAC1CFG0 - DAC1 Configuration Register 0 - 0x00C - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQ - Integer Frequency Divider Value - 0 - 19 - read-write - - - MODE - Enables and sets the Mode for DAC1 - 20 - 22 - read-write - - - value1 - disable/switch-off DAC - 0b000 - - - value2 - Single Value Mode - 0b001 - - - value3 - Data Mode - 0b010 - - - value4 - Patgen Mode - 0b011 - - - value5 - Noise Mode - 0b100 - - - value6 - Ramp Mode - 0b101 - - - value7 - na - 0b110 - - - value8 - na - 0b111 - - - - - SIGN - Selects between signed and unsigned DAC1 mode - 23 - 23 - read-write - - - value1 - DAC expects unsigned input data - 0b0 - - - value2 - DAC expects signed input data - 0b1 - - - - - FIFOIND - Current write position inside the data FIFO - 24 - 25 - read-only - - - FIFOEMP - Indicate if the FIFO is empty - 26 - 26 - read-only - - - value1 - FIFO not empty - 0b0 - - - value2 - FIFO empty - 0b1 - - - - - FIFOFUL - Indicate if the FIFO is full - 27 - 27 - read-only - - - value1 - FIFO not full - 0b0 - - - value2 - FIFO full - 0b1 - - - - - SIGNEN - Enable sign output of DAC1 pattern generator - 29 - 29 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - SREN - Enable DAC1 service request interrupt generation - 30 - 30 - read-write - - - value1 - disable - 0b0 - - - value2 - enable - 0b1 - - - - - RUN - RUN indicates the current DAC1 operation status - 31 - 31 - read-only - - - value1 - DAC1 channel disabled - 0b0 - - - value2 - DAC1 channel in operation - 0b1 - - - - - - - DAC1CFG1 - DAC1 Configuration Register 1 - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCALE - Scale value for up- or downscale of the DAC1 input data in steps by the power of 2 (=shift operation) - 0 - 2 - read-write - - - value1 - no shift = multiplication/division by 1 - 0b000 - - - value2 - shift by 1 = multiplication/division by 2 - 0b001 - - - value3 - shift by 2 = multiplication/division by 4 - 0b010 - - - value4 - shift left by 3 = multiplication/division by 8 - 0b011 - - - value5 - shift left by 4 = multiplication/division by 16 - 0b100 - - - value6 - shift left by 5 = multiplication/division by 32 - 0b101 - - - value7 - shift left by 6 = multiplication/division by 64 - 0b110 - - - value8 - shift left by 7 = multiplication/division by 128 - 0b111 - - - - - MULDIV - Switch between up- and downscale of the DAC1 input data values - 3 - 3 - read-write - - - value1 - downscale = division (shift SCALE positions to the right) - 0b0 - - - value2 - upscale = multiplication (shift SCALE positions to the left) - 0b1 - - - - - OFFS - 8-bit offset value addition - 4 - 11 - read-write - - - TRIGSEL - Selects one of the eight external trigger sources for DAC1 - 12 - 14 - read-write - - - SWTRIG - Software Trigger - 16 - 16 - read-write - - - TRIGMOD - Select the trigger source for channel 1 - 17 - 18 - read-write - - - value1 - internal Trigger (integer divided clock - see FREQ parameter) - 0b00 - - - value2 - external Trigger (preselected trigger by TRIGSEL parameter) - 0b01 - - - value3 - software Trigger (see SWTRIG parameter) - 0b10 - - - value4 - reserved - 0b11 - - - - - ANACFG - DAC1 analog configuration/calibration parameters - 19 - 23 - read-write - - - ANAEN - Enable analog DAC for channel 1 - 24 - 24 - read-write - - - value1 - DAC1 is set to standby (analog output only) - 0b0 - - - value2 - enable DAC1 (analog output only) - 0b1 - - - - - REFCFGH - Higher 4 band-gap configuration/calibration parameters - 28 - 31 - read-write - - - - - DAC0DATA - DAC0 Data Register - 0x014 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA0 - DAC0 Data Bits - 0 - 11 - read-write - - - - - DAC1DATA - DAC1 Data Register - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA1 - DAC1 Data Bits - 0 - 11 - read-write - - - - - DAC01DATA - DAC01 Data Register - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA0 - DAC0 Data Bits - 0 - 11 - read-write - - - DATA1 - DAC1 Data Bits - 16 - 27 - read-write - - - - - DAC0PATL - DAC0 Lower Pattern Register - 0x020 - 32 - 0x3568B0C0 - 0xFFFFFFFF - - - PAT0 - Pattern Number 0 for PATGEN of DAC0 - 0 - 4 - read-write - - - PAT1 - Pattern Number 1 for PATGEN of DAC0 - 5 - 9 - read-write - - - PAT2 - Pattern Number 2 for PATGEN of DAC0 - 10 - 14 - read-write - - - PAT3 - Pattern Number 3 for PATGEN of DAC0 - 15 - 19 - read-write - - - PAT4 - Pattern Number 4 for PATGEN of DAC0 - 20 - 24 - read-write - - - PAT5 - Pattern Number 5 for PATGEN of DAC0 - 25 - 29 - read-write - - - - - DAC0PATH - DAC0 Higher Pattern Register - 0x024 - 32 - 0x00007FDD - 0xFFFFFFFF - - - PAT6 - Pattern Number 6 for PATGEN of DAC0 - 0 - 4 - read-write - - - PAT7 - Pattern Number 7 for PATGEN of DAC0 - 5 - 9 - read-write - - - PAT8 - Pattern Number 8 for PATGEN of DAC0 - 10 - 14 - read-write - - - - - DAC1PATL - DAC1 Lower Pattern Register - 0x028 - 32 - 0x3568B0C0 - 0xFFFFFFFF - - - PAT0 - Pattern Number 0 for PATGEN of DAC1 - 0 - 4 - read-write - - - PAT1 - Pattern Number 1 for PATGEN of DAC1 - 5 - 9 - read-write - - - PAT2 - Pattern Number 2 for PATGEN of DAC1 - 10 - 14 - read-write - - - PAT3 - Pattern Number 3 for PATGEN of DAC1 - 15 - 19 - read-write - - - PAT4 - Pattern Number 4 for PATGEN of DAC1 - 20 - 24 - read-write - - - PAT5 - Pattern Number 5 for PATGEN of DAC1 - 25 - 29 - read-write - - - - - DAC1PATH - DAC1 Higher Pattern Register - 0x02C - 32 - 0x00007FDD - 0xFFFFFFFF - - - PAT6 - Pattern Number 6 for PATGEN of DAC1 - 0 - 4 - read-write - - - PAT7 - Pattern Number 7 for PATGEN of DAC1 - 5 - 9 - read-write - - - PAT8 - Pattern Number 8 for PATGEN of DAC1 - 10 - 14 - read-write - - - - - - - CCU40 - Capture Compare Unit 4 - Unit 0 - CCU4 - CCU4 - 0x4000C000 - - 0x0 - 0x4000 - registers - - - - GCTRL - Global Control Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRBC - Prescaler Clear Configuration - 0 - 2 - read-write - - - value1 - SW only - 0b000 - - - value2 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared. - 0b001 - - - value3 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared. - 0b010 - - - value4 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared. - 0b011 - - - value5 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared. - 0b100 - - - - - PCIS - Prescaler Input Clock Selection - 4 - 5 - read-write - - - value1 - Module clock - 0b00 - - - value2 - CCU4x.ECLKA - 0b01 - - - value3 - CCU4x.ECLKB - 0b10 - - - value4 - CCU4x.ECLKC - 0b11 - - - - - SUSCFG - Suspend Mode Configuration - 8 - 9 - read-write - - - value1 - Suspend request ignored. The module never enters in suspend - 0b00 - - - value2 - Stops all the running slices immediately. Safe stop is not applied. - 0b01 - - - value3 - Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. - 0b10 - - - value4 - Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. - 0b11 - - - - - MSE0 - Slice 0 Multi Channel shadow transfer enable - 10 - 10 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSE1 - Slice 1 Multi Channel shadow transfer enable - 11 - 11 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSE2 - Slice 2 Multi Channel shadow transfer enable - 12 - 12 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSE3 - Slice 3 Multi Channel shadow transfer enable - 13 - 13 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU4x.MCSS input. - 0b1 - - - - - MSDE - Multi Channel shadow transfer request configuration - 14 - 15 - read-write - - - value1 - Only the shadow transfer for period and compare values is requested - 0b00 - - - value2 - Shadow transfer for the compare, period and prescaler compare values is requested - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Shadow transfer for the compare, period, prescaler and dither compare values is requested - 0b11 - - - - - - - GSTAT - Global Status Register - 0x0004 - 32 - 0x0000000F - 0xFFFFFFFF - - - S0I - CC40 IDLE status - 0 - 0 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S1I - CC41 IDLE status - 1 - 1 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S2I - CC42 IDLE status - 2 - 2 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S3I - CC43 IDLE status - 3 - 3 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - PRB - Prescaler Run Bit - 8 - 8 - read-only - - - value1 - Prescaler is stopped - 0b0 - - - value2 - Prescaler is running - 0b1 - - - - - - - GIDLS - Global Idle Set - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SS0I - CC40 IDLE mode set - 0 - 0 - write-only - - - SS1I - CC41 IDLE mode set - 1 - 1 - write-only - - - SS2I - CC42 IDLE mode set - 2 - 2 - write-only - - - SS3I - CC43 IDLE mode set - 3 - 3 - write-only - - - CPRB - Prescaler Run Bit Clear - 8 - 8 - write-only - - - PSIC - Prescaler clear - 9 - 9 - write-only - - - - - GIDLC - Global Idle Clear - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - CS0I - CC40 IDLE mode clear - 0 - 0 - write-only - - - CS1I - CC41 IDLE mode clear - 1 - 1 - write-only - - - CS2I - CC42 IDLE mode clear - 2 - 2 - write-only - - - CS3I - CC43 IDLE mode clear - 3 - 3 - write-only - - - SPRB - Prescaler Run Bit Set - 8 - 8 - write-only - - - - - GCSS - Global Channel Set - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SE - Slice 0 shadow transfer set enable - 0 - 0 - write-only - - - S0DSE - Slice 0 Dither shadow transfer set enable - 1 - 1 - write-only - - - S0PSE - Slice 0 Prescaler shadow transfer set enable - 2 - 2 - write-only - - - S1SE - Slice 1 shadow transfer set enable - 4 - 4 - write-only - - - S1DSE - Slice 1 Dither shadow transfer set enable - 5 - 5 - write-only - - - S1PSE - Slice 1 Prescaler shadow transfer set enable - 6 - 6 - write-only - - - S2SE - Slice 2 shadow transfer set enable - 8 - 8 - write-only - - - S2DSE - Slice 2 Dither shadow transfer set enable - 9 - 9 - write-only - - - S2PSE - Slice 2 Prescaler shadow transfer set enable - 10 - 10 - write-only - - - S3SE - Slice 3 shadow transfer set enable - 12 - 12 - write-only - - - S3DSE - Slice 3 Dither shadow transfer set enable - 13 - 13 - write-only - - - S3PSE - Slice 3 Prescaler shadow transfer set enable - 14 - 14 - write-only - - - S0STS - Slice 0 status bit set - 16 - 16 - write-only - - - S1STS - Slice 1 status bit set - 17 - 17 - write-only - - - S2STS - Slice 2 status bit set - 18 - 18 - write-only - - - S3STS - Slice 3 status bit set - 19 - 19 - write-only - - - - - GCSC - Global Channel Clear - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SC - Slice 0 shadow transfer clear - 0 - 0 - write-only - - - S0DSC - Slice 0 Dither shadow transfer clear - 1 - 1 - write-only - - - S0PSC - Slice 0 Prescaler shadow transfer clear - 2 - 2 - write-only - - - S1SC - Slice 1 shadow transfer clear - 4 - 4 - write-only - - - S1DSC - Slice 1 Dither shadow transfer clear - 5 - 5 - write-only - - - S1PSC - Slice 1 Prescaler shadow transfer clear - 6 - 6 - write-only - - - S2SC - Slice 2 shadow transfer clear - 8 - 8 - write-only - - - S2DSC - Slice 2 Dither shadow transfer clear - 9 - 9 - write-only - - - S2PSC - Slice 2 Prescaler shadow transfer clear - 10 - 10 - write-only - - - S3SC - Slice 3 shadow transfer clear - 12 - 12 - write-only - - - S3DSC - Slice 3 Dither shadow transfer clear - 13 - 13 - write-only - - - S3PSC - Slice 3 Prescaler shadow transfer clear - 14 - 14 - write-only - - - S0STC - Slice 0 status bit clear - 16 - 16 - write-only - - - S1STC - Slice 1 status bit clear - 17 - 17 - write-only - - - S2STC - Slice 2 status bit clear - 18 - 18 - write-only - - - S3STC - Slice 3 status bit clear - 19 - 19 - write-only - - - - - GCST - Global Channel Status - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SS - Slice 0 shadow transfer status - 0 - 0 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S0DSS - Slice 0 Dither shadow transfer status - 1 - 1 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S0PSS - Slice 0 Prescaler shadow transfer status - 2 - 2 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S1SS - Slice 1 shadow transfer status - 4 - 4 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S1DSS - Slice 1 Dither shadow transfer status - 5 - 5 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S1PSS - Slice 1 Prescaler shadow transfer status - 6 - 6 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S2SS - Slice 2 shadow transfer status - 8 - 8 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S2DSS - Slice 2 Dither shadow transfer status - 9 - 9 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S2PSS - Slice 2 Prescaler shadow transfer status - 10 - 10 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S3SS - Slice 3 shadow transfer status - 12 - 12 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S3DSS - Slice 3 Dither shadow transfer status - 13 - 13 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S3PSS - Slice 3 Prescaler shadow transfer status - 14 - 14 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - CC40ST - Slice 0 status bit - 16 - 16 - read-only - - - CC41ST - Slice 1 status bit - 17 - 17 - read-only - - - CC42ST - Slice 2 status bit - 18 - 18 - read-only - - - CC43ST - Slice 3 status bit - 19 - 19 - read-only - - - - - ECRD - Extended Capture Mode Read - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPV - Timer Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Capture value - 16 - 19 - read-only - - - SPTR - Slice pointer - 20 - 21 - read-only - - - value1 - CC40 - 0b00 - - - value2 - CC41 - 0b01 - - - value3 - CC42 - 0b10 - - - value4 - CC43 - 0b11 - - - - - VPTR - Capture register pointer - 22 - 23 - read-only - - - value1 - Capture register 0 - 0b00 - - - value2 - Capture register 1 - 0b01 - - - value3 - Capture register 2 - 0b10 - - - value4 - Capture register 3 - 0b11 - - - - - FFL - Full Flag - 24 - 24 - read-only - - - value1 - No new value was captured into this register - 0b0 - - - value2 - A new value has been captured into this register - 0b1 - - - - - - - MIDR - Module Identification - 0x0080 - 32 - 0x00A6C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - - - CCU41 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010000 - - 0x0 - 0x4000 - registers - - - - CCU42 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014000 - - 0x0 - 0x4000 - registers - - - - CCU43 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004000 - - 0x0 - 0x4000 - registers - - - - CCU40_CC40 - Capture Compare Unit 4 - Unit 0 - CCU4 - CCU4_CC4 - 0x4000C100 - - 0x0 - 0x100 - registers - - - - INS - Input Selector Configuration - 0x000 - 32 - 0x00000000 - 0xFFFFFFFF - - - EV0IS - Event 0 signal selection - 0 - 3 - read-write - - - value1 - CCU4x.INyA - 0b0000 - - - value2 - CCU4x.INyB - 0b0001 - - - value3 - CCU4x.INyC - 0b0010 - - - value4 - CCU4x.INyD - 0b0011 - - - value5 - CCU4x.INyE - 0b0100 - - - value6 - CCU4x.INyF - 0b0101 - - - value7 - CCU4x.INyG - 0b0110 - - - value8 - CCU4x.INyH - 0b0111 - - - value9 - CCU4x.INyI - 0b1000 - - - value10 - CCU4x.INyJ - 0b1001 - - - value11 - CCU4x.INyK - 0b1010 - - - value12 - CCU4x.INyL - 0b1011 - - - value13 - CCU4x.INyM - 0b1100 - - - value14 - CCU4x.INyN - 0b1101 - - - value15 - CCU4x.INyO - 0b1110 - - - value16 - CCU4x.INyP - 0b1111 - - - - - EV1IS - Event 1 signal selection - 4 - 7 - read-write - - - EV2IS - Event 2 signal selection - 8 - 11 - read-write - - - EV0EM - Event 0 Edge Selection - 16 - 17 - read-write - - - value1 - No action - 0b00 - - - value2 - Signal active on rising edge - 0b01 - - - value3 - Signal active on falling edge - 0b10 - - - value4 - Signal active on both edges - 0b11 - - - - - EV1EM - Event 1 Edge Selection - 18 - 19 - read-write - - - EV2EM - Event 2 Edge Selection - 20 - 21 - read-write - - - EV0LM - Event 0 Level Selection - 22 - 22 - read-write - - - value1 - Active on HIGH level - 0b0 - - - value2 - Active on LOW level - 0b1 - - - - - EV1LM - Event 1 Level Selection - 23 - 23 - read-write - - - EV2LM - Event 2 Level Selection - 24 - 24 - read-write - - - LPF0M - Event 0 Low Pass Filter Configuration - 25 - 26 - read-write - - - value1 - LPF is disabled - 0b00 - - - value2 - 3 clock cycles of fCCU4 - 0b01 - - - value3 - 5 clock cycles of fCCU4 - 0b10 - - - value4 - 7 clock cycles of fCCU4 - 0b11 - - - - - LPF1M - Event 1 Low Pass Filter Configuration - 27 - 28 - read-write - - - LPF2M - Event 2 Low Pass Filter Configuration - 29 - 30 - read-write - - - - - CMC - Connection Matrix Control - 0x004 - 32 - 0x00000000 - 0xFFFFFFFF - - - STRTS - External Start Functionality Selector - 0 - 1 - read-write - - - value1 - External Start Function deactivated - 0b00 - - - value2 - External Start Function triggered by Event 0 - 0b01 - - - value3 - External Start Function triggered by Event 1 - 0b10 - - - value4 - External Start Function triggered by Event 2 - 0b11 - - - - - ENDS - External Stop Functionality Selector - 2 - 3 - read-write - - - value1 - External Stop Function deactivated - 0b00 - - - value2 - External Stop Function triggered by Event 0 - 0b01 - - - value3 - External Stop Function triggered by Event 1 - 0b10 - - - value4 - External Stop Function triggered by Event 2 - 0b11 - - - - - CAP0S - External Capture 0 Functionality Selector - 4 - 5 - read-write - - - value1 - External Capture 0 Function deactivated - 0b00 - - - value2 - External Capture 0 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 0 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 0 Function triggered by Event 2 - 0b11 - - - - - CAP1S - External Capture 1 Functionality Selector - 6 - 7 - read-write - - - value1 - External Capture 1 Function deactivated - 0b00 - - - value2 - External Capture 1 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 1 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 1 Function triggered by Event 2 - 0b11 - - - - - GATES - External Gate Functionality Selector - 8 - 9 - read-write - - - value1 - External Gating Function deactivated - 0b00 - - - value2 - External Gating Function triggered by Event 0 - 0b01 - - - value3 - External Gating Function triggered by Event 1 - 0b10 - - - value4 - External Gating Function triggered by Event 2 - 0b11 - - - - - UDS - External Up/Down Functionality Selector - 10 - 11 - read-write - - - value1 - External Up/Down Function deactivated - 0b00 - - - value2 - External Up/Down Function triggered by Event 0 - 0b01 - - - value3 - External Up/Down Function triggered by Event 1 - 0b10 - - - value4 - External Up/Down Function triggered by Event 2 - 0b11 - - - - - LDS - External Timer Load Functionality Selector - 12 - 13 - read-write - - - CNTS - External Count Selector - 14 - 15 - read-write - - - value1 - External Count Function deactivated - 0b00 - - - value2 - External Count Function triggered by Event 0 - 0b01 - - - value3 - External Count Function triggered by Event 1 - 0b10 - - - value4 - External Count Function triggered by Event 2 - 0b11 - - - - - OFS - Override Function Selector - 16 - 16 - read-write - - - value1 - Override functionality disabled - 0b0 - - - value2 - Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 - 0b1 - - - - - TS - Trap Function Selector - 17 - 17 - read-write - - - value1 - Trap function disabled - 0b0 - - - value2 - TRAP function connected to Event 2 - 0b1 - - - - - MOS - External Modulation Functionality Selector - 18 - 19 - read-write - - - TCE - Timer Concatenation Enable - 20 - 20 - read-write - - - value1 - Timer concatenation is disabled - 0b0 - - - value2 - Timer concatenation is enabled - 0b1 - - - - - - - TCST - Slice Timer Status - 0x008 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRB - Timer Run Bit - 0 - 0 - read-only - - - value1 - Timer is stopped - 0b0 - - - value2 - Timer is running - 0b1 - - - - - CDIR - Timer Counting Direction - 1 - 1 - read-only - - - value1 - Timer is counting up - 0b0 - - - value2 - Timer is counting down - 0b1 - - - - - - - TCSET - Slice Timer Run Set - 0x00C - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBS - Timer Run Bit set - 0 - 0 - write-only - - - - - TCCLR - Slice Timer Clear - 0x010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBC - Timer Run Bit Clear - 0 - 0 - write-only - - - TCC - Timer Clear - 1 - 1 - write-only - - - DITC - Dither Counter Clear - 2 - 2 - write-only - - - - - TC - Slice Timer Control - 0x014 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCM - Timer Counting Mode - 0 - 0 - read-write - - - value1 - Edge aligned mode - 0b0 - - - value2 - Center aligned mode - 0b1 - - - - - TSSM - Timer Single Shot Mode - 1 - 1 - read-write - - - value1 - Single shot mode is disabled - 0b0 - - - value2 - Single shot mode is enabled - 0b1 - - - - - CLST - Shadow Transfer on Clear - 2 - 2 - read-write - - - CMOD - Capture Compare Mode - 3 - 3 - read-only - - - value1 - Compare Mode - 0b0 - - - value2 - Capture Mode - 0b1 - - - - - ECM - Extended Capture Mode - 4 - 4 - read-write - - - value1 - Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. - 0b0 - - - value2 - Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared. - 0b1 - - - - - CAPC - Clear on Capture Control - 5 - 6 - read-write - - - value1 - Timer is never cleared on a capture event - 0b00 - - - value2 - Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) - 0b01 - - - value3 - Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) - 0b10 - - - value4 - Timer is always cleared in a capture event. - 0b11 - - - - - ENDM - Extended Stop Function Control - 8 - 9 - read-write - - - value1 - Clears the timer run bit only (default stop) - 0b00 - - - value2 - Clears the timer only (flush) - 0b01 - - - value3 - Clears the timer and run bit (flush/stop) - 0b10 - - - value4 - Reserved - 0b11 - - - - - STRM - Extended Start Function Control - 10 - 10 - read-write - - - value1 - Sets run bit only (default start) - 0b0 - - - value2 - Clears the timer and sets run bit (flush/start) - 0b1 - - - - - SCE - Equal Capture Event enable - 11 - 11 - read-write - - - value1 - Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b0 - - - value2 - Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b1 - - - - - CCS - Continuous Capture Enable - 12 - 12 - read-write - - - value1 - The capture into a specific capture register is done with the rules linked with the full flags, described at . - 0b0 - - - value2 - The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). - 0b1 - - - - - DITHE - Dither Enable - 13 - 14 - read-write - - - value1 - Dither is disabled - 0b00 - - - value2 - Dither is applied to the Period - 0b01 - - - value3 - Dither is applied to the Compare - 0b10 - - - value4 - Dither is applied to the Period and Compare - 0b11 - - - - - DIM - Dither input selector - 15 - 15 - read-write - - - value1 - Slice is using its own dither unit - 0b0 - - - value2 - Slice is connected to the dither unit of slice 0. - 0b1 - - - - - FPE - Floating Prescaler enable - 16 - 16 - read-write - - - value1 - Floating prescaler mode is disabled - 0b0 - - - value2 - Floating prescaler mode is enabled - 0b1 - - - - - TRAPE - TRAP enable - 17 - 17 - read-write - - - value1 - TRAP functionality has no effect on the output - 0b0 - - - value2 - TRAP functionality affects the output - 0b1 - - - - - TRPSE - TRAP Synchronization Enable - 21 - 21 - read-write - - - value1 - Exiting from TRAP state isn't synchronized with the PWM signal - 0b0 - - - value2 - Exiting from TRAP state is synchronized with the PWM signal - 0b1 - - - - - TRPSW - TRAP State Clear Control - 22 - 22 - read-write - - - value1 - The slice exits the TRAP state automatically when the TRAP condition is not present - 0b0 - - - value2 - The TRAP state can only be exited by a SW request. - 0b1 - - - - - EMS - External Modulation Synchronization - 23 - 23 - read-write - - - value1 - External Modulation functionality is not synchronized with the PWM signal - 0b0 - - - value2 - External Modulation functionality is synchronized with the PWM signal - 0b1 - - - - - EMT - External Modulation Type - 24 - 24 - read-write - - - value1 - External Modulation functionality is clearing the CC4yST bit. - 0b0 - - - value2 - External Modulation functionality is gating the outputs. - 0b1 - - - - - MCME - Multi Channel Mode Enable - 25 - 25 - read-write - - - value1 - Multi Channel Mode is disabled - 0b0 - - - value2 - Multi Channel Mode is enabled - 0b1 - - - - - - - PSL - Passive Level Config - 0x018 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSL - Output Passive Level - 0 - 0 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - - - DIT - Dither Config - 0x01C - 32 - 0x00000000 - 0xFFFFFFFF - - - DCV - Dither compare Value - 0 - 3 - read-only - - - DCNT - Dither counter actual value - 8 - 11 - read-only - - - - - DITS - Dither Shadow Register - 0x020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCVS - Dither Shadow Compare Value - 0 - 3 - read-write - - - - - PSC - Prescaler Control - 0x024 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSIV - Prescaler Initial Value - 0 - 3 - read-write - - - - - FPC - Floating Prescaler Control - 0x028 - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Compare Value - 0 - 3 - read-only - - - PVAL - Actual Prescaler Value - 8 - 11 - read-write - - - - - FPCS - Floating Prescaler Shadow - 0x02C - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Shadow Compare Value - 0 - 3 - read-write - - - - - PR - Timer Period Value - 0x030 - 32 - 0x00000000 - 0xFFFFFFFF - - - PR - Period Register - 0 - 15 - read-only - - - - - PRS - Timer Shadow Period Value - 0x034 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRS - Period Register - 0 - 15 - read-write - - - - - CR - Timer Compare Value - 0x038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR - Compare Register - 0 - 15 - read-only - - - - - CRS - Timer Shadow Compare Value - 0x03C - 32 - 0x00000000 - 0xFFFFFFFF - - - CRS - Compare Register - 0 - 15 - read-write - - - - - TIMER - Timer Value - 0x070 - 32 - 0x00000000 - 0xFFFFFFFF - - - TVAL - Timer Value - 0 - 15 - read-write - - - - - C0V - Capture Register 0 - 0x074 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C1V - Capture Register 1 - 0x078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C2V - Capture Register 2 - 0x07C - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C3V - Capture Register 3 - 0x080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - INTS - Interrupt Status - 0x0A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PMUS - Period Match while Counting Up - 0 - 0 - read-only - - - value1 - Period match while counting up not detected - 0b0 - - - value2 - Period match while counting up detected - 0b1 - - - - - OMDS - One Match while Counting Down - 1 - 1 - read-only - - - value1 - One match while counting down not detected - 0b0 - - - value2 - One match while counting down detected - 0b1 - - - - - CMUS - Compare Match while Counting Up - 2 - 2 - read-only - - - value1 - Compare match while counting up not detected - 0b0 - - - value2 - Compare match while counting up detected - 0b1 - - - - - CMDS - Compare Match while Counting Down - 3 - 3 - read-only - - - value1 - Compare match while counting down not detected - 0b0 - - - value2 - Compare match while counting down detected - 0b1 - - - - - E0AS - Event 0 Detection Status - 8 - 8 - read-only - - - value1 - Event 0 not detected - 0b0 - - - value2 - Event 0 detected - 0b1 - - - - - E1AS - Event 1 Detection Status - 9 - 9 - read-only - - - value1 - Event 1 not detected - 0b0 - - - value2 - Event 1 detected - 0b1 - - - - - E2AS - Event 2 Detection Status - 10 - 10 - read-only - - - value1 - Event 2 not detected - 0b0 - - - value2 - Event 2 detected - 0b1 - - - - - TRPF - Trap Flag Status - 11 - 11 - read-only - - - - - INTE - Interrupt Enable Control - 0x0A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - PME - Period match while counting up enable - 0 - 0 - read-write - - - value1 - Period Match interrupt is disabled - 0b0 - - - value2 - Period Match interrupt is enabled - 0b1 - - - - - OME - One match while counting down enable - 1 - 1 - read-write - - - value1 - One Match interrupt is disabled - 0b0 - - - value2 - One Match interrupt is enabled - 0b1 - - - - - CMUE - Compare match while counting up enable - 2 - 2 - read-write - - - value1 - Compare Match while counting up interrupt is disabled - 0b0 - - - value2 - Compare Match while counting up interrupt is enabled - 0b1 - - - - - CMDE - Compare match while counting down enable - 3 - 3 - read-write - - - value1 - Compare Match while counting down interrupt is disabled - 0b0 - - - value2 - Compare Match while counting down interrupt is enabled - 0b1 - - - - - E0AE - Event 0 interrupt enable - 8 - 8 - read-write - - - value1 - Event 0 detection interrupt is disabled - 0b0 - - - value2 - Event 0 detection interrupt is enabled - 0b1 - - - - - E1AE - Event 1 interrupt enable - 9 - 9 - read-write - - - value1 - Event 1 detection interrupt is disabled - 0b0 - - - value2 - Event 1 detection interrupt is enabled - 0b1 - - - - - E2AE - Event 2 interrupt enable - 10 - 10 - read-write - - - value1 - Event 2 detection interrupt is disabled - 0b0 - - - value2 - Event 2 detection interrupt is enabled - 0b1 - - - - - - - SRS - Service Request Selector - 0x0A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSR - Period/One match Service request selector - 0 - 1 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - CMSR - Compare match Service request selector - 2 - 3 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - E0SR - Event 0 Service request selector - 8 - 9 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - E1SR - Event 1 Service request selector - 10 - 11 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - E2SR - Event 2 Service request selector - 12 - 13 - read-write - - - value1 - Forward to CC4ySR0 - 0b00 - - - value2 - Forward to CC4ySR1 - 0b01 - - - value3 - Forward to CC4ySR2 - 0b10 - - - value4 - Forward to CC4ySR3 - 0b11 - - - - - - - SWS - Interrupt Status Set - 0x0AC - 32 - 0x00000000 - 0xFFFFFFFF - - - SPM - Period match while counting up set - 0 - 0 - write-only - - - SOM - One match while counting down set - 1 - 1 - write-only - - - SCMU - Compare match while counting up set - 2 - 2 - write-only - - - SCMD - Compare match while counting down set - 3 - 3 - write-only - - - SE0A - Event 0 detection set - 8 - 8 - write-only - - - SE1A - Event 1 detection set - 9 - 9 - write-only - - - SE2A - Event 2 detection set - 10 - 10 - write-only - - - STRPF - Trap Flag status set - 11 - 11 - write-only - - - - - SWR - Interrupt Status Clear - 0x0B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPM - Period match while counting up clear - 0 - 0 - write-only - - - ROM - One match while counting down clear - 1 - 1 - write-only - - - RCMU - Compare match while counting up clear - 2 - 2 - write-only - - - RCMD - Compare match while counting down clear - 3 - 3 - write-only - - - RE0A - Event 0 detection clear - 8 - 8 - write-only - - - RE1A - Event 1 detection clear - 9 - 9 - write-only - - - RE2A - Event 2 detection clear - 10 - 10 - write-only - - - RTRPF - Trap Flag status clear - 11 - 11 - write-only - - - - - - - CCU40_CC41 - Capture Compare Unit 4 - Unit 0 - CCU4 - 0x4000C200 - - 0x0 - 0x100 - registers - - - - CCU40_CC42 - Capture Compare Unit 4 - Unit 0 - CCU4 - 0x4000C300 - - 0x0 - 0x100 - registers - - - - CCU40_CC43 - Capture Compare Unit 4 - Unit 0 - CCU4 - 0x4000C400 - - 0x0 - 0x100 - registers - - - - CCU41_CC40 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010100 - - 0x0 - 0x100 - registers - - - - CCU41_CC41 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010200 - - 0x0 - 0x100 - registers - - - - CCU41_CC42 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010300 - - 0x0 - 0x100 - registers - - - - CCU41_CC43 - Capture Compare Unit 4 - Unit 1 - CCU4 - 0x40010400 - - 0x0 - 0x100 - registers - - - - CCU42_CC40 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014100 - - 0x0 - 0x100 - registers - - - - CCU42_CC41 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014200 - - 0x0 - 0x100 - registers - - - - CCU42_CC42 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014300 - - 0x0 - 0x100 - registers - - - - CCU42_CC43 - Capture Compare Unit 4 - Unit 2 - CCU4 - 0x40014400 - - 0x0 - 0x100 - registers - - - - CCU43_CC40 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004100 - - 0x0 - 0x100 - registers - - - - CCU43_CC41 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004200 - - 0x0 - 0x100 - registers - - - - CCU43_CC42 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004300 - - 0x0 - 0x100 - registers - - - - CCU43_CC43 - Capture Compare Unit 4 - Unit 3 - CCU4 - 0x48004400 - - 0x0 - 0x100 - registers - - - - CCU80 - Capture Compare Unit 8 - Unit 0 - CCU8 - CCU8 - 0x40020000 - - 0x0 - 0x4000 - registers - - - - GCTRL - Global Control Register - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRBC - Prescaler Clear Configuration - 0 - 2 - read-write - - - value1 - SW only - 0b000 - - - value2 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC80 is cleared. - 0b001 - - - value3 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC81 is cleared. - 0b010 - - - value4 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC82 is cleared. - 0b011 - - - value5 - GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC83 is cleared. - 0b100 - - - - - PCIS - Prescaler Input Clock Selection - 4 - 5 - read-write - - - value1 - Module clock - 0b00 - - - value2 - CCU8x.ECLKA - 0b01 - - - value3 - CCU8x.ECLKB - 0b10 - - - value4 - CCU8x.ECLKC - 0b11 - - - - - SUSCFG - Suspend Mode Configuration - 8 - 9 - read-write - - - value1 - Suspend request ignored. The module never enters in suspend - 0b00 - - - value2 - Stops all the running slices immediately. Safe stop is not applied. - 0b01 - - - value3 - Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. - 0b10 - - - value4 - Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. - 0b11 - - - - - MSE0 - Slice 0 Multi Channel shadow transfer enable - 10 - 10 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8x.MCSS input. - 0b1 - - - - - MSE1 - Slice 1 Multi Channel shadow transfer enable - 11 - 11 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8x.MCSS input. - 0b1 - - - - - MSE2 - Slice 2 Multi Channel shadow transfer enable - 12 - 12 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8xMCSS input. - 0b1 - - - - - MSE3 - Slice 3 Multi Channel shadow transfer enable - 13 - 13 - read-write - - - value1 - Shadow transfer can only be requested by SW - 0b0 - - - value2 - Shadow transfer can be requested via SW and via the CCU8x.MCSS input. - 0b1 - - - - - MSDE - Multi Channel shadow transfer request configuration - 14 - 15 - read-write - - - value1 - Only the shadow transfer for period and compare values is requested - 0b00 - - - value2 - Shadow transfer for the compare, period and prescaler compare values is requested - 0b01 - - - value3 - Reserved - 0b10 - - - value4 - Shadow transfer for the compare, period, prescaler and dither compare values is requested - 0b11 - - - - - - - GSTAT - Global Status Register - 0x0004 - 32 - 0x0000000F - 0xFFFFFFFF - - - S0I - CC80 IDLE status - 0 - 0 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S1I - CC81 IDLE status - 1 - 1 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S2I - CC82 IDLE status - 2 - 2 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - S3I - CC83 IDLE status - 3 - 3 - read-only - - - value1 - Running - 0b0 - - - value2 - Idle - 0b1 - - - - - PRB - Prescaler Run Bit - 8 - 8 - read-only - - - value1 - Prescaler is stopped - 0b0 - - - value2 - Prescaler is running - 0b1 - - - - - PCRB - Parity Checker Run Bit - 10 - 10 - read-only - - - value1 - Parity Checker is stopped - 0b0 - - - value2 - Parity Checker is running - 0b1 - - - - - - - GIDLS - Global Idle Set - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SS0I - CC80 IDLE mode set - 0 - 0 - write-only - - - SS1I - CC81 IDLE mode set - 1 - 1 - write-only - - - SS2I - CC82 IDLE mode set - 2 - 2 - write-only - - - SS3I - CC83 IDLE mode set - 3 - 3 - write-only - - - CPRB - Prescaler# Run Bit Clear - 8 - 8 - write-only - - - PSIC - Prescaler clear - 9 - 9 - write-only - - - CPCH - Parity Checker Run bit clear - 10 - 10 - write-only - - - - - GIDLC - Global Idle Clear - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - CS0I - CC80 IDLE mode clear - 0 - 0 - write-only - - - CS1I - CC81 IDLE mode clear - 1 - 1 - write-only - - - CS2I - CC82 IDLE mode clear - 2 - 2 - write-only - - - CS3I - CC83 IDLE mode clear - 3 - 3 - write-only - - - SPRB - Prescaler Run Bit Set - 8 - 8 - write-only - - - SPCH - Parity Checker run bit set - 10 - 10 - write-only - - - - - GCSS - Global Channel Set - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SE - Slice 0 shadow transfer set enable - 0 - 0 - write-only - - - S0DSE - Slice 0 Dither shadow transfer set enable - 1 - 1 - write-only - - - S0PSE - Slice 0 Prescaler shadow transfer set enable - 2 - 2 - write-only - - - S1SE - Slice 1 shadow transfer set enable - 4 - 4 - write-only - - - S1DSE - Slice 1 Dither shadow transfer set enable - 5 - 5 - write-only - - - S1PSE - Slice 1 Prescaler shadow transfer set enable - 6 - 6 - write-only - - - S2SE - Slice 2 shadow transfer set enable - 8 - 8 - write-only - - - S2DSE - Slice 2 Dither shadow transfer set enable - 9 - 9 - write-only - - - S2PSE - Slice 2 Prescaler shadow transfer set enable - 10 - 10 - write-only - - - S3SE - Slice 3 shadow transfer set enable - 12 - 12 - write-only - - - S3DSE - Slice 3 Dither shadow transfer set enable - 13 - 13 - write-only - - - S3PSE - Slice 3 Prescaler shadow transfer set enable - 14 - 14 - write-only - - - S0ST1S - Slice 0 status bit 1 set - 16 - 16 - write-only - - - S1ST1S - Slice 1 status bit 1 set - 17 - 17 - write-only - - - S2ST1S - Slice 2 status bit 1 set - 18 - 18 - write-only - - - S3ST1S - Slice 3 status bit 1 set - 19 - 19 - write-only - - - S0ST2S - Slice 0 status bit 2 set - 20 - 20 - write-only - - - S1ST2S - Slice 1 status bit 2 set - 21 - 21 - write-only - - - S2ST2S - Slice 2 status bit 2 set - 22 - 22 - write-only - - - S3ST2S - Slice 3 status bit 2 set - 23 - 23 - write-only - - - - - GCSC - Global Channel Clear - 0x0014 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SC - Slice 0 shadow transfer request clear - 0 - 0 - write-only - - - S0DSC - Slice 0 Dither shadow transfer clear - 1 - 1 - write-only - - - S0PSC - Slice 0 Prescaler shadow transfer clear - 2 - 2 - write-only - - - S1SC - Slice 1 shadow transfer clear - 4 - 4 - write-only - - - S1DSC - Slice 1 Dither shadow transfer clear - 5 - 5 - write-only - - - S1PSC - Slice 1 Prescaler shadow transfer clear - 6 - 6 - write-only - - - S2SC - Slice 2 shadow transfer clear - 8 - 8 - write-only - - - S2DSC - Slice 2 Dither shadow transfer clear - 9 - 9 - write-only - - - S2PSC - Slice 2 Prescaler shadow transfer clear - 10 - 10 - write-only - - - S3SC - Slice 3 shadow transfer clear - 12 - 12 - write-only - - - S3DSC - Slice 3 Dither shadow transfer clear - 13 - 13 - write-only - - - S3PSC - Slice 3 Prescaler shadow transfer clear - 14 - 14 - write-only - - - S0ST1C - Slice 0 status bit 1 clear - 16 - 16 - write-only - - - S1ST1C - Slice 1 status bit 1 clear - 17 - 17 - write-only - - - S2ST1C - Slice 2 status bit 1 clear - 18 - 18 - write-only - - - S3ST1C - Slice 3 status bit 1 clear - 19 - 19 - write-only - - - S0ST2C - Slice 0 status bit 2 clear - 20 - 20 - write-only - - - S1ST2C - Slice 1 status bit 2 clear - 21 - 21 - write-only - - - S2ST2C - Slice 2 status bit 2 clear - 22 - 22 - write-only - - - S3ST2C - Slice 3 status bit 2 clear - 23 - 23 - write-only - - - - - GCST - Global Channel status - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - S0SS - Slice 0 shadow transfer status - 0 - 0 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S0DSS - Slice 0 Dither shadow transfer status - 1 - 1 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S0PSS - Slice 0 Prescaler shadow transfer status - 2 - 2 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S1SS - Slice 1 shadow transfer status - 4 - 4 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S1DSS - Slice 1 Dither shadow transfer status - 5 - 5 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S1PSS - Slice 1 Prescaler shadow transfer status - 6 - 6 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S2SS - Slice 2 shadow transfer status - 8 - 8 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S2DSS - Slice 2 Dither shadow transfer status - 9 - 9 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S2PSS - Slice 2 Prescaler shadow transfer status - 10 - 10 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - S3SS - Slice 3 shadow transfer status - 12 - 12 - read-only - - - value1 - Shadow transfer has not been requested - 0b0 - - - value2 - Shadow transfer has been requested - 0b1 - - - - - S3DSS - Slice 3 Dither shadow transfer status - 13 - 13 - read-only - - - value1 - Dither shadow transfer has not been requested - 0b0 - - - value2 - Dither shadow transfer has been requested - 0b1 - - - - - S3PSS - Slice 3 Prescaler shadow transfer status - 14 - 14 - read-only - - - value1 - Prescaler shadow transfer has not been requested - 0b0 - - - value2 - Prescaler shadow transfer has been requested - 0b1 - - - - - CC80ST1 - Slice 0 compare channel 1 status bit - 16 - 16 - read-only - - - CC81ST1 - Slice 1 compare channel 1 status bit - 17 - 17 - read-only - - - CC82ST1 - Slice 2 compare channel 1 status bit - 18 - 18 - read-only - - - CC83ST1 - Slice 3 compare channel 1 status bit - 19 - 19 - read-only - - - CC80ST2 - Slice 0 compare channel 2 status bit - 20 - 20 - read-only - - - CC81ST2 - Slice 1 compare channel 2 status bit - 21 - 21 - read-only - - - CC82ST2 - Slice 2 compare channel 2 status bit - 22 - 22 - read-only - - - CC83ST2 - Slice 3 compare channel 2 status bit - 23 - 23 - read-only - - - - - GPCHK - Parity Checker Configuration - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - PASE - Parity Checker Automatic start/stop - 0 - 0 - read-write - - - PACS - Parity Checker Automatic start/stop selector - 1 - 2 - read-write - - - value1 - CC80 - 0b00 - - - value2 - CC81 - 0b01 - - - value3 - CC82 - 0b10 - - - value4 - CC83 - 0b11 - - - - - PISEL - Driver Input signal selector - 3 - 4 - read-write - - - value1 - CC8x.GP01 - driver output is connected to event 1 of slice 0 - 0b00 - - - value2 - CC8x.GP11 - drive output is connected to event 1 of slice 1 - 0b01 - - - value3 - CC8x.GP21 - driver output is connected to event 1 of slice 2 - 0b10 - - - value4 - CC8x.GP31 - driver output is connected to event 1 of slice 3 - 0b11 - - - - - PCDS - Parity Checker Delay Input Selector - 5 - 6 - read-write - - - value1 - CCU8x.IGBTA - 0b00 - - - value2 - CCU8x.IGBTB - 0b01 - - - value3 - CCU8x.IGBTC - 0b10 - - - value4 - CCU8x.IGBTD - 0b11 - - - - - PCTS - Parity Checker type selector - 7 - 7 - read-write - - - value1 - Even parity enabled - 0b0 - - - value2 - Odd parity enabled - 0b1 - - - - - PCST - Parity Checker XOR status - 15 - 15 - read-only - - - PCSEL0 - Parity Checker Slice 0 output selection - 16 - 19 - read-write - - - PCSEL1 - Parity Checker Slice 1 output selection - 20 - 23 - read-write - - - PCSEL2 - Parity Checker Slice 2 output selection - 24 - 27 - read-write - - - PCSEL3 - Parity Checker Slice 3 output selection - 28 - 31 - read-write - - - - - ECRD - Extended Capture Mode Read - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPV - Timer Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Capture value - 16 - 19 - read-only - - - SPTR - Slice pointer - 20 - 21 - read-only - - - value1 - CC80 - 0b00 - - - value2 - CC81 - 0b01 - - - value3 - CC82 - 0b10 - - - value4 - CC83 - 0b11 - - - - - VPTR - Capture register pointer - 22 - 23 - read-only - - - value1 - Capture register 0 - 0b00 - - - value2 - Capture register 1 - 0b01 - - - value3 - Capture register 2 - 0b10 - - - value4 - Capture register 3 - 0b11 - - - - - FFL - Full Flag - 24 - 24 - read-only - - - value1 - No new value was captured into this register - 0b0 - - - value2 - A new value has been captured into this register - 0b1 - - - - - - - MIDR - Module Identification - 0x0080 - 32 - 0x00A7C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - - - CCU81 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024000 - - 0x0 - 0x4000 - registers - - - - CCU80_CC80 - Capture Compare Unit 8 - Unit 0 - CCU8 - CCU8_CC8 - 0x40020100 - - 0x0 - 0x100 - registers - - - - INS - Input Selector Configuration - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - EV0IS - Event 0 signal selection - 0 - 3 - read-write - - - value1 - CCU8x.INyA - 0b0000 - - - value2 - CCU8x.INyB - 0b0001 - - - value3 - CCU8x.INyC - 0b0010 - - - value4 - CCU8x.INyD - 0b0011 - - - value5 - CCU8x.INyE - 0b0100 - - - value6 - CCU8x.INyF - 0b0101 - - - value7 - CCU8x.INyG - 0b0110 - - - value8 - CCU8x.INyH - 0b0111 - - - value9 - CCU8x.INyI - 0b1000 - - - value10 - CCU8x.INyJ - 0b1001 - - - value11 - CCU8x.INyK - 0b1010 - - - value12 - CCU8x.INyL - 0b1011 - - - value13 - CCU8x.INyM - 0b1100 - - - value14 - CCU8x.INyN - 0b1101 - - - value15 - CCU8x.INyO - 0b1110 - - - value16 - CCU8x.INyP - 0b1111 - - - - - EV1IS - Event 1 signal selection - 4 - 7 - read-write - - - EV2IS - Event 2 signal selection - 8 - 11 - read-write - - - EV0EM - Event 0 Edge Selection - 16 - 17 - read-write - - - value1 - No action - 0b00 - - - value2 - Signal active on rising edge - 0b01 - - - value3 - Signal active on falling edge - 0b10 - - - value4 - Signal active on both edges - 0b11 - - - - - EV1EM - Event 1 Edge Selection - 18 - 19 - read-write - - - EV2EM - Event 2 Edge Selection - 20 - 21 - read-write - - - EV0LM - Event 0 Level Selection - 22 - 22 - read-write - - - value1 - Active on HIGH level - 0b0 - - - value2 - Active on LOW level - 0b1 - - - - - EV1LM - Event 1 Level Selection - 23 - 23 - read-write - - - EV2LM - Event 2 Level Selection - 24 - 24 - read-write - - - LPF0M - Event 0 Low Pass Filter Configuration - 25 - 26 - read-write - - - value1 - LPF is disabled - 0b00 - - - value2 - 3 clock cycles of fCCU8 - 0b01 - - - value3 - 5 clock cycles of fCCU8 - 0b10 - - - value4 - 7 clock cycles of fCCU8 - 0b11 - - - - - LPF1M - Event 1 Low Pass Filter Configuration - 27 - 28 - read-write - - - LPF2M - Event 2 Low Pass Filter Configuration - 29 - 30 - read-write - - - - - CMC - Connection Matrix Control - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - STRTS - External Start Functionality Selector - 0 - 1 - read-write - - - value1 - External Start Function deactivated - 0b00 - - - value2 - External Start Function triggered by Event 0 - 0b01 - - - value3 - External Start Function triggered by Event 1 - 0b10 - - - value4 - External Start Function triggered by Event 2 - 0b11 - - - - - ENDS - External Stop Functionality Selector - 2 - 3 - read-write - - - value1 - External Stop Function deactivated - 0b00 - - - value2 - External Stop Function triggered by Event 0 - 0b01 - - - value3 - External Stop Function triggered by Event 1 - 0b10 - - - value4 - External Stop Function triggered by Event 2 - 0b11 - - - - - CAP0S - External Capture 0 Functionality Selector - 4 - 5 - read-write - - - value1 - External Capture 0 Function deactivated - 0b00 - - - value2 - External Capture 0 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 0 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 0 Function triggered by Event 2 - 0b11 - - - - - CAP1S - External Capture 1 Functionality Selector - 6 - 7 - read-write - - - value1 - External Capture 1 Function deactivated - 0b00 - - - value2 - External Capture 1 Function triggered by Event 0 - 0b01 - - - value3 - External Capture 1 Function triggered by Event 1 - 0b10 - - - value4 - External Capture 1 Function triggered by Event 2 - 0b11 - - - - - GATES - External Gate Functionality Selector - 8 - 9 - read-write - - - value1 - External Gating Function deactivated - 0b00 - - - value2 - External Gating Function triggered by Event 0 - 0b01 - - - value3 - External Gating Function triggered by Event 1 - 0b10 - - - value4 - External Gating Function triggered by Event 2 - 0b11 - - - - - UDS - External Up/Down Functionality Selector - 10 - 11 - read-write - - - value1 - External Up/Down Function deactivated - 0b00 - - - value2 - External Up/Down Function triggered by Event 0 - 0b01 - - - value3 - External Up/Down Function triggered by Event 1 - 0b10 - - - value4 - External Up/Down Function triggered by Event 2 - 0b11 - - - - - LDS - External Timer Load Functionality Selector - 12 - 13 - read-write - - - CNTS - External Count Selector - 14 - 15 - read-write - - - value1 - External Count Function deactivated - 0b00 - - - value2 - External Count Function triggered by Event 0 - 0b01 - - - value3 - External Count Function triggered by Event 1 - 0b10 - - - value4 - External Count Function triggered by Event 2 - 0b11 - - - - - OFS - Override Function Selector - 16 - 16 - read-write - - - value1 - Override functionality disabled - 0b0 - - - value2 - Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 - 0b1 - - - - - TS - Trap Function Selector - 17 - 17 - read-write - - - value1 - Trap function disabled - 0b0 - - - value2 - TRAP function connected to Event 2 - 0b1 - - - - - MOS - External Modulation Functionality Selector - 18 - 19 - read-write - - - TCE - Timer Concatenation Enable - 20 - 20 - read-write - - - value1 - Timer concatenation is disabled - 0b0 - - - value2 - Timer concatenation is enabled - 0b1 - - - - - - - TCST - Slice Timer Status - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRB - Timer Run Bit - 0 - 0 - read-only - - - value1 - Timer is stopped - 0b0 - - - value2 - Timer is running - 0b1 - - - - - CDIR - Timer Counting Direction - 1 - 1 - read-only - - - value1 - Timer is counting up - 0b0 - - - value2 - Timer is counting down - 0b1 - - - - - DTR1 - Dead Time Counter 1 Run bit - 3 - 3 - read-only - - - value1 - Dead Time counter is idle - 0b0 - - - value2 - Dead Time counter is running - 0b1 - - - - - DTR2 - Dead Time Counter 2 Run bit - 4 - 4 - read-only - - - value1 - Dead Time counter is idle - 0b0 - - - value2 - Dead Time counter is running - 0b1 - - - - - - - TCSET - Slice Timer Run Set - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBS - Timer Run Bit set - 0 - 0 - write-only - - - - - TCCLR - Slice Timer Clear - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRBC - Timer Run Bit Clear - 0 - 0 - write-only - - - TCC - Timer Clear - 1 - 1 - write-only - - - DITC - Dither Counter Clear - 2 - 2 - write-only - - - DTC1C - Dead Time Counter 1 Clear - 3 - 3 - write-only - - - DTC2C - Dead Time Counter 2 Clear - 4 - 4 - write-only - - - - - TC - Slice Timer Control - 0x0014 - 32 - 0x18000000 - 0xFFFFFFFF - - - TCM - Timer Counting Mode - 0 - 0 - read-write - - - value1 - Edge aligned mode - 0b0 - - - value2 - Center aligned mode - 0b1 - - - - - TSSM - Timer Single Shot Mode - 1 - 1 - read-write - - - value1 - Single shot mode is disabled - 0b0 - - - value2 - Single shot mode is enabled - 0b1 - - - - - CLST - Shadow Transfer on Clear - 2 - 2 - read-write - - - CMOD - Capture Compare Mode - 3 - 3 - read-only - - - value1 - Compare Mode - 0b0 - - - value2 - Capture Mode - 0b1 - - - - - ECM - Extended Capture Mode - 4 - 4 - read-write - - - value1 - Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. - 0b0 - - - value2 - Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared - 0b1 - - - - - CAPC - Clear on Capture Control - 5 - 6 - read-write - - - value1 - Timer is never cleared on a capture event - 0b00 - - - value2 - Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) - 0b01 - - - value3 - Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) - 0b10 - - - value4 - Timer is always cleared in a capture event. - 0b11 - - - - - TLS - Timer Load selector - 7 - 7 - read-write - - - value1 - Timer is loaded with the value of CR1 - 0b0 - - - value2 - Timer is loaded with the value of CR2 - 0b1 - - - - - ENDM - Extended Stop Function Control - 8 - 9 - read-write - - - value1 - Clears the timer run bit only (default stop) - 0b00 - - - value2 - Clears the timer only (flush) - 0b01 - - - value3 - Clears the timer and run bit (flush/stop) - 0b10 - - - value4 - Reserved - 0b11 - - - - - STRM - Extended Start Function Control - 10 - 10 - read-write - - - value1 - Sets run bit only (default start) - 0b0 - - - value2 - Clears the timer and sets run bit, if not set (flush/start) - 0b1 - - - - - SCE - Equal Capture Event enable - 11 - 11 - read-write - - - value1 - Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b0 - - - value2 - Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 - 0b1 - - - - - CCS - Continuous Capture Enable - 12 - 12 - read-write - - - value1 - The capture into a specific capture register is done with the rules linked with the full flags, described at . - 0b0 - - - value2 - The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). - 0b1 - - - - - DITHE - Dither Enable - 13 - 14 - read-write - - - value1 - Dither is disabled - 0b00 - - - value2 - Dither is applied to the Period - 0b01 - - - value3 - Dither is applied to the Compare - 0b10 - - - value4 - Dither is applied to the Period and Compare - 0b11 - - - - - DIM - Dither input selector - 15 - 15 - read-write - - - value1 - Slice is using it own dither unit - 0b0 - - - value2 - Slice is connected to the dither unit of slice 0. - 0b1 - - - - - FPE - Floating Prescaler enable - 16 - 16 - read-write - - - value1 - Floating prescaler mode is disabled - 0b0 - - - value2 - Floating prescaler mode is enabled - 0b1 - - - - - TRAPE0 - TRAP enable for CCU8x.OUTy0 - 17 - 17 - read-write - - - value1 - TRAP functionality has no effect on the CCU8x.OUTy0 output - 0b0 - - - value2 - TRAP functionality affects the CCU8x.OUTy0 output - 0b1 - - - - - TRAPE1 - TRAP enable for CCU8x.OUTy1 - 18 - 18 - read-write - - - TRAPE2 - TRAP enable for CCU8x.OUTy2 - 19 - 19 - read-write - - - TRAPE3 - TRAP enable for CCU8x.OUTy3 - 20 - 20 - read-write - - - TRPSE - TRAP Synchronization Enable - 21 - 21 - read-write - - - value1 - Exiting from TRAP state isn't synchronized with the PWM signal - 0b0 - - - value2 - Exiting from TRAP state is synchronized with the PWM signal - 0b1 - - - - - TRPSW - TRAP State Clear Control - 22 - 22 - read-write - - - value1 - The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW) - 0b0 - - - value2 - The TRAP state can only be exited by a SW request. - 0b1 - - - - - EMS - External Modulation Synchronization - 23 - 23 - read-write - - - value1 - External Modulation functionality is not synchronized with the PWM signal - 0b0 - - - value2 - External Modulation functionality is synchronized with the PWM signal - 0b1 - - - - - EMT - External Modulation Type - 24 - 24 - read-write - - - value1 - External Modulation functionality is clearing the CC8ySTx bits. - 0b0 - - - value2 - External Modulation functionality is gating the outputs. - 0b1 - - - - - MCME1 - Multi Channel Mode Enable for Channel 1 - 25 - 25 - read-write - - - value1 - Multi Channel Mode in Channel 1 is disabled - 0b0 - - - value2 - Multi Channel Mode in Channel 1 is enabled - 0b1 - - - - - MCME2 - Multi Channel Mode Enable for Channel 2 - 26 - 26 - read-write - - - value1 - Multi Channel Mode in Channel 2 is disabled - 0b0 - - - value2 - Multi Channel Mode in Channel 2 is enabled - 0b1 - - - - - EME - External Modulation Channel enable - 27 - 28 - read-write - - - value1 - External Modulation functionality doesn't affect any channel - 0b00 - - - value2 - External Modulation only applied on channel 1 - 0b01 - - - value3 - External Modulation only applied on channel 2 - 0b10 - - - value4 - External Modulation applied on both channels - 0b11 - - - - - STOS - Status bit output selector - 29 - 30 - read-write - - - value1 - CC8yST1 forward to CCU8x.STy - 0b00 - - - value2 - CC8yST2 forward to CCU8x.STy - 0b01 - - - value3 - CC8yST1 AND CC8yST2 forward to CCU8x.STy - 0b10 - - - value4 - Reserved - 0b11 - - - - - - - PSL - Passive Level Config - 0x0018 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSL11 - Output Passive Level for CCU8x.OUTy0 - 0 - 0 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - PSL12 - Output Passive Level for CCU8x.OUTy1 - 1 - 1 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - PSL21 - Output Passive Level for CCU8x.OUTy2 - 2 - 2 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - PSL22 - Output Passive Level for CCU8x.OUTy3 - 3 - 3 - read-write - - - value1 - Passive Level is LOW - 0b0 - - - value2 - Passive Level is HIGH - 0b1 - - - - - - - DIT - Dither Config - 0x001C - 32 - 0x00000000 - 0xFFFFFFFF - - - DCV - Dither compare Value - 0 - 3 - read-only - - - DCNT - Dither counter actual value - 8 - 11 - read-only - - - - - DITS - Dither Shadow Register - 0x0020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCVS - Dither Shadow Compare Value - 0 - 3 - read-write - - - - - PSC - Prescaler Control - 0x0024 - 32 - 0x00000000 - 0xFFFFFFFF - - - PSIV - Prescaler Initial Value - 0 - 3 - read-write - - - - - FPC - Floating Prescaler Control - 0x0028 - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Compare Value - 0 - 3 - read-only - - - PVAL - Actual Prescaler Value - 8 - 11 - read-write - - - - - FPCS - Floating Prescaler Shadow - 0x002C - 32 - 0x00000000 - 0xFFFFFFFF - - - PCMP - Floating Prescaler Shadow Compare Value - 0 - 3 - read-write - - - - - PR - Timer Period Value - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - PR - Period Register - 0 - 15 - read-only - - - - - PRS - Timer Shadow Period Value - 0x0034 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRS - Period Register - 0 - 15 - read-write - - - - - CR1 - Channel 1 Compare Value - 0x0038 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR1 - Compare Register for Channel 1 - 0 - 15 - read-only - - - - - CR1S - Channel 1 Compare Shadow Value - 0x003C - 32 - 0x00000000 - 0xFFFFFFFF - - - CR1S - Shadow Compare Register for Channel 1 - 0 - 15 - read-write - - - - - CR2 - Channel 2 Compare Value - 0x0040 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR2 - Compare Register for Channel 2 - 0 - 15 - read-only - - - - - CR2S - Channel 2 Compare Shadow Value - 0x0044 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR2S - Shadow Compare Register for Channel 2 - 0 - 15 - read-write - - - - - CHC - Channel Control - 0x0048 - 32 - 0x00000000 - 0xFFFFFFFF - - - ASE - Asymmetric PWM mode Enable - 0 - 0 - read-write - - - value1 - Asymmetric PWM is disabled - 0b0 - - - value2 - Asymmetric PWM is enabled - 0b1 - - - - - OCS1 - Output selector for CCU8x.OUTy0 - 1 - 1 - read-write - - - value1 - CC8yST1 signal path is connected to the CCU8x.OUTy0 - 0b0 - - - value2 - Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0 - 0b1 - - - - - OCS2 - Output selector for CCU8x.OUTy1 - 2 - 2 - read-write - - - value1 - Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1 - 0b0 - - - value2 - CC8yST1 signal path is connected to the CCU8x.OUTy1 - 0b1 - - - - - OCS3 - Output selector for CCU8x.OUTy2 - 3 - 3 - read-write - - - value1 - CC8yST2 signal path is connected to the CCU8x.OUTy2 - 0b0 - - - value2 - Inverted CCST2 signal path is connected to the CCU8x.OUTy2 - 0b1 - - - - - OCS4 - Output selector for CCU8x.OUTy3 - 4 - 4 - read-write - - - value1 - Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3 - 0b0 - - - value2 - CC8yST2 signal path is connected to the CCU8x.OUTy3 - 0b1 - - - - - - - DTC - Dead Time Control - 0x004C - 32 - 0x00000000 - 0xFFFFFFFF - - - DTE1 - Dead Time Enable for Channel 1 - 0 - 0 - read-write - - - value1 - Dead Time for channel 1 is disabled - 0b0 - - - value2 - Dead Time for channel 1 is enabled - 0b1 - - - - - DTE2 - Dead Time Enable for Channel 2 - 1 - 1 - read-write - - - value1 - Dead Time for channel 2 is disabled - 0b0 - - - value2 - Dead Time for channel 2 is enabled - 0b1 - - - - - DCEN1 - Dead Time Enable for CC8yST1 - 2 - 2 - read-write - - - value1 - Dead Time for CC8yST1 path is disabled - 0b0 - - - value2 - Dead Time for CC8yST1 path is enabled - 0b1 - - - - - DCEN2 - Dead Time Enable for inverted CC8yST1 - 3 - 3 - read-write - - - value1 - Dead Time for inverted CC8yST1 path is disabled - 0b0 - - - value2 - Dead Time for inverted CC8yST1 path is enabled - 0b1 - - - - - DCEN3 - Dead Time Enable for CC8yST2 - 4 - 4 - read-write - - - value1 - Dead Time for CC8yST2 path is disabled - 0b0 - - - value2 - Dead Time for CC8yST2 path is enabled - 0b1 - - - - - DCEN4 - Dead Time Enable for inverted CC8yST2 - 5 - 5 - read-write - - - value1 - Dead Time for inverted CC8yST2 path is disabled - 0b0 - - - value2 - Dead Time for inverted CC8yST2 path is enabled - 0b1 - - - - - DTCC - Dead Time clock control - 6 - 7 - read-write - - - value1 - ftclk - 0b00 - - - value2 - ftclk/2 - 0b01 - - - value3 - ftclk/4 - 0b10 - - - value4 - ftclk/8 - 0b11 - - - - - - - DC1R - Channel 1 Dead Time Values - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - DT1R - Rise Value for Dead Time of Channel 1 - 0 - 7 - read-write - - - DT1F - Fall Value for Dead Time of Channel 1 - 8 - 15 - read-write - - - - - DC2R - Channel 2 Dead Time Values - 0x0054 - 32 - 0x00000000 - 0xFFFFFFFF - - - DT2R - Rise Value for Dead Time of Channel 2 - 0 - 7 - read-write - - - DT2F - Fall Value for Dead Time of Channel 2 - 8 - 15 - read-write - - - - - TIMER - Timer Value - 0x0070 - 32 - 0x00000000 - 0xFFFFFFFF - - - TVAL - Timer Value - 0 - 15 - read-write - - - - - C0V - Capture Register 0 - 0x0074 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C1V - Capture Register 1 - 0x0078 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C2V - Capture Register 2 - 0x007C - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - C3V - Capture Register 3 - 0x0080 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPTV - Capture Value - 0 - 15 - read-only - - - FPCV - Prescaler Value - 16 - 19 - read-only - - - FFL - Full Flag - 20 - 20 - read-only - - - value1 - No new value was captured into the specific capture register - 0b0 - - - value2 - A new value was captured into the specific register - 0b1 - - - - - - - INTS - Interrupt Status - 0x00A0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PMUS - Period Match while Counting Up - 0 - 0 - read-only - - - value1 - Period match while counting up not detected - 0b0 - - - value2 - Period match while counting up detected - 0b1 - - - - - OMDS - One Match while Counting Down - 1 - 1 - read-only - - - value1 - One match while counting down not detected - 0b0 - - - value2 - One match while counting down detected - 0b1 - - - - - CMU1S - Channel 1 Compare Match while Counting Up - 2 - 2 - read-only - - - value1 - Compare match while counting up not detected - 0b0 - - - value2 - Compare match while counting up detected - 0b1 - - - - - CMD1S - Channel 1 Compare Match while Counting Down - 3 - 3 - read-only - - - value1 - Compare match while counting down not detected - 0b0 - - - value2 - Compare match while counting down detected - 0b1 - - - - - CMU2S - Channel 2 Compare Match while Counting Up - 4 - 4 - read-only - - - value1 - Compare match while counting up not detected - 0b0 - - - value2 - Compare match while counting up detected - 0b1 - - - - - CMD2S - Channel 2 Compare Match while Counting Down - 5 - 5 - read-only - - - value1 - Compare match while counting down not detected - 0b0 - - - value2 - Compare match while counting down detected - 0b1 - - - - - E0AS - Event 0 Detection Status - 8 - 8 - read-only - - - value1 - Event 0 not detected - 0b0 - - - value2 - Event 0 detected - 0b1 - - - - - E1AS - Event 1 Detection Status - 9 - 9 - read-only - - - value1 - Event 1 not detected - 0b0 - - - value2 - Event 1 detected - 0b1 - - - - - E2AS - Event 2 Detection Status - 10 - 10 - read-only - - - value1 - Event 2 not detected - 0b0 - - - value2 - Event 2 detected - 0b1 - - - - - TRPF - Trap Flag Status - 11 - 11 - read-only - - - - - INTE - Interrupt Enable Control - 0x00A4 - 32 - 0x00000000 - 0xFFFFFFFF - - - PME - Period match while counting up enable - 0 - 0 - read-write - - - value1 - Period Match interrupt is disabled - 0b0 - - - value2 - Period Match interrupt is enabled - 0b1 - - - - - OME - One match while counting down enable - 1 - 1 - read-write - - - value1 - One Match interrupt is disabled - 0b0 - - - value2 - One Match interrupt is enabled - 0b1 - - - - - CMU1E - Channel 1 Compare match while counting up enable - 2 - 2 - read-write - - - value1 - Compare Match while counting up interrupt is disabled - 0b0 - - - value2 - Compare Match while counting up interrupt is enabled - 0b1 - - - - - CMD1E - Channel 1 Compare match while counting down enable - 3 - 3 - read-write - - - value1 - Compare Match while counting down interrupt is disabled - 0b0 - - - value2 - Compare Match while counting down interrupt is enabled - 0b1 - - - - - CMU2E - Channel 2 Compare match while counting up enable - 4 - 4 - read-write - - - value1 - Compare Match while counting up interrupt is disabled - 0b0 - - - value2 - Compare Match while counting up interrupt is enabled - 0b1 - - - - - CMD2E - Channel 2 Compare match while counting down enable - 5 - 5 - read-write - - - value1 - Compare Match while counting down interrupt is disabled - 0b0 - - - value2 - Compare Match while counting down interrupt is enabled - 0b1 - - - - - E0AE - Event 0 interrupt enable - 8 - 8 - read-write - - - value1 - Event 0 detection interrupt is disabled - 0b0 - - - value2 - Event 0 detection interrupt is enabled - 0b1 - - - - - E1AE - Event 1 interrupt enable - 9 - 9 - read-write - - - value1 - Event 1 detection interrupt is disabled - 0b0 - - - value2 - Event 1 detection interrupt is enabled - 0b1 - - - - - E2AE - Event 2 interrupt enable - 10 - 10 - read-write - - - value1 - Event 2 detection interrupt is disabled - 0b0 - - - value2 - Event 2 detection interrupt is enabled - 0b1 - - - - - - - SRS - Service Request Selector - 0x00A8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSR - Period/One match Service request selector - 0 - 1 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - CM1SR - Channel 1 Compare match Service request selector - 2 - 3 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - CM2SR - Channel 2 Compare match Service request selector - 4 - 5 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - E0SR - Event 0 Service request selector - 8 - 9 - read-write - - - value1 - Forward to CCvySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - E1SR - Event 1 Service request selector - 10 - 11 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CC8ySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - E2SR - Event 2 Service request selector - 12 - 13 - read-write - - - value1 - Forward to CC8ySR0 - 0b00 - - - value2 - Forward to CCvySR1 - 0b01 - - - value3 - Forward to CC8ySR2 - 0b10 - - - value4 - Forward to CC8ySR3 - 0b11 - - - - - - - SWS - Interrupt Status Set - 0x00AC - 32 - 0x00000000 - 0xFFFFFFFF - - - SPM - Period match while counting up set - 0 - 0 - write-only - - - SOM - One match while counting down set - 1 - 1 - write-only - - - SCM1U - Channel 1 Compare match while counting up set - 2 - 2 - write-only - - - SCM1D - Channel 1 Compare match while counting down set - 3 - 3 - write-only - - - SCM2U - Compare match while counting up set - 4 - 4 - write-only - - - SCM2D - Compare match while counting down set - 5 - 5 - write-only - - - SE0A - Event 0 detection set - 8 - 8 - write-only - - - SE1A - Event 1 detection set - 9 - 9 - write-only - - - SE2A - Event 2 detection set - 10 - 10 - write-only - - - STRPF - Trap Flag status set - 11 - 11 - write-only - - - - - SWR - Interrupt Status Clear - 0x00B0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPM - Period match while counting up clear - 0 - 0 - write-only - - - ROM - One match while counting down clear - 1 - 1 - write-only - - - RCM1U - Channel 1 Compare match while counting up clear - 2 - 2 - write-only - - - RCM1D - Channel 1 Compare match while counting down clear - 3 - 3 - write-only - - - RCM2U - Channel 2 Compare match while counting up clear - 4 - 4 - write-only - - - RCM2D - Channel 2 Compare match while counting down clear - 5 - 5 - write-only - - - RE0A - Event 0 detection clear - 8 - 8 - write-only - - - RE1A - Event 1 detection clear - 9 - 9 - write-only - - - RE2A - Event 2 detection clear - 10 - 10 - write-only - - - RTRPF - Trap Flag status clear - 11 - 11 - write-only - - - - - - - CCU80_CC81 - Capture Compare Unit 8 - Unit 0 - CCU8 - 0x40020200 - - 0x0 - 0x100 - registers - - - - CCU80_CC82 - Capture Compare Unit 8 - Unit 0 - CCU8 - 0x40020300 - - 0x0 - 0x100 - registers - - - - CCU80_CC83 - Capture Compare Unit 8 - Unit 0 - CCU8 - 0x40020400 - - 0x0 - 0x100 - registers - - - - CCU81_CC80 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024100 - - 0x0 - 0x100 - registers - - - - CCU81_CC81 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024200 - - 0x0 - 0x100 - registers - - - - CCU81_CC82 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024300 - - 0x0 - 0x100 - registers - - - - CCU81_CC83 - Capture Compare Unit 8 - Unit 1 - CCU8 - 0x40024400 - - 0x0 - 0x100 - registers - - - - POSIF0 - Position Interface 0 - POSIF - POSIF - 0x40028000 - - 0x0 - 0x4000 - registers - - - - PCONF - POSIF configuration - 0x0000 - 32 - 0x00000000 - 0xFFFFFFFF - - - FSEL - Function Selector - 0 - 1 - read-write - - - value1 - Hall Sensor Mode enabled - 0b00 - - - value2 - Quadrature Decoder Mode enabled - 0b01 - - - value3 - stand-alone Multi-Channel Mode enabled - 0b10 - - - value4 - Quadrature Decoder and stand-alone Multi-Channel Mode enabled - 0b11 - - - - - QDCM - Position Decoder Mode selection - 2 - 2 - read-write - - - value1 - Position encoder is in Quadrature Mode - 0b0 - - - value2 - Position encoder is in Direction Count Mode. - 0b1 - - - - - HIDG - Idle generation enable - 4 - 4 - read-write - - - MCUE - Multi-Channel Pattern SW update enable - 5 - 5 - read-write - - - value1 - Multi-Channel pattern update is controlled via HW - 0b0 - - - value2 - Multi-Channel pattern update is controlled via SW - 0b1 - - - - - INSEL0 - PhaseA/Hal input 1 selector - 8 - 9 - read-write - - - value1 - POSIFx.IN0A - 0b00 - - - value2 - POSIFx.IN0B - 0b01 - - - value3 - POSIFx.IN0C - 0b10 - - - value4 - POSIFx.IN0D - 0b11 - - - - - INSEL1 - PhaseB/Hall input 2 selector - 10 - 11 - read-write - - - value1 - POSIFx.IN1A - 0b00 - - - value2 - POSIFx.IN1B - 0b01 - - - value3 - POSIFx.IN1C - 0b10 - - - value4 - POSIFx.IN1D - 0b11 - - - - - INSEL2 - Index/Hall input 3 selector - 12 - 13 - read-write - - - value1 - POSIFx.IN2A - 0b00 - - - value2 - POSIFx.IN2B - 0b01 - - - value3 - POSIFx.IN2C - 0b10 - - - value4 - POSIFx.IN2D - 0b11 - - - - - DSEL - Delay Pin selector - 16 - 16 - read-write - - - value1 - POSIFx.HSDA - 0b0 - - - value2 - POSIFx.HSDB - 0b1 - - - - - SPES - Edge selector for the sampling trigger - 17 - 17 - read-write - - - value1 - Rising edge - 0b0 - - - value2 - Falling edge - 0b1 - - - - - MSETS - Pattern update signal select - 18 - 20 - read-write - - - value1 - POSIFx.MSETA - 0b000 - - - value2 - POSIFx.MSETB - 0b001 - - - value3 - POSIFx.MSETC - 0b010 - - - value4 - POSIFx.MSETD - 0b011 - - - value5 - POSIFx.MSETE - 0b100 - - - value6 - POSIFx.MSETF - 0b101 - - - value7 - POSIFx.MSETG - 0b110 - - - value8 - POSIFx.MSETH - 0b111 - - - - - MSES - Multi-Channel pattern update trigger edge - 21 - 21 - read-write - - - value1 - The signal used to enable a pattern update is active on the rising edge - 0b0 - - - value2 - The signal used to enable a pattern update is active on the falling edge - 0b1 - - - - - MSYNS - PWM synchronization signal selector - 22 - 23 - read-write - - - value1 - POSIFx.MSYNCA - 0b00 - - - value2 - POSIFx.MSYNCB - 0b01 - - - value3 - POSIFx.MSYNCC - 0b10 - - - value4 - POSIFx.MSYNCD - 0b11 - - - - - EWIS - Wrong Hall Event selection - 24 - 25 - read-write - - - value1 - POSIFx.EWHEA - 0b00 - - - value2 - POSIFx.EWHEB - 0b01 - - - value3 - POSIFx.EWHEC - 0b10 - - - value4 - POSIFx.EWHED - 0b11 - - - - - EWIE - External Wrong Hall Event enable - 26 - 26 - read-write - - - value1 - External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled - 0b0 - - - value2 - External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled. - 0b1 - - - - - EWIL - External Wrong Hall Event active level - 27 - 27 - read-write - - - value1 - POSIFx.EWHE[D...A] signal is active HIGH - 0b0 - - - value2 - POSIFx.EWHE[D...A] signal is active LOW - 0b1 - - - - - LPC - Low Pass Filters Configuration - 28 - 30 - read-write - - - value1 - Low pass filter disabled - 0b000 - - - value2 - Low pass of 1 clock cycle - 0b001 - - - value3 - Low pass of 2 clock cycles - 0b010 - - - value4 - Low pass of 4 clock cycles - 0b011 - - - value5 - Low pass of 8 clock cycles - 0b100 - - - value6 - Low pass of 16 clock cycles - 0b101 - - - value7 - Low pass of 32 clock cycles - 0b110 - - - value8 - Low pass of 64 clock cycles - 0b111 - - - - - - - PSUS - POSIF Suspend Config - 0x0004 - 32 - 0x00000000 - 0xFFFFFFFF - - - QSUS - Quadrature Mode Suspend Config - 0 - 1 - read-write - - - value1 - Suspend request ignored - 0b00 - - - value2 - Stop immediately - 0b01 - - - value3 - Suspend in the next index occurrence - 0b10 - - - value4 - Suspend in the next phase (PhaseA or PhaseB) occurrence - 0b11 - - - - - MSUS - Multi-Channel Mode Suspend Config - 2 - 3 - read-write - - - value1 - Suspend request ignored - 0b00 - - - value2 - Stop immediately. Multi-Channel pattern is not set to the reset value. - 0b01 - - - value3 - Stop immediately. Multi-Channel pattern is set to the reset value. - 0b10 - - - value4 - Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization. - 0b11 - - - - - - - PRUNS - POSIF Run Bit Set - 0x0008 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRB - Set Run bit - 0 - 0 - write-only - - - - - PRUNC - POSIF Run Bit Clear - 0x000C - 32 - 0x00000000 - 0xFFFFFFFF - - - CRB - Clear Run bit - 0 - 0 - write-only - - - CSM - Clear Current internal status - 1 - 1 - write-only - - - - - PRUN - POSIF Run Bit Status - 0x0010 - 32 - 0x00000000 - 0xFFFFFFFF - - - RB - Run Bit - 0 - 0 - read-only - - - value1 - IDLE - 0b0 - - - value2 - Running - 0b1 - - - - - - - MIDR - Module Identification register - 0x0020 - 32 - 0x00A8C000 - 0xFFFFFF00 - - - MODR - Module Revision - 0 - 7 - read-only - - - MODT - Module Type - 8 - 15 - read-only - - - MODN - Module Number - 16 - 31 - read-only - - - - - HALP - Hall Sensor Patterns - 0x0030 - 32 - 0x00000000 - 0xFFFFFFFF - - - HCP - Hall Current Pattern - 0 - 2 - read-only - - - HEP - Hall Expected Pattern - 3 - 5 - read-only - - - - - HALPS - Hall Sensor Shadow Patterns - 0x0034 - 32 - 0x00000000 - 0xFFFFFFFF - - - HCPS - Shadow Hall Current Pattern - 0 - 2 - read-write - - - HEPS - Shadow Hall expected Pattern - 3 - 5 - read-write - - - - - MCM - Multi-Channel Pattern - 0x0040 - 32 - 0x00000000 - 0xFFFFFFFF - - - MCMP - Multi-Channel Pattern - 0 - 15 - read-only - - - - - MCSM - Multi-Channel Shadow Pattern - 0x0044 - 32 - 0x00000000 - 0xFFFFFFFF - - - MCMPS - Shadow Multi-Channel Pattern - 0 - 15 - read-write - - - - - MCMS - Multi-Channel Pattern Control set - 0x0048 - 32 - 0x00000000 - 0xFFFFFFFF - - - MNPS - Multi-Channel Pattern Update Enable Set - 0 - 0 - write-only - - - STHR - Hall Pattern Shadow Transfer Request - 1 - 1 - write-only - - - STMR - Multi-Channel Shadow Transfer Request - 2 - 2 - write-only - - - - - MCMC - Multi-Channel Pattern Control clear - 0x004C - 32 - 0x00000000 - 0xFFFFFFFF - - - MNPC - Multi-Channel Pattern Update Enable Clear - 0 - 0 - write-only - - - MPC - Multi-Channel Pattern clear - 1 - 1 - write-only - - - - - MCMF - Multi-Channel Pattern Control flag - 0x0050 - 32 - 0x00000000 - 0xFFFFFFFF - - - MSS - Multi-Channel Pattern update status - 0 - 0 - read-only - - - value1 - Update of the Multi-Channel pattern is set - 0b0 - - - value2 - Update of the Multi-Channel pattern is not set - 0b1 - - - - - - - QDC - Quadrature Decoder Control - 0x0060 - 32 - 0x00000000 - 0xFFFFFFFF - - - PALS - Phase A Level selector - 0 - 0 - read-write - - - value1 - Phase A is active HIGH - 0b0 - - - value2 - Phase A is active LOW - 0b1 - - - - - PBLS - Phase B Level selector - 1 - 1 - read-write - - - value1 - Phase B is active HIGH - 0b0 - - - value2 - Phase B is active LOW - 0b1 - - - - - PHS - Phase signals swap - 2 - 2 - read-write - - - value1 - Phase A is the leading signal for clockwise rotation - 0b0 - - - value2 - Phase B is the leading signal for clockwise rotation - 0b1 - - - - - ICM - Index Marker generations control - 4 - 5 - read-write - - - value1 - No index marker generation on POSIFx.OUT3 - 0b00 - - - value2 - Only first index occurrence generated on POSIFx.OUT3 - 0b01 - - - value3 - All index occurrences generated on POSIFx.OUT3 - 0b10 - - - value4 - Reserved - 0b11 - - - - - DVAL - Current rotation direction - 8 - 8 - read-only - - - value1 - Counterclockwise rotation - 0b0 - - - value2 - Clockwise rotation - 0b1 - - - - - - - PFLG - POSIF Interrupt Flags - 0x0070 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHES - Correct Hall Event Status - 0 - 0 - read-only - - - value1 - Correct Hall Event not detected - 0b0 - - - value2 - Correct Hall Event detected - 0b1 - - - - - WHES - Wrong Hall Event Status - 1 - 1 - read-only - - - value1 - Wrong Hall Event not detected - 0b0 - - - value2 - Wrong Hall Event detected - 0b1 - - - - - HIES - Hall Inputs Update Status - 2 - 2 - read-only - - - value1 - Transition on the Hall Inputs not detected - 0b0 - - - value2 - Transition on the Hall Inputs detected - 0b1 - - - - - MSTS - Multi-Channel pattern shadow transfer status - 4 - 4 - read-only - - - value1 - Shadow transfer not done - 0b0 - - - value2 - Shadow transfer done - 0b1 - - - - - INDXS - Quadrature Index Status - 8 - 8 - read-only - - - value1 - Index event not detected - 0b0 - - - value2 - Index event detected - 0b1 - - - - - ERRS - Quadrature Phase Error Status - 9 - 9 - read-only - - - value1 - Phase Error event not detected - 0b0 - - - value2 - Phase Error event detected - 0b1 - - - - - CNTS - Quadrature CLK Status - 10 - 10 - read-only - - - value1 - Quadrature clock not generated - 0b0 - - - value2 - Quadrature clock generated - 0b1 - - - - - DIRS - Quadrature Direction Change - 11 - 11 - read-only - - - value1 - Change on direction not detected - 0b0 - - - value2 - Change on direction detected - 0b1 - - - - - PCLKS - Quadrature Period Clk Status - 12 - 12 - read-only - - - value1 - Period clock not generated - 0b0 - - - value2 - Period clock generated - 0b1 - - - - - - - PFLGE - POSIF Interrupt Enable - 0x0074 - 32 - 0x00000000 - 0xFFFFFFFF - - - ECHE - Correct Hall Event Enable - 0 - 0 - read-write - - - value1 - Correct Hall Event interrupt disabled - 0b0 - - - value2 - Correct Hall Event interrupt enabled - 0b1 - - - - - EWHE - Wrong Hall Event Enable - 1 - 1 - read-write - - - value1 - Wrong Hall Event interrupt disabled - 0b0 - - - value2 - Wrong Hall Event interrupt enabled - 0b1 - - - - - EHIE - Hall Input Update Enable - 2 - 2 - read-write - - - value1 - Update of the Hall Inputs interrupt is disabled - 0b0 - - - value2 - Update of the Hall Inputs interrupt is enabled - 0b1 - - - - - EMST - Multi-Channel pattern shadow transfer enable - 4 - 4 - read-write - - - value1 - Shadow transfer event interrupt disabled - 0b0 - - - value2 - Shadow transfer event interrupt enabled - 0b1 - - - - - EINDX - Quadrature Index Event Enable - 8 - 8 - read-write - - - value1 - Index event interrupt disabled - 0b0 - - - value2 - Index event interrupt enabled - 0b1 - - - - - EERR - Quadrature Phase Error Enable - 9 - 9 - read-write - - - value1 - Phase error event interrupt disabled - 0b0 - - - value2 - Phase error event interrupt enabled - 0b1 - - - - - ECNT - Quadrature CLK interrupt Enable - 10 - 10 - read-write - - - value1 - Quadrature CLK event interrupt disabled - 0b0 - - - value2 - Quadrature CLK event interrupt enabled - 0b1 - - - - - EDIR - Quadrature direction change interrupt Enable - 11 - 11 - read-write - - - value1 - Direction change event interrupt disabled - 0b0 - - - value2 - Direction change event interrupt enabled - 0b1 - - - - - EPCLK - Quadrature Period CLK interrupt Enable - 12 - 12 - read-write - - - value1 - Quadrature Period CLK event interrupt disabled - 0b0 - - - value2 - Quadrature Period CLK event interrupt enabled - 0b1 - - - - - CHESEL - Correct Hall Event Service Request Selector - 16 - 16 - read-write - - - value1 - Correct Hall Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Correct Hall Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - WHESEL - Wrong Hall Event Service Request Selector - 17 - 17 - read-write - - - value1 - Wrong Hall Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Wrong Hall Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - HIESEL - Hall Inputs Update Event Service Request Selector - 18 - 18 - read-write - - - value1 - Hall Inputs Update Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Hall Inputs Update Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - MSTSEL - Multi-Channel pattern Update Event Service Request Selector - 20 - 20 - read-write - - - value1 - Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - INDSEL - Quadrature Index Event Service Request Selector - 24 - 24 - read-write - - - value1 - Quadrature Index Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Index Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - ERRSEL - Quadrature Phase Error Event Service Request Selector - 25 - 25 - read-write - - - value1 - Quadrature Phase error Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Phase error Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - CNTSEL - Quadrature Clock Event Service Request Selector - 26 - 26 - read-write - - - value1 - Quadrature Clock Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Clock Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - DIRSEL - Quadrature Direction Update Event Service Request Selector - 27 - 27 - read-write - - - value1 - Quadrature Direction Update Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Direction Update Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - PCLSEL - Quadrature Period clock Event Service Request Selector - 28 - 28 - read-write - - - value1 - Quadrature Period clock Event interrupt forward to POSIFx.SR0 - 0b0 - - - value2 - Quadrature Period clock Event interrupt forward to POSIFx.SR1 - 0b1 - - - - - - - SPFLG - POSIF Interrupt Set - 0x0078 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCHE - Correct Hall Event flag set - 0 - 0 - write-only - - - SWHE - Wrong Hall Event flag set - 1 - 1 - write-only - - - SHIE - Hall Inputs Update Event flag set - 2 - 2 - write-only - - - SMST - Multi-Channel Pattern shadow transfer flag set - 4 - 4 - write-only - - - SINDX - Quadrature Index flag set - 8 - 8 - write-only - - - SERR - Quadrature Phase Error flag set - 9 - 9 - write-only - - - SCNT - Quadrature CLK flag set - 10 - 10 - write-only - - - SDIR - Quadrature Direction flag set - 11 - 11 - write-only - - - SPCLK - Quadrature period clock flag set - 12 - 12 - write-only - - - - - RPFLG - POSIF Interrupt Clear - 0x007C - 32 - 0x00000000 - 0xFFFFFFFF - - - RCHE - Correct Hall Event flag clear - 0 - 0 - write-only - - - RWHE - Wrong Hall Event flag clear - 1 - 1 - write-only - - - RHIE - Hall Inputs Update Event flag clear - 2 - 2 - write-only - - - RMST - Multi-Channel Pattern shadow transfer flag clear - 4 - 4 - write-only - - - RINDX - Quadrature Index flag clear - 8 - 8 - write-only - - - RERR - Quadrature Phase Error flag clear - 9 - 9 - write-only - - - RCNT - Quadrature CLK flag clear - 10 - 10 - write-only - - - RDIR - Quadrature Direction flag clear - 11 - 11 - write-only - - - RPCLK - Quadrature period clock flag clear - 12 - 12 - write-only - - - - - PDBG - POSIF Debug register - 0x0100 - 32 - 0x00000000 - 0xFFFFFFFF - - - QCSV - Quadrature Decoder Current state - 0 - 1 - read-only - - - QPSV - Quadrature Decoder Previous state - 2 - 3 - read-only - - - IVAL - Current Index Value - 4 - 4 - read-only - - - HSP - Hall Current Sampled Pattern - 5 - 7 - read-only - - - LPP0 - Actual count of the Low Pass Filter for POSI0 - 8 - 13 - read-only - - - LPP1 - Actual count of the Low Pass Filter for POSI1 - 16 - 21 - read-only - - - LPP2 - Actual count of the Low Pass Filter for POSI2 - 22 - 27 - read-only - - - - - - - POSIF1 - Position Interface 1 - POSIF - 0x4002C000 - - 0x0 - 0x4000 - registers - - - - PORT0 - Port 0 - PORTS - 0x48028000 - - 0x0 - 0x0100 - registers - - - - OUT - Port 0 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 0 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 0 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 0 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 0 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 0 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 0 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 0 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 0 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 0 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 0 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 0 Pin Hardware Select Register - 0x74 - 32 - 0x00014000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT1 - Port 1 - PORTS - 0x48028100 - - 0x0 - 0x0100 - registers - - - - OUT - Port 1 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 1 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 1 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 1 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 1 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 1 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 1 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 1 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 1 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 1 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 1 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 1 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT2 - Port 2 - PORTS - 0x48028200 - - 0x0 - 0x0100 - registers - - - - OUT - Port 2 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 2 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 2 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 2 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 2 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 2 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 2 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 2 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 2 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 2 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 2 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 2 Pin Hardware Select Register - 0x74 - 32 - 0x00000004 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT3 - Port 3 - PORTS - 0x48028300 - - 0x0 - 0x0100 - registers - - - - OUT - Port 3 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 3 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 3 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 3 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 3 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 3 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 3 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 3 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 3 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 3 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 3 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 3 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT4 - Port 4 - PORTS - 0x48028400 - - 0x0 - 0x0100 - registers - - - - OUT - Port 4 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 4 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 4 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 4 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IN - Port 4 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 4 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDISC - Port 4 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 4 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 4 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT5 - Port 5 - PORTS - 0x48028500 - - 0x0 - 0x0100 - registers - - - - OUT - Port 5 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 5 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 5 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 5 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 5 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IN - Port 5 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 5 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDR1 - Port 5 Pad Driver Mode 1 Register - 0x44 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD8 - Pad Driver Mode for Pn.8 - 0 - 2 - read-write - - - PD9 - Pad Driver Mode for Pn.9 - 4 - 6 - read-write - - - PD10 - Pad Driver Mode for Pn.10 - 8 - 10 - read-write - - - PD11 - Pad Driver Mode for Pn.11 - 12 - 14 - read-write - - - PD12 - Pad Driver Mode for Pn.12 - 16 - 18 - read-write - - - PD13 - Pad Driver Mode for Pn.13 - 20 - 22 - read-write - - - PD14 - Pad Driver Mode for Pn.14 - 24 - 26 - read-write - - - PD15 - Pad Driver Mode for Pn.15 - 28 - 30 - read-write - - - - - PDISC - Port 5 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 5 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 5 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT6 - Port 6 - PORTS - 0x48028600 - - 0x0 - 0x0100 - registers - - - - OUT - Port 6 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 6 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 6 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 6 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IN - Port 6 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDR0 - Port 6 Pad Driver Mode 0 Register - 0x40 - 32 - 0x22222222 - 0xFFFFFFFF - - - PD0 - Pad Driver Mode for Pn.0 - 0 - 2 - read-write - - - PD1 - Pad Driver Mode for Pn.1 - 4 - 6 - read-write - - - PD2 - Pad Driver Mode for Pn.2 - 8 - 10 - read-write - - - PD3 - Pad Driver Mode for Pn.3 - 12 - 14 - read-write - - - PD4 - Pad Driver Mode for Pn.4 - 16 - 18 - read-write - - - PD5 - Pad Driver Mode for Pn.5 - 20 - 22 - read-write - - - PD6 - Pad Driver Mode for Pn.6 - 24 - 26 - read-write - - - PD7 - Pad Driver Mode for Pn.7 - 28 - 30 - read-write - - - - - PDISC - Port 6 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port n Pin 0 - 0 - 0 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS1 - Pad Disable for Port n Pin 1 - 1 - 1 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS2 - Pad Disable for Port n Pin 2 - 2 - 2 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS3 - Pad Disable for Port n Pin 3 - 3 - 3 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS4 - Pad Disable for Port n Pin 4 - 4 - 4 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS5 - Pad Disable for Port n Pin 5 - 5 - 5 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS6 - Pad Disable for Port n Pin 6 - 6 - 6 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS7 - Pad Disable for Port n Pin 7 - 7 - 7 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS8 - Pad Disable for Port n Pin 8 - 8 - 8 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS9 - Pad Disable for Port n Pin 9 - 9 - 9 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS10 - Pad Disable for Port n Pin 10 - 10 - 10 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS11 - Pad Disable for Port n Pin 11 - 11 - 11 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS12 - Pad Disable for Port n Pin 12 - 12 - 12 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS13 - Pad Disable for Port n Pin 13 - 13 - 13 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS14 - Pad Disable for Port n Pin 14 - 14 - 14 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - PDIS15 - Pad Disable for Port n Pin 15 - 15 - 15 - read-only - - - value1 - Pad Pn.x is enabled. - 0b0 - - - value2 - Pad Pn.x is disabled. - 0b1 - - - - - - - PPS - Port 6 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 6 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT14 - Port 14 - PORTS - 0x48028E00 - - 0x0 - 0x0100 - registers - - - - OUT - Port 14 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 14 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 14 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 14 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 14 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 14 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 14 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDISC - Port 14 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS0 - Pad Disable for Port 14 Pin 0 - 0 - 0 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 0 selected. - 0b1 - - - - - PDIS1 - Pad Disable for Port 14 Pin 1 - 1 - 1 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 1 selected. - 0b1 - - - - - PDIS2 - Pad Disable for Port 14 Pin 2 - 2 - 2 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 and ADC 1 analog input 2 selected. - 0b1 - - - - - PDIS3 - Pad Disable for Port 14 Pin 3 - 3 - 3 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 and ADC 1 analog input 3 selected. - 0b1 - - - - - PDIS4 - Pad Disable for Port 14 Pin 4 - 4 - 4 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 4 and ADC 2 analog input 0 and DAC Reference selected. - 0b1 - - - - - PDIS5 - Pad Disable for Port 14 Pin 5 - 5 - 5 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 5 and ADC 2 analog input 1 selected. - 0b1 - - - - - PDIS6 - Pad Disable for Port 14 Pin 6 - 6 - 6 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 0 analog input 6 selected. - 0b1 - - - - - PDIS7 - Pad Disable for Port 14 Pin 7 - 7 - 7 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC0 analog input 7 selected. - 0b1 - - - - - PDIS8 - Pad Disable for Port 14 Pin 8 - 8 - 8 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 0 and ADC 2 analog input 4 and DAC output 0 selected. - 0b1 - - - - - PDIS9 - Pad Disable for Port 14 Pin 9 - 9 - 9 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 1 and ADC 2 analog input 5 and DAC output 1 selected. - 0b1 - - - - - PDIS12 - Pad Disable for Port 14 Pin 12 - 12 - 12 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 4 selected. - 0b1 - - - - - PDIS13 - Pad Disable for Port 14 Pin 13 - 13 - 13 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 5 selected. - 0b1 - - - - - PDIS14 - Pad Disable for Port 14 Pin 14 - 14 - 14 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 6 selected. - 0b1 - - - - - PDIS15 - Pad Disable for Port 14 Pin 15 - 15 - 15 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 1 analog input 7 selected. - 0b1 - - - - - - - PPS - Port 14 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 14 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - PORT15 - Port 15 - PORTS - 0x48028F00 - - 0x0 - 0x0100 - registers - - - - OUT - Port 15 Output Register - 0x00 - 32 - 0x00000000 - 0xFFFFFFFF - - - P0 - Port n Output Bit 0 - 0 - 0 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Output Bit 1 - 1 - 1 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Output Bit 2 - 2 - 2 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Output Bit 3 - 3 - 3 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Output Bit 4 - 4 - 4 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Output Bit 5 - 5 - 5 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Output Bit 6 - 6 - 6 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Output Bit 7 - 7 - 7 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Output Bit 8 - 8 - 8 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Output Bit 9 - 9 - 9 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Output Bit 10 - 10 - 10 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Output Bit 11 - 11 - 11 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Output Bit 12 - 12 - 12 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Output Bit 13 - 13 - 13 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Output Bit 14 - 14 - 14 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Output Bit 15 - 15 - 15 - read-write - - - value1 - The output level of Pn.x is 0. - 0b0 - - - value2 - The output level of Pn.x is 1. - 0b1 - - - - - - - OMR - Port 15 Output Modification Register - 0x04 - 32 - 0x00000000 - 0xFFFFFFFF - - - PS0 - Port n Set Bit 0 - 0 - 0 - write-only - - - PS1 - Port n Set Bit 1 - 1 - 1 - write-only - - - PS2 - Port n Set Bit 2 - 2 - 2 - write-only - - - PS3 - Port n Set Bit 3 - 3 - 3 - write-only - - - PS4 - Port n Set Bit 4 - 4 - 4 - write-only - - - PS5 - Port n Set Bit 5 - 5 - 5 - write-only - - - PS6 - Port n Set Bit 6 - 6 - 6 - write-only - - - PS7 - Port n Set Bit 7 - 7 - 7 - write-only - - - PS8 - Port n Set Bit 8 - 8 - 8 - write-only - - - PS9 - Port n Set Bit 9 - 9 - 9 - write-only - - - PS10 - Port n Set Bit 10 - 10 - 10 - write-only - - - PS11 - Port n Set Bit 11 - 11 - 11 - write-only - - - PS12 - Port n Set Bit 12 - 12 - 12 - write-only - - - PS13 - Port n Set Bit 13 - 13 - 13 - write-only - - - PS14 - Port n Set Bit 14 - 14 - 14 - write-only - - - PS15 - Port n Set Bit 15 - 15 - 15 - write-only - - - PR0 - Port n Reset Bit 0 - 16 - 16 - write-only - - - PR1 - Port n Reset Bit 1 - 17 - 17 - write-only - - - PR2 - Port n Reset Bit 2 - 18 - 18 - write-only - - - PR3 - Port n Reset Bit 3 - 19 - 19 - write-only - - - PR4 - Port n Reset Bit 4 - 20 - 20 - write-only - - - PR5 - Port n Reset Bit 5 - 21 - 21 - write-only - - - PR6 - Port n Reset Bit 6 - 22 - 22 - write-only - - - PR7 - Port n Reset Bit 7 - 23 - 23 - write-only - - - PR8 - Port n Reset Bit 8 - 24 - 24 - write-only - - - PR9 - Port n Reset Bit 9 - 25 - 25 - write-only - - - PR10 - Port n Reset Bit 10 - 26 - 26 - write-only - - - PR11 - Port n Reset Bit 11 - 27 - 27 - write-only - - - PR12 - Port n Reset Bit 12 - 28 - 28 - write-only - - - PR13 - Port n Reset Bit 13 - 29 - 29 - write-only - - - PR14 - Port n Reset Bit 14 - 30 - 30 - write-only - - - PR15 - Port n Reset Bit 15 - 31 - 31 - write-only - - - - - IOCR0 - Port 15 Input/Output Control Register 0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC0 - Port Control for Port n Pin 0 to 3 - 3 - 7 - read-write - - - PC1 - Port Control for Port n Pin 0 to 3 - 11 - 15 - read-write - - - PC2 - Port Control for Port n Pin 0 to 3 - 19 - 23 - read-write - - - PC3 - Port Control for Port n Pin 0 to 3 - 27 - 31 - read-write - - - - - IOCR4 - Port 15 Input/Output Control Register 4 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC4 - Port Control for Port n Pin 4 to 7 - 3 - 7 - read-write - - - PC5 - Port Control for Port n Pin 4 to 7 - 11 - 15 - read-write - - - PC6 - Port Control for Port n Pin 4 to 7 - 19 - 23 - read-write - - - PC7 - Port Control for Port n Pin 4 to 7 - 27 - 31 - read-write - - - - - IOCR8 - Port 15 Input/Output Control Register 8 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PC8 - Port Control for Port n Pin 8 to 11 - 3 - 7 - read-write - - - PC9 - Port Control for Port n Pin 8 to 11 - 11 - 15 - read-write - - - PC10 - Port Control for Port n Pin 8 to 11 - 19 - 23 - read-write - - - PC11 - Port Control for Port n Pin 8 to 11 - 27 - 31 - read-write - - - - - IOCR12 - Port 15 Input/Output Control Register 12 - 0x1C - 32 - 0x00000000 - 0xFFFFFFFF - - - PC12 - Port Control for Port n Pin 12 to 15 - 3 - 7 - read-write - - - PC13 - Port Control for Port n Pin 12 to 15 - 11 - 15 - read-write - - - PC14 - Port Control for Port n Pin 12 to 15 - 19 - 23 - read-write - - - PC15 - Port Control for Port n Pin 12 to 15 - 27 - 31 - read-write - - - - - IN - Port 15 Input Register - 0x24 - 32 - 0x00000000 - 0xFFFF0000 - - - P0 - Port n Input Bit 0 - 0 - 0 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P1 - Port n Input Bit 1 - 1 - 1 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P2 - Port n Input Bit 2 - 2 - 2 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P3 - Port n Input Bit 3 - 3 - 3 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P4 - Port n Input Bit 4 - 4 - 4 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P5 - Port n Input Bit 5 - 5 - 5 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P6 - Port n Input Bit 6 - 6 - 6 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P7 - Port n Input Bit 7 - 7 - 7 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P8 - Port n Input Bit 8 - 8 - 8 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P9 - Port n Input Bit 9 - 9 - 9 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P10 - Port n Input Bit 10 - 10 - 10 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P11 - Port n Input Bit 11 - 11 - 11 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P12 - Port n Input Bit 12 - 12 - 12 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P13 - Port n Input Bit 13 - 13 - 13 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P14 - Port n Input Bit 14 - 14 - 14 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - P15 - Port n Input Bit 15 - 15 - 15 - read-only - - - value1 - The input level of Pn.x is 0. - 0b0 - - - value2 - The input level of Pn.x is 1. - 0b1 - - - - - - - PDISC - Port 15 Pin Function Decision Control Register - 0x60 - 32 - 0x00000000 - 0xFFFF0000 - - - PDIS2 - Pad Disable for Port 15 Pin 2 - 2 - 2 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 2. - 0b1 - - - - - PDIS3 - Pad Disable for Port 15 Pin 3 - 3 - 3 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 3. - 0b1 - - - - - PDIS4 - Pad Disable for Port 15 Pin 4 - 4 - 4 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 4. - 0b1 - - - - - PDIS5 - Pad Disable for Port 15 Pin 5 - 5 - 5 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 5. - 0b1 - - - - - PDIS6 - Pad Disable for Port 15 Pin 6 - 6 - 6 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 6. - 0b1 - - - - - PDIS7 - Pad Disable for Port 15 Pin 7 - 7 - 7 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 2 analog input 7. - 0b1 - - - - - PDIS8 - Pad Disable for Port 15 Pin 8 - 8 - 8 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 0. - 0b1 - - - - - PDIS9 - Pad Disable for Port 15 Pin 9 - 9 - 9 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 1. - 0b1 - - - - - PDIS12 - Pad Disable for Port 15 Pin 12 - 12 - 12 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 4. - 0b1 - - - - - PDIS13 - Pad Disable for Port 15 Pin 13 - 13 - 13 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 5. - 0b1 - - - - - PDIS14 - Pad Disable for Port 15 Pin 14 - 14 - 14 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 6. - 0b1 - - - - - PDIS15 - Pad Disable for Port 15 Pin 15 - 15 - 15 - read-write - - - value1 - Pad is enabled, digital input selected. - 0b0 - - - value2 - Pad is disabled, ADC 3 analog input 7. - 0b1 - - - - - - - PPS - Port 15 Pin Power Save Register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS0 - Port n Pin Power Save Bit 0 - 0 - 0 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS1 - Port n Pin Power Save Bit 1 - 1 - 1 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS2 - Port n Pin Power Save Bit 2 - 2 - 2 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS3 - Port n Pin Power Save Bit 3 - 3 - 3 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS4 - Port n Pin Power Save Bit 4 - 4 - 4 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS5 - Port n Pin Power Save Bit 5 - 5 - 5 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS6 - Port n Pin Power Save Bit 6 - 6 - 6 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS7 - Port n Pin Power Save Bit 7 - 7 - 7 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS8 - Port n Pin Power Save Bit 8 - 8 - 8 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS9 - Port n Pin Power Save Bit 9 - 9 - 9 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS10 - Port n Pin Power Save Bit 10 - 10 - 10 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS11 - Port n Pin Power Save Bit 11 - 11 - 11 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS12 - Port n Pin Power Save Bit 12 - 12 - 12 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS13 - Port n Pin Power Save Bit 13 - 13 - 13 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS14 - Port n Pin Power Save Bit 14 - 14 - 14 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - PPS15 - Port n Pin Power Save Bit 15 - 15 - 15 - read-write - - - value1 - Pin Power Save of Pn.x is disabled. - 0b0 - - - value2 - Pin Power Save of Pn.x is enabled. - 0b1 - - - - - - - HWSEL - Port 15 Pin Hardware Select Register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - HW0 - Port n Pin Hardware Select Bit 0 - 0 - 1 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW1 - Port n Pin Hardware Select Bit 1 - 2 - 3 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW2 - Port n Pin Hardware Select Bit 2 - 4 - 5 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW3 - Port n Pin Hardware Select Bit 3 - 6 - 7 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW4 - Port n Pin Hardware Select Bit 4 - 8 - 9 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW5 - Port n Pin Hardware Select Bit 5 - 10 - 11 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW6 - Port n Pin Hardware Select Bit 6 - 12 - 13 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW7 - Port n Pin Hardware Select Bit 7 - 14 - 15 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW8 - Port n Pin Hardware Select Bit 8 - 16 - 17 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW9 - Port n Pin Hardware Select Bit 9 - 18 - 19 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW10 - Port n Pin Hardware Select Bit 10 - 20 - 21 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW11 - Port n Pin Hardware Select Bit 11 - 22 - 23 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW12 - Port n Pin Hardware Select Bit 12 - 24 - 25 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW13 - Port n Pin Hardware Select Bit 13 - 26 - 27 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW14 - Port n Pin Hardware Select Bit 14 - 28 - 29 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - HW15 - Port n Pin Hardware Select Bit 15 - 30 - 31 - read-write - - - value1 - Software control only. - 0b00 - - - value2 - HW0 control path can override the software configuration. - 0b01 - - - value3 - HW1 control path can override the software configuration. - 0b10 - - - value4 - Reserved. - 0b11 - - - - - - - - - + + + + + + + + + + + + + + + + + Infineon + XMC4700 + 1.3.0 (Reference Manual v1.3) + SVD file + + CM4 + r2p0 + little + true + true + 6 + false + + 8 + 32 + + + PPB + Cortex-M4 Private Peripheral Block + 0xE000E000 + + 0x0 + 0x1000 + registers + + + + ACTLR + Auxiliary Control Register + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + DISMCYCINT + Disable load/store multiple + 0 + 0 + read-write + + + DISDEFWBUF + Disable write buffer + 1 + 1 + read-write + + + DISFOLD + Disable IT folding + 2 + 2 + read-write + + + DISFPCA + Disable FPCA update + 8 + 8 + read-write + + + DISOOFP + Disable out of order FP execution + 9 + 9 + read-write + + + + + SYST_CSR + SysTick Control and Status Register + 0x010 + 32 + 0x00000004 + 0xFFFFFFFF + + + ENABLE + Enable + 0 + 0 + read-write + + + value1 + counter disabled + #0 + + + value2 + counter enabled. + #1 + + + + + TICKINT + Tick Interrupt Enable + 1 + 1 + read-write + + + value1 + counting down to zero does not assert the SysTick exception request + #0 + + + value2 + counting down to zero to asserts the SysTick exception request. + #1 + + + + + CLKSOURCE + Indicates the clock source: + 2 + 2 + read-write + + + value1 + external clock + #0 + + + value2 + processor clock. + #1 + + + + + COUNTFLAG + Counter Flag + 16 + 16 + read-write + + + + + SYST_RVR + SysTick Reload Value Register + 0x014 + 32 + 0x00000000 + 0x00000000 + + + RELOAD + Reload Value + 0 + 23 + read-write + + + + + SYST_CVR + SysTick Current Value Register + 0x018 + 32 + 0x00000000 + 0x00000000 + + + CURRENT + Current Value + 0 + 23 + read-write + + + + + SYST_CALIB + SysTick Calibration Value Register r + 0x01C + 32 + 0xC0000000 + 0xFFFFFFFF + + + TENMS + Ten Milliseconds Reload Value + 0 + 23 + read-write + + + SKEW + Ten Milliseconds Skewed + 30 + 30 + read-write + + + value1 + TENMS value is exact + #0 + + + value2 + TENMS value is inexact, or not given. + #1 + + + + + NOREF + No Reference Clock + 31 + 31 + read-write + + + value1 + reference clock provided + #0 + + + value2 + no reference clock provided. + #1 + + + + + + + NVIC_ISER0 + Interrupt Set-enable Register 0 + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISER1 + Interrupt Set-enable Register 1 + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISER2 + Interrupt Set-enable Register 2 + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISER3 + Interrupt Set-enable Register 3 + 0x10C + 32 + 0x00000000 + 0xFFFFFFFF + + + SETENA + Interrupt set-enable bits + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER0 + Interrupt Clear-enable Register 0 + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER1 + Interrupt Clear-enable Register 1 + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER2 + Interrupt Clear-enable Register 2 + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ICER3 + Interrupt Clear-enable Register 3 + 0x18C + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits. + 0 + 31 + read-write + + + value3 + interrupt disabled + #0 + + + value4 + interrupt enabled. + #1 + + + + + + + NVIC_ISPR0 + Interrupt Set-pending Register 0 + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ISPR1 + Interrupt Set-pending Register 1 + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ISPR2 + Interrupt Set-pending Register 2 + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ISPR3 + Interrupt Set-pending Register 3 + 0x20C + 32 + 0x00000000 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR0 + Interrupt Clear-pending Register 0 + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR1 + Interrupt Clear-pending Register 1 + 0x284 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR2 + Interrupt Clear-pending Register 2 + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_ICPR3 + Interrupt Clear-pending Register 3 + 0x28C + 32 + 0x00000000 + 0xFFFFFFFF + + + CLRPEND + Interrupt set-pending bits. + 0 + 31 + read-write + + + value3 + interrupt is not pending + #0 + + + value4 + interrupt is pending. + #1 + + + + + + + NVIC_IABR0 + Interrupt Active Bit Register 0 + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IABR1 + Interrupt Active Bit Register 1 + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IABR2 + Interrupt Active Bit Register 2 + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IABR3 + Interrupt Active Bit Register 3 + 0x30C + 32 + 0x00000000 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags: + 0 + 31 + read-write + + + value1 + interrupt not active + #0 + + + value2 + interrupt active + #1 + + + + + + + NVIC_IPR0 + Interrupt Priority Register 0 + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR1 + Interrupt Priority Register 1 + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR2 + Interrupt Priority Register 2 + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR3 + Interrupt Priority Register 3 + 0x40C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR4 + Interrupt Priority Register 4 + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR5 + Interrupt Priority Register 5 + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR6 + Interrupt Priority Register 6 + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR7 + Interrupt Priority Register 7 + 0x41C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR8 + Interrupt Priority Register 8 + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR9 + Interrupt Priority Register 9 + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR10 + Interrupt Priority Register 10 + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR11 + Interrupt Priority Register 11 + 0x42C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR12 + Interrupt Priority Register 12 + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR13 + Interrupt Priority Register 13 + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR14 + Interrupt Priority Register 14 + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR15 + Interrupt Priority Register 15 + 0x43C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR16 + Interrupt Priority Register 16 + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR17 + Interrupt Priority Register 17 + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR18 + Interrupt Priority Register 18 + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR19 + Interrupt Priority Register 19 + 0x44C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR20 + Interrupt Priority Register 20 + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR21 + Interrupt Priority Register 21 + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR22 + Interrupt Priority Register 22 + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR23 + Interrupt Priority Register 23 + 0x45C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR24 + Interrupt Priority Register 24 + 0x460 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR25 + Interrupt Priority Register 25 + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR26 + Interrupt Priority Register 26 + 0x468 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + NVIC_IPR27 + Interrupt Priority Register 27 + 0x46C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_0 + Priority value 0 + 0 + 7 + read-write + + + PRI_1 + Priority value 1 + 8 + 15 + read-write + + + PRI_2 + Priority value 2 + 16 + 23 + read-write + + + PRI_3 + Priority value 3 + 24 + 31 + read-write + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + 0x410FC241 + 0xFFFFFFFF + + + Revision + Revision number + 0 + 3 + read-only + + + value1 + Patch 1 + 0x1 + + + + + PartNo + Part number of the processor + 4 + 15 + read-only + + + value1 + Cortex-M4 + 0xC24 + + + + + Constant + Reads as 0xF + 16 + 19 + read-only + + + Variant + Variant number + 20 + 23 + read-only + + + value1 + Revision 0 + 0x0 + + + + + Implementer + Implementer code + 24 + 31 + read-only + + + value1 + ARM + 0x41 + + + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + 0x00000000 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 8 + read-only + + + value1 + Thread mode + 0x00 + + + + + RETTOBASE + Return to Base + 11 + 11 + read-only + + + value1 + there are preempted active exceptions to execute + #0 + + + value2 + there are no active exceptions, or the currently-executing exception is the only active exception. + #1 + + + + + VECTPENDING + Vector Pending + 12 + 17 + read-only + + + value1 + no pending exceptions + 0x0 + + + + + ISRPENDING + Interrupt pending flag + 22 + 22 + read-only + + + value1 + interrupt not pending + #0 + + + value2 + interrupt pending. + #1 + + + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 25 + write-only + + + value1 + no effect + #0 + + + value2 + removes the pending state from the SysTick exception. + #1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 26 + read-write + + + value1 + no effect + #0 + + + value2 + changes SysTick exception state to pending. + #1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 27 + write-only + + + value1 + no effect + #0 + + + value2 + removes the pending state from the PendSV exception. + #1 + + + + + PENDSVSET + PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending., + 28 + 28 + read-write + + + NMIPENDSET + NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending., + 31 + 31 + read-write + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset field + 10 + 31 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + Reserved for Debug use. + 0 + 0 + write-only + + + VECTCLRACTIVE + Reserved for Debug use. + 1 + 1 + write-only + + + SYSRESETREQ + System reset request + 2 + 2 + write-only + + + value1 + no system reset request + #0 + + + value2 + asserts a signal to the outer system that requests a reset. + #1 + + + + + PRIGROUP + Interrupt priority grouping field + 8 + 10 + read-write + + + ENDIANNESS + Data endianness bit + 15 + 15 + read-only + + + value1 + Little-endian + #0 + + + value2 + Big-endian. + #1 + + + + + VECTKEY + Register key + 16 + 31 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLEEPONEXIT + Sleep on Exit + 1 + 1 + read-write + + + value1 + do not sleep when returning to Thread mode. + #0 + + + value2 + enter sleep, or deep sleep, on return from an ISR. + #1 + + + + + SLEEPDEEP + Sleep or Deep Sleep + 2 + 2 + read-write + + + value1 + sleep + #0 + + + value2 + deep sleep + #1 + + + + + SEVONPEND + Send Event on Pending bit: + 4 + 4 + read-write + + + value1 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + #0 + + + value2 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + #1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + 0x00000200 + 0xFFFFFFFF + + + NONBASETHRDENA + Non Base Thread Mode Enable + 0 + 0 + read-write + + + value1 + processor can enter Thread mode only when no exception is active. + #0 + + + value2 + processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. . + #1 + + + + + USERSETMPEND + User Set Pending Enable + 1 + 1 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + UNALIGN_TRP + Unaligned Access Trap Enable + 3 + 3 + read-write + + + value1 + do not trap unaligned halfword and word accesses + #0 + + + value2 + trap unaligned halfword and word accesses. + #1 + + + + + DIV_0_TRP + Divide by Zero Trap Enable + 4 + 4 + read-write + + + value1 + do not trap divide by 0 + #0 + + + value2 + trap divide by 0. + #1 + + + + + BFHFNMIGN + Bus Fault Hard Fault and NMI Ignore + 8 + 8 + read-write + + + value1 + data bus faults caused by load and store instructions cause a lock-up + #0 + + + value2 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. + #1 + + + + + STKALIGN + Stack Alignment + 9 + 9 + read-write + + + value1 + 4-byte aligned + #0 + + + value2 + 8-byte aligned. + #1 + + + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 7 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 15 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 23 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 31 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14 + 16 + 23 + read-write + + + PRI_15 + Priority of system handler 15 + 24 + 31 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + 0x00000000 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active bit + 0 + 0 + read-write + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + read-write + + + USGFAULTACT + UsageFault exception active bit + 3 + 3 + read-write + + + SVCALLACT + SVCall active bit + 7 + 7 + read-write + + + MONITORACT + Debug monitor active bit + 8 + 8 + read-write + + + PENDSVACT + PendSV exception active bit + 10 + 10 + read-write + + + SYSTICKACT + SysTick exception active bit + 11 + 11 + read-write + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 12 + read-write + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 13 + read-write + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 14 + read-write + + + SVCALLPENDED + SVCall pending bit + 15 + 15 + read-write + + + MEMFAULTENA + MemManage enable bit + 16 + 16 + read-write + + + BUSFAULTENA + BusFault enable bit + 17 + 17 + read-write + + + USGFAULTENA + UsageFault enable bit + 18 + 18 + read-write + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + 0x00000000 + 0xFFFFFFFF + + + IACCVIOL + Instruction access violation flag + 0 + 0 + read-write + + + value1 + no instruction access violation fault + #0 + + + value2 + the processor attempted an instruction fetch from a location that does not permit execution. + #1 + + + + + DACCVIOL + Data access violation flag + 1 + 1 + read-write + + + value1 + no data access violation fault + #0 + + + value2 + the processor attempted a load or store at a location that does not permit the operation. + #1 + + + + + MUNSTKERR + MemManage fault on unstacking for a return from exception + 3 + 3 + read-write + + + value1 + no unstacking fault + #0 + + + value2 + unstack for an exception return has caused one or more access violations. + #1 + + + + + MSTKERR + MemManage fault on stacking for exception entry + 4 + 4 + read-write + + + value1 + no stacking fault + #0 + + + value2 + stacking for an exception entry has caused one or more access violations. + #1 + + + + + MLSPERR + MemManage fault during floating point lazy state preservation + 5 + 5 + read-write + + + value1 + No MemManage fault occurred during floating-point lazy state preservation + #0 + + + value2 + A MemManage fault occurred during floating-point lazy state preservation + #1 + + + + + MMARVALID + MemManage Fault Address Register (MMFAR) valid flag + 7 + 7 + read-write + + + value1 + value in MMAR is not a valid fault address + #0 + + + value2 + MMAR holds a valid fault address. + #1 + + + + + IBUSERR + Instruction bus error + 8 + 8 + read-write + + + value1 + no instruction bus error + #0 + + + value2 + instruction bus error. + #1 + + + + + PRECISERR + Precise data bus error + 9 + 9 + read-write + + + value1 + no precise data bus error + #0 + + + value2 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. + #1 + + + + + IMPRECISERR + Imprecise data bus error + 10 + 10 + read-write + + + value1 + no imprecise data bus error + #0 + + + value2 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. + #1 + + + + + UNSTKERR + BusFault on unstacking for a return from exception + 11 + 11 + read-write + + + value1 + no unstacking fault + #0 + + + value2 + stacking for an exception entry has caused one or more BusFaults. + #1 + + + + + STKERR + BusFault on stacking for exception entry + 12 + 12 + read-write + + + value1 + no stacking fault + #0 + + + value2 + stacking for an exception entry has caused one or more BusFaults. + #1 + + + + + LSPERR + BusFault during floating point lazy state preservation + 13 + 13 + read-write + + + value1 + No bus fault occurred during floating-point lazy state preservation. + #0 + + + value2 + A bus fault occurred during floating-point lazy state preservation + #1 + + + + + BFARVALID + BusFault Address Register (BFAR) valid flag + 15 + 15 + read-write + + + value1 + value in BFAR is not a valid fault address + #0 + + + value2 + BFAR holds a valid fault address. + #1 + + + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 16 + read-write + + + value1 + no undefined instruction UsageFault + #0 + + + value2 + the processor has attempted to execute an undefined instruction. + #1 + + + + + INVSTATE + Invalid state UsageFault + 17 + 17 + read-write + + + value1 + no invalid state UsageFault + #0 + + + value2 + the processor has attempted to execute an instruction that makes illegal use of the EPSR. + #1 + + + + + INVPC + Invalid PC load UsageFault + 18 + 18 + read-write + + + value1 + no invalid PC load UsageFault + #0 + + + value2 + the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. + #1 + + + + + NOCP + No coprocessor UsageFault + 19 + 19 + read-write + + + value1 + no UsageFault caused by attempting to access a coprocessor + #0 + + + value2 + the processor has attempted to access a coprocessor. + #1 + + + + + UNALIGNED + Unaligned access UsageFault + 24 + 24 + read-write + + + value1 + no unaligned access fault, or unaligned access trapping not enabled + #0 + + + value2 + the processor has made an unaligned memory access. + #1 + + + + + DIVBYZERO + Divide by zero UsageFault + 25 + 25 + read-write + + + value1 + no divide by zero fault, or divide by zero trapping not enabled + #0 + + + value2 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + #1 + + + + + + + HFSR + HardFault Status Register + 0xD2C + 32 + 0x00000000 + 0xFFFFFFFF + + + VECTTBL + BusFault on vector table read + 1 + 1 + read-write + + + value1 + no BusFault on vector table read + #0 + + + value2 + BusFault on vector table read + #1 + + + + + FORCED + Forced HardFault + 30 + 30 + read-write + + + value1 + no forced HardFault + #0 + + + value2 + forced HardFault. + #1 + + + + + DEBUGEVT + Reserved for Debug use + 31 + 31 + read-write + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + 0x00000000 + 0x00000000 + + + ADDRESS + Address causing the fault + 0 + 31 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + 0x00000000 + 0x00000000 + + + ADDRESS + Address causing the fault + 0 + 31 + read-write + + + + + AFSR + Auxiliary Fault Status Register + 0xD3C + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + Reserved + 0 + 31 + read-write + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + 0x00000000 + 0xFFFFFFFF + + + CP10 + Access privileges for coprocessor 10 + 20 + 21 + read-write + + + value1 + Access denied. Any attempted access generates a NOCP UsageFault. + #00 + + + value2 + Privileged access only. An unprivileged access generates a NOCP fault. + #01 + + + value4 + Full access. + #11 + + + + + CP11 + Access privileges for coprocessor 11 + 22 + 23 + read-write + + + value1 + Access denied. Any attempted access generates a NOCP UsageFault. + #00 + + + value2 + Privileged access only. An unprivileged access generates a NOCP fault. + #01 + + + value4 + Full access. + #11 + + + + + + + MPU_TYPE + MPU Type Register + 0xD90 + 32 + 0x00000800 + 0xFFFFFFFF + + + SEPARATE + Support for unified or separate instruction and date memory maps + 0 + 0 + read-only + + + DREGION + Number of supported MPU data regions + 8 + 15 + read-only + + + IREGION + Number of supported MPU instruction regions + 16 + 23 + read-only + + + + + MPU_CTRL + MPU Control Register + 0xD94 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Enable MPU + 0 + 0 + read-write + + + value1 + MPU disabled + #0 + + + value2 + MPU enabled. + #1 + + + + + HFNMIENA + Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers + 1 + 1 + read-write + + + value1 + MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit + #0 + + + value2 + the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. + #1 + + + + + PRIVDEFENA + Enables privileged software access to the default memory map + 2 + 2 + read-write + + + value1 + If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. + #0 + + + value2 + If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. + #1 + + + + + + + MPU_RNR + MPU Region Number Register + 0xD98 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + Region + 0 + 7 + read-write + + + + + MPU_RBAR + MPU Region Base Address Register + 0xD9C + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR + MPU Region Attribute and Size Register + 0xDA0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + MPU_RBAR_A1 + MPU Region Base Address Register A1 + 0xDA4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR_A1 + MPU Region Attribute and Size Register A1 + 0xDA8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + MPU_RBAR_A2 + MPU Region Base Address Register A2 + 0xDAC + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR_A2 + MPU Region Attribute and Size Register A2 + 0xDB0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + MPU_RBAR_A3 + MPU Region Base Address Register A3 + 0xDB4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGION + MPU region field + 0 + 3 + read-write + + + VALID + MPU Region Number valid bit + 4 + 4 + read-write + + + value1 + MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field + #0 + + + value2 + the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. + #1 + + + + + ADDR + Region base address field + 9 + 31 + read-write + + + + + MPU_RASR_A3 + MPU Region Attribute and Size Register A3 + 0xDB8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + Region enable bit. + 0 + 0 + read-write + + + SIZE + MPU protection region size + 1 + 5 + read-write + + + SRD + Subregion disable bits + 8 + 15 + read-write + + + value1 + corresponding sub-region is enabled + #0 + + + value2 + corresponding sub-region is disabled + #1 + + + + + B + Memory access attribute + 16 + 16 + read-write + + + C + Memory access attribute + 17 + 17 + read-write + + + S + Shareable bit + 18 + 18 + read-write + + + TEX + Memory access attribute + 19 + 21 + read-write + + + AP + Access permission field + 24 + 26 + read-write + + + XN + Instruction access disable bit + 28 + 28 + read-write + + + value1 + instruction fetches enabled + #0 + + + value2 + instruction fetches disabled. + #1 + + + + + + + STIR + Software Trigger Interrupt Register + 0xF00 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger + 0 + 8 + write-only + + + + + FPCCR + Floating-point Context Control Register + 0xF34 + 32 + 0x00000000 + 0xFFFFFFFF + + + LSPACT + Lazy State Preservation Active + 0 + 0 + read-write + + + value1 + Lazy state preservation is not active. + #0 + + + value2 + Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. + #1 + + + + + USER + User allocated Stack Frame + 1 + 1 + read-write + + + value1 + Privilege level was not user when the floating-point stack frame was allocated. + #0 + + + value2 + Privilege level was user when the floating-point stack frame was allocated. + #1 + + + + + THREAD + Thread Mode allocated Stack Frame + 3 + 3 + read-write + + + value1 + Mode was not Thread Mode when the floating-point stack frame was allocated. + #0 + + + value2 + Mode was Thread Mode when the floating-point stack frame was allocated. + #1 + + + + + HFRDY + HardFault Ready + 4 + 4 + read-write + + + value1 + Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. + #0 + + + value2 + Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. + #1 + + + + + MMRDY + MemManage Ready + 5 + 5 + read-write + + + value1 + MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. + #0 + + + value2 + MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. + #1 + + + + + BFRDY + BusFault Ready + 6 + 6 + read-write + + + value1 + BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. + #0 + + + value2 + BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. + #1 + + + + + MONRDY + Monitor Ready + 8 + 8 + read-write + + + value1 + Debug Monitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. + #0 + + + value2 + Debug Monitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. + #1 + + + + + LSPEN + Lazy State Preservation Enabled + 30 + 30 + read-write + + + value1 + Disable automatic lazy state preservation for floating-point context. + #0 + + + value2 + Enable automatic lazy state preservation for floating-point context. + #1 + + + + + ASPEN + Automatic State Preservation + 31 + 31 + read-write + + + value1 + Disable CONTROL setting on execution of a floating-point instruction. + #0 + + + value2 + Enable CONTROL setting on execution of a floating-point instruction. + #1 + + + + + + + FPCAR + Floating-point Context Address Register + 0xF38 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRESS + Address + 3 + 31 + read-write + + + + + FPDSCR + Floating-point Default Status Control Register + 0xF3C + 32 + 0x00000000 + 0xFFFFFFFF + + + RMode + Default value for FPSCR.RMode + 22 + 23 + read-write + + + FZ + Default value for FPSCR.FZ + 24 + 24 + read-write + + + DN + Default value for FPSCR.DN + 25 + 25 + read-write + + + AHP + Default value for FPSCR.AHP + 26 + 26 + read-write + + + + + + + DLR + DMA Line Router + 0x50004900 + + 0x0 + 0x0100 + registers + + + + OVRSTAT + Overrun Status + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + LN0 + Line 0 Overrun Status + 0 + 0 + read-only + + + LN1 + Line 1 Overrun Status + 1 + 1 + read-only + + + LN2 + Line 2 Overrun Status + 2 + 2 + read-only + + + LN3 + Line 3 Overrun Status + 3 + 3 + read-only + + + LN4 + Line 4 Overrun Status + 4 + 4 + read-only + + + LN5 + Line 5 Overrun Status + 5 + 5 + read-only + + + LN6 + Line 6 Overrun Status + 6 + 6 + read-only + + + LN7 + Line 7 Overrun Status + 7 + 7 + read-only + + + LN8 + Line 8 Overrun Status + 8 + 8 + read-only + + + LN9 + Line 9 Overrun Status + 9 + 9 + read-only + + + LN10 + Line 10 Overrun Status + 10 + 10 + read-only + + + LN11 + Line 11 Overrun Status + 11 + 11 + read-only + + + + + OVRCLR + Overrun Clear + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + LN0 + Line 0 Overrun Status Clear + 0 + 0 + write-only + + + LN1 + Line 1 Overrun Status Clear + 1 + 1 + write-only + + + LN2 + Line 2 Overrun Status Clear + 2 + 2 + write-only + + + LN3 + Line 3 Overrun Status Clear + 3 + 3 + write-only + + + LN4 + Line 4 Overrun Status Clear + 4 + 4 + write-only + + + LN5 + Line 5 Overrun Status Clear + 5 + 5 + write-only + + + LN6 + Line 6 Overrun Status Clear + 6 + 6 + write-only + + + LN7 + Line 7 Overrun Status Clear + 7 + 7 + write-only + + + LN8 + Line 8 Overrun Status Clear + 8 + 8 + write-only + + + LN9 + Line 9 Overrun Status Clear + 9 + 9 + write-only + + + LN10 + Line 10 Overrun Status Clear + 10 + 10 + write-only + + + LN11 + Line 11 Overrun Status Clear + 11 + 11 + write-only + + + + + SRSEL0 + Service Request Selection 0 + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + RS0 + Request Source for Line 0 + 0 + 3 + read-write + + + RS1 + Request Source for Line 1 + 4 + 7 + read-write + + + RS2 + Request Source for Line 2 + 8 + 11 + read-write + + + RS3 + Request Source for Line 3 + 12 + 15 + read-write + + + RS4 + Request Source for Line 4 + 16 + 19 + read-write + + + RS5 + Request Source for Line 5 + 20 + 23 + read-write + + + RS6 + Request Source for Line 6 + 24 + 27 + read-write + + + RS7 + Request Source for Line 7 + 28 + 31 + read-write + + + + + SRSEL1 + Service Request Selection 1 + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + RS8 + Request Source for Line 8 + 0 + 3 + read-write + + + RS9 + Request Source for Line 9 + 4 + 7 + read-write + + + RS10 + Request Source for Line 10 + 8 + 11 + read-write + + + RS11 + Request Source for Line 11 + 12 + 15 + read-write + + + + + LNEN + Line Enable + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + LN0 + Line 0 Enable + 0 + 0 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN1 + Line 1 Enable + 1 + 1 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN2 + Line 2 Enable + 2 + 2 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN3 + Line 3 Enable + 3 + 3 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN4 + Line 4 Enable + 4 + 4 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN5 + Line 5 Enable + 5 + 5 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN6 + Line 6 Enable + 6 + 6 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN7 + Line 7 Enable + 7 + 7 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN8 + Line 8 Enable + 8 + 8 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN9 + Line 9 Enable + 9 + 9 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN10 + Line 10 Enable + 10 + 10 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + LN11 + Line 11 Enable + 11 + 11 + read-write + + + value1 + Disables the line + #0 + + + value2 + Enables the line and resets a pending request + #1 + + + + + + + + + ERU0 + Event Request Unit 0 + ERU + ERU + 0x50004800 + + 0x0 + 0x0100 + registers + + + ERU0_0 + External Request Unit 0 + 1 + + + ERU0_1 + External Request Unit 0 + 2 + + + ERU0_2 + External Request Unit 0 + 3 + + + ERU0_3 + External Request Unit 0 + 4 + + + + EXISEL + Event Input Select + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + EXS0A + Event Source Select for A0 (ERS0) + 0 + 1 + read-write + + + value1 + Input ERU_0A0 is selected + #00 + + + value2 + Input ERU_0A1 is selected + #01 + + + value3 + Input ERU_0A2 is selected + #10 + + + value4 + Input ERU_0A3 is selected + #11 + + + + + EXS0B + Event Source Select for B0 (ERS0) + 2 + 3 + read-write + + + value1 + Input ERU_0B0 is selected + #00 + + + value2 + Input ERU_0B1 is selected + #01 + + + value3 + Input ERU_0B2 is selected + #10 + + + value4 + Input ERU_0B3 is selected + #11 + + + + + EXS1A + Event Source Select for A1 (ERS1) + 4 + 5 + read-write + + + value1 + Input ERU_1A0 is selected + #00 + + + value2 + Input ERU_1A1 is selected + #01 + + + value3 + Input ERU_1A2 is selected + #10 + + + value4 + Input ERU_1A3 is selected + #11 + + + + + EXS1B + Event Source Select for B1 (ERS1) + 6 + 7 + read-write + + + value1 + Input ERU_1B0 is selected + #00 + + + value2 + Input ERU_1B1 is selected + #01 + + + value3 + Input ERU_1B2 is selected + #10 + + + value4 + Input ERU_1B3 is selected + #11 + + + + + EXS2A + Event Source Select for A2 (ERS2) + 8 + 9 + read-write + + + value1 + Input ERU_2A0 is selected + #00 + + + value2 + Input ERU_2A1 is selected + #01 + + + value3 + Input ERU_2A2 is selected + #10 + + + value4 + Input ERU_2A3 is selected + #11 + + + + + EXS2B + Event Source Select for B2 (ERS2) + 10 + 11 + read-write + + + value1 + Input ERU_2B0 is selected + #00 + + + value2 + Input ERU_2B1 is selected + #01 + + + value3 + Input ERU_2B2 is selected + #10 + + + value4 + Input ERU_2B3 is selected + #11 + + + + + EXS3A + Event Source Select for A3 (ERS3) + 12 + 13 + read-write + + + value1 + Input ERU_3A0 is selected + #00 + + + value2 + Input ERU_3A1 is selected + #01 + + + value3 + Input ERU_3A2 is selected + #10 + + + value4 + Input ERU_3A3 is selected + #11 + + + + + EXS3B + Event Source Select for B3 (ERS3) + 14 + 15 + read-write + + + value1 + Input ERU_3B0 is selected + #00 + + + value2 + Input ERU_3B1 is selected + #01 + + + value3 + Input ERU_3B2 is selected + #10 + + + value4 + Input ERU_3B3 is selected + #11 + + + + + + + 4 + 4 + EXICON[%s] + Event Input Control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PE + Output Trigger Pulse Enable for ETLx + 0 + 0 + read-write + + + value1 + The trigger pulse generation is disabled + #0 + + + value2 + The trigger pulse generation is enabled + #1 + + + + + LD + Rebuild Level Detection for Status Flag for ETLx + 1 + 1 + read-write + + + value1 + The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software. + #0 + + + value2 + The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0. + #1 + + + + + RE + Rising Edge Detection Enable ETLx + 2 + 2 + read-write + + + value1 + A rising edge is not considered as edge event + #0 + + + value2 + A rising edge is considered as edge event + #1 + + + + + FE + Falling Edge Detection Enable ETLx + 3 + 3 + read-write + + + value1 + A falling edge is not considered as edge event + #0 + + + value2 + A falling edge is considered as edge event + #1 + + + + + OCS + Output Channel Select for ETLx Output Trigger Pulse + 4 + 6 + read-write + + + value1 + Trigger pulses are sent to OGU0 + #000 + + + value2 + Trigger pulses are sent to OGU1 + #001 + + + value3 + Trigger pulses are sent to OGU2 + #010 + + + value4 + Trigger pulses are sent to OGU3 + #011 + + + + + FL + Status Flag for ETLx + 7 + 7 + read-write + + + value1 + The enabled edge event has not been detected + #0 + + + value2 + The enabled edge event has been detected + #1 + + + + + SS + Input Source Select for ERSx + 8 + 9 + read-write + + + value1 + Input A without additional combination + #00 + + + value2 + Input B without additional combination + #01 + + + value3 + Input A OR input B + #10 + + + value4 + Input A AND input B + #11 + + + + + NA + Input A Negation Select for ERSx + 10 + 10 + read-write + + + value1 + Input A is used directly + #0 + + + value2 + Input A is inverted + #1 + + + + + NB + Input B Negation Select for ERSx + 11 + 11 + read-write + + + value1 + Input B is used directly + #0 + + + value2 + Input B is inverted + #1 + + + + + + + 4 + 4 + EXOCON[%s] + Event Output Trigger Control + 0x20 + 32 + 0x00000008 + 0xFFFFFFFF + + + ISS + Internal Trigger Source Selection + 0 + 1 + read-write + + + value1 + The peripheral trigger function is disabled + #00 + + + value2 + Input ERU_OGUy1 is selected + #01 + + + value3 + Input ERU_OGUy2 is selected + #10 + + + value4 + Input ERU_OGUy3 is selected + #11 + + + + + GEEN + Gating Event Enable + 2 + 2 + read-write + + + value1 + The event detection is disabled + #0 + + + value2 + The event detection is enabled + #1 + + + + + PDR + Pattern Detection Result Flag + 3 + 3 + read-only + + + value1 + A pattern miss is detected + #0 + + + value2 + A pattern match is detected + #1 + + + + + GP + Gating Selection for Pattern Detection Result + 4 + 5 + read-write + + + value1 + ERU_GOUTy is always disabled and ERU_IOUTy can not be activated + #00 + + + value2 + ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy + #01 + + + value3 + ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1) + #10 + + + value4 + ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0) + #11 + + + + + IPEN0 + Pattern Detection Enable for ETL0 + 12 + 12 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + IPEN1 + Pattern Detection Enable for ETL1 + 13 + 13 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + IPEN2 + Pattern Detection Enable for ETL2 + 14 + 14 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + IPEN3 + Pattern Detection Enable for ETL3 + 15 + 15 + read-write + + + value1 + Flag EXICONx.FL is excluded from the pattern detection + #0 + + + value2 + Flag EXICONx.FL is included in the pattern detection + #1 + + + + + + + + + ERU1 + Event Request Unit 1 + ERU + 0x40044000 + + 0x0 + 0x4000 + registers + + + ERU1_0 + External Request Unit 1 + 5 + + + ERU1_1 + External Request Unit 1 + 6 + + + ERU1_2 + External Request Unit 1 + 7 + + + ERU1_3 + External Request Unit 1 + 8 + + + + GPDMA0 + General Purpose DMA Unit 0 + GPDMA + 0x500142C0 + + 0x0 + 0x3D40 + registers + + + GPDMA0_0 + General Purpose DMA Unit 0 + 105 + + + + RAWTFR + Raw IntTfr Status + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWBLOCK + Raw IntBlock Status + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWSRCTRAN + Raw IntSrcTran Status + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWDSTTRAN + Raw IntBlock Status + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + RAWERR + Raw IntErr Status + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + CH4 + Raw Interrupt Status for channel 4 + 4 + 4 + read-write + + + CH5 + Raw Interrupt Status for channel 5 + 5 + 5 + read-write + + + CH6 + Raw Interrupt Status for channel 6 + 6 + 6 + read-write + + + CH7 + Raw Interrupt Status for channel 7 + 7 + 7 + read-write + + + + + STATUSTFR + IntTfr Status + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSBLOCK + IntBlock Status + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSSRCTRAN + IntSrcTran Status + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSDSTTRAN + IntBlock Status + 0x040 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + STATUSERR + IntErr Status + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + CH4 + Interrupt Status for channel 4 + 4 + 4 + read-only + + + CH5 + Interrupt Status for channel 5 + 5 + 5 + read-only + + + CH6 + Interrupt Status for channel 6 + 6 + 6 + read-only + + + CH7 + Interrupt Status for channel 7 + 7 + 7 + read-only + + + + + MASKTFR + Mask for Raw IntTfr Status + 0x050 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKBLOCK + Mask for Raw IntBlock Status + 0x058 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKSRCTRAN + Mask for Raw IntSrcTran Status + 0x060 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKDSTTRAN + Mask for Raw IntBlock Status + 0x068 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKERR + Mask for Raw IntErr Status + 0x070 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Write enable for mask bit of channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Write enable for mask bit of channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Write enable for mask bit of channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Write enable for mask bit of channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH4 + Mask bit for channel 4 + 4 + 4 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH5 + Mask bit for channel 5 + 5 + 5 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH6 + Mask bit for channel 6 + 6 + 6 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH7 + Mask bit for channel 7 + 7 + 7 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + CLEARTFR + IntTfr Status + 0x078 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARBLOCK + IntBlock Status + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARSRCTRAN + IntSrcTran Status + 0x088 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARDSTTRAN + IntBlock Status + 0x090 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARERR + IntErr Status + 0x098 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH4 + Clear Interrupt Status and Raw Status for channel 4 + 4 + 4 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH5 + Clear Interrupt Status and Raw Status for channel 5 + 5 + 5 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH6 + Clear Interrupt Status and Raw Status for channel 6 + 6 + 6 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH7 + Clear Interrupt Status and Raw Status for channel 7 + 7 + 7 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + STATUSINT + Combined Interrupt Status Register + 0x0A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ERR + OR of the contents of STATUSERR register + 4 + 4 + read-only + + + DSTT + OR of the contents of STATUSDSTTRAN register + 3 + 3 + read-only + + + SRCT + OR of the contents of STATUSSRCTRAN register + 2 + 2 + read-only + + + BLOCK + OR of the contents of STATUSBLOCK register + 1 + 1 + read-only + + + TFR + OR of the contents of STATUSTFR register + 0 + 0 + read-only + + + + + REQSRCREG + Source Software Transaction Request Register + 0x0A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + REQDSTREG + Destination Software Transaction Request Register + 0x0B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + SGLREQSRCREG + Single Source Transaction Request Register + 0x0B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + SGLREQDSTREG + Single Destination Transaction Request Register + 0x0C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + CH4 + Source request for channel 4 + 4 + 4 + read-write + + + CH5 + Source request for channel 5 + 5 + 5 + read-write + + + CH6 + Source request for channel 6 + 6 + 6 + read-write + + + CH7 + Source request for channel 7 + 7 + 7 + read-write + + + + + LSTSRCREG + Last Source Transaction Request Register + 0x0C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Source last transaction request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Source last transaction request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Source last transaction request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Source last transaction request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Source last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Source last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Source last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH4 + Source last request for channel 4 + 4 + 4 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH5 + Source last request for channel 5 + 5 + 5 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH6 + Source last request for channel 6 + 6 + 6 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH7 + Source last request for channel 7 + 7 + 7 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + LSTDSTREG + Last Destination Transaction Request Register + 0x0D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Destination last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Destination last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Destination last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Destination last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH4 + Destination last transaction request write enable for channel 4 + 12 + 12 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH5 + Destination last transaction request write enable for channel 5 + 13 + 13 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH6 + Destination last transaction request write enable for channel 6 + 14 + 14 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH7 + Destination last transaction request write enable for channel 7 + 15 + 15 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Destination last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Destination last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Destination last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Destination last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH4 + Destination last request for channel 4 + 4 + 4 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH5 + Destination last request for channel 5 + 5 + 5 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH6 + Destination last request for channel 6 + 6 + 6 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH7 + Destination last request for channel 7 + 7 + 7 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + DMACFGREG + GPDMA Configuration Register + 0x0D8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DMA_EN + GPDMA Enable bit. + 0 + 0 + read-write + + + value1 + GPDMA Disabled + #0 + + + value2 + GPDMA Enabled. + #1 + + + + + + + CHENREG + GPDMA Channel Enable Register + 0x0E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH + Channel enable write enable + 8 + 15 + write-only + + + CH + Enables/Disables the channel + 0 + 7 + read-write + + + value1 + Disable the Channel + #0 + + + value2 + Enable the Channel + #1 + + + + + + + ID + GPDMA0 ID Register + 0x0E8 + 32 + 0x00AFC000 + 0xFFFFFF00 + + + VALUE + Hardcoded GPDMA Peripheral ID + 0 + 31 + read-only + + + + + TYPE + GPDMA Component Type + 0x138 + 32 + 0x44571110 + 0xFFFFFFFF + + + VALUE + Component Type + 0 + 31 + read-only + + + + + VERSION + DMA Component Version + 0x13C + 32 + 0x3231342A + 0xFFFFFFFF + + + VALUE + Version number of the component + 0 + 31 + read-only + + + + + + + GPDMA0_CH0 + General Purpose DMA Unit 0 + GPDMA + GPDMA0_CH0_1 + 0x50014000 + + 0x0 + 0x55 + registers + + + + SAR + Source Address Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + SAR + Current Source Address of DMA transfer + 0 + 31 + read-write + + + + + DAR + Destination Address Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAR + Current Destination address of DMA transfer + 0 + 31 + read-write + + + + + LLP + Linked List Pointer Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + Starting Address In Memory + 2 + 31 + read-write + + + + + CTLL + Control Register Low + 0x18 + 32 + 0x00304801 + 0xFFFFFFFF + + + LLP_SRC_EN + Linked List Pointer for Source Enable + 28 + 28 + read-write + + + LLP_DST_EN + Linked List Pointer for Destination Enable + 27 + 27 + read-write + + + TT_FC + Transfer Type and Flow Control + 20 + 22 + read-write + + + DST_SCATTER_EN + Destination scatter enable + 18 + 18 + read-write + + + value1 + Scatter disabled + #0 + + + value2 + Scatter enabled + #1 + + + + + SRC_GATHER_EN + Source gather enable + 17 + 17 + read-write + + + value1 + Gather disabled + #0 + + + value2 + Gather enabled + #1 + + + + + SRC_MSIZE + Source Burst Transaction Length + 14 + 16 + read-write + + + DEST_MSIZE + Destination Burst Transaction Length + 11 + 13 + read-write + + + SINC + Source Address Increment + 9 + 10 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + DINC + Destination Address Increment + 7 + 8 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + SRC_TR_WIDTH + Source Transfer Width + 4 + 6 + read-write + + + DST_TR_WIDTH + Destination Transfer Width + 1 + 3 + read-write + + + INT_EN + Interrupt Enable Bit + 0 + 0 + read-write + + + + + CTLH + Control Register High + 0x1C + 32 + 0x00000002 + 0xFFFFFFFF + + + DONE + Done bit + 12 + 12 + read-write + + + BLOCK_TS + Block Transfer Size + 0 + 11 + read-write + + + + + SSTAT + Source Status Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SSTAT + Source Status + 0 + 31 + read-write + + + + + DSTAT + Destination Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTAT + Destination Status + 0 + 31 + read-write + + + + + SSTATAR + Source Status Address Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + SSTATAR + Source Status Address + 0 + 31 + read-write + + + + + DSTATAR + Destination Status Address Register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTATAR + Destination Status Address + 0 + 31 + read-write + + + + + CFGL + Configuration Register Low + 0x40 + 32 + 0x00000E00 + 0xFFFFFF0F + + + RELOAD_DST + Automatic Destination Reload + 31 + 31 + read-write + + + RELOAD_SRC + Automatic Source Reload + 30 + 30 + read-write + + + MAX_ABRST + Maximum AMBA Burst Length + 20 + 29 + read-write + + + SRC_HS_POL + Source Handshaking Interface Polarity + 19 + 19 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + DST_HS_POL + Destination Handshaking Interface Polarity + 18 + 18 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + LOCK_B + Bus Lock Bit + 17 + 17 + read-write + + + LOCK_CH + Channel Lock Bit + 16 + 16 + read-write + + + LOCK_B_L + Bus Lock Level + 14 + 15 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + LOCK_CH_L + Channel Lock Level + 12 + 13 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + HS_SEL_SRC + Source Software or Hardware Handshaking Select + 11 + 11 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware-initiated transaction requests are ignored. + #1 + + + + + HS_SEL_DST + Destination Software or Hardware Handshaking Select + 10 + 10 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware- initiated transaction requests are ignored. + #1 + + + + + FIFO_EMPTY + Indicates if there is data left in the channel FIFO + 9 + 9 + read-only + + + value1 + Channel FIFO empty + #1 + + + value2 + Channel FIFO not empty + #0 + + + + + CH_SUSP + Channel Suspend + 8 + 8 + read-write + + + value1 + Not suspended. + #0 + + + value2 + Suspend DMA transfer from the source. + #1 + + + + + CH_PRIOR + Channel priority + 5 + 7 + read-write + + + + + CFGH + Configuration Register High + 0x44 + 32 + 0x00000004 + 0xFFFFFFFF + + + DEST_PER + Destination Peripheral + 11 + 14 + read-write + + + SRC_PER + Source Peripheral + 7 + 10 + read-write + + + SS_UPD_EN + Source Status Update Enable + 6 + 6 + read-write + + + DS_UPD_EN + Destination Status Update Enable + 5 + 5 + read-write + + + PROTCTL + Protection Control + 2 + 4 + read-write + + + FIFO_MODE + FIFO Mode Select + 1 + 1 + read-write + + + value1 + Space/data available for single AHB transfer of the specified transfer width. + #0 + + + value2 + Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. + #1 + + + + + FCMODE + Flow Control Mode + 0 + 0 + read-write + + + value1 + Source transaction requests are serviced when they occur. Data pre-fetching is enabled. + #0 + + + value2 + Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. + #1 + + + + + + + SGR + Source Gather Register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + SGC + Source gather count + 20 + 31 + read-write + + + SGI + Source gather interval + 0 + 19 + read-write + + + + + DSR + Destination Scatter Register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSC + Destination scatter count + 20 + 31 + read-write + + + DSI + Destination scatter interval + 0 + 19 + read-write + + + + + + + GPDMA0_CH1 + General Purpose DMA Unit 0 + GPDMA + 0x50014058 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH2 + General Purpose DMA Unit 0 + GPDMA + GPDMA0_CH2_7 + 0x500140B0 + + 0x0 + 0x55 + registers + + + + SAR + Source Address Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + SAR + Current Source Address of DMA transfer + 0 + 31 + read-write + + + + + DAR + Destination Address Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAR + Current Destination address of DMA transfer + 0 + 31 + read-write + + + + + CTLL + Control Register Low + 0x18 + 32 + 0x00304801 + 0xFFFFFFFF + + + TT_FC + Transfer Type and Flow Control + 20 + 22 + read-write + + + SRC_MSIZE + Source Burst Transaction Length + 14 + 16 + read-write + + + DEST_MSIZE + Destination Burst Transaction Length + 11 + 13 + read-write + + + SINC + Source Address Increment + 9 + 10 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + DINC + Destination Address Increment + 7 + 8 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + SRC_TR_WIDTH + Source Transfer Width + 4 + 6 + read-write + + + DST_TR_WIDTH + Destination Transfer Width + 1 + 3 + read-write + + + INT_EN + Interrupt Enable Bit + 0 + 0 + read-write + + + + + CTLH + Control Register High + 0x1C + 32 + 0x00000002 + 0xFFFFFFFF + + + DONE + Done bit + 12 + 12 + read-write + + + BLOCK_TS + Block Transfer Size + 0 + 11 + read-write + + + + + CFGL + Configuration Register Low + 0x40 + 32 + 0x00000E00 + 0xFFFFFF0F + + + MAX_ABRST + Maximum AMBA Burst Length + 20 + 29 + read-write + + + SRC_HS_POL + Source Handshaking Interface Polarity + 19 + 19 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + DST_HS_POL + Destination Handshaking Interface Polarity + 18 + 18 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + LOCK_B + Bus Lock Bit + 17 + 17 + read-write + + + LOCK_CH + Channel Lock Bit + 16 + 16 + read-write + + + LOCK_B_L + Bus Lock Level + 14 + 15 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + LOCK_CH_L + Channel Lock Level + 12 + 13 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + HS_SEL_SRC + Source Software or Hardware Handshaking Select + 11 + 11 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware-initiated transaction requests are ignored. + #1 + + + + + HS_SEL_DST + Destination Software or Hardware Handshaking Select + 10 + 10 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware- initiated transaction requests are ignored. + #1 + + + + + FIFO_EMPTY + Indicates if there is data left in the channel FIFO + 9 + 9 + read-only + + + value1 + Channel FIFO empty + #1 + + + value2 + Channel FIFO not empty + #0 + + + + + CH_SUSP + Channel Suspend + 8 + 8 + read-write + + + value1 + Not suspended. + #0 + + + value2 + Suspend DMA transfer from the source. + #1 + + + + + CH_PRIOR + Channel priority + 5 + 7 + read-write + + + + + CFGH + Configuration Register High + 0x44 + 32 + 0x00000004 + 0xFFFFFFFF + + + DEST_PER + Destination Peripheral + 11 + 14 + read-write + + + SRC_PER + Source Peripheral + 7 + 10 + read-write + + + PROTCTL + Protection Control + 2 + 4 + read-write + + + FIFO_MODE + FIFO Mode Select + 1 + 1 + read-write + + + value1 + Space/data available for single AHB transfer of the specified transfer width. + #0 + + + value2 + Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. + #1 + + + + + FCMODE + Flow Control Mode + 0 + 0 + read-write + + + value1 + Source transaction requests are serviced when they occur. Data pre-fetching is enabled. + #0 + + + value2 + Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. + #1 + + + + + + + + + GPDMA0_CH3 + General Purpose DMA Unit 0 + GPDMA + 0x50014108 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH4 + General Purpose DMA Unit 0 + GPDMA + 0x50014160 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH5 + General Purpose DMA Unit 0 + GPDMA + 0x500141B8 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH6 + General Purpose DMA Unit 0 + GPDMA + 0x50014210 + + 0x0 + 0x55 + registers + + + + GPDMA0_CH7 + General Purpose DMA Unit 0 + GPDMA + 0x50014268 + + 0x0 + 0x55 + registers + + + + GPDMA1 + General Purpose DMA Unit 1 + GPDMA + 0x500182C0 + + 0x0 + 0x7D40 + registers + + + GPDMA1_0 + General Purpose DMA Unit 1 + 110 + + + + RAWTFR + Raw IntTfr Status + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWBLOCK + Raw IntBlock Status + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWSRCTRAN + Raw IntSrcTran Status + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWDSTTRAN + Raw IntBlock Status + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + RAWERR + Raw IntErr Status + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Raw Interrupt Status for channel 0 + 0 + 0 + read-write + + + CH1 + Raw Interrupt Status for channel 1 + 1 + 1 + read-write + + + CH2 + Raw Interrupt Status for channel 2 + 2 + 2 + read-write + + + CH3 + Raw Interrupt Status for channel 3 + 3 + 3 + read-write + + + + + STATUSTFR + IntTfr Status + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSBLOCK + IntBlock Status + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSSRCTRAN + IntSrcTran Status + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSDSTTRAN + IntBlock Status + 0x040 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + STATUSERR + IntErr Status + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Interrupt Status for channel 0 + 0 + 0 + read-only + + + CH1 + Interrupt Status for channel 1 + 1 + 1 + read-only + + + CH2 + Interrupt Status for channel 2 + 2 + 2 + read-only + + + CH3 + Interrupt Status for channel 3 + 3 + 3 + read-only + + + + + MASKTFR + Mask for Raw IntTfr Status + 0x050 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKBLOCK + Mask for Raw IntBlock Status + 0x058 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKSRCTRAN + Mask for Raw IntSrcTran Status + 0x060 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKDSTTRAN + Mask for Raw IntBlock Status + 0x068 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + MASKERR + Mask for Raw IntErr Status + 0x070 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Write enable for mask bit of channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Write enable for mask bit of channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Write enable for mask bit of channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Write enable for mask bit of channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Mask bit for channel 0 + 0 + 0 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH1 + Mask bit for channel 1 + 1 + 1 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH2 + Mask bit for channel 2 + 2 + 2 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + CH3 + Mask bit for channel 3 + 3 + 3 + read-write + + + value1 + masked + #0 + + + value2 + unmasked + #1 + + + + + + + CLEARTFR + IntTfr Status + 0x078 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARBLOCK + IntBlock Status + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARSRCTRAN + IntSrcTran Status + 0x088 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARDSTTRAN + IntBlock Status + 0x090 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + CLEARERR + IntErr Status + 0x098 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0 + Clear Interrupt Status and Raw Status for channel 0 + 0 + 0 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH1 + Clear Interrupt Status and Raw Status for channel 1 + 1 + 1 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH2 + Clear Interrupt Status and Raw Status for channel 2 + 2 + 2 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + CH3 + Clear Interrupt Status and Raw Status for channel 3 + 3 + 3 + write-only + + + value1 + no effect + #0 + + + value2 + clear status + #1 + + + + + + + STATUSINT + Combined Interrupt Status Register + 0x0A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ERR + OR of the contents of STATUSERR register + 4 + 4 + read-only + + + DSTT + OR of the contents of STATUSDSTTRAN register + 3 + 3 + read-only + + + SRCT + OR of the contents of STATUSSRCTRAN register + 2 + 2 + read-only + + + BLOCK + OR of the contents of STATUSBLOCK register + 1 + 1 + read-only + + + TFR + OR of the contents of STATUSTFR register + 0 + 0 + read-only + + + + + REQSRCREG + Source Software Transaction Request Register + 0x0A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + REQDSTREG + Destination Software Transaction Request Register + 0x0B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + SGLREQSRCREG + Single Source Transaction Request Register + 0x0B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + SGLREQDSTREG + Single Destination Transaction Request Register + 0x0C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source request for channel 0 + 0 + 0 + read-write + + + CH1 + Source request for channel 1 + 1 + 1 + read-write + + + CH2 + Source request for channel 2 + 2 + 2 + read-write + + + CH3 + Source request for channel 3 + 3 + 3 + read-write + + + + + LSTSRCREG + Last Source Transaction Request Register + 0x0C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Source last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Source last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Source last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Source last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Source last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Source last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Source last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Source last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + LSTDSTREG + Last Destination Transaction Request Register + 0x0D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH0 + Destination last transaction request write enable for channel 0 + 8 + 8 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH1 + Destination last transaction request write enable for channel 1 + 9 + 9 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH2 + Destination last transaction request write enable for channel 2 + 10 + 10 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + WE_CH3 + Destination last transaction request write enable for channel 3 + 11 + 11 + write-only + + + value1 + write disabled + #0 + + + value2 + write enabled + #1 + + + + + CH0 + Destination last request for channel 0 + 0 + 0 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH1 + Destination last request for channel 1 + 1 + 1 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH2 + Destination last request for channel 2 + 2 + 2 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + CH3 + Destination last request for channel 3 + 3 + 3 + read-write + + + value1 + Not last transaction in current block + #0 + + + value2 + Last transaction in current block + #1 + + + + + + + DMACFGREG + GPDMA Configuration Register + 0x0D8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DMA_EN + GPDMA Enable bit. + 0 + 0 + read-write + + + value1 + GPDMA Disabled + #0 + + + value2 + GPDMA Enabled. + #1 + + + + + + + CHENREG + GPDMA Channel Enable Register + 0x0E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WE_CH + Channel enable write enable + 8 + 11 + write-only + + + CH + Enables/Disables the channel + 0 + 3 + read-write + + + value1 + Disable the Channel + #0 + + + value2 + Enable the Channel + #1 + + + + + + + ID + GPDMA1 ID Register + 0x0E8 + 32 + 0x00B0C000 + 0xFFFFFF00 + + + VALUE + Hardcoded GPDMA Peripheral ID + 0 + 31 + read-only + + + + + TYPE + GPDMA Component Type + 0x138 + 32 + 0x44571110 + 0xFFFFFFFF + + + VALUE + Component Type + 0 + 31 + read-only + + + + + VERSION + DMA Component Version + 0x13C + 32 + 0x3231342A + 0xFFFFFFFF + + + VALUE + Version number of the component + 0 + 31 + read-only + + + + + + + GPDMA1_CH0 + General Purpose DMA Unit 1 + GPDMA + GPDMA1_CH + 0x50018000 + + 0x0 + 0x55 + registers + + + + SAR + Source Address Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + SAR + Current Source Address of DMA transfer + 0 + 31 + read-write + + + + + DAR + Destination Address Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAR + Current Destination address of DMA transfer + 0 + 31 + read-write + + + + + CTLL + Control Register Low + 0x18 + 32 + 0x00304801 + 0xFFFFFFFF + + + TT_FC + Transfer Type and Flow Control + 20 + 22 + read-write + + + SRC_MSIZE + Source Burst Transaction Length + 14 + 16 + read-write + + + DEST_MSIZE + Destination Burst Transaction Length + 11 + 13 + read-write + + + SINC + Source Address Increment + 9 + 10 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + DINC + Destination Address Increment + 7 + 8 + read-write + + + value1 + Increment + #00 + + + value2 + Decrement + #01 + + + value3 + No change + #10 + + + + + SRC_TR_WIDTH + Source Transfer Width + 4 + 6 + read-write + + + DST_TR_WIDTH + Destination Transfer Width + 1 + 3 + read-write + + + INT_EN + Interrupt Enable Bit + 0 + 0 + read-write + + + + + CTLH + Control Register High + 0x1C + 32 + 0x00000002 + 0xFFFFFFFF + + + DONE + Done bit + 12 + 12 + read-write + + + BLOCK_TS + Block Transfer Size + 0 + 11 + read-write + + + + + CFGL + Configuration Register Low + 0x40 + 32 + 0x00000E00 + 0xFFFFFF0F + + + MAX_ABRST + Maximum AMBA Burst Length + 20 + 29 + read-write + + + SRC_HS_POL + Source Handshaking Interface Polarity + 19 + 19 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + DST_HS_POL + Destination Handshaking Interface Polarity + 18 + 18 + read-write + + + value1 + Active high + #0 + + + value2 + Active low + #1 + + + + + LOCK_B + Bus Lock Bit + 17 + 17 + read-write + + + LOCK_CH + Channel Lock Bit + 16 + 16 + read-write + + + LOCK_B_L + Bus Lock Level + 14 + 15 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + LOCK_CH_L + Channel Lock Level + 12 + 13 + read-write + + + value1 + Over complete DMA transfer + #00 + + + value2 + Over complete DMA block transfer + #01 + + + value3 + Over complete DMA transaction + #10 + + + + + HS_SEL_SRC + Source Software or Hardware Handshaking Select + 11 + 11 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware-initiated transaction requests are ignored. + #1 + + + + + HS_SEL_DST + Destination Software or Hardware Handshaking Select + 10 + 10 + read-write + + + value1 + Hardware handshaking interface. Software-initiated transaction requests are ignored. + #0 + + + value2 + Software handshaking interface. Hardware- initiated transaction requests are ignored. + #1 + + + + + FIFO_EMPTY + Indicates if there is data left in the channel FIFO + 9 + 9 + read-only + + + value1 + Channel FIFO empty + #1 + + + value2 + Channel FIFO not empty + #0 + + + + + CH_SUSP + Channel Suspend + 8 + 8 + read-write + + + value1 + Not suspended. + #0 + + + value2 + Suspend DMA transfer from the source. + #1 + + + + + CH_PRIOR + Channel priority + 5 + 7 + read-write + + + + + CFGH + Configuration Register High + 0x44 + 32 + 0x00000004 + 0xFFFFFFFF + + + DEST_PER + Destination Peripheral + 11 + 14 + read-write + + + SRC_PER + Source Peripheral + 7 + 10 + read-write + + + PROTCTL + Protection Control + 2 + 4 + read-write + + + FIFO_MODE + FIFO Mode Select + 1 + 1 + read-write + + + value1 + Space/data available for single AHB transfer of the specified transfer width. + #0 + + + value2 + Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. + #1 + + + + + FCMODE + Flow Control Mode + 0 + 0 + read-write + + + value1 + Source transaction requests are serviced when they occur. Data pre-fetching is enabled. + #0 + + + value2 + Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. + #1 + + + + + + + + + GPDMA1_CH1 + General Purpose DMA Unit 1 + GPDMA + 0x50018058 + + 0x0 + 0x55 + registers + + + + GPDMA1_CH2 + General Purpose DMA Unit 1 + GPDMA + 0x500180B0 + + 0x0 + 0x55 + registers + + + + GPDMA1_CH3 + General Purpose DMA Unit 1 + GPDMA + 0x50018108 + + 0x0 + 0x55 + registers + + + + FCE + Flexible CRC Engine + FCE + 0x50020000 + + 0x0 + 0x20 + registers + + + FCE0_0 + Flexible CRC Engine + 104 + + + + CLC + Clock Control Register + 0x00 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + + + ID + Module Identification Register + 0x08 + 32 + 0x00CAC001 + 0xFFFFFFFF + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + + + FCE_KE0 + Flexible CRC Engine + FCE + FCE_KE + 0x50020020 + + 0x0 + 0x20 + registers + + + + IR + Input Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + IR + Input Register + 0 + 31 + read-write + + + + + RES + CRC Result Register + 0x04 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RES + Result Register + 0 + 31 + read-only + + + + + CFG + CRC Configuration Register + 0x08 + 32 + 0x00000700 + 0xFFFFFFFF + + + CMI + CRC Mismatch Interrupt + 0 + 0 + read-write + + + value1 + CRC Mismatch Interrupt is disabled + #0 + + + value2 + CRC Mismatch Interrupt is enabled + #1 + + + + + CEI + Configuration Error Interrupt + 1 + 1 + read-write + + + value1 + Configuration Error Interrupt is disabled + #0 + + + value2 + Configuration Error Interrupt is enabled + #1 + + + + + LEI + Length Error Interrupt + 2 + 2 + read-write + + + value1 + Length Error Interrupt is disabled + #0 + + + value2 + Length Error Interrupt is enabled + #1 + + + + + BEI + Bus Error Interrupt + 3 + 3 + read-write + + + value1 + Bus Error Interrupt is disabled + #0 + + + value2 + Bus Error Interrupt is enabled + #1 + + + + + CCE + CRC Check Comparison + 4 + 4 + read-write + + + value1 + CRC check comparison at the end of a message is disabled + #0 + + + value2 + CRC check comparison at the end of a message is enabled + #1 + + + + + ALR + Automatic Length Reload + 5 + 5 + read-write + + + value1 + Disables automatic reload of the LENGTH field. + #0 + + + value2 + Enables automatic reload of the LENGTH field at the end of a message. + #1 + + + + + REFIN + IR Byte Wise Reflection + 8 + 8 + read-write + + + value1 + IR Byte Wise Reflection is disabled + #0 + + + value2 + IR Byte Wise Reflection is enabled + #1 + + + + + REFOUT + CRC 32-Bit Wise Reflection + 9 + 9 + read-write + + + value1 + CRC 32-bit wise is disabled + #0 + + + value2 + CRC 32-bit wise is enabled + #1 + + + + + XSEL + Selects the value to be xored with the final CRC + 10 + 10 + read-write + + + value1 + 0x00000000 + #0 + + + value2 + 0xFFFFFFFF + #1 + + + + + + + STS + CRC Status Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + CMF + CRC Mismatch Flag + 0 + 0 + read-write + + + CEF + Configuration Error Flag + 1 + 1 + read-write + + + LEF + Length Error Flag + 2 + 2 + read-write + + + BEF + Bus Error Flag + 3 + 3 + read-write + + + + + LENGTH + CRC Length Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + LENGTH + Message Length Register + 0 + 15 + read-write + + + + + CHECK + CRC Check Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHECK + CHECK Register + 0 + 31 + read-write + + + + + CRC + CRC Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC + CRC Register + 0 + 31 + read-write + + + + + CTR + CRC Test Register + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + FCM + Force CRC Mismatch + 0 + 0 + read-write + + + FRM_CFG + Force CFG Register Mismatch + 1 + 1 + read-write + + + FRM_CHECK + Force Check Register Mismatch + 2 + 2 + read-write + + + + + + + FCE_KE1 + Flexible CRC Engine + FCE + 0x50020040 + + 0x0 + 0x20 + registers + + + + FCE_KE2 + Flexible CRC Engine + FCE + 0x50020060 + + 0x0 + 0x20 + registers + + + + FCE_KE3 + Flexible CRC Engine + FCE + 0x50020080 + + 0x0 + 0x20 + registers + + + + PBA0 + Peripheral Bridge AHB 0 + PBA + PBA + 0x40000000 + + 0x0 + 0x4000 + registers + + + + STS + Peripheral Bridge Status Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + WERR + Bufferable Write Access Error + 0 + 0 + read-write + + + value1 + no write error occurred. + #0 + + + value2 + write error occurred, interrupt request is pending. + #1 + + + + + + + WADDR + PBA Write Error Address Register + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + WADDR + Write Error Address + 0 + 31 + read-only + + + + + + + PBA1 + Peripheral Bridge AHB 1 + PBA + 0x48000000 + + 0x0 + 0x4000 + registers + + + + FLASH0 + Flash Memory Controller + FLASH + 0x58001000 + + 0x0 + 0x1400 + registers + + + + ID + Flash Module Identification Register + 0x1008 + 32 + 0x0092C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + FSR + Flash Status Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + PBUSY + Program Flash Busy + 0 + 0 + read-only + + + value1 + PFLASH ready, not busy; PFLASH in read mode. + #0 + + + value2 + PFLASH busy; PFLASH not in read mode. + #1 + + + + + FABUSY + Flash Array Busy + 1 + 1 + read-only + + + PROG + Programming State + 4 + 4 + read-only + + + value1 + There is no program operation requested or in progress or just finished. + #0 + + + value2 + Programming operation (write page) requested (from FIM) or in action or finished. + #1 + + + + + ERASE + Erase State + 5 + 5 + read-only + + + value1 + There is no erase operation requested or in progress or just finished + #0 + + + value2 + Erase operation requested (from FIM) or in action or finished. + #1 + + + + + PFPAGE + Program Flash in Page Mode + 6 + 6 + read-only + + + value1 + Program Flash not in page mode + #0 + + + value2 + Program Flash in page mode; assembly buffer of PFLASH (256 byte) is in use (being filled up) + #1 + + + + + PFOPER + Program Flash Operation Error + 8 + 8 + read-only + + + value1 + No operation error reported by Program Flash + #0 + + + value2 + Flash array operation aborted, because of a Flash array failure, e.g. an ECC error in microcode. + #1 + + + + + SQER + Command Sequence Error + 10 + 10 + read-only + + + value1 + No sequence error + #0 + + + value2 + Command state machine operation unsuccessful because of improper address or command sequence. + #1 + + + + + PROER + Protection Error + 11 + 11 + read-only + + + value1 + No protection error + #0 + + + value2 + Protection error. + #1 + + + + + PFSBER + PFLASH Single-Bit Error and Correction + 12 + 12 + read-only + + + value1 + No Single-Bit Error detected during read access to PFLASH + #0 + + + value2 + Single-Bit Error detected and corrected + #1 + + + + + PFDBER + PFLASH Double-Bit Error + 14 + 14 + read-only + + + value1 + No Double-Bit Error detected during read access to PFLASH + #0 + + + value2 + Double-Bit Error detected in PFLASH + #1 + + + + + PROIN + Protection Installed + 16 + 16 + read-only + + + value1 + No protection is installed + #0 + + + value2 + Read or/and write protection for one or more users is configured and correctly confirmed in the User Configuration Block(s). + #1 + + + + + RPROIN + Read Protection Installed + 18 + 18 + read-only + + + value1 + No read protection installed + #0 + + + value2 + Read protection and global write protection is configured and correctly confirmed in the User Configuration Block 0. + #1 + + + + + RPRODIS + Read Protection Disable State + 19 + 19 + read-only + + + value1 + Read protection (if installed) is not disabled + #0 + + + value2 + Read and global write protection is temporarily disabled. + #1 + + + + + WPROIN0 + Sector Write Protection Installed for User 0 + 21 + 21 + read-only + + + value1 + No write protection installed for user 0 + #0 + + + value2 + Sector write protection for user 0 is configured and correctly confirmed in the User Configuration Block 0. + #1 + + + + + WPROIN1 + Sector Write Protection Installed for User 1 + 22 + 22 + read-only + + + value1 + No write protection installed for user 1 + #0 + + + value2 + Sector write protection for user 1 is configured and correctly confirmed in the User Configuration Block 1. + #1 + + + + + WPROIN2 + Sector OTP Protection Installed for User 2 + 23 + 23 + read-only + + + value1 + No OTP write protection installed for user 2 + #0 + + + value2 + Sector OTP write protection with ROM functionality is configured and correctly confirmed in the UCB2. The protection is locked for ever. + #1 + + + + + WPRODIS0 + Sector Write Protection Disabled for User 0 + 25 + 25 + read-only + + + value1 + All protected sectors of user 0 are locked if write protection is installed + #0 + + + value2 + All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection. + #1 + + + + + WPRODIS1 + Sector Write Protection Disabled for User 1 + 26 + 26 + read-only + + + value1 + All protected sectors of user 1 are locked if write protection is installed + #0 + + + value2 + All write-protected sectors of user 1 are temporarily unlocked, if not coincidently locked by user 0 or user 2 or via read protection. + #1 + + + + + SLM + Flash Sleep Mode + 28 + 28 + read-only + + + value1 + Flash not in sleep mode + #0 + + + value2 + Flash is in sleep or shut down mode + #1 + + + + + VER + Verify Error + 31 + 31 + read-only + + + value1 + The page is correctly programmed or the sector correctly erased. All programmed or erased bits have full expected quality. + #0 + + + value2 + A program verify error or an erase verify error has been detected. Full quality (retention time) of all programmed ("1") or erased ("0") bits cannot be guaranteed. + #1 + + + + + + + FCON + Flash Configuration Register + 0x1014 + 32 + 0x00000006 + 0xFFF0FFFF + + + WSPFLASH + Wait States for read access to PFLASH + 0 + 3 + read-write + + + value1 + PFLASH access in one clock cycle + #0000 + + + value2 + PFLASH access in one clock cycle + #0001 + + + value3 + PFLASH access in two clock cycles + #0010 + + + value4 + PFLASH access in three clock cycles + #0011 + + + value5 + PFLASH access in fifteen clock cycles. + #1111 + + + + + WSECPF + Wait State for Error Correction of PFLASH + 4 + 4 + read-write + + + value1 + No additional wait state for error correction + #0 + + + value2 + One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer. + #1 + + + + + IDLE + Dynamic Flash Idle + 13 + 13 + read-write + + + value1 + Normal/standard Flash read operation + #0 + + + value2 + Dynamic idle of Program Flash enabled for power saving; static prefetching disabled + #1 + + + + + ESLDIS + External Sleep Request Disable + 14 + 14 + read-write + + + value1 + External sleep request signal input is enabled + #0 + + + value2 + Externally requested Flash sleep is disabled + #1 + + + + + SLEEP + Flash SLEEP + 15 + 15 + read-write + + + value1 + Normal state or wake-up + #0 + + + value2 + Flash sleep mode is requested + #1 + + + + + RPA + Read Protection Activated + 16 + 16 + read-only + + + value1 + The Flash-internal read protection is not activated. Bits DCF, DDF are not taken into account. Bits DCF, DDFx can be cleared + #0 + + + value2 + The Flash-internal read protection is activated. Bits DCF, DDF are enabled and evaluated. + #1 + + + + + DCF + Disable Code Fetch from Flash Memory + 17 + 17 + read-write + + + value1 + Code fetching from the Flash memory area is allowed. + #0 + + + value2 + Code fetching from the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. + #1 + + + + + DDF + Disable Any Data Fetch from Flash + 18 + 18 + read-write + + + value1 + Data read access to the Flash memory area is allowed. + #0 + + + value2 + Data read access to the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. + #1 + + + + + VOPERM + Verify and Operation Error Interrupt Mask + 24 + 24 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + Flash interrupt because of Verify Error or Operation Error in Flash array (FSI) is enabled + #1 + + + + + SQERM + Command Sequence Error Interrupt Mask + 25 + 25 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + Flash interrupt because of Sequence Error is enabled + #1 + + + + + PROERM + Protection Error Interrupt Mask + 26 + 26 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + Flash interrupt because of Protection Error is enabled + #1 + + + + + PFSBERM + PFLASH Single-Bit Error Interrupt Mask + 27 + 27 + read-write + + + value1 + No Single-Bit Error interrupt enabled + #0 + + + value2 + Single-Bit Error interrupt enabled for PFLASH + #1 + + + + + PFDBERM + PFLASH Double-Bit Error Interrupt Mask + 29 + 29 + read-write + + + value1 + Double-Bit Error interrupt for PFLASH not enabled + #0 + + + value2 + Double-Bit Error interrupt for PFLASH enabled. Especially intended for margin check + #1 + + + + + EOBM + End of Busy Interrupt Mask + 31 + 31 + read-write + + + value1 + Interrupt not enabled + #0 + + + value2 + EOB interrupt is enabled + #1 + + + + + + + MARP + Margin Control Register PFLASH + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + MARGIN + PFLASH Margin Selection + 0 + 3 + read-write + + + value1 + Standard (default) margin. + #0000 + + + value2 + Tight margin for 0 (low) level. Suboptimal 0-bits are read as 1s. + #0001 + + + value3 + Tight margin for 1 (high) level. Suboptimal 1-bits are read as 0s. + #0100 + + + + + TRAPDIS + PFLASH Double-Bit Error Trap Disable + 15 + 15 + read-write + + + value1 + If a double-bit error occurs in PFLASH, a bus error trap is generated. + #0 + + + value2 + The double-bit error trap is disabled. Shall be used only during margin check + #1 + + + + + + + PROCON0 + Flash Protection Configuration Register User 0 + 0x1020 + 32 + 0x00000000 + 0xFFFF0000 + + + S0L + Sector 0 Locked for Write Protection by User 0 + 0 + 0 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S1L + Sector 1 Locked for Write Protection by User 0 + 1 + 1 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S2L + Sector 2 Locked for Write Protection by User 0 + 2 + 2 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S3L + Sector 3 Locked for Write Protection by User 0 + 3 + 3 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S4L + Sector 4 Locked for Write Protection by User 0 + 4 + 4 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S5L + Sector 5 Locked for Write Protection by User 0 + 5 + 5 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S6L + Sector 6 Locked for Write Protection by User 0 + 6 + 6 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S7L + Sector 7 Locked for Write Protection by User 0 + 7 + 7 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S8L + Sector 8 Locked for Write Protection by User 0 + 8 + 8 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S9L + Sector 9 Locked for Write Protection by User 0 + 9 + 9 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S10_S11L + Sectors 10 and 11 Locked for Write Protection by User 0 + 10 + 10 + read-only + + + value1 + No write protection is configured for sectors 10+11. + #0 + + + value2 + Write protection is configured for sectors 10+11. + #1 + + + + + S12_S13L + Sectors 12 and 13 Locked for Write Protection by User 0 + 11 + 11 + read-only + + + value1 + No write protection is configured for sectors 12+13. + #0 + + + value2 + Write protection is configured for sectors 12+13. + #1 + + + + + S14_S15L + Sectors 14 and 15 Locked for Write Protection by User 0 + 12 + 12 + read-only + + + value1 + No write protection is configured for sectors 14+15. + #0 + + + value2 + Write protection is configured for sectors 14+15. + #1 + + + + + RPRO + Read Protection Configuration + 15 + 15 + read-only + + + value1 + No read protection configured + #0 + + + value2 + Read protection and global write protection is configured by user 0 (master user) + #1 + + + + + + + PROCON1 + Flash Protection Configuration Register User 1 + 0x1024 + 32 + 0x00000000 + 0xFFFF0000 + + + S0L + Sector 0 Locked for Write Protection by User 1 + 0 + 0 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S1L + Sector 1 Locked for Write Protection by User 1 + 1 + 1 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S2L + Sector 2 Locked for Write Protection by User 1 + 2 + 2 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S3L + Sector 3 Locked for Write Protection by User 1 + 3 + 3 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S4L + Sector 4 Locked for Write Protection by User 1 + 4 + 4 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S5L + Sector 5 Locked for Write Protection by User 1 + 5 + 5 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S6L + Sector 6 Locked for Write Protection by User 1 + 6 + 6 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S7L + Sector 7 Locked for Write Protection by User 1 + 7 + 7 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S8L + Sector 8 Locked for Write Protection by User 1 + 8 + 8 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S9L + Sector 9 Locked for Write Protection by User 1 + 9 + 9 + read-only + + + value1 + No write protection is configured for sector n. + #0 + + + value2 + Write protection is configured for sector n. + #1 + + + + + S10_S11L + Sectors 10 and 11 Locked for Write Protection by User 1 + 10 + 10 + read-only + + + value1 + No write protection is configured for sectors 10+11. + #0 + + + value2 + Write protection is configured for sectors 10+11. + #1 + + + + + S12_S13L + Sectors 12 and 13 Locked for Write Protection by User 1 + 11 + 11 + read-only + + + value1 + No write protection is configured for sectors 12+13. + #0 + + + value2 + Write protection is configured for sectors 12+13. + #1 + + + + + S14_S15L + Sectors 14 and 15 Locked for Write Protection by User 1 + 12 + 12 + read-only + + + value1 + No write protection is configured for sectors 14+15. + #0 + + + value2 + Write protection is configured for sectors 14+15. + #1 + + + + + PSR + Physical Sector Repair + 16 + 16 + read-only + + + value1 + Physical Sector Repair command disabled; Erase Physical Sector command sequence available. + #0 + + + value2 + Physical Sector Repair command sequence enabled; Erase Physical Sector command sequence disabled. + #1 + + + + + + + PROCON2 + Flash Protection Configuration Register User 2 + 0x1028 + 32 + 0x00000000 + 0xFFFF0000 + + + S0ROM + Sector 0 Locked Forever by User 2 + 0 + 0 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S1ROM + Sector 1 Locked Forever by User 2 + 1 + 1 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S2ROM + Sector 2 Locked Forever by User 2 + 2 + 2 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S3ROM + Sector 3 Locked Forever by User 2 + 3 + 3 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S4ROM + Sector 4 Locked Forever by User 2 + 4 + 4 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S5ROM + Sector 5 Locked Forever by User 2 + 5 + 5 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S6ROM + Sector 6 Locked Forever by User 2 + 6 + 6 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S7ROM + Sector 7 Locked Forever by User 2 + 7 + 7 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S8ROM + Sector 8 Locked Forever by User 2 + 8 + 8 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S9ROM + Sector 9 Locked Forever by User 2 + 9 + 9 + read-only + + + value1 + No ROM functionality configured for sector n. + #0 + + + value2 + ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. + #1 + + + + + S10_S11ROM + Sectors 10 and 11 Locked Forever by User 2 + 10 + 10 + read-only + + + value1 + No ROM functionality is configured for sectors 10+11. + #0 + + + value2 + ROM functionality is configured for sectors 10+11. + #1 + + + + + S12_S13ROM + Sectors 12 and 13 Locked Forever by User 2 + 11 + 11 + read-only + + + value1 + No ROM functionality is configured for sectors 12+13. + #0 + + + value2 + ROM functionality is configured for sectors 12+13. + #1 + + + + + S14_S15ROM + Sectors 14 and 15 Locked Forever by User 2 + 12 + 12 + read-only + + + value1 + No ROM functionality is configured for sectors 14+15. + #0 + + + value2 + ROM functionality is configured for sectors 14+15. + #1 + + + + + + + + + PREF + Prefetch Unit + 0x58004000 + + 0 + 4 + registers + + + + PCON + Prefetch Configuration Register + 0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IBYP + Instruction Prefetch Buffer Bypass + 0 + 0 + read-write + + + value1 + Instruction prefetch buffer not bypassed. + #0 + + + value2 + Instruction prefetch buffer bypassed. + #1 + + + + + IINV + Instruction Prefetch Buffer Invalidate + 1 + 1 + write-only + + + value1 + No effect. + #0 + + + value2 + Initiate invalidation of entire instruction cache. + #1 + + + + + DBYP + Data Buffer Bypass + 4 + 4 + read-write + + + value1 + Prefetch Data buffer not bypassed. + #0 + + + value2 + Prefetch Data buffer bypassed. + #1 + + + + + + + + + PMU0 + Program Management Unit + PMU + 0x58000508 + + 0 + 4 + registers + + + PMU0_0 + Program Management Unit + 12 + + + + ID + PMU0 Identification Register + 0 + 32 + 0x0091C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + + + WDT + Watch Dog Timer + 0x50008000 + + 0x0 + 0x4000 + registers + + + + ID + WDT ID Register + 0x00 + 32 + 0x00ADC000 + 0xFFFFFF00 + + + MOD_REV + Module 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0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43 + CCU43 Gating Set + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + LEDTSCU0 + LEDTS Gating Set + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + MCAN0 + MultiCAN Gating Set + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + DAC + DAC Gating Set + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + MMCI + MMC Interface Gating Set + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + USIC1 + USIC1 Gating Set + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + USIC2 + USIC2 Gating Set + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + PPORTS + PORTS Gating Set + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + + + CGATCLR1 + Peripheral 1 Clock Gating Clear + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43 + CCU43 Gating Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + LEDTSCU0 + LEDTS Gating Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + MCAN0 + MultiCAN Gating Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + DAC + DAC Gating Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + MMCI + MMC Interface Gating Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + USIC1 + USIC1 Gating Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + USIC2 + USIC2 Gating Clear + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + PPORTS + PORTS Gating Clear + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + + + CGATSTAT2 + Peripheral 2 Clock Gating Status + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT + WDT Gating Status + 1 + 1 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + ETH0 + ETH0 Gating Status + 2 + 2 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + DMA0 + DMA0 Gating Status + 4 + 4 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + DMA1 + DMA1 Gating Status + 5 + 5 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + FCE + FCE Gating Status + 6 + 6 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + USB + USB Gating Status + 7 + 7 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + + + CGATSET2 + Peripheral 2 Clock Gating Set + 0x5C + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT + WDT Gating Set + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + ETH0 + ETH0 Gating Set + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + DMA0 + DMA0 Gating Set + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + DMA1 + DMA1 Gating Set + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + FCE + FCE Gating Set + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + USB + USB Gating Set + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + + + CGATCLR2 + Peripheral 2 Clock Gating Clear + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT + WDT Gating Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + ETH0 + ETH0 Gating Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + DMA0 + DMA0 Gating Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + DMA1 + DMA1 Gating Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + FCE + FCE Gating Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + USB + USB Gating Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + + + CGATSTAT3 + Peripheral 3 Clock Gating Status + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBU + EBU Gating Status + 2 + 2 + read-only + + + value1 + Gating de-asserted + #0 + + + value2 + Gating asserted + #1 + + + + + + + CGATSET3 + Peripheral 3 Clock Gating Set + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBU + EBU Gating Set + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Enable gating + #1 + + + + + + + CGATCLR3 + Peripheral 3 Clock Gating Clear + 0x6C + 32 + 0x00000000 + 0xFFFFFFFF + + + EBU + EBU Gating Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Disable gating + #1 + + + + + + + + + SCU_OSC + System Control Unit + SCU + 0x50004700 + + 0x0 + 0x10 + registers + + + + OSCHPSTAT + OSC_HP Status Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + X1D + XTAL1 Data Value + 0 + 0 + read-only + + + + + OSCHPCTRL + OSC_HP Control Register + 0x04 + 32 + 0x0000003C + 0xFFFFFFFF + + + X1DEN + XTAL1 Data Enable + 0 + 0 + read-write + + + value1 + Bit X1D is not updated + #0 + + + value2 + Bit X1D can be updated + #1 + + + + + SHBY + Shaper Bypass + 1 + 1 + read-write + + + value1 + The shaper is not bypassed + #0 + + + value2 + The shaper is bypassed + #1 + + + + + GAINSEL + Oscillator Gain Selection + 2 + 3 + read-write + + + value1 + The gain control is configured for frequencies from 4 MHz to 8 MHz + #00 + + + value2 + The gain control is configured for frequencies from 4 MHz to 16 MHz + #01 + + + value3 + The gain control is configured for frequencies from 4 MHz to 20 MHz + #10 + + + value4 + The gain control is configured for frequencies from 4 MHz to 25 MHz + #11 + + + + + MODE + Oscillator Mode + 4 + 5 + read-write + + + value1 + External Crystal Mode and External Input Clock Mode. The oscillator Power-Saving Mode is not entered. + #00 + + + value2 + OSC is disabled. The oscillator Power-Saving Mode is not entered. + #01 + + + value3 + External Input Clock Mode and the oscillator Power-Saving Mode is entered + #10 + + + value4 + OSC is disabled. The oscillator Power-Saving Mode is entered. + #11 + + + + + OSCVAL + OSC Frequency Value + 16 + 19 + read-write + + + + + CLKCALCONST + Clock Calibration Constant Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + CALIBCONST + Clock Calibration Constant Value + 0 + 3 + read-write + + + + + + + SCU_PLL + System Control Unit + SCU + 0x50004710 + + 0x0 + 0x38 + registers + + + + PLLSTAT + PLL Status Register + 0x00 + 32 + 0x00000002 + 0xFFFFFFFF + + + VCOBYST + VCO Bypass Status + 0 + 0 + read-only + + + value1 + Free-running / Normal Mode is entered + #0 + + + value2 + Prescaler Mode is entered + #1 + + + + + PWDSTAT + PLL Power-saving Mode Status + 1 + 1 + read-only + + + value1 + PLL Power-saving Mode was not entered + #0 + + + value2 + PLL Power-saving Mode was entered + #1 + + + + + VCOLOCK + PLL LOCK Status + 2 + 2 + read-only + + + value1 + PLL not locked + #0 + + + value2 + PLL locked + #1 + + + + + K1RDY + K1 Divider Ready Status + 4 + 4 + read-only + + + value1 + K1-Divider does not operate with the new value + #0 + + + value2 + K1-Divider operate with the new value + #1 + + + + + K2RDY + K2 Divider Ready Status + 5 + 5 + read-only + + + value1 + K2-Divider does not operate with the new value + #0 + + + value2 + K2-Divider operate with the new value + #1 + + + + + BY + Bypass Mode Status + 6 + 6 + read-only + + + value1 + Bypass Mode is not entered + #0 + + + value2 + Bypass Mode is entered. Input fOSC is selected as output fPLL. + #1 + + + + + PLLLV + Oscillator for PLL Valid Low Status Bit + 7 + 7 + read-only + + + value1 + The OSC frequency is not usable. Frequency fREF is too low. + #0 + + + value2 + The OSC frequency is usable + #1 + + + + + PLLHV + Oscillator for PLL Valid High Status Bit + 8 + 8 + read-only + + + value1 + The OSC frequency is not usable. Frequency fOSC is too high. + #0 + + + value2 + The OSC frequency is usable + #1 + + + + + PLLSP + Oscillator for PLL Valid Spike Status Bit + 9 + 9 + read-only + + + value1 + The OSC frequency is not usable. Spikes are detected that disturb a locked operation + #0 + + + value2 + The OSC frequency is usable + #1 + + + + + + + PLLCON0 + PLL Configuration 0 Register + 0x04 + 32 + 0x00030003 + 0xFFFFFFFF + + + VCOBYP + VCO Bypass + 0 + 0 + read-write + + + value1 + Normal operation, VCO is not bypassed + #0 + + + value2 + Prescaler Mode, VCO is bypassed + #1 + + + + + VCOPWD + VCO Power Saving Mode + 1 + 1 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The VCO is put into a Power Saving Mode and can no longer be used. Only the Bypass and Prescaler Mode are active if previously selected. + #1 + + + + + VCOTR + VCO Trim Control + 2 + 2 + read-write + + + value1 + VCO bandwidth is operation in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #0 + + + value2 + VCO bandwidth is operation in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #1 + + + + + FINDIS + Disconnect Oscillator from VCO + 4 + 4 + read-write + + + value1 + connect oscillator to the VCO part + #0 + + + value2 + disconnect oscillator from the VCO part. + #1 + + + + + OSCDISCDIS + Oscillator Disconnect Disable + 6 + 6 + read-write + + + value1 + In case of a PLL loss-of-lock bit FINDIS is set + #0 + + + value2 + In case of a PLL loss-of-lock bit FINDIS is cleared + #1 + + + + + PLLPWD + PLL Power Saving Mode + 16 + 16 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The complete PLL block is put into a Power Saving Mode and can no longer be used. Only the Bypass Mode is active if previously selected. + #1 + + + + + OSCRES + Oscillator Watchdog Reset + 17 + 17 + read-write + + + value1 + The Oscillator Watchdog of the PLL is not cleared and remains active + #0 + + + value2 + The Oscillator Watchdog of the PLL is cleared and restarted + #1 + + + + + RESLD + Restart VCO Lock Detection + 18 + 18 + write-only + + + AOTREN + Automatic Oscillator Calibration Enable + 19 + 19 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + FOTR + Factory Oscillator Calibration + 20 + 20 + read-write + + + value1 + No effect + #0 + + + value2 + Force fixed-value trimming + #1 + + + + + + + PLLCON1 + PLL Configuration 1 Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + K1DIV + K1-Divider Value + 0 + 6 + read-write + + + NDIV + N-Divider Value + 8 + 14 + read-write + + + K2DIV + K2-Divider Value + 16 + 22 + read-write + + + PDIV + P-Divider Value + 24 + 27 + read-write + + + + + PLLCON2 + PLL Configuration 2 Register + 0x0C + 32 + 0x00000001 + 0xFFFFFFFF + + + PINSEL + P-Divider Input Selection + 0 + 0 + read-write + + + value1 + PLL external oscillator selected + #0 + + + value2 + Backup clock fofi selected + #1 + + + + + K1INSEL + K1-Divider Input Selection + 8 + 8 + read-write + + + value1 + PLL external oscillator selected + #0 + + + value2 + Backup clock fofi selected + #1 + + + + + + + USBPLLSTAT + USB PLL Status Register + 0x10 + 32 + 0x00000002 + 0xFFFFFFFF + + + VCOBYST + VCO Bypass Status + 0 + 0 + read-only + + + value1 + Normal Mode is entered + #0 + + + value2 + Prescaler Mode is entered + #1 + + + + + PWDSTAT + PLL Power-saving Mode Status + 1 + 1 + read-only + + + value1 + PLL Power-saving Mode was not entered + #0 + + + value2 + PLL Power-saving Mode was entered + #1 + + + + + VCOLOCK + PLL VCO Lock Status + 2 + 2 + read-only + + + value1 + The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency. + #0 + + + value2 + The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation + #1 + + + + + BY + Bypass Mode Status + 6 + 6 + read-only + + + value1 + Bypass Mode is not entered + #0 + + + value2 + Bypass Mode is entered. Input fOSC is selected as output fPLL. + #1 + + + + + VCOLOCKED + PLL LOCK Status + 7 + 7 + read-only + + + value1 + PLL not locked + #0 + + + value2 + PLL locked + #1 + + + + + + + USBPLLCON + USB PLL Configuration Register + 0x14 + 32 + 0x00010003 + 0xFFFFFFFF + + + VCOBYP + VCO Bypass + 0 + 0 + read-write + + + value1 + Normal operation, VCO is not bypassed + #0 + + + value2 + Prescaler Mode, VCO is bypassed + #1 + + + + + VCOPWD + VCO Power Saving Mode + 1 + 1 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The VCO is put into a Power Saving Mode + #1 + + + + + VCOTR + VCO Trim Control + 2 + 2 + read-write + + + value1 + VCO bandwidth is operating in the normal range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #0 + + + value2 + VCO bandwidth is operating in the test range. VCO output frequency is between 260 and 520 MHz for a input frequency between 8 and 16 MHz. + #1 + + + + + FINDIS + Disconnect Oscillator from VCO + 4 + 4 + read-write + + + value1 + Connect oscillator to the VCO part + #0 + + + value2 + Disconnect oscillator from the VCO part. + #1 + + + + + OSCDISCDIS + Oscillator Disconnect Disable + 6 + 6 + read-write + + + value1 + In case of a PLL loss-of-lock bit FINDIS is set + #0 + + + value2 + In case of a PLL loss-of-lock bit FINDIS is cleared + #1 + + + + + NDIV + N-Divider Value + 8 + 14 + read-write + + + PLLPWD + PLL Power Saving Mode + 16 + 16 + read-write + + + value1 + Normal behavior + #0 + + + value2 + The complete PLL block is put into a Power Saving Mode. Only the Bypass Mode is active if previously selected. + #1 + + + + + RESLD + Restart VCO Lock Detection + 18 + 18 + write-only + + + PDIV + P-Divider Value + 24 + 27 + read-write + + + + + CLKMXSTAT + Clock Multiplexing Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SYSCLKMUX + Status of System Clock Multiplexing Upon Source Switching + 0 + 1 + read-only + + + value1 + fOFI clock active + #01 + + + value2 + fPLL clock active + #10 + + + + + + + + + SCU_GENERAL + System Control Unit + SCU + 0x50004000 + + 0x0 + 0x100 + registers + + + + ID + SCU Module ID Register + 0x0000 + 32 + 0x0090C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + IDCHIP + Chip ID Register + 0x0004 + 32 + 0x00000000 + 0x00000000 + + + IDCHIP + Chip ID + 0 + 31 + read-only + + + + + IDMANUF + Manufactory ID Register + 0x0008 + 32 + 0x00001820 + 0xFFFFFFFF + + + DEPT + Department Identification Number + 0 + 4 + read-only + + + MANUF + Manufacturer Identification Number + 5 + 15 + read-only + + + + + STCON + Startup Configuration Register + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + HWCON + HW Configuration + 0 + 1 + read-only + + + value1 + Normal mode, JTAG + #00 + + + value2 + ASC BSL enabled + #01 + + + value3 + BMI customized boot enabled + #10 + + + value4 + CAN BSL enabled + #11 + + + + + SWCON + SW Configuration + 8 + 11 + read-write + + + value1 + Normal mode, boot from Boot ROM + #0000 + + + value2 + ASC BSL enabled + #0001 + + + value3 + BMI customized boot enabled + #0010 + + + value4 + CAN BSL enabled + #0011 + + + value5 + Boot from Code SRAM + #0100 + + + value6 + Boot from alternate Flash Address 0 + #1000 + + + value7 + Boot from alternate Flash Address 1 + #1100 + + + value8 + Enable fallback Alternate Boot Mode (ABM) + #1110 + + + + + + + GPR0 + General Purpose Register 0 + 0x002C + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + User Data + 0 + 31 + read-write + + + + + GPR1 + General Purpose Register 1 + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + User Data + 0 + 31 + read-write + + + + + CCUCON + CCU Control Register + 0x004C + 32 + 0x00000000 + 0xFFFFFFFF + + + GSC40 + Global Start Control CCU40 + 0 + 0 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC41 + Global Start Control CCU41 + 1 + 1 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC42 + Global Start Control CCU42 + 2 + 2 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC43 + Global Start Control CCU43 + 3 + 3 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC80 + Global Start Control CCU80 + 8 + 8 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + GSC81 + Global Start Control CCU81 + 9 + 9 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + + + DTSCON + Die Temperature Sensor Control Register + 0x008C + 32 + 0x00000001 + 0xFFFFFFFF + + + PWD + Sensor Power Down + 0 + 0 + read-write + + + value1 + The DTS is powered + #0 + + + value2 + The DTS is not powered + #1 + + + + + START + Sensor Measurement Start + 1 + 1 + write-only + + + value1 + No DTS measurement is started + #0 + + + value2 + A DTS measurement is started + #1 + + + + + OFFSET + Offset Calibration Value + 4 + 10 + read-write + + + GAIN + Gain Calibration Value + 11 + 16 + read-write + + + REFTRIM + Reference Trim Calibration Value + 17 + 19 + read-write + + + BGTRIM + Bandgap Trim Calibration Value + 20 + 23 + read-write + + + + + DTSSTAT + Die Temperature Sensor Status Register + 0x0090 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of the DTS Measurement + 0 + 9 + read-only + + + RDY + Sensor Ready Status + 14 + 14 + read-only + + + value1 + The DTS is not ready + #0 + + + value2 + The DTS is ready + #1 + + + + + BUSY + Sensor Busy Status + 15 + 15 + read-only + + + value1 + not busy + #0 + + + value2 + busy + #1 + + + + + + + SDMMCDEL + SD-MMC Delay Control Register + 0x009C + 32 + 0x00000000 + 0xFFFFFFFF + + + TAPEN + Enable delay on the CMD/DAT out lines + 0 + 0 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + TAPDEL + Number of Delay Elements Select + 4 + 7 + read-write + + + + + G0ORCEN + Out of Range Comparator Enable Register 0 + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENORC6 + Enable Out of Range Comparator, Channel 6 + 6 + 6 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + ENORC7 + Enable Out of Range Comparator, Channel 7 + 7 + 7 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + + + G1ORCEN + Out of Range Comparator Enable Register 1 + 0x00A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENORC6 + Enable Out of Range Comparator, Channel 6 + 6 + 6 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + ENORC7 + Enable Out of Range Comparator, Channel 7 + 7 + 7 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + + + MIRRSTS + Mirror Write Status Register + 0x00C4 + 32 + 0x00000000 + 0xFFFFFFFF + + + HDCLR + HDCLR Mirror Register Write Status + 1 + 1 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + HDSET + HDSET Mirror Register Write Status + 2 + 2 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + HDCR + HDCR Mirror Register Write Status + 3 + 3 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + OSCSICTRL + OSCSICTRL Mirror Register Write Status + 5 + 5 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + OSCULCTRL + OSCULCTRL Mirror Register Write Status + 7 + 7 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_CTR + RTC CTR Mirror Register Write Status + 8 + 8 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_ATIM0 + RTC ATIM0 Mirror Register Write Status + 9 + 9 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_ATIM1 + RTC ATIM1 Mirror Register Write Status + 10 + 10 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_TIM0 + RTC TIM0 Mirror Register Write Status + 11 + 11 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_TIM1 + RTC TIM1 Mirror Register Write Status + 12 + 12 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RMX + Retention Memory Access Register Update Status + 13 + 13 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_MSKSR + RTC MSKSSR Mirror Register Write Status + 14 + 14 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + RTC_CLRSR + RTC CLRSR Mirror Register Write Status + 15 + 15 + read-only + + + value1 + Ready + #0 + + + value2 + Busy + #1 + + + + + + + RMACR + Retention Memory Access Control Register + 0x00C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDWR + Hibernate Retention Memory Register Update Control + 0 + 0 + read-write + + + value1 + transfer data from Retention Memory in Hibernate domain to RMDATA register + #0 + + + value2 + transfer data from RMDATA into Retention Memory in Hibernate domain + #1 + + + + + ADDR + Hibernate Retention Memory Register Address Select + 16 + 19 + read-write + + + + + RMDATA + Retention Memory Access Data Register + 0x00CC + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Hibernate Retention Memory Data + 0 + 31 + read-write + + + + + + + SCU_INTERRUPT + System Control Unit + SCU + 0x50004074 + + 0x0 + 0x18 + registers + + + SCU_0 + System Control + 0 + + + + SRSTAT + SCU Service Request Status + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRWARN + WDT pre-warning Interrupt Status + 0 + 0 + read-only + + + value1 + Inactive + #0 + + + value2 + Active + #1 + + + + + PI + RTC Periodic Interrupt Status + 1 + 1 + read-only + + + AI + Alarm Interrupt Status + 2 + 2 + read-only + + + DLROVR + DLR Request Overrun Interrupt Status + 3 + 3 + read-only + + + HDCLR + HDCLR Mirror Register Update Status + 17 + 17 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + HDSET + HDSET Mirror Register Update Status + 18 + 18 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + HDCR + HDCR Mirror Register Update Status + 19 + 19 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + OSCSICTRL + OSCSICTRL Mirror Register Update Status + 21 + 21 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + OSCULCTRL + OSCULCTRL Mirror Register Update Status + 23 + 23 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_CTR + RTC CTR Mirror Register Update Status + 24 + 24 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_ATIM0 + RTC ATIM0 Mirror Register Update Status + 25 + 25 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_ATIM1 + RTC ATIM1 Mirror Register Update Status + 26 + 26 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_TIM0 + RTC TIM0 Mirror Register Update Status + 27 + 27 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RTC_TIM1 + RTC TIM1 Mirror Register Update Status + 28 + 28 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + RMX + Retention Memory Mirror Register Update Status + 29 + 29 + read-only + + + value1 + Not updated + #0 + + + value2 + Update completed + #1 + + + + + + + SRRAW + SCU Raw Service Request Status + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRWARN + WDT pre-warning Interrupt Status Before Masking + 0 + 0 + read-only + + + value1 + Inactive + #0 + + + value2 + Active + #1 + + + + + PI + RTC Raw Periodic Interrupt Status Before Masking + 1 + 1 + read-only + + + AI + RTC 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Memory + 17 + 17 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + PETEETH0RX + Parity Error Trap Enable for ETH0 RX Memory + 18 + 18 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + PETESD0 + Parity Error Trap Enable for SDMMC SRAM 0 Memory + 19 + 19 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + PETESD1 + Parity Error Trap Enable for SDMMC SRAM 1 Memory + 20 + 20 + read-write + + + value1 + Disabled + #0 + + + value2 + Enabled + #1 + + + + + + + PERSTEN + Parity Error Reset Enable Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + RSEN + System Reset Enable upon Parity Error Trap + 0 + 0 + read-write + + + value1 + Reset request disabled + #0 + + + value2 + Reset request enabled + #1 + + + + + + + PEFLAG + Parity Error Flag Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PEFPS + Parity Error Flag for PSRAM + 0 + 0 + read-write + + + value1 + No parity error detected + #0 + + + value2 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read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTEU2 + Test Enable Control for USIC2 Memory + 10 + 10 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTEMC + Test Enable Control for MultiCAN Memory + 12 + 12 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTEPPRF + Test Enable Control for PMU Prefetch Memory + 13 + 13 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTUSB + Test Enable Control for USB Memory + 16 + 16 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTETH0TX + Test Enable Control for ETH TX Memory + 17 + 17 + read-write + + + value1 + Standard operation + #0 + + + value2 + Parity bits under test + #1 + + + + + MTETH0RX + Test Enable Control for ETH RX Memory + 18 + 18 + read-write + + + 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pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + SVCOLCKT + System VCO Lock Trap Raw Status + 2 + 2 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + UVCOLCKT + USB VCO Lock Trap Raw Status + 3 + 3 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + PET + Parity Error Trap Raw Status + 4 + 4 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + BRWNT + Brown Out Trap Raw Status + 5 + 5 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + ULPWDGT + OSC_ULP Oscillator Watchdog Trap Raw Status + 6 + 6 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap request + #1 + + + + + BWERR0T + Peripheral Bridge 0 Trap Raw Status + 7 + 7 + read-only + + + value1 + No pending trap request + #0 + + + value2 + Pending trap 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+ 0x00000000 + 0xFFFFFFFF + + + EPEV + Wake-up Pin Event Positive Edge + 0 + 0 + read-only + + + value1 + Wake-up on positive edge pin event inactive + #0 + + + value2 + Wake-up on positive edge pin event active + #1 + + + + + ENEV + Wake-up Pin Event Negative Edge + 1 + 1 + read-only + + + value1 + Wake-up on negative edge pin event inactive + #0 + + + value2 + Wake-up on negative edge pin event active + #1 + + + + + RTCEV + RTC Event + 2 + 2 + read-only + + + value1 + Wake-up on RTC event inactive + #0 + + + value2 + Wake-up on RTC event active + #1 + + + + + ULPWDG + ULP WDG Alarm Status + 3 + 3 + read-only + + + value1 + Watchdog alarm did not occur + #0 + + + value2 + Watchdog alarm occurred + #1 + + + + + HIBNOUT + Hibernate Control Status + 4 + 4 + read-only + + + value1 + Hibernate not driven active to pads + #0 + + + value2 + Hibernate driven active to pads + #1 + + + + + + + HDCLR + Hibernate Domain Status Clear Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPEV + Wake-up Pin Event Positive Edge Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Clear wake-up event + #1 + + + + + ENEV + Wake-up Pin Event Negative Edge Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Clear wake-up event + #1 + + + + + RTCEV + RTC Event Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Clear wake-up event + #1 + + + + + ULPWDG + ULP WDG Alarm Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Clear watchdog alarm + #1 + + + + + + + HDSET + Hibernate Domain Status Set Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPEV + Wake-up Pin Event Positive Edge Set + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Set wake-up event + #1 + + + + + ENEV + Wake-up Pin Event Negative Edge Set + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Set wake-up event + #1 + + + + + RTCEV + RTC Event Set + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Set wake-up event + #1 + + + + + ULPWDG + ULP WDG Alarm Set + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Set watchdog alarm + #1 + + + + + + + HDCR + Hibernate Domain Control Register + 0x0C + 32 + 0x000C2000 + 0xFFFFFFFF + + + WKPEP + Wake-Up on Pin Event Positive Edge Enable + 0 + 0 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + WKPEN + Wake-up on Pin Event Negative Edge Enable + 1 + 1 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + RTCE + Wake-up on RTC Event Enable + 2 + 2 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + ULPWDGEN + ULP WDG Alarm Enable + 3 + 3 + read-write + + + value1 + Wake-up event disabled + #0 + + + value2 + Wake-up event enabled + #1 + + + + + HIB + Hibernate Request Value Set + 4 + 4 + read-write + + + value1 + External hibernate request inactive + #0 + + + value2 + External hibernate request active + #1 + + + + + RCS + fRTC Clock Selection + 6 + 6 + read-write + + + value1 + fOSI selected + #0 + + + value2 + fULP selected + #1 + + + + + STDBYSEL + fSTDBY Clock Selection + 7 + 7 + read-write + + + value1 + fOSI selected + #0 + + + value2 + fULP selected + #1 + + + + + WKUPSEL + Wake-Up from Hibernate Trigger Input Selection + 8 + 8 + read-write + + + value1 + HIB_IO_1 pin selected + #0 + + + value2 + HIB_IO_0 pin selected + #1 + + + + + GPI0SEL + General Purpose Input 0 Selection + 10 + 10 + read-write + + + value1 + HIB_IO_1 pin selected + #0 + + + value2 + HIB_IO_0 pin selected + #1 + + + + + HIBIO0POL + HIBIO0 Polarity Set + 12 + 12 + read-write + + + value1 + Direct value + #0 + + + value2 + Inverted value + #1 + + + + + HIBIO1POL + HIBIO1 Polarity Set + 13 + 13 + read-write + + + value1 + Direct value + #0 + + + value2 + Inverted value + #1 + + + + + HIBIO0SEL + HIB_IO_0 Pin I/O Control (default HIBOUT) + 16 + 19 + read-write + + + value1 + Direct input, No input pull device connected + #0000 + + + value2 + Direct input, Input pull-down device connected + #0001 + + + value3 + Direct input, Input pull-up device connected + #0010 + + + value4 + Push-pull HIB Control output + #1000 + + + value5 + Push-pull WDT service output + #1001 + + + value6 + Push-pull GPIO output + #1010 + + + value7 + Open-drain HIB Control output + #1100 + + + value8 + Open-drain WDT service output + #1101 + + + value9 + Open-drain GPIO output + #1110 + + + value10 + Analog input + #1111 + + + + + HIBIO1SEL + HIB_IO_1 Pin I/O Control (Default WKUP) + 20 + 23 + read-write + + + value1 + Direct input, No input pull device connected + #0000 + + + value2 + Direct input, Input pull-down device connected + #0001 + + + value3 + Direct input, Input pull-up device connected + #0010 + + + value4 + Push-pull HIB Control output + #1000 + + + value5 + Push-pull WDT service output + #1001 + + + value6 + Push-pull GPIO output + #1010 + + + value7 + Open-drain HIB Control output + #1100 + + + value8 + Open-drain WDT service output + #1101 + + + value9 + Open-drain GPIO output + #1110 + + + value10 + Analog input + #1111 + + + + + + + OSCSICTRL + fOSI Control Register + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + PWD + Turn OFF the fOSI Clock Source + 0 + 0 + read-write + + + value1 + Enabled + #0 + + + value2 + Disabled + #1 + + + + + + + OSCULSTAT + OSC_ULP Status Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + X1D + XTAL1 Data Value + 0 + 0 + read-only + + + + + OSCULCTRL + OSC_ULP Control Register + 0x1C + 32 + 0x00000020 + 0xFFFFFFFF + + + X1DEN + XTAL1 Data General Purpose Input Enable + 0 + 0 + read-write + + + value1 + Data input inactivated, power down + #0 + + + value2 + Data input active + #1 + + + + + MODE + Oscillator Mode + 4 + 5 + read-write + + + value1 + Oscillator is enabled, in operation + #00 + + + value2 + Oscillator is enabled, in bypass mode + #01 + + + value3 + Oscillator in power down + #10 + + + value4 + Oscillator in power down, can be used as GPI + #11 + + + + + + + + + SCU_POWER + System Control Unit + SCU + 0x50004200 + + 0x0 + 0x100 + registers + + + + PWRSTAT + PCU Status Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIBEN + Hibernate Domain Enable Status + 0 + 0 + read-only + + + value1 + Inactive + #0 + + + value2 + Active + #1 + + + + + USBPHYPDQ + USB PHY Transceiver State + 16 + 16 + read-only + + + value1 + Power-down + #0 + + + value2 + Active + #1 + + + + + USBOTGEN + USB On-The-Go Comparators State + 17 + 17 + read-only + + + value1 + Power-down + #0 + + + value2 + Active + #1 + + + + + USBPUWQ + USB Weak Pull-Up at PADN State + 18 + 18 + read-only + + + value1 + Pull-up active + #0 + + + value2 + Pull-up not active + #1 + + + + + + + PWRSET + PCU Set Control Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIB + Set Hibernate Domain Enable + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Enable Hibernate domain + #1 + + + + + USBPHYPDQ + Set USB PHY Transceiver Disable + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + Active + #1 + + + + + USBOTGEN + Set USB On-The-Go Comparators Enable + 17 + 17 + write-only + + + value1 + No effect + #0 + + + value2 + Active + #1 + + + + + USBPUWQ + Set USB Weak Pull-Up at PADN Enable + 18 + 18 + write-only + + + value1 + No effect + #0 + + + value2 + Pull-up not active + #1 + + + + + + + PWRCLR + PCU Clear Control Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIB + Clear Disable Hibernate Domain + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Disable Hibernate domain + #1 + + + + + USBPHYPDQ + Clear USB PHY Transceiver Disable + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + Power-down + #1 + + + + + USBOTGEN + Clear USB On-The-Go Comparators Enable + 17 + 17 + write-only + + + value1 + No effect + #0 + + + value2 + Power-down + #1 + + + + + USBPUWQ + Clear USB Weak Pull-Up at PADN Enable + 18 + 18 + write-only + + + value1 + No effect + #0 + + + value2 + Pull-up active + #1 + + + + + + + EVRSTAT + EVR Status Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + OV13 + Regulator Overvoltage for 1.3 V + 1 + 1 + read-only + + + value1 + No overvoltage condition + #0 + + + value2 + Regulator is in overvoltage + #1 + + + + + + + EVRVADCSTAT + EVR VADC Status Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VADC13V + VADC 1.3 V Conversion Result + 0 + 7 + read-only + + + VADC33V + VADC 3.3 V Conversion Result + 8 + 15 + read-only + + + + + PWRMON + Power Monitor Control + 0x2C + 32 + 0x00000000 + 0xFFFFFFFF + + + THRS + Threshold + 0 + 7 + read-write + + + INTV + Interval + 8 + 15 + read-write + + + ENB + Enable + 16 + 16 + read-write + + + + + + + SCU_RESET + System Control Unit + SCU + 0x50004400 + + 0x0 + 0x100 + registers + + + + RSTSTAT + RCU Reset Status + 0x00 + 32 + 0x00000000 + 0xFFFF0000 + + + RSTSTAT + Reset Status Information + 0 + 7 + read-only + + + value1 + PORST reset + #00000001 + + + value2 + SWD reset + #00000010 + + + value3 + PV reset + #00000100 + + + value4 + CPU system reset + #00001000 + + + value5 + CPU lockup reset + #00010000 + + + value6 + WDT reset + #00100000 + + + value8 + Parity Error reset + #10000000 + + + + + HIBWK + Hibernate Wake-up Status + 8 + 8 + read-only + + + value1 + No Wake-up + #0 + + + value2 + Wake-up event + #1 + + + + + HIBRS + Hibernate Reset Status + 9 + 9 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + LCKEN + Enable Lockup Status + 10 + 10 + read-only + + + value1 + Reset by Lockup disabled + #0 + + + value2 + Reset by Lockup enabled + #1 + + + + + + + RSTSET + RCU Reset Set Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + HIBWK + Set Hibernate Wake-up Reset Status + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset status bit + #1 + + + + + HIBRS + Set Hibernate Reset + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + LCKEN + Enable Lockup Reset + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + Enable reset when Lockup gets asserted + #1 + + + + + + + RSTCLR + RCU Reset Clear Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSCLR + Clear Reset Status + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Clears field RSTSTAT.RSTSTAT + #1 + + + + + HIBWK + Clear Hibernate Wake-up Reset Status + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset status bit + #1 + + + + + HIBRS + Clear Hibernate Reset + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + LCKEN + Enable Lockup Reset + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + Disable reset when Lockup gets asserted + #1 + + + + + + + PRSTAT0 + RCU Peripheral 0 Reset Status + 0x0C + 32 + 0x00010F9F + 0xFFFFFFFF + + + VADCRS + VADC Reset Status + 0 + 0 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DSDRS + DSD Reset Status + 1 + 1 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU40RS + CCU40 Reset Status + 2 + 2 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU41RS + CCU41 Reset Status + 3 + 3 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU42RS + CCU42 Reset Status + 4 + 4 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU80RS + CCU80 Reset Status + 7 + 7 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + CCU81RS + CCU81 Reset Status + 8 + 8 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + POSIF0RS + POSIF0 Reset Status + 9 + 9 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + POSIF1RS + POSIF1 Reset Status + 10 + 10 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USIC0RS + USIC0 Reset Status + 11 + 11 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + ERU1RS + ERU1 Reset Status + 16 + 16 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET0 + RCU Peripheral 0 Reset Set + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VADCRS + VADC Reset Assert + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DSDRS + DSD Reset Assert + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU40RS + CCU40 Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU41RS + CCU41 Reset Assert + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU42RS + CCU42 Reset Assert + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU80RS + CCU80 Reset Assert + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + CCU81RS + CCU81 Reset Assert + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + POSIF0RS + POSIF0 Reset Assert + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + POSIF1RS + POSIF1 Reset Assert + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USIC0RS + USIC0 Reset Assert + 11 + 11 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + ERU1RS + ERU1 Reset Assert + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR0 + RCU Peripheral 0 Reset Clear + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VADCRS + VADC Reset Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DSDRS + DSD Reset Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU40RS + CCU40 Reset Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU41RS + CCU41 Reset Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU42RS + CCU42 Reset Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU80RS + CCU80 Reset Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + CCU81RS + CCU81 Reset Clear + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + POSIF0RS + POSIF0 Reset Clear + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + POSIF1RS + POSIF1 Reset Clear + 10 + 10 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USIC0RS + USIC0 Reset Clear + 11 + 11 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + ERU1RS + ERU1 Reset Clear + 16 + 16 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + PRSTAT1 + RCU Peripheral 1 Reset Status + 0x18 + 32 + 0x000001F9 + 0xFFFFFFFF + + + CCU43RS + CCU43 Reset Status + 0 + 0 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + LEDTSCU0RS + LEDTS Reset Status + 3 + 3 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + MCAN0RS + MultiCAN Reset Status + 4 + 4 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DACRS + DAC Reset Status + 5 + 5 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + MMCIRS + MMC Interface Reset Status + 6 + 6 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USIC1RS + USIC1 Reset Status + 7 + 7 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USIC2RS + USIC2 Reset Status + 8 + 8 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + PPORTSRS + PORTS Reset Status + 9 + 9 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET1 + RCU Peripheral 1 Reset Set + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43RS + CCU43 Reset Assert + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + LEDTSCU0RS + LEDTS Reset Assert + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + MCAN0RS + MultiCAN Reset Assert + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DACRS + DAC Reset Assert + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + MMCIRS + MMC Interface Reset Assert + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USIC1RS + USIC1 Reset Assert + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USIC2RS + USIC2 Reset Assert + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + PPORTSRS + PORTS Reset Assert + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR1 + RCU Peripheral 1 Reset Clear + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CCU43RS + CCU43 Reset Clear + 0 + 0 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + LEDTSCU0RS + LEDTS Reset Clear + 3 + 3 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + MCAN0RS + MultiCAN Reset Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DACRS + DAC Reset Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + MMCIRS + MMC Interface Reset Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USIC1RS + USIC1 Reset Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USIC2RS + USIC2 Reset Clear + 8 + 8 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + PPORTSRS + PORTS Reset Clear + 9 + 9 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + PRSTAT2 + RCU Peripheral 2 Reset Status + 0x24 + 32 + 0x000004F6 + 0xFFFFFFFF + + + WDTRS + WDT Reset Status + 1 + 1 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + ETH0RS + ETH0 Reset Status + 2 + 2 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DMA0RS + DMA0 Reset Status + 4 + 4 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + DMA1RS + DMA1 Reset Status + 5 + 5 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + FCERS + FCE Reset Status + 6 + 6 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + USBRS + USB Reset Status + 7 + 7 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET2 + RCU Peripheral 2 Reset Set + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDTRS + WDT Reset Assert + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + ETH0RS + ETH0 Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DMA0RS + DMA0 Reset Assert + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + DMA1RS + DMA1 Reset Assert + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + FCERS + FCE Reset Assert + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + USBRS + USB Reset Assert + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR2 + RCU Peripheral 2 Reset Clear + 0x2C + 32 + 0x00000000 + 0xFFFFFFFF + + + WDTRS + WDT Reset Clear + 1 + 1 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + ETH0RS + ETH0 Reset Clear + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DMA0RS + DMA0 Reset Clear + 4 + 4 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + DMA1RS + DMA1 Reset Clear + 5 + 5 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + FCERS + FCE Reset Clear + 6 + 6 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + USBRS + USB Reset Clear + 7 + 7 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + PRSTAT3 + RCU Peripheral 3 Reset Status + 0x30 + 32 + 0x00000004 + 0xFFFFFFFF + + + EBURS + EBU Reset Status + 2 + 2 + read-only + + + value1 + Reset de-asserted + #0 + + + value2 + Reset asserted + #1 + + + + + + + PRSET3 + RCU Peripheral 3 Reset Set + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBURS + EBU Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + Assert reset + #1 + + + + + + + PRCLR3 + RCU Peripheral 3 Reset Clear + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + EBURS + EBU Reset Assert + 2 + 2 + write-only + + + value1 + No effect + #0 + + + value2 + De-assert reset + #1 + + + + + + + + + LEDTS0 + LED and Touch Sense Unit 0 + LEDTS + 0x48010000 + + 0x0 + 0x0100 + registers + + + LEDTS0_0 + LED and Touch Sense Control Unit (Module 0) + 102 + + + + ID + Module Identification Register + 0x0000 + 32 + 0x00ABC000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + GLOBCTL + Global Control Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS_EN + Touch-Sense Function Enable + 0 + 0 + read-write + + + LD_EN + LED Function Enable + 1 + 1 + read-write + + + CMTR + Clock Master Disable + 2 + 2 + read-write + + + value1 + Kernel generates its own clock for LEDTS-counter based on SFR setting + #0 + + + value2 + LEDTS-counter takes its clock from another master kernel + #1 + + + + + ENSYNC + Enable Autoscan Time Period Synchronization + 3 + 3 + read-write + + + value1 + No synchronization + #0 + + + value2 + Synchronization enabled on Kernel0 autoscan time period + #1 + + + + + SUSCFG + Suspend Request Configuration + 8 + 8 + read-write + + + value1 + Ignore suspend request + #0 + + + value2 + Enable suspend according to request + #1 + + + + + MASKVAL + Mask Number of LSB Bits for Event Validation + 9 + 11 + read-write + + + value1 + Mask LSB bit + 0 + + + value2 + Mask 2 LSB bits + 1 + + + value3 + Mask 8 LSB bits + 7 + + + + + FENVAL + Enable (Extended) Time Frame Validation + 12 + 12 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + ITS_EN + Enable Time Slice Interrupt + 13 + 13 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + ITF_EN + Enable (Extended) Time Frame Interrupt + 14 + 14 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + ITP_EN + Enable Autoscan Time Period Interrupt + 15 + 15 + read-write + + + value1 + Disable + #0 + + + value2 + Enable (valid only for case of hardware-enabled pad turn control) + #1 + + + + + CLK_PS + LEDTS-Counter Clock Pre-Scale Factor + 16 + 31 + read-write + + + + + FNCTL + Function Control Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + PADT + Touch-Sense TSIN Pad Turn + 0 + 2 + read-write + + + value1 + TSIN0 + 0 + + + value2 + TSIN7 + 7 + + + + + PADTSW + Software Control for Touch-Sense Pad Turn + 3 + 3 + read-write + + + value1 + The hardware automatically enables the touch-sense inputs in sequence round-robin, starting from TSIN0. + #0 + + + value2 + Disable hardware control for software control only. The touch-sense input is configured in bit PADT. + #1 + + + + + EPULL + Enable External Pull-up Configuration on Pin COLA + 4 + 4 + read-write + + + value1 + HW over-rule to enable internal pull-up is active on TSIN[x] for set duration in touch-sense time slice. With this setting, it is not specified to assign the COLA to any pin. + #0 + + + value2 + Enable external pull-up: Output 1 on pin COLA for whole duration of touch-sense time slice. + #1 + + + + + FNCOL + Previous Active Function/LED Column Status + 5 + 7 + read-only + + + ACCCNT + Accumulate Count on Touch-Sense Input + 16 + 19 + read-write + + + value1 + 1 time + 0 + + + value2 + 2 times + 1 + + + value3 + 16 times + 15 + + + + + TSCCMP + Common Compare Enable for Touch-Sense + 20 + 20 + read-write + + + value1 + Disable common compare for touch-sense + #0 + + + value2 + Enable common compare for touch-sense + #1 + + + + + TSOEXT + Extension for Touch-Sense Output for Pin-Low-Level + 21 + 22 + read-write + + + value1 + Extend by 1 ledts_clk + #00 + + + value2 + Extend by 4 ledts_clk + #01 + + + value3 + Extend by 8 ledts_clk + #10 + + + value4 + Extend by 16 ledts_clk + #11 + + + + + TSCTRR + TS-Counter Auto Reset + 23 + 23 + read-write + + + value1 + Disable TS-counter automatic reset + #0 + + + value2 + Enable TS-counter automatic reset to 00H on the first pad turn of a new TSIN[x]. Triggered on compare match in time slice. + #1 + + + + + TSCTRSAT + Saturation of TS-Counter + 24 + 24 + read-write + + + value1 + Disable + #0 + + + value2 + Enable. TS-counter stops counting in the touch-sense time slice(s) of the same (extended) frame when it reaches FFH. Counter starts to count again on the first pad turn of a new TSIN[x], triggered on compare match. + #1 + + + + + NR_TSIN + Number of Touch-Sense Input + 25 + 27 + read-write + + + value1 + 1 + 0 + + + value2 + 8 + 7 + + + + + COLLEV + Active Level of LED Column + 28 + 28 + read-write + + + value1 + Active low + #0 + + + value2 + Active high + #1 + + + + + NR_LEDCOL + Number of LED Columns + 29 + 31 + read-write + + + value1 + 1 LED column + #000 + + + value2 + 2 LED columns + #001 + + + value3 + 3 LED columns + #010 + + + value4 + 4 LED columns + #011 + + + value5 + 5 LED columns + #100 + + + value6 + 6 LED columns + #101 + + + value7 + 7 LED columns + #110 + + + value8 + 8 LED columns (max. LED columns = 7 if bit TS_EN = 1) + #111 + + + + + + + EVFR + Event Flag Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + TSF + Time Slice Interrupt Flag + 0 + 0 + read-only + + + TFF + (Extended) Time Frame Interrupt Flag + 1 + 1 + read-only + + + TPF + Autoscan Time Period Interrupt Flag + 2 + 2 + read-only + + + TSCTROVF + TS-Counter Overflow Indication + 3 + 3 + read-only + + + value1 + No overflow has occurred. + #0 + + + value2 + The TS-counter has overflowed at least once. + #1 + + + + + CTSF + Clear Time Slice Interrupt Flag + 16 + 16 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TSF is cleared. + #1 + + + + + CTFF + Clear (Extended) Time Frame Interrupt Flag + 17 + 17 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TFF is cleared. + #1 + + + + + CTPF + Clear Autoscan Time Period Interrupt Flag + 18 + 18 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TPF is cleared. + #1 + + + + + + + TSVAL + Touch-sense TS-Counter Value + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSCTRVALR + Shadow TS-Counter (Read) + 0 + 15 + read-only + + + TSCTRVAL + TS-Counter Value + 16 + 31 + read-write + + + + + LINE0 + Line Pattern Register 0 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINE_0 + Output on LINE[x] + 0 + 7 + read-write + + + LINE_1 + Output on LINE[x] + 8 + 15 + read-write + + + LINE_2 + Output on LINE[x] + 16 + 23 + read-write + + + LINE_3 + Output on LINE[x] + 24 + 31 + read-write + + + + + LINE1 + Line Pattern Register 1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINE_4 + Output on LINE[x] + 0 + 7 + read-write + + + LINE_5 + Output on LINE[x] + 8 + 15 + read-write + + + LINE_6 + Output on LINE[x] + 16 + 23 + read-write + + + LINE_A + Output on LINE[x] + 24 + 31 + read-write + + + + + LDCMP0 + LED Compare Register 0 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_LD0 + Compare Value for LED COL[x] + 0 + 7 + read-write + + + CMP_LD1 + Compare Value for LED COL[x] + 8 + 15 + read-write + + + CMP_LD2 + Compare Value for LED COL[x] + 16 + 23 + read-write + + + CMP_LD3 + Compare Value for LED COL[x] + 24 + 31 + read-write + + + + + LDCMP1 + LED Compare Register 1 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_LD4 + Compare Value for LED COL[x] + 0 + 7 + read-write + + + CMP_LD5 + Compare Value for LED COL[x] + 8 + 15 + read-write + + + CMP_LD6 + Compare Value for LED COL[x] + 16 + 23 + read-write + + + CMP_LDA_TSCOM + Compare Value for LED COLA / Common Compare Value for Touch-sense Pad Turns + 24 + 31 + read-write + + + + + TSCMP0 + Touch-sense Compare Register 0 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_TS0 + Compare Value for Touch-Sense TSIN[x] + 0 + 7 + read-write + + + CMP_TS1 + Compare Value for Touch-Sense TSIN[x] + 8 + 15 + read-write + + + CMP_TS2 + Compare Value for Touch-Sense TSIN[x] + 16 + 23 + read-write + + + CMP_TS3 + Compare Value for Touch-Sense TSIN[x] + 24 + 31 + read-write + + + + + TSCMP1 + Touch-sense Compare Register 1 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_TS4 + Compare Value for Touch-Sense TSIN[x] + 0 + 7 + read-write + + + CMP_TS5 + Compare Value for Touch-Sense TSIN[x] + 8 + 15 + read-write + + + CMP_TS6 + Compare Value for Touch-Sense TSIN[x] + 16 + 23 + read-write + + + CMP_TS7 + Compare Value for Touch-Sense TSIN[x] + 24 + 31 + read-write + + + + + + + SDMMC_CON + SD and Multimediacard Control Register + 0x500040B4 + + 0 + 4 + registers + + + + SDMMC_CON + SDMMC Configuration + 0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WPSEL + SDMMC Write Protection Input Multiplexer Control + 0 + 0 + read-write + + + value1 + P1.1 input pin selected + #0 + + + value2 + Software bit WPVAL is selected + #1 + + + + + WPSVAL + SDMMC Write Protect Software Control + 4 + 4 + read-write + + + value1 + No write protection + #0 + + + value2 + Write protection active + #1 + + + + + CDSEL + SDMMC Card Detection Control + 16 + 16 + read-write + + + value1 + P1.10 input pin selected + #0 + + + value2 + Software bit CDSVAL is selected + #1 + + + + + CDSVAL + SDMMC Write Protect Software Control + 20 + 20 + read-write + + + value1 + No card detected + #0 + + + value2 + Card detected + #1 + + + + + + + + + SDMMC + SD and Multimediacard Interface + 0x4801C000 + + 0x0 + 0x4000 + registers + + + SDMMC0_0 + Multi Media Card Interface + 106 + + + + BLOCK_SIZE + Block Size Register + 0x0004 + 16 + 0x0000 + 0xFFFF + + + TX_BLOCK_SIZE_12 + Transfer Block Size 12th bit. + 15 + 15 + read-write + + + TX_BLOCK_SIZE + Transfer Block Size + 0 + 11 + read-write + + + + + BLOCK_COUNT + Block Count Register + 0x0006 + 16 + 0x0000 + 0xFFFF + + + BLOCK_COUNT + Blocks Count for Current Transfer + 0 + 15 + read-write + + + + + ARGUMENT1 + Argument1 Register + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMENT1 + Command Argument + 0 + 31 + read-write + + + + + TRANSFER_MODE + Transfer Mode Register + 0x000C + 16 + 0x0000 + 0xFFFF + + + CMD_COMP_ATA + Command Completion Signal Enable for CE-ATA Device + 6 + 6 + read-write + + + value1 + Device will send command completion Signal + #1 + + + value2 + Device will not send command completion Signal + #0 + + + + + MULTI_BLOCK_SELECT + Multi / Single Block Select + 5 + 5 + read-write + + + value1 + Single Block + #0 + + + value2 + Multiple Block + #1 + + + + + TX_DIR_SELECT + Data Transfer Direction Select + 4 + 4 + read-write + + + value1 + Write (Host to Card) + #0 + + + value2 + Read (Card to Host) + #1 + + + + + ACMD_EN + Auto CMD Enable + 2 + 3 + read-write + + + value1 + Auto Command Disabled + #00 + + + value2 + Auto CMD12 Enable + #01 + + + + + BLOCK_COUNT_EN + Block Count Enable + 1 + 1 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + + + COMMAND + Command Register + 0x000E + 16 + 0x0000 + 0xFFFF + + + CMD_IND + Command Index + 8 + 13 + read-write + + + CMD_TYPE + Command Type + 6 + 7 + read-write + + + value1 + Normal + #00 + + + value2 + Suspend + #01 + + + value3 + Resume + #10 + + + value4 + Abort + #11 + + + + + DATA_PRESENT_SELECT + Data Present Select + 5 + 5 + read-write + + + value1 + No Data Present + #0 + + + value2 + Data Present + #1 + + + + + CMD_IND_CHECK_EN + Command Index Check Enable + 4 + 4 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + CMD_CRC_CHECK_EN + Command CRC Check Enable + 3 + 3 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + RESP_TYPE_SELECT + Response Type Select + 0 + 1 + read-write + + + value1 + No Response + #00 + + + value2 + Response length 136 + #01 + + + value3 + Response length 48 + #10 + + + value4 + Response length 48 check Busy after response + #11 + + + + + + + RESPONSE0 + Response 0 Register + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE1 + Response1 + 16 + 31 + read-only + + + RESPONSE0 + Response0 + 0 + 15 + read-only + + + + + RESPONSE2 + Response 2 Register + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE3 + Response3 + 16 + 31 + read-only + + + RESPONSE2 + Response2 + 0 + 15 + read-only + + + + + RESPONSE4 + Response 4 Register + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE5 + Response5 + 16 + 31 + read-only + + + RESPONSE4 + Response4 + 0 + 15 + read-only + + + + + RESPONSE6 + Response 6 Register + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + RESPONSE7 + Response7 + 16 + 31 + read-only + + + RESPONSE6 + Response6 + 0 + 15 + read-only + + + + + DATA_BUFFER + Data Buffer Register + 0x0020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_BUFFER + Data Buffer + 0 + 31 + read-write + + + + + PRESENT_STATE + Present State Register + 0x0024 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT_7_4_PIN_LEVEL + Line Signal Level + 25 + 28 + read-only + + + CMD_LINE_LEVEL + CMD Line Signal Level + 24 + 24 + read-only + + + DAT_3_0_PIN_LEVEL + Line Signal Level + 20 + 23 + read-only + + + WRITE_PROTECT_PIN_LEVEL + Write Protect Switch Pin Level + 19 + 19 + read-only + + + value1 + Write protected (SDWP = 1) + #0 + + + value2 + Write enabled (SDWP = 0) + #1 + + + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level + 18 + 18 + read-only + + + value1 + No Card present (SDCD = 1) + #0 + + + value2 + Card present (SDCD = 0) + #1 + + + + + CARD_STATE_STABLE + Card State Stable + 17 + 17 + read-only + + + value1 + Reset of Debouncing + #0 + + + value2 + No Card or Inserted + #1 + + + + + CARD_INSERTED + Card Inserted + 16 + 16 + read-only + + + value1 + Reset or Debouncing or No Card + #0 + + + value2 + Card Inserted + #1 + + + + + BUFFER_READ_ENABLE + Buffer Read Enable + 11 + 11 + read-only + + + value1 + Read Disable + #0 + + + value2 + Read Enable. + #1 + + + + + BUFFER_WRITE_ENABLE + Buffer Write Enable + 10 + 10 + read-only + + + value1 + Write Disable + #0 + + + value2 + Write Enable. + #1 + + + + + READ_TRANSFER_ACTIVE + Read Transfer Active + 9 + 9 + read-only + + + value1 + No valid data + #0 + + + value2 + Transferring data + #1 + + + + + WRITE_TRANSFER_ACTIVE + Write Transfer Active + 8 + 8 + read-only + + + value1 + No valid data + #0 + + + value2 + Transferring data + #1 + + + + + DAT_LINE_ACTIVE + DAT Line Active + 2 + 2 + read-only + + + value1 + DAT line inactive + #0 + + + value2 + DAT line active + #1 + + + + + COMMAND_INHIBIT_DAT + Command Inhibit (DAT) + 1 + 1 + read-only + + + value1 + Can issue command which uses the DAT line + #0 + + + value2 + Cannot issue command which uses the DAT line + #1 + + + + + COMMAND_INHIBIT_CMD + Command Inhibit (CMD) + 0 + 0 + read-only + + + + + HOST_CTRL + Host Control Register + 0x0028 + 8 + 0x00 + 0xFF + + + CARD_DET_SIGNAL_DETECT + Card detect signal detetction + 7 + 7 + read-write + + + value1 + SDCD is selected (for normal use) + #0 + + + value2 + The card detect test level is selected + #1 + + + + + CARD_DETECT_TEST_LEVEL + Card Detect Test Level + 6 + 6 + read-write + + + value1 + No Card + #0 + + + value2 + Card Inserted + #1 + + + + + SD_8BIT_MODE + Extended Data Transfer Width + 5 + 5 + read-write + + + value1 + Bus Width is selected by Data Transfer Width + #0 + + + value2 + 8-bit Bus Width + #1 + + + + + HIGH_SPEED_EN + High Speed Enable + 2 + 2 + read-write + + + value1 + Normal Speed Mode + #0 + + + value2 + High Speed Mode + #1 + + + + + DATA_TX_WIDTH + Data Transfer Width (SD1 or SD4) + 1 + 1 + read-write + + + value1 + 1 bit mode + #0 + + + value2 + 4-bit mode + #1 + + + + + LED_CTRL + LED Control + 0 + 0 + read-write + + + value1 + LED off + #0 + + + value2 + LED on + #1 + + + + + + + POWER_CTRL + Power Control Register + 0x0029 + 8 + 0x00 + 0xFF + + + HARDWARE_RESET + Hardware reset + 4 + 4 + read-write + + + SD_BUS_VOLTAGE_SEL + SD Bus Voltage Select + 1 + 3 + read-write + + + value1 + 3.3V (Flattop.) + #111 + + + + + SD_BUS_POWER + SD Bus Power + 0 + 0 + read-write + + + value1 + Power off + #0 + + + value2 + Power on + #1 + + + + + + + BLOCK_GAP_CTRL + Block Gap Control Register + 0x002A + 8 + 0x00 + 0xFF + + + INT_AT_BLOCK_GAP + Interrupt At Block Gap + 3 + 3 + read-write + + + READ_WAIT_CTRL + Read Wait Control + 2 + 2 + read-write + + + value1 + Disable Read Wait Control + #0 + + + value2 + Enable Read Wait Control + #1 + + + + + CONTINUE_REQ + Continue Request + 1 + 1 + read-write + + + value1 + Ignored + #0 + + + value2 + Restart + #1 + + + + + STOP_AT_BLOCK_GAP + Stop At Block Gap Request + 0 + 0 + read-write + + + value1 + Transfer + #0 + + + value2 + Stop + #1 + + + + + + + WAKEUP_CTRL + Wake-up Control Register + 0x002B + 8 + 0x00 + 0xFF + + + WAKEUP_EVENT_EN_REM + Wakeup Event Enable On SD Card Removal + 2 + 2 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + WAKEUP_EVENT_EN_INS + Wakeup Event Enable On SD Card Insertion + 1 + 1 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + WAKEUP_EVENT_EN_INT + Wakeup Event Enable On Card Interrupt + 0 + 0 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + + + CLOCK_CTRL + Clock Control Register + 0x002C + 16 + 0x0000 + 0xFFFF + + + SDCLK_FREQ_SEL + SDCLK Frequency Select + 8 + 15 + read-write + + + value1 + base clock(10MHz-63MHz) + 0x00 + + + value2 + base clock divided by 2 + 0x01 + + + value3 + base clock divided by 32 + 0x10 + + + value4 + base clock divided by 4 + 0x02 + + + value5 + base clock divided by 8 + 0x04 + + + value6 + base clock divided by 16 + 0x08 + + + value7 + base clock divided by 64 + 0x20 + + + value8 + base clock divided by 128 + 0x40 + + + value9 + base clock divided by 256 + 0x80 + + + + + SDCLOCK_EN + SD Clock Enable + 2 + 2 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + INTERNAL_CLOCK_STABLE + Internal Clock Stable + 1 + 1 + read-only + + + value1 + Not Ready + #0 + + + value2 + Ready + #1 + + + + + INTERNAL_CLOCK_EN + Internal Clock Enable + 0 + 0 + read-write + + + value1 + Stop + #0 + + + value2 + Oscillate + #1 + + + + + + + TIMEOUT_CTRL + Timeout Control Register + 0x002E + 8 + 0x00 + 0xFF + + + DAT_TIMEOUT_CNT_VAL + Data Timeout Counter Value + 0 + 3 + read-write + + + value1 + TMCLK * 2^13 + #0000 + + + value2 + TMCLK * 2^14 + #0001 + + + value3 + TMCLK * 2^27 + #1110 + + + + + + + SW_RESET + Software Reset Register + 0x002F + 8 + 0x00 + 0xFF + + + SW_RST_DAT_LINE + Software Reset for DAT Line + 2 + 2 + read-write + + + value1 + Work + #0 + + + value2 + Reset + #1 + + + + + SW_RST_CMD_LINE + Software Reset for CMD Line + 1 + 1 + read-write + + + value1 + Work + #0 + + + value2 + Reset + #1 + + + + + SW_RST_ALL + Software Reset for All + 0 + 0 + read-write + + + + + INT_STATUS_NORM + Normal Interrupt Status Register + 0x0030 + 16 + 0x0000 + 0xFFFF + + + ERR_INT + Error Interrupt + 15 + 15 + read-only + + + value1 + No Error. + #0 + + + value2 + Error. + #1 + + + + + CARD_INT + Card Interrupt + 8 + 8 + read-only + + + value1 + No Card Interrupt + #0 + + + value2 + Generate Card Interrupt + #1 + + + + + CARD_REMOVAL + Card Removal + 7 + 7 + read-write + + + value1 + Card State Stable or Debouncing + #0 + + + value2 + Card Removed + #1 + + + + + CARD_INS + Card Insertion + 6 + 6 + read-write + + + value1 + Card State Stable or Debouncing + #0 + + + value2 + Card Inserted + #1 + + + + + BUFF_READ_READY + Buffer Read Ready + 5 + 5 + read-write + + + value1 + Not Ready to read Buffer. + #0 + + + value2 + Ready to read Buffer. + #1 + + + + + BUFF_WRITE_READY + Buffer Write Ready + 4 + 4 + read-write + + + value1 + Not Ready to Write Buffer. + #0 + + + value2 + Ready to Write Buffer. + #1 + + + + + BLOCK_GAP_EVENT + Block Gap Event + 2 + 2 + read-write + + + value1 + No Block Gap Event + #0 + + + value2 + Transaction stopped at Block Gap + #1 + + + + + TX_COMPLETE + Transfer Complete + 1 + 1 + read-write + + + value1 + No Data Transfer Complete + #0 + + + value2 + Data Transfer Complete + #1 + + + + + CMD_COMPLETE + Command Complete + 0 + 0 + read-write + + + value1 + No Command Complete + #0 + + + value2 + Command Complete + #1 + + + + + + + INT_STATUS_ERR + Error Interrupt Status Register + 0x0032 + 16 + 0x0000 + 0xFFFF + + + CEATA_ERR + Ceata Error Status + 13 + 13 + read-write + + + value1 + no error + #0 + + + value2 + error + #1 + + + + + ACMD_ERR + Auto CMD Error + 8 + 8 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + CURRENT_LIMIT_ERR + Current Limit Error + 7 + 7 + read-write + + + value1 + No Error + #0 + + + value2 + Power Fail + #1 + + + + + DATA_END_BIT_ERR + Data End Bit Error + 6 + 6 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + DATA_CRC_ERR + Data CRC Error + 5 + 5 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + DATA_TIMEOUT_ERR + Data Timeout Error + 4 + 4 + read-write + + + value1 + No Error + #0 + + + value2 + Timeout + #1 + + + + + CMD_IND_ERR + Command Index Error + 3 + 3 + read-write + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + CMD_END_BIT_ERR + Command End Bit Error + 2 + 2 + read-write + + + value1 + No Error + #0 + + + value2 + End Bit Error Generated + #1 + + + + + CMD_CRC_ERR + Command CRC Error + 1 + 1 + read-write + + + value1 + No Error + #0 + + + value2 + CRC Error Generated + #1 + + + + + CMD_TIMEOUT_ERR + Command Timeout Error + 0 + 0 + read-write + + + value1 + No Error + #0 + + + value2 + Timeout + #1 + + + + + + + EN_INT_STATUS_NORM + Normal Interrupt Status Enable Register + 0x0034 + 16 + 0x0000 + 0xFFFF + + + FIXED_TO_0 + Fixed to 0 + 15 + 15 + read-only + + + CARD_INT_EN + Card Interrupt Status Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_REMOVAL_EN + Card Removal Status Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_INS_EN + Card Insertion Status Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_READ_READY_EN + Buffer Read Ready Status Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_WRITE_READY_EN + Buffer Write Ready Status Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BLOCK_GAP_EVENT_EN + Block Gap Event Status Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TX_COMPLETE_EN + Transfer Complete Status Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_COMPLETE_EN + Command Complete Status Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + EN_INT_STATUS_ERR + Error Interrupt Status Enable Register + 0x0036 + 16 + 0x0000 + 0xFFFF + + + CEATA_ERR_EN + Ceata Error Status Enable + 13 + 13 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TARGET_RESP_ERR_EN + Target Response Error Status Enable + 12 + 12 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + ACMD_ERR_EN + Auto CMD12 Error Status Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CURRENT_LIMIT_ERR_EN + Current Limit Error Status Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_END_BIT_ERR_EN + Data End Bit Error Status Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_CRC_ERR_EN + Data CRC Error Status Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_TIMEOUT_ERR_EN + Data Timeout Error Status Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_IND_ERR_EN + Command Index Error Status Enable + 3 + 3 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_END_BIT_ERR_EN + Command End Bit Error Status Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_CRC_ERR_EN + Command CRC Error Status Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_TIMEOUT_ERR_EN + Command Timeout Error Status Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + EN_INT_SIGNAL_NORM + Normal Interrupt Signal Enable Register + 0x0038 + 16 + 0x0000 + 0xFFFF + + + FIXED_TO_0 + Fixed to 0 + 15 + 15 + read-only + + + CARD_INT_EN + Card Interrupt Signal Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_REMOVAL_EN + Card Removal Signal Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CARD_INS_EN + Card Insertion Signal Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_READ_READY_EN + Buffer Read Ready Signal Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BUFF_WRITE_READY_EN + Buffer Write Ready Signal Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + BLOCK_GAP_EVENT_EN + Block Gap Event Signal Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TX_COMPLETE_EN + Transfer Complete Signal Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_COMPLETE_EN + Command Complete Signal Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + EN_INT_SIGNAL_ERR + Error Interrupt Signal Enable Register + 0x003A + 16 + 0x0000 + 0xFFFF + + + CEATA_ERR_EN + Ceata Error Signal Enable + 13 + 13 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + TARGET_RESP_ERR_EN + Target Response Error Signal Enable + 12 + 12 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + ACMD_ERR_EN + Auto CMD12 Error Signal Enable + 8 + 8 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CURRENT_LIMIT_ERR_EN + Current Limit Error Signal Enable + 7 + 7 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_END_BIT_ERR_EN + Data End Bit Error Signal Enable + 6 + 6 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_CRC_ERR_EN + Data CRC Error Signal Enable + 5 + 5 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + DATA_TIMEOUT_ERR_EN + Data Timeout Error Signal Enable + 4 + 4 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_IND_ERR_EN + Command Index Error Signal Enable + 3 + 3 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_END_BIT_ERR_EN + Command End Bit Error Signal Enable + 2 + 2 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_CRC_ERR_EN + Command CRC Error Signal Enable + 1 + 1 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + CMD_TIMEOUT_ERR_EN + Command Timeout Error Signal Enable + 0 + 0 + read-write + + + value1 + Masked + #0 + + + value2 + Enabled + #1 + + + + + + + ACMD_ERR_STATUS + Auto CMD Error Status Register + 0x003C + 16 + 0x0000 + 0xFFFF + + + CMD_NOT_ISSUED_BY_ACMD12_ERR + Command Not Issued By Auto CMD12 Error + 7 + 7 + read-only + + + value1 + No Error + #0 + + + value2 + Not Issued + #1 + + + + + ACMD_IND_ERR + Auto CMD Index Error + 4 + 4 + read-only + + + value1 + No Error + #0 + + + value2 + Error + #1 + + + + + ACMD_END_BIT_ERR + Auto CMD End Bit Error + 3 + 3 + read-only + + + value1 + No Error + #0 + + + value2 + End Bit Error Generated + #1 + + + + + ACMD_CRC_ERR + Auto CMD CRC Error + 2 + 2 + read-only + + + value1 + No Error + #0 + + + value2 + CRC Error Generated + #1 + + + + + ACMD_TIMEOUT_ERR + Auto CMD Timeout Error + 1 + 1 + read-only + + + value1 + No Error + #0 + + + value2 + Timeout + #1 + + + + + ACMD12_NOT_EXEC_ERR + Auto CMD12 Not Executed + 0 + 0 + read-only + + + value1 + Executed + #0 + + + value2 + Not Executed + #1 + + + + + + + CAPABILITIES + Capabilities Register + 0x0040 + 32 + 0x01A030B0 + 0xFFFFFFFF + + + TIMEOUT_CLOCK_FREQ + Timeout Clock Frequency + 0 + 5 + read-only + + + value1 + 48 MHz + #110000 + + + + + TIMEOUT_CLOCK_UNIT + Timeout Clock Unit + 7 + 7 + read-only + + + value1 + MHz + #1 + + + + + BASE_SD_CLOCK_FREQ + Base Clock Frequency for SD Clock + 8 + 15 + read-only + + + value1 + 48 MHz + 0x30 + + + + + MAX_BLOCK_LENGTH + Max Block Length + 16 + 17 + read-only + + + value1 + 512 byte + #00 + + + + + EXT_MEDIA_BUS_SUPPORT + Extended Media Bus Support + 18 + 18 + read-only + + + value1 + Extended Media Bus not supported + #0 + + + + + ADMA2_SUPPORT + ADMA2 Support + 19 + 19 + read-only + + + value1 + ADMA not supported + #0 + + + + + HIGH_SPEED_SUPPORT + High Speed Support + 21 + 21 + read-only + + + value1 + High Speed supported + #1 + + + + + SDMA_SUPPORT + SDMA Support + 22 + 22 + read-only + + + value1 + SDMA not supported + #0 + + + + + SUSPEND_RESUME_SUPPORT + Suspend / Resume Support + 23 + 23 + read-only + + + value1 + Supported + #1 + + + + + VOLTAGE_SUPPORT_3_3V + Voltage Support 3.3V + 24 + 24 + read-only + + + value1 + 3.3V supported + #1 + + + + + VOLTAGE_SUPPORT_3V + Voltage Support 3.0V + 25 + 25 + read-only + + + value1 + 3.0V not supported + #0 + + + + + VOLTAGE_SUPPORT_1_8V + Voltage Support 1.8V + 26 + 26 + read-only + + + value1 + 1.8V not supported + #0 + + + + + SYSBUS_64_SUPPORT + 64-bit System Bus Support + 28 + 28 + read-only + + + value1 + Does not support 64-bit system address + #0 + + + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support + 29 + 29 + read-only + + + value1 + Asynchronous Interrupt not supported + #0 + + + + + SLOT_TYPE + Slot Type + 30 + 31 + read-only + + + value1 + Removable Card Slot + #00 + + + + + + + CAPABILITIES_HI + Capabilities Register High + 0x0044 + 32 + 0x03000000 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 Support + 0 + 0 + read-only + + + value1 + SDR50 is not supported + #0 + + + + + SDR104_SUPPORT + SDR104 Support + 1 + 1 + read-only + + + value1 + SDR104 is not supported + #0 + + + + + DDR50_SUPPORT + DDR50 Support + 2 + 2 + read-only + + + value1 + DDR50 is not supported + #0 + + + + + DRV_A_SUPPORT + Driver Type A Support + 4 + 4 + read-only + + + value1 + Driver Type A is not supported + #0 + + + + + DRV_C_SUPPORT + Driver Type C Support + 5 + 5 + read-only + + + value1 + Driver Type C is not supported + #0 + + + + + DRV_D_SUPPORT + Driver Type D Support + 6 + 6 + read-only + + + value1 + Driver Type D is not supported + #0 + + + + + TIM_CNT_RETUNE + Timer count for Re-Tuning + 8 + 11 + read-only + + + value1 + Get information via other source + 0x0 + + + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 13 + 13 + read-only + + + value1 + SDR50 does not require tuning + #0 + + + + + RE_TUNING_MODES + Re-tuning modes + 14 + 15 + read-only + + + value1 + Mode 1 + #00 + + + + + CLK_MULT + Clock Multiplier + 16 + 23 + read-only + + + value1 + Clock Multiplier not supported + 0x00 + + + + + + + MAX_CURRENT_CAP + Maximum Current Capabilities Register + 0x0048 + 32 + 0x00000001 + 0xFFFFFFFF + + + MAX_CURRENT_FOR_3_3V + Maximum Current for 3.3V + 0 + 7 + read-only + + + + + FORCE_EVENT_ACMD_ERR_STATUS + Force Event Register for Auto CMD Error Status + 0x0050 + 16 + 0x0000 + 0xFFFF + + + FE_CMD_NOT_ISSUED_ACMD12_ERR + Force Event for CMD not issued by Auto CMD12 Error + 7 + 7 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_IND_ERR + Force Event for Auto CMD Index Error + 4 + 4 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_END_BIT_ERR + Force Event for Auto CMD End bit Error + 3 + 3 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_CRC_ERR + Force Event for Auto CMD CRC Error + 2 + 2 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_TIMEOUT_ERR + Force Event for Auto CMD timeout Error + 1 + 1 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD_NOT_EXEC + Force Event for Auto CMD12 NOT Executed + 0 + 0 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + + + FORCE_EVENT_ERR_STATUS + Force Event Register for Error Interrupt Status + 0x0052 + 16 + 0x0000 + 0xFFFF + + + FE_CEATA_ERR + Force Event for Ceata Error + 13 + 13 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_TARGET_RESPONSE_ERR + Force event for Target Response Error + 12 + 12 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_ACMD12_ERR + Force Event for Auto CMD Error + 8 + 8 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CURRENT_LIMIT_ERR + Force Event for Current Limit Error + 7 + 7 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_DATA_END_BIT_ERR + Force Event for Data End Bit Error + 6 + 6 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_DATA_CRC_ERR + Force Event for Data CRC Error + 5 + 5 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_DATA_TIMEOUT_ERR + Force Event for Data Timeout Error + 4 + 4 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_IND_ERR + Force Event for Command Index Error + 3 + 3 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_END_BIT_ERR + Force Event for Command End Bit Error + 2 + 2 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_CRC_ERR + Force Event for Command CRC Error + 1 + 1 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + FE_CMD_TIMEOUT_ERR + Force Event for Command Timeout Error + 0 + 0 + write-only + + + value1 + No interrupt + #0 + + + value2 + Interrupt is generated + #1 + + + + + + + DEBUG_SEL + Debug Selection Register + 0x0074 + 32 + 0x00000000 + 0xFFFFFFFF + + + DEBUG_SEL + Debug_sel + 0 + 0 + write-only + + + value1 + receiver module and fifo_ctrl module signals are probed out + #0 + + + value2 + cmd register, Interrupt status, transmitter module and clk sdcard signals are probed out. + #1 + + + + + + + SLOT_INT_STATUS + Slot Interrupt Status Register + 0x00FC + 16 + 0x0000 + 0xFFFF + + + SLOT_INT_STATUS + Interrupt Signal for Card Slot + 0 + 7 + read-only + + + value1 + Slot 1 + 0x00 + + + + + + + + + EBU + External Bus Unit + 0x58008000 + + 0x0 + 0x4000 + registers + + + + CLC + EBU Clock Control Register + 0x00 + 32 + 0x00110000 + 0xFFFFFFFF + + + DISR + EBU Disable Request Bit + 0 + 0 + read-write + + + value1 + EBU disable is not requested + #0 + + + value2 + EBU disable is requested + #1 + + + + + DISS + EBU Disable Status Bit + 1 + 1 + read-only + + + value1 + EBU is enabled (default after reset) + #0 + + + value2 + EBU is disabled + #1 + + + + + SYNC + EBU Clocking Mode + 16 + 16 + read-write + + + value1 + request EBU to run asynchronously to AHB bus clock and use separate clock source + #0 + + + value2 + request EBU to run synchronously to ARM processor (default after reset) + #1 + + + + + DIV2 + DIV2 Clocking Mode + 17 + 17 + read-write + + + value1 + standard clocking mode. clock input selected by SYNC bitfield (default after reset). + #0 + + + value2 + request EBU to run off AHB bus clock divided by 2. + #1 + + + + + EBUDIV + EBU Clock Divide Ratio + 18 + 19 + read-write + + + value1 + request EBU to run off input clock (default after reset) + #00 + + + value2 + request EBU to run off input clock divided by 2 + #01 + + + value3 + request EBU to run off input clock divided by 3 + #10 + + + value4 + request EBU to run off input clock divided by 4 + #11 + + + + + SYNCACK + EBU Clocking Mode Status + 20 + 20 + read-only + + + value1 + the EBU is asynchronous to the AHB bus clock and is using a separate clock source + #0 + + + value2 + EBU is synchronous to the AHB bus clock (default after reset) + #1 + + + + + DIV2ACK + DIV2 Clocking Mode Status + 21 + 21 + read-only + + + value1 + EBU is using standard clocking mode. clock input selected by SYNC bitfield (default after reset). + #0 + + + value2 + EBU is running off AHB bus clock divided by 2. + #1 + + + + + EBUDIVACK + EBU Clock Divide Ratio Status + 22 + 23 + read-only + + + value1 + EBU is running off input clock (default after reset) + #00 + + + value2 + EBU is running off input clock divided by 2 + #01 + + + value3 + EBU is running off input clock divided by 3 + #10 + + + value4 + EBU is running off input clock divided by 4 + #11 + + + + + + + MODCON + EBU Configuration Register + 0x04 + 32 + 0x00000020 + 0xFFFFFFFF + + + STS + Memory Status Bit + 0 + 0 + read-only + + + LCKABRT + Lock Abort + 1 + 1 + read-only + + + SDTRI + SDRAM Tristate + 2 + 2 + read-write + + + value1 + SDRAM control signals are driven by the EBU when the EBU does not own the external bus. SDRAM cannot be shared. + #0 + + + value2 + SDRAM control signals are tri-stated by the EBU when the EBU does not own the external bus. The SDRAM can be shared. + #1 + + + + + EXTLOCK + External Bus Lock Control + 4 + 4 + read-write + + + value1 + External bus is not locked after the EBU gains ownership + #0 + + + value2 + External bus is locked after the EBU gains ownership + #1 + + + + + ARBSYNC + Arbitration Signal Synchronization Control + 5 + 5 + read-write + + + value1 + Arbitration inputs are synchronous + #0 + + + value2 + Arbitration inputs are asynchronous + #1 + + + + + ARBMODE + Arbitration Mode Selection + 6 + 7 + read-write + + + value1 + No Bus arbitration mode selected + #00 + + + value2 + Arbiter Mode arbitration mode selected + #01 + + + value3 + Participant arbitration mode selected + #10 + + + value4 + Sole Master arbitration mode selected + #11 + + + + + TIMEOUTC + Bus Time-out Control + 8 + 15 + read-write + + + value1 + Time-out is disabled. + 0x00 + + + value2 + Time-out is generated after 1 8 clock cycles. + 0x01 + + + value3 + Time-out is generated after 255 8 clock cycles. + 0xFF + + + + + LOCKTIMEOUT + Lock Timeout Counter Preload + 16 + 23 + read-write + + + GLOBALCS + Global Chip Select Enable + 24 + 27 + read-write + + + ACCSINH + Access Inhibit request + 28 + 28 + read-write + + + ACCSINHACK + Access inhibit acknowledge + 29 + 29 + read-only + + + ALE + ALE Mode + 31 + 31 + read-write + + + value1 + Output is ADV + #0 + + + value2 + Output is ALE + #1 + + + + + + + ID + EBU Module Identification Register + 0x08 + 32 + 0x0014C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + USERCON + EBU Test/Control Configuration Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + DIP + Disable Internal Pipelining + 0 + 0 + read-write + + + ADDIO + Address Pins to GPIO Mode + 16 + 24 + read-write + + + value1 + Address Bit is required for addressing memory + #0 + + + value2 + Address Bit is available for GPIO function + #1 + + + + + ADVIO + ADV Pin to GPIO Mode + 25 + 25 + read-write + + + value1 + ADV pin is required for controlling memory + #0 + + + value2 + ADV pin is available for GPIO function + #1 + + + + + + + ADDRSEL0 + EBU Address Select Register 0 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + ADDRSEL1 + EBU Address Select Register 1 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + ADDRSEL2 + EBU Address Select Register 2 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + ADDRSEL3 + EBU Address Select Register 3 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + REGENAB + Memory Region Enable + 0 + 0 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + ALTENAB + Alternate Region Enable + 1 + 1 + read-write + + + value1 + Memory region is disabled (default after reset). + #0 + + + value2 + Memory region is enabled. + #1 + + + + + WPROT + Memory Region Write Protect + 2 + 2 + read-write + + + value1 + Region is enabled for write accesses + #0 + + + value2 + Region is write protected. + #1 + + + + + + + BUSRCON0 + EBU Bus Configuration Register + 0x28 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP0 + EBU Bus Read Access Parameter Register + 0x2C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON0 + EBU Bus Write Configuration Register + 0x30 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP0 + EBU Bus Write Access Parameter Register + 0x34 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSRCON1 + EBU Bus Configuration Register + 0x38 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP1 + EBU Bus Read Access Parameter Register + 0x3C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON1 + EBU Bus Write Configuration Register + 0x40 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP1 + EBU Bus Write Access Parameter Register + 0x44 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSRCON2 + EBU Bus Configuration Register + 0x48 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP2 + EBU Bus Read Access Parameter Register + 0x4C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON2 + EBU Bus Write Configuration Register + 0x50 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP2 + EBU Bus Write Access Parameter Register + 0x54 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSRCON3 + EBU Bus Configuration Register + 0x58 + 32 + 0x00D30040 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction is transferred in a single burst. + #1 + + + + + BFSSS + Read Single Stage Synchronization: + 4 + 4 + read-write + + + value1 + Two stages of synchronization used. (maximum margin) + #0 + + + value2 + One stage of synchronization used. (minimum latency) + #1 + + + + + FDBKEN + Burst FLASH Clock Feedback Enable + 5 + 5 + read-write + + + value1 + BFCLK feedback not used. + #0 + + + value2 + Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. + #1 + + + + + BFCMSEL + Burst Flash Clock Mode Select + 6 + 6 + read-write + + + value1 + Burst Flash Clock runs continuously with values selected by this register + #0 + + + value2 + Burst Flash Clock is disabled between accesses + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-write + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + DBA + Disable Burst Address Wrapping + 18 + 18 + read-write + + + value1 + Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. + #0 + + + value2 + Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-write + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSRAP3 + EBU Bus Read Access Parameter Register + 0x5C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RDDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + RDRECOVC + Recovery Cycles after Read Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITRDC + Programmed Wait States for read accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Read Accesses + 12 + 15 + read-write + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + BUSWCON3 + EBU Bus Write Configuration Register + 0x60 + 32 + 0x00D30000 + 0xFFFFFFFF + + + FETBLEN + Burst Length for Synchronous Burst + 0 + 2 + read-write + + + value1 + 1 data access (default after reset). + #000 + + + value2 + 2 data accesses. + #001 + + + value3 + 4 data accesses. + #010 + + + value4 + 8 data accesses. + #011 + + + + + FBBMSEL + Synchronous burst buffer mode select + 3 + 3 + read-write + + + value1 + Burst buffer length defined by value in FETBLEN (default after reset). + #0 + + + value2 + Continuous mode. All data required for transaction transferred in single burst + #1 + + + + + NAA + Enable flash non-array access workaround + 7 + 7 + read-only + + + ECSE + Early Chip Select for Synchronous Burst + 16 + 16 + read-write + + + value1 + CS is delayed. + #0 + + + value2 + CS is not delayed. + #1 + + + + + EBSE + Early Burst Signal Enable for Synchronous Burst + 17 + 17 + read-write + + + value1 + ADV is delayed. + #0 + + + value2 + ADV is not delayed. + #1 + + + + + WAITINV + Reversed polarity at WAIT + 19 + 19 + read-write + + + value1 + input at WAIT pin is active low (default after reset). + #0 + + + value2 + input at WAIT pin is active high. + #1 + + + + + BCGEN + Byte Control Signal Control + 20 + 21 + read-write + + + value1 + Byte control signals follow chip select timing. + #00 + + + value2 + Byte control signals follow control signal timing (RD, RD/WR) (default after reset). + #01 + + + value3 + Byte control signals follow write enable signal timing (RD/WR only). + #10 + + + + + PORTW + Device Addressing Mode + 22 + 23 + read-only + + + WAIT + External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., + 24 + 25 + read-write + + + AAP + Asynchronous Address phase: + 26 + 26 + read-write + + + value1 + Clock is enabled at beginning of access. + #0 + + + value2 + Clock is enabled at after address phase. + #1 + + + + + LOCKCS + Lock Chip Select + 27 + 27 + read-write + + + value1 + Chip Select cannot be locked (default after reset). + #0 + + + value2 + Chip Select will be automatically locked when written to from the processor data port. + #1 + + + + + AGEN + Device Type for Region + 28 + 31 + read-write + + + + + BUSWAP3 + EBU Bus Write Access Parameter Register + 0x64 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + WRDTACS + Recovery Cycles between Different Regions + 0 + 3 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + WRRECOVC + Recovery Cycles after Write Accesses + 4 + 6 + read-write + + + value1 + No Recovery Phase clock cycles available. + #000 + + + value2 + 1 clock cycle selected. + #001 + + + value3 + 6 clock cycles selected. + #110 + + + value4 + 7 clock cycles selected. + #111 + + + + + WAITWRC + Programmed Wait States for write accesses + 7 + 11 + read-write + + + value1 + 1 wait state. + #00000 + + + value2 + 1 wait states. + #00001 + + + value3 + 2 wait state. + #00010 + + + value4 + 30 wait states. + #11110 + + + value5 + 31 wait states. + #11111 + + + + + DATAC + Data Hold Cycles for Write Accesses + 12 + 15 + read-write + + + value1 + No Recovery Phase clock cycles available. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + EXTCLOCK + Frequency of external clock at pin BFCLKO + 16 + 17 + read-write + + + value1 + Equal to INT_CLK frequency. + #00 + + + value2 + 1/2 of INT_CLK frequency. + #01 + + + value3 + 1/3 of INT_CLK frequency. + #10 + + + value4 + 1/4 of INT_CLK frequency (default after reset). + #11 + + + + + EXTDATA + Extended data + 18 + 19 + read-write + + + value1 + external memory outputs data every BFCLK cycle + #00 + + + value2 + external memory outputs data every two BFCLK cycles + #01 + + + value3 + external memory outputs data every four BFCLK cycles + #10 + + + value4 + external memory outputs data every eight BFCLK cycles + #11 + + + + + CMDDELAY + Command Delay Cycles + 20 + 23 + read-write + + + value1 + 0 clock cycle selected. + #0000 + + + value2 + 1 clock cycle selected. + #0001 + + + value3 + 14 clock cycles selected. + #1110 + + + value4 + 15 clock cycles selected. + #1111 + + + + + AHOLDC + Address Hold Cycles + 24 + 27 + read-write + + + value1 + 0 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + ADDRC + Address Cycles + 28 + 31 + read-write + + + value1 + 1 clock cycle selected + #0000 + + + value2 + 1 clock cycle selected + #0001 + + + value3 + 14 clock cycles selected + #1110 + + + value4 + 15 clock cycles selected + #1111 + + + + + + + SDRMCON + EBU SDRAM Control Register + 0x68 + 32 + 0x80000000 + 0xFFFFFFFF + + + SDCMSEL + SDRAM clock mode select + 31 + 31 + read-write + + + value1 + clock disabled between accesses + #1 + + + value2 + clock continuously runs + #0 + + + + + PWR_MODE + Power Save Mode used for gated clock mode + 29 + 30 + read-write + + + value1 + precharge before clock stop (default after reset) + 0x0 + + + value2 + auto-precharge before clock stop + 0x1 + + + value3 + active power down (stop clock without precharge) + 0x2 + + + value4 + clock stop power down + 0x3 + + + + + CLKDIS + Disable SDRAM clock output + 28 + 28 + read-write + + + value1 + clock enabled + #0 + + + value2 + clock disabled + #1 + + + + + CRCE + Row cycle time counter extension + 25 + 27 + read-write + + + BANKM + Mask for bank tag + 22 + 24 + read-write + + + value2 + Address bit 21 to 20 + 0x1 + + + value3 + Address bit 22 to 21 + 0x2 + + + value4 + Address bit 23 to 22 + 0x3 + + + value5 + Address bit 24 to 23 + 0x4 + + + value6 + Address bit 25 to 24 + 0x5 + + + value7 + Address bit 26 to 25 + 0x6 + + + value8 + Address bit 26 + 0x7 + + + + + ROWM + Mask for row tag + 19 + 21 + read-write + + + value2 + Address bit 26 to 9 + 0x1 + + + value3 + Address bit 26 to 10 + 0x2 + + + value4 + Address bit 26 to 11 + 0x3 + + + value5 + Address bit 26 to 12 + 0x4 + + + value6 + Address bit 26 to 13 + 0x5 + + + + + CRC + Row cycle time counter + 16 + 18 + read-write + + + CRCD + Row to column delay counter + 14 + 15 + read-write + + + AWIDTH + Width of column address + 12 + 13 + read-write + + + value1 + do not use + 0x0 + + + value2 + Address(8:0) + 0x1 + + + value3 + Address(9:0) + 0x2 + + + value4 + Address(10:0) + 0x3 + + + + + CRP + Row precharge time counter + 10 + 11 + read-write + + + CRSC + Mode register set-up time + 8 + 9 + read-write + + + CRFSH + Initialization refresh commands counter + 4 + 7 + read-write + + + CRAS + Row to precharge delay counter + 0 + 3 + read-write + + + + + SDRMOD + EBU SDRAM Mode Register + 0x6C + 32 + 0x00000020 + 0xFFFFFFFF + + + XBA + Extended Operation Bank Select + 28 + 31 + read-write + + + XOPM + Extended Operation Mode + 16 + 27 + read-write + + + COLDSTART + SDRAM coldstart + 15 + 15 + write-only + + + OPMODE + Operation Mode + 7 + 13 + read-write + + + value1 + Only this value must be written (default after reset) + #000000 + + + + + CASLAT + CAS latency + 4 + 6 + read-write + + + value1 + Two clocks (default after reset) + 2 + + + value2 + Three clocks + 3 + + + + + BTYP + Burst type + 3 + 3 + read-write + + + value1 + Only this value should be written (default after reset) + #0 + + + + + BURSTL + Burst length + 0 + 2 + read-write + + + value1 + 1 (default after reset) + 0 + + + value2 + 2 + 1 + + + value3 + 4 + 2 + + + value4 + 8 + 3 + + + value5 + 16 + 4 + + + + + + + SDRMREF + EBU SDRAM Refresh Control Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + RES_DLY + Delay on Power Down Exit + 25 + 27 + read-write + + + ARFSH + Auto Refresh on Self refresh Exit + 24 + 24 + read-write + + + SELFREX_DLY + Self Refresh Exit Delay + 16 + 23 + read-write + + + ERFSHC + Extended Refresh Counter Period + 14 + 15 + read-write + + + AUTOSELFR + Automatic Self Refresh + 13 + 13 + read-write + + + SELFREN + Self Refresh Entry + 12 + 12 + read-write + + + SELFRENST + Self Refresh Entry Status. + 11 + 11 + read-only + + + SELFREX + Self Refresh Exit (Power Up). + 10 + 10 + read-write + + + SELFREXST + Self Refresh Exit Status. + 9 + 9 + read-only + + + REFRESHR + Number of refresh commands + 6 + 8 + read-write + + + REFRESHC + Refresh counter period + 0 + 5 + read-write + + + + + SDRSTAT + EBU SDRAM Status Register + 0x74 + 32 + 0x00010000 + 0xFFFFFFFF + + + SDERR + SDRAM read error + 2 + 2 + read-only + + + value1 + Reads running successfully + #0 + + + value2 + Read error condition has been detected + #1 + + + + + SDRMBUSY + SDRAM Busy + 1 + 1 + read-only + + + value1 + Power-up initialization sequence is not running + #0 + + + value2 + Power-up initialization sequence is running + #1 + + + + + REFERR + SDRAM Refresh Error + 0 + 0 + read-only + + + value1 + No refresh error. + #0 + + + value2 + Refresh error occurred. + #1 + + + + + + + + + ETH0_CON + Ethernet Control Register + ETH + 0x50004040 + + 0 + 4 + registers + + + + ETH0_CON + Ethernet 0 Port Control Register + 0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXD0 + MAC Receive Input 0 + 0 + 1 + read-write + + + value1 + Data input RXD0A is selected + #00 + + + value2 + Data input RXD0B is selected + #01 + + + value3 + Data input RXD0C is selected + #10 + + + value4 + Data input RXD0D is selected + #11 + + + + + RXD1 + MAC Receive Input 1 + 2 + 3 + read-write + + + value1 + Data input RXD1A is selected + #00 + + + value2 + Data input RXD1B is selected + #01 + + + value3 + Data input RXD1C is selected + #10 + + + value4 + Data input RXD1D is selected + #11 + + + + + RXD2 + MAC Receive Input 2 + 4 + 5 + read-write + + + value1 + Data input RXD2A is selected + #00 + + + value2 + Data input RXD2B is selected + #01 + + + value3 + Data input RXD2C is selected + #10 + + + value4 + Data input RXD2D is selected + #11 + + + + + RXD3 + MAC Receive Input 3 + 6 + 7 + read-write + + + value1 + Data input RXD3A is selected + #00 + + + value2 + Data input RXD3B is selected + #01 + + + value3 + Data input RXD3C is selected + #10 + + + value4 + Data input RXD3D is selected + #11 + + + + + CLK_RMII + RMII clock input + 8 + 9 + read-write + + + value1 + Data input RMIIA is selected + #00 + + + value2 + Data input RMIIB is selected + #01 + + + value3 + Data input RMIIC is selected + #10 + + + value4 + Data input RMIID is selected + #11 + + + + + CRS_DV + CRS_DV input + 10 + 11 + read-write + + + value1 + Data input CRS_DVA is selected + #00 + + + value2 + Data input CRS_DVB is selected + #01 + + + value3 + Data input CRS_DVC is selected + #10 + + + value4 + Data input CRS_DVD is selected + #11 + + + + + CRS + CRS input + 12 + 13 + read-write + + + value1 + Data input CRSA + #00 + + + value2 + Data input CRSB + #01 + + + value3 + Data input CRSC + #10 + + + value4 + Data input CRSD + #11 + + + + + RXER + RXER Input + 14 + 15 + read-write + + + value1 + Data input RXERA is selected + #00 + + + value2 + Data input RXERB is selected + #01 + + + value3 + Data input RXERC is selected + #10 + + + value4 + Data input RXERD is selected + #11 + + + + + COL + COL input + 16 + 17 + read-write + + + value1 + Data input COLA is selected + #00 + + + value2 + Data input COLB is selected + #01 + + + value3 + Data input COLC is selected + #10 + + + value4 + Data input COLD is selected + #11 + + + + + CLK_TX + CLK_TX input + 18 + 19 + read-write + + + value1 + Data input CLK_TXA is selected + #00 + + + value2 + Data input CLK_TXB is selected + #01 + + + value3 + Data input CLK_TXC is selected + #10 + + + value4 + Data input CLK_TXD is selected + #11 + + + + + MDIO + MDIO Input Select + 22 + 23 + read-write + + + value1 + Data input MDIA is selected + #00 + + + value2 + Data input MDIB is selected + #01 + + + value3 + Data input MDIC is selected + #10 + + + value4 + Data input MDID is selected + #11 + + + + + INFSEL + Ethernet MAC Interface Selection + 26 + 26 + read-write + + + value1 + MII + #0 + + + value2 + RMII + #1 + + + + + + + + + ETH0 + Ethernet Unit 0 + ETH + ETH + 0x5000C000 + + 0x0 + 0x4000 + registers + + + ETH0_0 + Ethernet (Module 0) + 108 + + + + MAC_CONFIGURATION + MAC Configuration Register + 0x0000 + 32 + 0x00008000 + 0xFFFFFFFF + + + PRELEN + Preamble Length for Transmit Frames + 0 + 1 + read-write + + + RE + Receiver Enable + 2 + 2 + read-write + + + TE + Transmitter Enable + 3 + 3 + read-write + + + DC + Deferral Check + 4 + 4 + read-write + + + BL + Back-Off Limit + 5 + 6 + read-write + + + ACS + Automatic Pad or CRC Stripping + 7 + 7 + read-write + + + DR + Disable Retry + 9 + 9 + read-write + + + IPC + Checksum Offload + 10 + 10 + read-write + + + DM + Duplex Mode + 11 + 11 + read-write + + + LM + Loopback Mode + 12 + 12 + read-write + + + DO + Disable Receive Own + 13 + 13 + read-write + + + FES + Speed + 14 + 14 + read-write + + + DCRS + Disable Carrier Sense During Transmission + 16 + 16 + read-write + + + IFG + Inter-Frame Gap + 17 + 19 + read-write + + + JE + Jumbo Frame Enable + 20 + 20 + read-write + + + BE + Frame Burst Enable + 21 + 21 + read-only + + + JD + Jabber Disable + 22 + 22 + read-write + + + WD + Watchdog Disable + 23 + 23 + read-write + + + TC + Transmit Configuration in RMII + 24 + 24 + read-only + + + CST + CRC Stripping of Type Frames + 25 + 25 + read-write + + + TWOKPE + IEEE 802.3as support for 2K packets Enable + 27 + 27 + read-write + + + SARC + Source Address Insertion or Replacement Control + 28 + 30 + read-only + + + + + MAC_FRAME_FILTER + MAC Frame Filter + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + PR + Promiscuous Mode + 0 + 0 + read-write + + + HUC + Hash Unicast + 1 + 1 + read-write + + + HMC + Hash Multicast + 2 + 2 + read-write + + + DAIF + DA Inverse Filtering + 3 + 3 + read-write + + + PM + Pass All Multicast + 4 + 4 + read-write + + + DBF + Disable Broadcast Frames + 5 + 5 + read-write + + + PCF + Pass Control Frames + 6 + 7 + read-write + + + SAIF + SA Inverse Filtering + 8 + 8 + read-write + + + SAF + Source Address Filter Enable + 9 + 9 + read-write + + + HPF + Hash or Perfect Filter + 10 + 10 + read-write + + + VTFE + VLAN Tag Filter Enable + 16 + 16 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + 20 + 20 + read-only + + + DNTU + Drop non-TCP/UDP over IP Frames + 21 + 21 + read-only + + + RA + Receive All + 31 + 31 + read-write + + + + + HASH_TABLE_HIGH + Hash Table High Register + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + 0 + 31 + read-write + + + + + HASH_TABLE_LOW + Hash Table Low Register + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + 0 + 31 + read-write + + + + + GMII_ADDRESS + MII Address Register + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + MB + MII Busy + 0 + 0 + read-write + + + MW + MII Write + 1 + 1 + read-write + + + CR + CSR Clock Range + 2 + 5 + read-write + + + MR + MII Register + 6 + 10 + read-write + + + PA + Physical Layer Address + 11 + 15 + read-write + + + + + GMII_DATA + MII Data Register + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + MD + MII Data + 0 + 15 + read-write + + + + + FLOW_CONTROL + Flow Control Register + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + FCA_BPA + Flow Control Busy or Backpressure Activate + 0 + 0 + read-write + + + TFE + Transmit Flow Control Enable + 1 + 1 + read-write + + + RFE + Receive Flow Control Enable + 2 + 2 + read-write + + + UP + Unicast Pause Frame Detect + 3 + 3 + read-write + + + PLT + Pause Low Threshold + 4 + 5 + read-write + + + DZPQ + Disable Zero-Quanta Pause + 7 + 7 + read-write + + + PT + Pause Time + 16 + 31 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + VL + VLAN Tag Identifier for Receive Frames + 0 + 15 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + 16 + 16 + read-write + + + VTIM + VLAN Tag Inverse Match Enable + 17 + 17 + read-write + + + ESVL + Enable S-VLAN + 18 + 18 + read-write + + + VTHM + VLAN Tag Hash Table Match Enable + 19 + 19 + read-only + + + + + VERSION + Version Register + 0x0020 + 32 + 0x00001037 + 0xFFFFFFFF + + + SNPSVER + Synopsys-defined Version (3.7) + 0 + 7 + read-only + + + USERVER + User-defined Version (Configured with the coreConsultant) + 8 + 15 + read-only + + + + + DEBUG + Debug Register + 0x0024 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPESTS + MAC MII Receive Protocol Engine Status + 0 + 0 + read-only + + + RFCFCSTS + MAC Receive Frame Controller FIFO Status + 1 + 2 + read-only + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + 4 + 4 + read-only + + + RRCSTS + MTL Rx FIFO Read Controller State + 5 + 6 + read-only + + + RXFSTS + MTL Rx FIFO Fill-level Status + 8 + 9 + read-only + + + TPESTS + MAC MII Transmit Protocol Engine Status + 16 + 16 + read-only + + + TFCSTS + MAC Transmit Frame Controller Status + 17 + 18 + read-only + + + TXPAUSED + MAC transmitter in PAUSE + 19 + 19 + read-only + + + TRCSTS + MTL Tx FIFO Read Controller Status + 20 + 21 + read-only + + + TWCSTS + MTL Tx FIFO Write Controller Active Status + 22 + 22 + read-only + + + TXFSTS + MTL Tx FIFO Not Empty Status + 24 + 24 + read-only + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + 25 + 25 + read-only + + + + + REMOTE_WAKE_UP_FRAME_FILTER + Remote Wake Up Frame Filter Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFTR + Remote Wake-Up Frame Filter + 0 + 31 + read-write + + + + + PMT_CONTROL_STATUS + PMT Control and Status Register + 0x002C + 32 + 0x00000000 + 0xFFFFFFFF + + + PWRDWN + Power Down + 0 + 0 + read-write + + + MGKPKTEN + Magic Packet Enable + 1 + 1 + read-write + + + RWKPKTEN + Wake-Up Frame Enable + 2 + 2 + read-write + + + MGKPRCVD + Magic Packet Received + 5 + 5 + read-only + + + RWKPRCVD + Wake-Up Frame Received + 6 + 6 + read-only + + + GLBLUCAST + Global Unicast + 9 + 9 + read-write + + + RWKFILTRST + Wake-Up Frame Filter Register Pointer Reset + 31 + 31 + read-write + + + + + INTERRUPT_STATUS + Interrupt Register + 0x0038 + 32 + 0x00000000 + 0xFFFFFFFF + + + PMTIS + PMT Interrupt Status + 3 + 3 + read-only + + + MMCIS + MMC Interrupt Status + 4 + 4 + read-only + + + MMCRXIS + MMC Receive Interrupt Status + 5 + 5 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status + 6 + 6 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status + 7 + 7 + read-only + + + TSIS + Timestamp Interrupt Status + 9 + 9 + read-only + + + + + INTERRUPT_MASK + Interrupt Mask Register + 0x003C + 32 + 0x00000000 + 0xFFFFFFFF + + + PMTIM + PMT Interrupt Mask + 3 + 3 + read-write + + + TSIM + Timestamp Interrupt Mask + 9 + 9 + read-write + + + + + MAC_ADDRESS0_HIGH + MAC Address0 High Register + 0x0040 + 32 + 0x8000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address0 [47:32] + 0 + 15 + read-write + + + AE + Address Enable + 31 + 31 + read-only + + + + + MAC_ADDRESS0_LOW + MAC Address0 Low Register + 0x0044 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + 0 + 31 + read-write + + + + + MAC_ADDRESS1_HIGH + MAC Address1 High Register + 0x0048 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address1 [47:32] + 0 + 15 + read-write + + + MBC + Mask Byte Control + 24 + 29 + read-write + + + SA + Source Address + 30 + 30 + read-write + + + AE + Address Enable + 31 + 31 + read-write + + + + + MAC_ADDRESS1_LOW + MAC Address1 Low Register + 0x004C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] + 0 + 31 + read-write + + + + + MAC_ADDRESS2_HIGH + MAC Address2 High Register + 0x0050 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address2 [47:32] + 0 + 15 + read-write + + + MBC + Mask Byte Control + 24 + 29 + read-write + + + SA + Source Address + 30 + 30 + read-write + + + AE + Address Enable + 31 + 31 + read-write + + + + + MAC_ADDRESS2_LOW + MAC Address2 Low Register + 0x0054 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address2 [31:0] + 0 + 31 + read-write + + + + + MAC_ADDRESS3_HIGH + MAC Address3 High Register + 0x0058 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + ADDRHI + MAC Address3 [47:32] + 0 + 15 + read-write + + + MBC + Mask Byte Control + 24 + 29 + read-write + + + SA + Source Address + 30 + 30 + read-write + + + AE + Address Enable + 31 + 31 + read-write + + + + + MAC_ADDRESS3_LOW + MAC Address3 Low Register + 0x005C + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ADDRLO + MAC Address3 [31:0] + 0 + 31 + read-write + + + + + MMC_CONTROL + MMC Control Register + 0x0100 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTRST + Counters Reset + 0 + 0 + read-write + + + CNTSTOPRO + Counters Stop Rollover + 1 + 1 + read-write + + + RSTONRD + Reset on Read + 2 + 2 + read-write + + + CNTFREEZ + MMC Counter Freeze + 3 + 3 + read-write + + + CNTPRST + Counters Preset + 4 + 4 + read-write + + + CNTPRSTLVL + Full-Half Preset + 5 + 5 + read-write + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames + 8 + 8 + read-write + + + + + MMC_RECEIVE_INTERRUPT + MMC Receive Interrupt Register + 0x0104 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status + 0 + 0 + read-only + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status + 1 + 1 + read-only + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status. + 2 + 2 + read-only + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status. + 3 + 3 + read-only + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status + 4 + 4 + read-only + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status + 5 + 5 + read-only + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status + 6 + 6 + read-only + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status + 7 + 7 + read-only + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status + 8 + 8 + read-only + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status + 9 + 9 + read-only + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status + 10 + 10 + read-only + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + 11 + 11 + read-only + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + 12 + 12 + read-only + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + 13 + 13 + read-only + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + 14 + 14 + read-only + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + 15 + 15 + read-only + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + 16 + 16 + read-only + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status + 17 + 17 + read-only + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status + 18 + 18 + read-only + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status + 19 + 19 + read-only + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status + 20 + 20 + read-only + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status + 21 + 21 + read-only + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status + 22 + 22 + read-only + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status + 23 + 23 + read-only + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status + 24 + 24 + read-only + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status + 25 + 25 + read-only + + + + + MMC_TRANSMIT_INTERRUPT + MMC Transmit Interrupt Register + 0x0108 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status + 0 + 0 + read-only + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status + 1 + 1 + read-only + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status + 2 + 2 + read-only + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status + 3 + 3 + read-only + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. + 4 + 4 + read-only + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + 5 + 5 + read-only + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + 6 + 6 + read-only + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + 7 + 7 + read-only + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + 8 + 8 + read-only + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + 9 + 9 + read-only + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + 10 + 10 + read-only + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + 11 + 11 + read-only + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + 12 + 12 + read-only + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status + 13 + 13 + read-only + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status + 14 + 14 + read-only + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + 15 + 15 + read-only + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status + 16 + 16 + read-only + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status + 17 + 17 + read-only + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status + 18 + 18 + read-only + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status + 19 + 19 + read-only + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status + 20 + 20 + read-only + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status + 21 + 21 + read-only + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status + 22 + 22 + read-only + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status + 23 + 23 + read-only + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status + 24 + 24 + read-only + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status + 25 + 25 + read-only + + + + + MMC_RECEIVE_INTERRUPT_MASK + MMC Reveive Interrupt Mask Register + 0x010C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXGBFRMIM + MMC Receive Good Bad Frame Counter Interrupt Mask + 0 + 0 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask + 1 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask + 2 + 2 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask + 3 + 3 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask + 4 + 4 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask + 5 + 5 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask + 6 + 6 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask + 7 + 7 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask + 8 + 8 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask + 9 + 9 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask + 10 + 10 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + 11 + 11 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + 12 + 12 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + 13 + 13 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + 14 + 14 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + 15 + 15 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + 16 + 16 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask + 17 + 17 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask + 18 + 18 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask + 19 + 19 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask + 20 + 20 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask + 21 + 21 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + 22 + 22 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask + 23 + 23 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask + 24 + 24 + read-write + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask + 25 + 25 + read-write + + + + + MMC_TRANSMIT_INTERRUPT_MASK + MMC Transmit Interrupt Mask Register + 0x0110 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask + 0 + 0 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask + 1 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask + 2 + 2 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask + 3 + 3 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + 4 + 4 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + 5 + 5 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + 6 + 6 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + 7 + 7 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + 8 + 8 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + 9 + 9 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + 10 + 10 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + 11 + 11 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + 12 + 12 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask + 13 + 13 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask + 14 + 14 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + 15 + 15 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask + 16 + 16 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask + 17 + 17 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask + 18 + 18 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask + 19 + 19 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask + 20 + 20 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask + 21 + 21 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + 22 + 22 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask + 23 + 23 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask + 24 + 24 + read-write + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask + 25 + 25 + read-write + + + + + TX_OCTET_COUNT_GOOD_BAD + Transmit Octet Count for Good and Bad Frames Register + 0x0114 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXOCTGB + This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes. + 0 + 31 + read-only + + + + + TX_FRAME_COUNT_GOOD_BAD + Transmit Frame Count for Goodand Bad Frames Register + 0x0118 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFRMGB + This field indicates the number of good and bad frames transmitted, exclusive of retried frames + 0 + 31 + read-only + + + + + TX_BROADCAST_FRAMES_GOOD + Transmit Frame Count for Good Broadcast Frames + 0x011C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXBCASTG + This field indicates the number of transmitted good broadcast frames. + 0 + 31 + read-only + + + + + TX_MULTICAST_FRAMES_GOOD + Transmit Frame Count for Good Multicast Frames + 0x0120 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXMCASTG + This field indicates the number of transmitted good multicast frames. + 0 + 31 + read-only + + + + + TX_64OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 64 Byte Frames + 0x0124 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX64OCTGB + This field indicates the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_65TO127OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames + 0x0128 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX65_127OCTGB + This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_128TO255OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames + 0x012C + 32 + 0x00000000 + 0xFFFFFFFF + + + TX128_255OCTGB + This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_256TO511OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames + 0x0130 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX256_511OCTGB + This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_512TO1023OCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames + 0x0134 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX512_1023OCTGB + This field indicates the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD + Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames + 0x0138 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX1024_MAXOCTGB + This field indicates the number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + TX_UNICAST_FRAMES_GOOD_BAD + Transmit Frame Count for Good and Bad Unicast Frames + 0x013C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXUCASTGB + This field indicates the number of transmitted good and bad unicast frames. + 0 + 31 + read-only + + + + + TX_MULTICAST_FRAMES_GOOD_BAD + Transmit Frame Count for Good and Bad Multicast Frames + 0x0140 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXMCASTGB + This field indicates the number of transmitted good and bad multicast frames. + 0 + 31 + read-only + + + + + TX_BROADCAST_FRAMES_GOOD_BAD + Transmit Frame Count for Good and Bad Broadcast Frames + 0x0144 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXBCASTGB + This field indicates the number of transmitted good and bad broadcast frames. + 0 + 31 + read-only + + + + + TX_UNDERFLOW_ERROR_FRAMES + Transmit Frame Count for Underflow Error Frames + 0x0148 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXUNDRFLW + This field indicates the number of frames aborted because of frame underflow error. + 0 + 31 + read-only + + + + + TX_SINGLE_COLLISION_GOOD_FRAMES + Transmit Frame Count for Frames Transmitted after Single Collision + 0x014C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXSNGLCOLG + This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode. + 0 + 31 + read-only + + + + + TX_MULTIPLE_COLLISION_GOOD_FRAMES + Transmit Frame Count for Frames Transmitted after Multiple Collision + 0x0150 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXMULTCOLG + This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode. + 0 + 31 + read-only + + + + + TX_DEFERRED_FRAMES + Tx Deferred Frames Register + 0x0154 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXDEFRD + This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode. + 0 + 31 + read-only + + + + + TX_LATE_COLLISION_FRAMES + Transmit Frame Count for Late Collision Error Frames + 0x0158 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXLATECOL + This field indicates the number of frames aborted because of late collision error. + 0 + 31 + read-only + + + + + TX_EXCESSIVE_COLLISION_FRAMES + Transmit Frame Count for Excessive Collision Error Frames + 0x015C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXEXSCOL + This field indicates the number of frames aborted because of excessive (16) collision error. + 0 + 31 + read-only + + + + + TX_CARRIER_ERROR_FRAMES + Transmit Frame Count for Carrier Sense Error Frames + 0x0160 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXCARR + This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier). + 0 + 31 + read-only + + + + + TX_OCTET_COUNT_GOOD + Tx Octet Count Good Register + 0x0164 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXOCTG + This field indicates the number of bytes transmitted, exclusive of preamble, in good frames. + 0 + 31 + read-only + + + + + TX_FRAME_COUNT_GOOD + Tx Frame Count Good Register + 0x0168 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFRMG + This field indicates the number of transmitted good frames, exclusive of preamble. + 0 + 31 + read-only + + + + + TX_EXCESSIVE_DEFERRAL_ERROR + Transmit Frame Count for Excessive Deferral Error Frames + 0x016C + 32 + 0x00000000 + 0xFFFFFFFF + + + TXEXSDEF + This field indicates the number of frames aborted because of excessive deferral error, that is, frames deferred for more than two max-sized frame times. + 0 + 31 + read-only + + + + + TX_PAUSE_FRAMES + Transmit Frame Count for Good PAUSE Frames + 0x0170 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXPAUSE + This field indicates the number of transmitted good PAUSE frames. + 0 + 31 + read-only + + + + + TX_VLAN_FRAMES_GOOD + Transmit Frame Count for Good VLAN Frames + 0x0174 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXVLANG + This register maintains the number of transmitted good VLAN frames, exclusive of retried frames. + 0 + 31 + read-only + + + + + TX_OSIZE_FRAMES_GOOD + Transmit Frame Count for Good Oversize Frames + 0x0178 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXOSIZG + This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled by setting MAC Configuration.2KPE). + 0 + 31 + read-only + + + + + RX_FRAMES_COUNT_GOOD_BAD + Receive Frame Count for Good and Bad Frames + 0x0180 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFRMGB + This field indicates the number of received good and bad frames. + 0 + 31 + read-only + + + + + RX_OCTET_COUNT_GOOD_BAD + Receive Octet Count for Good and Bad Frames + 0x0184 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOCTGB + This field indicates the number of bytes received, exclusive of preamble, in good and bad frames. + 0 + 31 + read-only + + + + + RX_OCTET_COUNT_GOOD + Rx Octet Count Good Register + 0x0188 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOCTG + This field indicates the number of bytes received, exclusive of preamble, only in good frames. + 0 + 31 + read-only + + + + + RX_BROADCAST_FRAMES_GOOD + Receive Frame Count for Good Broadcast Frames + 0x018C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXBCASTG + This field indicates the number of received good broadcast frames. + 0 + 31 + read-only + + + + + RX_MULTICAST_FRAMES_GOOD + Receive Frame Count for Good Multicast Frames + 0x0190 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXMCASTG + This field indicates the number of received good multicast frames. + 0 + 31 + read-only + + + + + RX_CRC_ERROR_FRAMES + Receive Frame Count for CRC Error Frames + 0x0194 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXCRCERR + This field indicates the number of frames received with CRC error. + 0 + 31 + read-only + + + + + RX_ALIGNMENT_ERROR_FRAMES + Receive Frame Count for Alignment Error Frames + 0x0198 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXALGNERR + This field indicates the number of frames received with alignment (dribble) error. + 0 + 31 + read-only + + + + + RX_RUNT_ERROR_FRAMES + Receive Frame Count for Runt Error Frames + 0x019C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXRUNTERR + This field indicates the number of frames received with runt error(<64 bytes and CRC error). + 0 + 31 + read-only + + + + + RX_JABBER_ERROR_FRAMES + Receive Frame Count for Jabber Error Frames + 0x01A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXJABERR + This field indicates the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. + 0 + 31 + read-only + + + + + RX_UNDERSIZE_FRAMES_GOOD + Receive Frame Count for Undersize Frames + 0x01A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUNDERSZG + This field indicates the number of frames received with length less than 64 bytes and without errors. + 0 + 31 + read-only + + + + + RX_OVERSIZE_FRAMES_GOOD + Rx Oversize Frames Good Register + 0x01A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOVERSZG + This field indicates the number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled by setting MAC Configuration.2KPE). + 0 + 31 + read-only + + + + + RX_64OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 64 Byte Frames + 0x01AC + 32 + 0x00000000 + 0xFFFFFFFF + + + RX64OCTGB + This field indicates the number of received good and bad frames with length 64 bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_65TO127OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 65 to 127 Bytes Frames + 0x01B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX65_127OCTGB + This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_128TO255OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 128 to 255 Bytes Frames + 0x01B4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX128_255OCTGB + This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_256TO511OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 256 to 511 Bytes Frames + 0x01B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX256_511OCTGB + This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_512TO1023OCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames + 0x01BC + 32 + 0x00000000 + 0xFFFFFFFF + + + RX512_1023OCTGB + This field indicates the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. + 0 + 31 + read-only + + + + + RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX1024_MAXOCTGB + This field indicates the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 31 + read-only + + + + + RX_UNICAST_FRAMES_GOOD + Receive Frame Count for Good Unicast Frames + 0x01C4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUCASTG + This field indicates the number of received good unicast frames. + 0 + 31 + read-only + + + + + RX_LENGTH_ERROR_FRAMES + Receive Frame Count for Length Error Frames + 0x01C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXLENERR + This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field. + 0 + 31 + read-only + + + + + RX_OUT_OF_RANGE_TYPE_FRAMES + Receive Frame Count for Out of Range Frames + 0x01CC + 32 + 0x00000000 + 0xFFFFFFFF + + + RXOUTOFRNG + This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). + 0 + 31 + read-only + + + + + RX_PAUSE_FRAMES + Receive Frame Count for PAUSE Frames + 0x01D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXPAUSEFRM + This field indicates the number of received good and valid PAUSE frames. + 0 + 31 + read-only + + + + + RX_FIFO_OVERFLOW_FRAMES + Receive Frame Count for FIFO Overflow Frames + 0x01D4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFOOVFL + This field indicates the number of received frames missed because of FIFO overflow. + 0 + 31 + read-only + + + + + RX_VLAN_FRAMES_GOOD_BAD + Receive Frame Count for Good and Bad VLAN Frames + 0x01D8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXVLANFRGB + This field indicates the number of received good and bad VLAN frames. + 0 + 31 + read-only + + + + + RX_WATCHDOG_ERROR_FRAMES + Receive Frame Count for Watchdog Error Frames + 0x01DC + 32 + 0x00000000 + 0xFFFFFFFF + + + RXWDGERR + This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). + 0 + 31 + read-only + + + + + RX_RECEIVE_ERROR_FRAMES + Receive Frame Count for Receive Error Frames + 0x01E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXRCVERR + This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). + 0 + 31 + read-only + + + + + RX_CONTROL_FRAMES_GOOD + Receive Frame Count for Good Control Frames Frames + 0x01E4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXCTRLG + This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load). + 0 + 31 + read-only + + + + + MMC_IPC_RECEIVE_INTERRUPT_MASK + MMC Receive Checksum Offload Interrupt Mask Register + 0x0200 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask + 0 + 0 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask + 1 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask + 2 + 2 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask + 3 + 3 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask + 4 + 4 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask + 5 + 5 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask + 6 + 6 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask + 7 + 7 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask + 8 + 8 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask + 9 + 9 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask + 10 + 10 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask + 11 + 11 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask + 12 + 12 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask + 13 + 13 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask + 16 + 16 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask + 17 + 17 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask + 18 + 18 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask + 19 + 19 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask + 20 + 20 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask + 21 + 21 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask + 22 + 22 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask + 23 + 23 + read-write + + + RXUDPGOIM + MMC Receive UDP Good Octet Counter Interrupt Mask + 24 + 24 + read-write + + + RXUDPEROIM + MMC Receive UDP Error Octet Counter Interrupt Mask + 25 + 25 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask + 26 + 26 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask + 27 + 27 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask + 28 + 28 + read-write + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask + 29 + 29 + read-write + + + + + MMC_IPC_RECEIVE_INTERRUPT + MMC Receive Checksum Offload Interrupt Register + 0x0208 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status + 0 + 0 + read-only + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status + 1 + 1 + read-only + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status + 2 + 2 + read-only + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status + 3 + 3 + read-only + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status + 4 + 4 + read-only + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status + 5 + 5 + read-only + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status + 6 + 6 + read-only + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status + 7 + 7 + read-only + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status + 8 + 8 + read-only + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status + 9 + 9 + read-only + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status + 10 + 10 + read-only + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status + 11 + 11 + read-only + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status + 12 + 12 + read-only + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status + 13 + 13 + read-only + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status + 16 + 16 + read-only + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status + 17 + 17 + read-only + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status + 18 + 18 + read-only + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status + 19 + 19 + read-only + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status + 20 + 20 + read-only + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status + 21 + 21 + read-only + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status + 22 + 22 + read-only + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status + 23 + 23 + read-only + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status + 24 + 24 + read-only + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status + 25 + 25 + read-only + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status + 26 + 26 + read-only + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status + 27 + 27 + read-only + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status + 28 + 28 + read-only + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status + 29 + 29 + read-only + + + + + RXIPV4_GOOD_FRAMES + RxIPv4 Good Frames Register + 0x0210 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GDFRM + This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. + 0 + 31 + read-only + + + + + RXIPV4_HEADER_ERROR_FRAMES + Receive IPV4 Header Error Frame Counter Register + 0x0214 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4HDRERRFRM + This field indicates the number of IPv4 datagrams received with header errors (checksum, length, or version mismatch). + 0 + 31 + read-only + + + + + RXIPV4_NO_PAYLOAD_FRAMES + Receive IPV4 No Payload Frame Counter Register + 0x0218 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4NOPAYFRM + This field indicates the number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine. + 0 + 31 + read-only + + + + + RXIPV4_FRAGMENTED_FRAMES + Receive IPV4 Fragmented Frame Counter Register + 0x021C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4FRAGFRM + This field indicates the number of good IPv4 datagrams received with fragmentation. + 0 + 31 + read-only + + + + + RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES + Receive IPV4 UDP Checksum Disabled Frame Counter Register + 0x0220 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4UDSBLFRM + This field indicates the number of received good IPv4 datagrams which have the UDP payload with checksum disabled. + 0 + 31 + read-only + + + + + RXIPV6_GOOD_FRAMES + RxIPv6 Good Frames Register + 0x0224 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6GDFRM + This field indicates the number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads. + 0 + 31 + read-only + + + + + RXIPV6_HEADER_ERROR_FRAMES + Receive IPV6 Header Error Frame Counter Register + 0x0228 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6HDRERRFRM + This field indicates the number of IPv6 datagrams received with header errors (length or version mismatch). + 0 + 31 + read-only + + + + + RXIPV6_NO_PAYLOAD_FRAMES + Receive IPV6 No Payload Frame Counter Register + 0x022C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6NOPAYFRM + This field indicates the number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers. + 0 + 31 + read-only + + + + + RXUDP_GOOD_FRAMES + RxUDP Good Frames Register + 0x0230 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPGDFRM + This field indicates the number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented. + 0 + 31 + read-only + + + + + RXUDP_ERROR_FRAMES + RxUDP Error Frames Register + 0x0234 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPERRFRM + This field indicates the number of good IP datagrams whose UDP payload has a checksum error. + 0 + 31 + read-only + + + + + RXTCP_GOOD_FRAMES + RxTCP Good Frames Register + 0x0238 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPGDFRM + This field indicates the number of good IP datagrams with a good TCP payload. + 0 + 31 + read-only + + + + + RXTCP_ERROR_FRAMES + RxTCP Error Frames Register + 0x023C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPERRFRM + This field indicates the number of good IP datagrams whose TCP payload has a checksum error. + 0 + 31 + read-only + + + + + RXICMP_GOOD_FRAMES + RxICMP Good Frames Register + 0x0240 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPGDFRM + This field indicates the number of good IP datagrams with a good ICMP payload. + 0 + 31 + read-only + + + + + RXICMP_ERROR_FRAMES + RxICMP Error Frames Register + 0x0244 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPERRFRM + This field indicates the number of good IP datagrams whose ICMP payload has a checksum error. + 0 + 31 + read-only + + + + + RXIPV4_GOOD_OCTETS + RxIPv4 Good Octets Register + 0x0250 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4GDOCT + This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. The Ethernet header, FCS, pad, or IP pad + 0 + 31 + read-only + + + + + RXIPV4_HEADER_ERROR_OCTETS + Receive IPV4 Header Error Octet Counter Register + 0x0254 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4HDRERROCT + This field indicates the number of bytes received in the IPv4 datagrams with header errors (checksum, length, or version mismatch). The value in the Length field of IPv4 header is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV4_NO_PAYLOAD_OCTETS + Receive IPV4 No Payload Octet Counter Register + 0x0258 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4NOPAYOCT + This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV4_FRAGMENTED_OCTETS + Receive IPV4 Fragmented Octet Counter Register + 0x025C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4FRAGOCT + This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS + Receive IPV4 Fragmented Octet Counter Register + 0x0260 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV4UDSBLOCT + This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXIPV6_GOOD_OCTETS + RxIPv6 Good Octets Register + 0x0264 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6GDOCT + Thsi field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data. + 0 + 31 + read-only + + + + + RXIPV6_HEADER_ERROR_OCTETS + Receive IPV6 Header Error Octet Counter Register + 0x0268 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6HDRERROCT + This field indicates the number of bytes received in IPv6 datagrams with header errors (length or version mismatch). The value in the IPv6 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXIPV6_NO_PAYLOAD_OCTETS + Receive IPV6 No Payload Octet Counter Register + 0x026C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXIPV6NOPAYOCT + This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter. + 0 + 31 + read-only + + + + + RXUDP_GOOD_OCTETS + Receive UDP Good Octets Register + 0x0270 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPGDOCT + This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXUDP_ERROR_OCTETS + Receive UDP Error Octets Register + 0x0274 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXUDPERROCT + This field indicates the number of bytes received in a UDP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXTCP_GOOD_OCTETS + Receive TCP Good Octets Register + 0x0278 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPGDOCT + This field indicates the number of bytes received in a good TCP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXTCP_ERROR_OCTETS + Receive TCP Error Octets Register + 0x027C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXTCPERROCT + Thsi field indicates the number of bytes received in a TCP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXICMP_GOOD_OCTETS + Receive ICMP Good Octets Register + 0x0280 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPGDOCT + This field indicates the number of bytes received in a good ICMP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter. + 0 + 31 + read-only + + + + + RXICMP_ERROR_OCTETS + Receive ICMP Error Octets Register + 0x0284 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXICMPERROCT + Number of bytes received in an ICMP segment with checksum errors + 0 + 31 + read-only + + + + + TIMESTAMP_CONTROL + Timestamp Control Register + 0x0700 + 32 + 0x00002000 + 0xFFFFFFFF + + + TSENA + Timestamp Enable + 0 + 0 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update + 1 + 1 + read-write + + + TSINIT + Timestamp Initialize + 2 + 2 + read-write + + + TSUPDT + Timestamp Update + 3 + 3 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable + 4 + 4 + read-write + + + TSADDREG + Addend Reg Update + 5 + 5 + read-write + + + TSENALL + Enable Timestamp for All Frames + 8 + 8 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control + 9 + 9 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format + 10 + 10 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames + 11 + 11 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent Over IPv6-UDP + 12 + 12 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + 13 + 13 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages + 14 + 14 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master + 15 + 15 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + 16 + 17 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering + 18 + 18 + read-write + + + + + SUB_SECOND_INCREMENT + Sub-Second Increment Register + 0x0704 + 32 + 0x00000000 + 0xFFFFFFFF + + + SSINC + Sub-second Increment Value + 0 + 7 + read-write + + + + + SYSTEM_TIME_SECONDS + System Time - Seconds Register + 0x0708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + 0 + 31 + read-only + + + + + SYSTEM_TIME_NANOSECONDS + System Time Nanoseconds Register + 0x070C + 32 + 0x00000000 + 0xFFFFFFFF + + + TSSS + Timestamp Sub Seconds + 0 + 30 + read-only + + + + + SYSTEM_TIME_SECONDS_UPDATE + System Time - Seconds Update Register + 0x0710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + 0 + 31 + read-write + + + + + SYSTEM_TIME_NANOSECONDS_UPDATE + System Time Nanoseconds Update Register + 0x0714 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSSS + Timestamp Sub Second + 0 + 30 + read-write + + + ADDSUB + Add or subtract time + 31 + 31 + read-write + + + + + TIMESTAMP_ADDEND + Timestamp Addend Register + 0x0718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register + 0 + 31 + read-write + + + + + TARGET_TIME_SECONDS + Target Time Seconds Register + 0x071C + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + 0 + 31 + read-write + + + + + TARGET_TIME_NANOSECONDS + Target Time Nanoseconds Register + 0x0720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TTSLO + Target Timestamp Low Register + 0 + 30 + read-write + + + TRGTBUSY + Target Time Register Busy + 31 + 31 + read-only + + + + + SYSTEM_TIME_HIGHER_WORD_SECONDS + System Time - Higher Word Seconds Register + 0x0724 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSHWR + Timestamp Higher Word Register + 0 + 15 + read-write + + + + + TIMESTAMP_STATUS + Timestamp Status Register + 0x0728 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSSOVF + Timestamp Seconds Overflow + 0 + 0 + read-only + + + TSTARGT + Timestamp Target Time Reached + 1 + 1 + read-only + + + TSTRGTERR + Timestamp Target Time Error + 3 + 3 + read-only + + + TSTARGT1 + Timestamp Target Time Reached for Target Time PPS1 + 4 + 4 + read-only + + + TSTRGTERR1 + Timestamp Target Time Error + 5 + 5 + read-only + + + TSTARGT2 + Timestamp Target Time Reached for Target Time PPS2 + 6 + 6 + read-only + + + TSTRGTERR2 + Timestamp Target Time Error + 7 + 7 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 + 8 + 8 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error + 9 + 9 + read-only + + + + + BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00020101 + 0xFFFFFFFF + + + SWR + Software Reset + 0 + 0 + read-write + + + DA + DMA Arbitration Scheme + 1 + 1 + read-write + + + DSL + Descriptor Skip Length + 2 + 6 + read-write + + + ATDS + Alternate Descriptor Size + 7 + 7 + read-write + + + PBL + Programmable Burst Length + 8 + 13 + read-write + + + PR + Priority Ratio + 14 + 15 + read-write + + + FB + Fixed Burst + 16 + 16 + read-write + + + RPBL + Rx DMA PBL + 17 + 22 + read-write + + + USP + Use Seperate PBL + 23 + 23 + read-write + + + PBLX8 + 8xPBL Mode + 24 + 24 + read-write + + + AAL + Address Aligned Beats + 25 + 25 + read-write + + + MB + Mixed Burst + 26 + 26 + read-write + + + TXPR + Transmit Priority + 27 + 27 + read-write + + + PRWG + Channel Priority Weights + 28 + 29 + read-only + + + + + TRANSMIT_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand + 0 + 31 + read-write + + + + + RECEIVE_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand + 0 + 31 + read-write + + + + + RECEIVE_DESCRIPTOR_LIST_ADDRESS + Receive Descriptor Address Register + 0x100C + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA_32bit + Start of Receive List + 2 + 31 + read-write + + + + + TRANSMIT_DESCRIPTOR_LIST_ADDRESS + Transmit descripter Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA_32bit + Start of Transmit List + 2 + 31 + read-write + + + + + STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0xFFFFFFFF + + + TI + Transmit Interrupt + 0 + 0 + read-write + + + TPS + Transmit Process Stopped + 1 + 1 + read-write + + + TU + Transmit Buffer Unavailable + 2 + 2 + read-write + + + TJT + Transmit Jabber Timeout + 3 + 3 + read-write + + + OVF + Receive Overflow + 4 + 4 + read-write + + + UNF + Transmit Underflow + 5 + 5 + read-write + + + RI + Receive Interrupt + 6 + 6 + read-write + + + RU + Receive Buffer Unavailable + 7 + 7 + read-write + + + RPS + Receive Process Stopped + 8 + 8 + read-write + + + RWT + Receive Watchdog Timeout + 9 + 9 + read-write + + + ETI + Early Transmit Interrupt + 10 + 10 + read-write + + + FBI + Fatal Bus Error Interrupt + 13 + 13 + read-write + + + ERI + Early Receive Interrupt + 14 + 14 + read-write + + + AIS + Abnormal Interrupt Summary + 15 + 15 + read-write + + + NIS + Normal Interrupt Summary + 16 + 16 + read-write + + + RS + Received Process State + 17 + 19 + read-only + + + TS + Transmit Process State + 20 + 22 + read-only + + + EB + Error Bits + 23 + 25 + read-only + + + EMI + ETH MMC Interrupt + 27 + 27 + read-only + + + EPI + ETH PMT Interrupt + 28 + 28 + read-only + + + TTI + Timestamp Trigger Interrupt + 29 + 29 + read-only + + + + + OPERATION_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + SR + Start or Stop Receive + 1 + 1 + read-write + + + OSF + Operate on Second Frame + 2 + 2 + read-write + + + RTC + Receive Threshold Control + 3 + 4 + read-write + + + FUF + Forward Undersized Good Frames + 6 + 6 + read-write + + + FEF + Forward Error Frames + 7 + 7 + read-write + + + ST + Start or Stop Transmission Command + 13 + 13 + read-write + + + TTC + Transmit Threshold Control + 14 + 16 + read-write + + + FTF + Flush Transmit FIFO + 20 + 20 + read-write + + + TSF + Transmit Store and Forward + 21 + 21 + read-write + + + DFF + Disable Flushing of Received Frames + 24 + 24 + read-write + + + RSF + Receive Store and Forward + 25 + 25 + read-write + + + DT + Disable Dropping of TCP/IP Checksum Error Frames + 26 + 26 + read-write + + + + + INTERRUPT_ENABLE + Interrupt Enable Register + 0x101C + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmit Interrupt Enable + 0 + 0 + read-write + + + TSE + Transmit Stopped Enable + 1 + 1 + read-write + + + TUE + Transmit Buffer Unvailable Enable + 2 + 2 + read-write + + + TJE + Transmit Jabber Timeout Enable + 3 + 3 + read-write + + + OVE + Overflow Interrupt Enable + 4 + 4 + read-write + + + UNE + Underflow Interrupt Enable + 5 + 5 + read-write + + + RIE + Receive Interrupt Enable + 6 + 6 + read-write + + + RUE + Receive Buffer Unavailable Enable + 7 + 7 + read-write + + + RSE + Receive Stopped Enable + 8 + 8 + read-write + + + RWE + Receive Watchdog Timeout Enable + 9 + 9 + read-write + + + ETE + Early Transmit Interrupt Enable + 10 + 10 + read-write + + + FBE + Fatal Bus Error Enable + 13 + 13 + read-write + + + ERE + Early Receive Interrupt Enable + 14 + 14 + read-write + + + AIE + Abnormal Interrupt Summary Enable + 15 + 15 + read-write + + + NIE + Normal Interrupt Summary Enable + 16 + 16 + read-write + + + + + MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER + Missed Frame and Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0xFFFFFFFF + + + MISFRMCNT + This field indicates the number of frames missed by the controller because of the RAM Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read. + 0 + 15 + read-only + + + MISCNTOVF + Overflow bit for Missed Frame Counter + 16 + 16 + read-only + + + OVFFRMCNT + This field indicates the number of frames missed by the application. The counter is cleared when this register is read. + 17 + 27 + read-only + + + OVFCNTOVF + Overflow bit for FIFO Overflow Counter + 28 + 28 + read-only + + + + + RECEIVE_INTERRUPT_WATCHDOG_TIMER + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0xFFFFFFFF + + + RIWT + RI Watchdog Timer Count + 0 + 7 + read-write + + + + + AHB_STATUS + AHB Status Register + 0x102C + 32 + 0x00000000 + 0xFFFFFFFF + + + AHBMS + AHB Master Status + 0 + 0 + read-only + + + + + CURRENT_HOST_TRANSMIT_DESCRIPTOR + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer + 0 + 31 + read-only + + + + + CURRENT_HOST_RECEIVE_DESCRIPTOR + Current Host Receive Descriptor Register + 0x104C + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer + 0 + 31 + read-only + + + + + CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer + 0 + 31 + read-only + + + + + CURRENT_HOST_RECEIVE_BUFFER_ADDRESS + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer + 0 + 31 + read-only + + + + + HW_FEATURE + HW Feature Register + 0x1058 + 32 + 0x03052F35 + 0xFFFFFFFF + + + MIISEL + 10 or 100 Mbps support + 0 + 0 + read-only + + + GMIISEL + 1000 Mbps support + 1 + 1 + read-only + + + HDSEL + Half-Duplex support + 2 + 2 + read-only + + + EXTHASHEN + Expanded DA Hash Filter + 3 + 3 + read-only + + + HASHSEL + HASH Filter + 4 + 4 + read-only + + + ADDMACADRSEL + Multiple MAC Address Registers + 5 + 5 + read-only + + + PCSSEL + PCS registers (TBI, SGMII, or RTBI PHY interface) + 6 + 6 + read-only + + + L3L4FLTREN + Layer 3 and Layer 4 Filter Feature + 7 + 7 + read-only + + + SMASEL + SMA (MDIO) Interface + 8 + 8 + read-only + + + RWKSEL + PMT Remote Wakeup + 9 + 9 + read-only + + + MGKSEL + PMT Magic Packet + 10 + 10 + read-only + + + MMCSEL + RMON Module + 11 + 11 + read-only + + + TSVER1SEL + Only IEEE 1588-2002 Timestamp + 12 + 12 + read-only + + + TSVER2SEL + IEEE 1588-2008 Advanced Timestamp + 13 + 13 + read-only + + + EEESEL + Energy Efficient Ethernet + 14 + 14 + read-only + + + AVSEL + AV Feature + 15 + 15 + read-only + + + TXCOESEL + Checksum Offload in Tx + 16 + 16 + read-only + + + RXTYP1COE + IP Checksum Offload (Type 1) in Rx + 17 + 17 + read-only + + + RXTYP2COE + IP Checksum Offload (Type 2) in Rx + 18 + 18 + read-only + + + RXFIFOSIZE + Rx FIFO > 2,048 Bytes + 19 + 19 + read-write + + + RXCHCNT + Number of additional Rx channels + 20 + 21 + read-only + + + TXCHCNT + Number of additional Tx channels + 22 + 23 + read-only + + + ENHDESSEL + Alternate (Enhanced Descriptor) + 24 + 24 + read-only + + + INTTSEN + Timestamping with Internal System Time + 25 + 25 + read-only + + + FLEXIPPSEN + Flexible Pulse-Per-Second Output + 26 + 26 + read-only + + + SAVLANINS + Source Address or VLAN Insertion + 27 + 27 + read-only + + + ACTPHYIF + Active or Selected PHY interface + 28 + 30 + read-only + + + + + + + USB0 + Universal Serial Bus + USB + USB + 0x50040000 + + 0x0 + 0x040000 + registers + + + USB0_0 + Universal Serial Bus (Module 0) + 107 + + + + GOTGCTL + Control and Status Register + 0x000 + 32 + 0x00010000 + 0xFFFFFFFF + + + SesReqScs + Session Request Success + 0 + 0 + read-only + + + value1 + Session request failure + #0 + + + value2 + Session request success + #1 + + + + + SesReq + Session Request + 1 + 1 + read-write + + + value1 + No session request + #0 + + + value2 + Session request + #1 + + + + + VbvalidOvEn + VBUS Valid Override Enable + 2 + 2 + read-write + + + value1 + Override is disabled and vbus valid signal from the PHY is used internally by the core. + #0 + + + value2 + Internally vbus valid received from the PHY is overridden with GOTGCTL.VbvalidOvVal. + #1 + + + + + VbvalidOvVal + VBUS Valid Override Value + 3 + 3 + read-write + + + value1 + vbusvalid value is 0# when GOTGCTL.VbvalidOvEn = 1 + #0 + + + value2 + vbusvalid value is 1# when GOTGCTL.VbvalidOvEn = 1 + #1 + + + + + AvalidOvEn + A-Peripheral Session Valid Override Enable + 4 + 4 + read-write + + + value1 + Override is disabled and Avalid signal from the PHY is used internally by the core. + #0 + + + value2 + Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal. + #1 + + + + + AvalidOvVal + A-Peripheral Session Valid Override Value + 5 + 5 + read-write + + + value1 + Avalid value is 0# when GOTGCTL.AvalidOvEn = 1 + #0 + + + value2 + Avalid value is 1# when GOTGCTL.AvalidOvEn = 1 + #1 + + + + + BvalidOvEn + B-Peripheral Session Valid Override Enable + 6 + 6 + read-write + + + value1 + Override is disabled and Bvalid signal from the PHY is used internally by the core. + #0 + + + value2 + Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal. + #1 + + + + + BvalidOvVal + B-Peripheral Session Valid Override Value + 7 + 7 + read-write + + + value1 + Bvalid value is 0# when GOTGCTL.BvalidOvEn = 1 + #0 + + + value2 + Bvalid value is 1# when GOTGCTL.BvalidOvEn = 1 + #1 + + + + + HstNegScs + Host Negotiation Success + 8 + 8 + read-only + + + value1 + Host negotiation failure + #0 + + + value2 + Host negotiation success + #1 + + + + + HNPReq + HNP Request + 9 + 9 + read-write + + + value1 + No HNP request + #0 + + + value2 + HNP request + #1 + + + + + HstSetHNPEn + Host Set HNP Enable + 10 + 10 + read-write + + + value1 + Host Set HNP is not enabled + #0 + + + value2 + Host Set HNP is enabled + #1 + + + + + DevHNPEn + Device HNP Enabled + 11 + 11 + read-write + + + value1 + HNP is not enabled in the application + #0 + + + value2 + HNP is enabled in the application + #1 + + + + + ConlDSts + Connector ID Status + 16 + 16 + read-only + + + value1 + The USB core is in A-Device mode + #0 + + + value2 + The USB core is in B-Device mode + #1 + + + + + DbncTime + Long/Short Debounce Time + 17 + 17 + read-only + + + value1 + Long debounce time, used for physical connections (100 ms + 2.5 us) + #0 + + + value2 + Short debounce time, used for soft connections (2.5 us) + #1 + + + + + ASesVId + A-Session Valid + 18 + 18 + read-only + + + value1 + A-session is not valid + #0 + + + value2 + A-session is valid + #1 + + + + + BSesVld + B-Session Valid + 19 + 19 + read-only + + + value1 + B-session is not valid. + #0 + + + value2 + B-session is valid. + #1 + + + + + OTGVer + OTG Version + 20 + 20 + read-write + + + value1 + OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP. + #0 + + + value2 + OTG Version 2.0. In this version the core supports only Data line pulsing for SRP. + #1 + + + + + + + GOTGINT + OTG Interrupt Register + 0x004 + 32 + 0x00000000 + 0xFFFFFFFF + + + SesEndDet + Session End Detected + 2 + 2 + read-write + + + SesReqSucStsChng + Session Request Success Status Change + 8 + 8 + read-write + + + HstNegSucStsChng + Host Negotiation Success Status Change + 9 + 9 + read-write + + + HstNegDet + Host Negotiation Detected + 17 + 17 + read-write + + + ADevTOUTChg + A-Device Timeout Change + 18 + 18 + read-write + + + DbnceDone + Debounce Done + 19 + 19 + read-write + + + + + GAHBCFG + AHB Configuration Register + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + GlblIntrMsk + Global Interrupt Mask + 0 + 0 + read-write + + + value1 + Mask the interrupt assertion to the application. + #0 + + + value2 + Unmask the interrupt assertion to the application. + #1 + + + + + HBstLen + Burst Length/Type + 1 + 4 + read-write + + + value1 + Single + #0000 + + + value2 + INCR + #0001 + + + value3 + INCR4 + #0011 + + + value4 + INCR8 + #0101 + + + value5 + INCR16 + #0111 + + + + + DMAEn + DMA Enable + 5 + 5 + read-write + + + value1 + Core operates in Slave mode + #0 + + + value2 + Core operates in a DMA mode + #1 + + + + + NPTxFEmpLvl + Non-Periodic TxFIFO Empty Level + 7 + 7 + read-write + + + value1 + DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty + #0 + + + value2 + DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty + #1 + + + + + PTxFEmpLvl + Periodic TxFIFO Empty Level + 8 + 8 + read-write + + + value1 + GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty + #0 + + + value2 + GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty + #1 + + + + + AHBSingle + AHB Single Support + 23 + 23 + read-write + + + value1 + The remaining data in a transfer is sent using INCR burst size. This is the default mode. + #0 + + + value2 + The remaining data in a transfer is sent using single burst size. + #1 + + + + + + + GUSBCFG + USB Configuration Register + 0x00C + 32 + 0x00001440 + 0xFFFFFFFF + + + TOutCal + FS Timeout Calibration + 0 + 2 + read-write + + + PHYSel + USB 1.1 Full-Speed Serial Transceiver Select + 6 + 6 + read-only + + + value2 + USB 1.1 full-speed serial transceiver + #1 + + + + + SRPCap + SRP-Capable + 8 + 8 + read-write + + + value1 + SRP capability is not enabled. + #0 + + + value2 + SRP capability is enabled. + #1 + + + + + HNPCap + HNP-Capable + 9 + 9 + read-write + + + value1 + HNP capability is not enabled. + #0 + + + value2 + HNP capability is enabled. + #1 + + + + + USBTrdTim + USB Turnaround Time + 10 + 13 + read-write + + + OtgI2CSel + UTMIFS Interface Select + 16 + 16 + read-write + + + value1 + UTMI USB 1.1 Full-Speed interface for OTG signals + #0 + + + + + TxEndDelay + Tx End Delay + 28 + 28 + read-write + + + value1 + Normal mode + #0 + + + value2 + Introduce Tx end delay timers + #1 + + + + + ForceHstMode + Force Host Mode + 29 + 29 + read-write + + + value1 + Normal Mode + #0 + + + value2 + Force Host Mode + #1 + + + + + ForceDevMode + Force Device Mode + 30 + 30 + read-write + + + value1 + Normal Mode + #0 + + + value2 + Force Device Mode + #1 + + + + + CTP + Corrupt Tx packet + 31 + 31 + read-write + + + + + GRSTCTL + Reset Register + 0x010 + 32 + 0x10000000 + 0xFFFFFFFF + + + CSftRst + Core Soft Reset + 0 + 0 + read-write + + + FrmCntrRst + Host Frame Counter Reset + 2 + 2 + read-write + + + RxFFlsh + RxFIFO Flush + 4 + 4 + read-write + + + TxFFlsh + TxFIFO Flush + 5 + 5 + read-write + + + TxFNum + TxFIFO Number + 6 + 10 + read-write + + + value1 + Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode + 0x00 + + + value2 + Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode + 0x01 + + + value3 + Tx FIFO 2 flush in device mode + 0x02 + + + value4 + Tx FIFO 15 flush in device mode + 0x0F + + + value5 + Flush all the transmit FIFOs in device or host mode. + 0x10 + + + + + DMAReq + DMA Request Signal + 30 + 30 + read-only + + + AHBIdle + AHB Master Idle + 31 + 31 + read-only + + + + + GINTSTS_HOSTMODE + Interrupt Register [HOSTMODE] + 0x014 + 32 + 0x14000020 + 0xFFFFFFFF + + + CurMod + Current Mode of Operation + 0 + 0 + read-only + + + value1 + Device mode + #0 + + + value2 + Host mode + #1 + + + + + ModeMis + Mode Mismatch Interrupt + 1 + 1 + read-write + + + OTGInt + OTG Interrupt + 2 + 2 + read-only + + + Sof + Start of Frame + 3 + 3 + read-write + + + RxFLvl + RxFIFO Non-Empty + 4 + 4 + read-only + + + incomplP + Incomplete Periodic Transfer + 21 + 21 + read-write + + + PrtInt + Host Port Interrupt + 24 + 24 + read-only + + + HChInt + Host Channels Interrupt + 25 + 25 + read-only + + + PTxFEmp + Periodic TxFIFO Empty + 26 + 26 + read-only + + + ConIDStsChng + Connector ID Status Change + 28 + 28 + read-write + + + DisconnInt + Disconnect Detected Interrupt + 29 + 29 + read-write + + + SessReqInt + Session Request/New Session Detected Interrupt + 30 + 30 + read-write + + + WkUpInt + Resume/Remote Wakeup Detected Interrupt + 31 + 31 + read-write + + + + + GINTSTS_DEVICEMODE + Interrupt Register [DEVICEMODE] + GINTSTS_HOSTMODE + 0x014 + 32 + 0x14000020 + 0xFFFFFFFF + + + CurMod + Current Mode of Operation + 0 + 0 + read-only + + + value1 + Device mode + #0 + + + value2 + Host mode + #1 + + + + + ModeMis + Mode Mismatch Interrupt + 1 + 1 + read-write + + + OTGInt + OTG Interrupt + 2 + 2 + read-only + + + Sof + Start of Frame + 3 + 3 + read-write + + + RxFLvl + RxFIFO Non-Empty + 4 + 4 + read-only + + + GINNakEff + Global IN Non-Periodic NAK Effective + 6 + 6 + read-only + + + GOUTNakEff + Global OUT NAK Effective + 7 + 7 + read-only + + + ErlySusp + Early Suspend + 10 + 10 + read-write + + + USBSusp + USB Suspend + 11 + 11 + read-write + + + USBRst + USB Reset + 12 + 12 + read-write + + + EnumDone + Enumeration Done + 13 + 13 + read-write + + + ISOOutDrop + Isochronous OUT Packet Dropped Interrupt + 14 + 14 + read-write + + + EOPF + End of Periodic Frame Interrupt + 15 + 15 + read-write + + + IEPInt + IN Endpoints Interrupt + 18 + 18 + read-only + + + OEPInt + OUT Endpoints Interrupt + 19 + 19 + read-only + + + incompISOIN + Incomplete Isochronous IN Transfer + 20 + 20 + read-write + + + incomplSOOUT + Incomplete Isochronous OUT Transfer + 21 + 21 + read-write + + + ConIDStsChng + Connector ID Status Change + 28 + 28 + read-write + + + SessReqInt + Session Request/New Session Detected Interrupt + 30 + 30 + read-write + + + WkUpInt + Resume/Remote Wakeup Detected Interrupt + 31 + 31 + read-write + + + + + GINTMSK_HOSTMODE + Interrupt Mask Register [HOSTMODE] + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ModeMisMsk + Mode Mismatch Interrupt Mask + 1 + 1 + read-write + + + OTGIntMsk + OTG Interrupt Mask + 2 + 2 + read-write + + + SofMsk + Start of Frame Mask + 3 + 3 + read-write + + + RxFLvlMsk + Receive FIFO Non-Empty Mask + 4 + 4 + read-write + + + incomplPMsk + Incomplete Periodic Transfer Mask + 21 + 21 + read-write + + + PrtIntMsk + Host Port Interrupt Mask + 24 + 24 + read-write + + + HChIntMsk + Host Channels Interrupt Mask + 25 + 25 + read-write + + + PTxFEmpMsk + Periodic TxFIFO Empty Mask + 26 + 26 + read-write + + + ConIDStsChngMsk + Connector ID Status Change Mask + 28 + 28 + read-write + + + DisconnIntMsk + Disconnect Detected Interrupt Mask + 29 + 29 + read-write + + + SessReqIntMsk + Session Request/New Session Detected Interrupt Mask + 30 + 30 + read-write + + + WkUpIntMsk + Resume/Remote Wakeup Detected Interrupt Mask + 31 + 31 + read-write + + + + + GINTMSK_DEVICEMODE + Interrupt Mask Register [DEVICEMODE] + GINTMSK_HOSTMODE + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ModeMisMsk + Mode Mismatch Interrupt Mask + 1 + 1 + read-write + + + OTGIntMsk + OTG Interrupt Mask + 2 + 2 + read-write + + + SofMsk + Start of Frame Mask + 3 + 3 + read-write + + + RxFLvlMsk + Receive FIFO Non-Empty Mask + 4 + 4 + read-write + + + GINNakEffMsk + Global Non-periodic IN NAK Effective Mask + 6 + 6 + read-write + + + GOUTNakEffMsk + Global OUT NAK Effective Mask + 7 + 7 + read-write + + + ErlySuspMsk + Early Suspend Mask + 10 + 10 + read-write + + + USBSuspMsk + USB Suspend Mask + 11 + 11 + read-write + + + USBRstMsk + USB Reset Mask + 12 + 12 + read-write + + + EnumDoneMsk + Enumeration Done Mask + 13 + 13 + read-write + + + ISOOutDropMsk + Isochronous OUT Packet Dropped Interrupt Mask + 14 + 14 + read-write + + + EOPFMsk + End of Periodic Frame Interrupt Mask + 15 + 15 + read-write + + + IEPIntMsk + IN Endpoints Interrupt Mask + 18 + 18 + read-write + + + OEPIntMsk + OUT Endpoints Interrupt Mask + 19 + 19 + read-write + + + incompISOINMsk + Incomplete Isochronous IN Transfer Mask + 20 + 20 + read-write + + + incomplSOOUTMsk + Incomplete Isochronous OUT Transfer Mask + 21 + 21 + read-write + + + ConIDStsChngMsk + Connector ID Status Change Mask + 28 + 28 + read-write + + + DisconnIntMsk + Disconnect Detected Interrupt Mask + 29 + 29 + read-write + + + SessReqIntMsk + Session Request/New Session Detected Interrupt Mask + 30 + 30 + read-write + + + WkUpIntMsk + Resume/Remote Wakeup Detected Interrupt Mask + 31 + 31 + read-write + + + + + GRXSTSR_HOSTMODE + Receive Status Debug Read Register [HOSTMODE] + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + ChNum + Channel Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + IN data packet received + #0010 + + + value2 + IN transfer completed (triggers an interrupt) + #0011 + + + value3 + Data toggle error (triggers an interrupt) + #0101 + + + value4 + Channel halted (triggers an interrupt) + #0111 + + + + + + + GRXSTSR_DEVICEMODE + Receive Status Debug Read Register [DEVICEMODE] + GRXSTSR_HOSTMODE + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + EPNum + Endpoint Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + Global OUT NAK (triggers an interrupt) + #0001 + + + value2 + OUT data packet received + #0010 + + + value3 + OUT transfer completed (triggers an interrupt) + #0011 + + + value4 + SETUP transaction completed (triggers an interrupt) + #0100 + + + value5 + SETUP data packet received + #0110 + + + + + FN + Frame Number + 21 + 24 + read-only + + + + + GRXSTSP_DEVICEMODE + Receive Status Read and Pop Register [DEVICEMODE] + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + EPNum + Endpoint Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + Global OUT NAK (triggers an interrupt) + #0001 + + + value2 + OUT data packet received + #0010 + + + value3 + OUT transfer completed (triggers an interrupt) + #0011 + + + value4 + SETUP transaction completed (triggers an interrupt) + #0100 + + + value5 + SETUP data packet received + #0110 + + + + + FN + Frame Number + 21 + 24 + read-only + + + + + GRXSTSP_HOSTMODE + Receive Status Read and Pop Register [HOSTMODE] + GRXSTSP_DEVICEMODE + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + ChNum + Channel Number + 0 + 3 + read-only + + + BCnt + Byte Count + 4 + 14 + read-only + + + DPID + Data PID + 15 + 16 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA1 + #10 + + + value3 + DATA2 + #01 + + + value4 + MDATA + #11 + + + + + PktSts + Packet Status + 17 + 20 + read-only + + + value1 + IN data packet received + #0010 + + + value2 + IN transfer completed (triggers an interrupt) + #0011 + + + value3 + Data toggle error (triggers an interrupt) + #0101 + + + value4 + Channel halted (triggers an interrupt) + #0111 + + + + + + + GRXFSIZ + Receive FIFO Size Register + 0x024 + 32 + 0x0000011A + 0xFFFFFFFF + + + RxFDep + RxFIFO Depth + 0 + 15 + read-write + + + + + GNPTXFSIZ_HOSTMODE + Non-Periodic Transmit FIFO Size Register [HOSTMODE] + 0x028 + 32 + 0x0010011A + 0xFFFFFFFF + + + NPTxFStAddr + Non-periodic Transmit RAM Start Address + 0 + 15 + read-write + + + NPTxFDep + Non-periodic TxFIFO Depth + 16 + 31 + read-write + + + + + GNPTXFSIZ_DEVICEMODE + Non-Periodic Transmit FIFO Size Register [DEVICEMODE] + GNPTXFSIZ_HOSTMODE + 0x028 + 32 + 0x00100000 + 0xFFFFFFFF + + + INEPTxF0StAddr + IN Endpoint FIFO0 Transmit RAM Start Address + 0 + 15 + read-write + + + INEPTxF0Dep + IN Endpoint TxFIFO 0 Depth + 16 + 31 + read-write + + + + + GNPTXSTS + Non-Periodic Transmit FIFO/Queue Status Register + 0x02C + 32 + 0x00080010 + 0xFFFFFFFF + + + NPTxFSpcAvail + Non-periodic TxFIFO Space Avail + 0 + 15 + read-only + + + value1 + Non-periodic TxFIFO is full + 0x0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + NPTxQSpcAvail + Non-periodic Transmit Request Queue Space Available + 16 + 23 + read-only + + + value1 + Non-periodic Transmit Request Queue is full + 0x0 + + + value2 + 1 location available + 0x1 + + + value3 + 2 locations available + 0x2 + + + + + NPTxQTop + Top of the Non-periodic Transmit Request Queue + 24 + 30 + read-only + + + value1 + IN/OUT token + #00 + + + value2 + Zero-length transmit packet (device IN/host OUT) + #01 + + + value4 + Channel halt command + #11 + + + + + + + GUID + USB Module Identification Register + 0x03C + 32 + 0x00AEC000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-write + + + MOD_TYPE + Module Type + 8 + 15 + read-write + + + MOD_NUMBER + Module Number + 16 + 31 + read-write + + + + + GDFIFOCFG + Global DFIFO Software Config Register + 0x05C + 32 + 0x027A02B2 + 0xFFFFFFFF + + + GDFIFOCfg + GDFIFOCfg + 0 + 15 + read-write + + + EPInfoBaseAddr + EPInfoBaseAddr + 16 + 31 + read-write + + + + + HPTXFSIZ + Host Periodic Transmit FIFO Size Register + 0x100 + 32 + 0x0100012A + 0xFFFFFFFF + + + PTxFStAddr + Host Periodic TxFIFO Start Address + 0 + 15 + read-write + + + PTxFSize + Host Periodic TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF1 + Device IN Endpoint Transmit FIFO Size Register + 0x104 + 32 + 0x0100012A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF2 + Device IN Endpoint Transmit FIFO Size Register + 0x108 + 32 + 0x0100022A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF3 + Device IN Endpoint Transmit FIFO Size Register + 0x10C + 32 + 0x0100032A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF4 + Device IN Endpoint Transmit FIFO Size Register + 0x110 + 32 + 0x0100042A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF5 + Device IN Endpoint Transmit FIFO Size Register + 0x114 + 32 + 0x0100052A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + DIEPTXF6 + Device IN Endpoint Transmit FIFO Size Register + 0x118 + 32 + 0x0100062A + 0xFFFFFFFF + + + INEPnTxFStAddr + IN Endpoint FIFOn Transmit RAM Start Address + 0 + 15 + read-write + + + INEPnTxFDep + IN Endpoint TxFIFO Depth + 16 + 31 + read-write + + + + + HCFG + Host Configuration Register + 0x400 + 32 + 0x00000200 + 0xFFFFFFFF + + + FSLSPclkSel + FS PHY Clock Select + 0 + 1 + read-write + + + value1 + PHY clock is running at 48 MHz + #01 + + + + + FSLSSupp + FS-Only Support + 2 + 2 + read-write + + + value1 + FS-only, connected device can supports also only FS. + #0 + + + value2 + FS-only, even if the connected device can support HS + #1 + + + + + DescDMA + Enable Scatter/gather DMA in Host mode + 23 + 23 + read-write + + + FrListEn + Frame List Entries + 24 + 25 + read-write + + + value1 + 8 Entries + #00 + + + value2 + 16 Entries + #01 + + + value3 + 32 Entries + #10 + + + value4 + 64 Entries + #11 + + + + + PerSchedEna + Enable Periodic Scheduling + 26 + 26 + read-write + + + + + HFIR + Host Frame Interval Register + 0x404 + 32 + 0x0000EA60 + 0xFFFFFFFF + + + FrInt + Frame Interval + 0 + 15 + read-write + + + HFIRRldCtrl + Reload Control + 16 + 16 + read-write + + + value1 + HFIR cannot be reloaded dynamically + #0 + + + value2 + HFIR can be dynamically reloaded during runtime + #1 + + + + + + + HFNUM + Host Frame Number/Frame Time Remaining Register + 0x408 + 32 + 0x00003FFF + 0xFFFFFFFF + + + FrNum + Frame Number + 0 + 15 + read-write + + + FrRem + Frame Time Remaining + 16 + 31 + read-only + + + + + HPTXSTS + Host Periodic Transmit FIFO/ Queue Status Register + 0x410 + 32 + 0x00080100 + 0xFFFFFFFF + + + PTxFSpcAvail + Periodic Transmit Data FIFO Space Available + 0 + 15 + read-write + + + value1 + Periodic TxFIFO is full + #0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + PTxQSpcAvail + Periodic Transmit Request Queue Space Available + 16 + 23 + read-only + + + value1 + Periodic Transmit Request Queue is full + 0x0 + + + value2 + 1 location available + 0x1 + + + value3 + 2 locations available + 0x2 + + + + + PTxQTop + Top of the Periodic Transmit Request Queue + 24 + 31 + read-only + + + + + HAINT + Host All Channels Interrupt Register + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + HAINT + Channel Interrupts + 0 + 13 + read-only + + + + + HAINTMSK + Host All Channels Interrupt Mask Register + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + HAINTMsk + Channel Interrupt Mask + 0 + 13 + read-write + + + + + HFLBADDR + Host Frame List Base Address Register + 0x41C + 32 + 0x00000000 + 0xFFFFFFFF + + + Starting_Address + Starting Address + 0 + 31 + read-write + + + + + HPRT + Host Port Control and Status Register + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + PrtConnSts + Port Connect Status + 0 + 0 + read-only + + + value1 + No device is attached to the port. + #0 + + + value2 + A device is attached to the port. + #1 + + + + + PrtConnDet + Port Connect Detected + 1 + 1 + read-write + + + PrtEna + Port Enable + 2 + 2 + read-write + + + value1 + Port disabled + #0 + + + value2 + Port enabled + #1 + + + + + PrtEnChng + Port Enable/Disable Change + 3 + 3 + read-write + + + PrtOvrCurrAct + Port Overcurrent Active + 4 + 4 + read-only + + + value1 + No overcurrent condition + #0 + + + value2 + Overcurrent condition + #1 + + + + + PrtOvrCurrChng + Port Overcurrent Change + 5 + 5 + read-write + + + PrtRes + Port Resume + 6 + 6 + read-write + + + value1 + No resume driven + #0 + + + value2 + Resume driven + #1 + + + + + PrtSusp + Port Suspend + 7 + 7 + read-write + + + value1 + Port not in Suspend mode + #0 + + + value2 + Port in Suspend mode + #1 + + + + + PrtRst + Port Reset + 8 + 8 + read-write + + + value1 + Port not in reset + #0 + + + value2 + Port in reset + #1 + + + + + PrtLnSts + Port Line Status + 10 + 11 + read-only + + + PrtPwr + Port Power + 12 + 12 + read-write + + + value1 + Power off + #0 + + + value2 + Power on + #1 + + + + + PrtSpd + Port Speed + 17 + 18 + read-only + + + value1 + Full speed + #01 + + + + + + + DCFG + Device Configuration Register + 0x800 + 32 + 0x08200000 + 0xFFFFFFFF + + + DevSpd + Device Speed + 0 + 1 + read-write + + + value4 + Full speed (USB 1.1 transceiver clock is 48 MHz) + #11 + + + + + NZStsOUTHShk + Non-Zero-Length Status OUT Handshake + 2 + 2 + read-write + + + value1 + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. + #1 + + + value2 + Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register. + #0 + + + + + DevAddr + Device Address + 4 + 10 + read-write + + + PerFrInt + Periodic Frame Interval + 11 + 12 + read-write + + + value1 + 80% of the frame interval + #00 + + + value2 + 85% + #01 + + + value3 + 90% + #10 + + + value4 + 95% + #11 + + + + + DescDMA + Enable Scatter/Gather DMA in Device mode. + 23 + 23 + read-write + + + PerSchIntvl + Periodic Scheduling Interval + 24 + 25 + read-write + + + value1 + 25% of frame. + #00 + + + value2 + 50% of frame. + #01 + + + value3 + 75% of frame. + #10 + + + + + + + DCTL + Device Control Register + 0x804 + 32 + 0x00000002 + 0xFFFFFFFF + + + RmtWkUpSig + Remote Wakeup Signaling + 0 + 0 + read-write + + + SftDiscon + Soft Disconnect + 1 + 1 + read-write + + + value1 + Normal operation. When this bit is cleared after a soft disconnect, the core drives a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. + #0 + + + value2 + The core drives a device disconnect event to the USB host. + #1 + + + + + GNPINNakSts + Global Non-periodic IN NAK Status + 2 + 2 + read-only + + + value1 + A handshake is sent out based on the data availability in the transmit FIFO. + #0 + + + value2 + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + #1 + + + + + GOUTNakSts + Global OUT NAK Status + 3 + 3 + read-only + + + value1 + A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + #0 + + + value2 + No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + #1 + + + + + SGNPInNak + Set Global Non-periodic IN NAK + 7 + 7 + write-only + + + CGNPInNak + Clear Global Non-periodic IN NAK + 8 + 8 + write-only + + + SGOUTNak + Set Global OUT NAK + 9 + 9 + write-only + + + CGOUTNak + Clear Global OUT NAK + 10 + 10 + write-only + + + GMC + Global Multi Count + 13 + 14 + read-write + + + value1 + Invalid. + #00 + + + value2 + 1 packet. + #01 + + + value3 + 2 packets. + #10 + + + value4 + 3 packets. + #11 + + + + + IgnrFrmNum + Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA + 15 + 15 + read-write + + + value1 + Scatter/Gather enabled: The core transmits the packets only in the frame number in which they are intended to be transmitted. Scatter/Gather disabled: Periodic transfer interrupt feature is disabled; the application must program transfers for periodic endpoints every frame + #0 + + + value2 + Scatter/Gather enabled: The core ignores the frame number, sending packets immediately as the packets are ready. Scatter/Gather disabled: Periodic transfer interrupt feature is enabled; the application can program transfers for multiple frames for periodic endpoints. + #1 + + + + + NakOnBble + Set NAK automatically on babble + 16 + 16 + read-write + + + EnContOnBNA + Enable continue on BNA + 17 + 17 + read-write + + + value1 + After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor. + #0 + + + value2 + After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt. + #1 + + + + + + + DSTS + Device Status Register + 0x808 + 32 + 0x00000002 + 0xFFFFFFFF + + + SuspSts + Suspend Status + 0 + 0 + read-only + + + EnumSpd + Enumerated Speed + 1 + 2 + read-only + + + value4 + Full speed (PHY clock is running at 48 MHz) + #11 + + + + + ErrticErr + Erratic Error + 3 + 3 + read-only + + + SOFFN + Frame Number of the Received SOF + 8 + 21 + read-only + + + + + DIEPMSK + Device IN Endpoint Common Interrupt Mask Register + 0x810 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferComplMsk + Transfer Completed Interrupt Mask + 0 + 0 + read-write + + + EPDisbldMsk + Endpoint Disabled Interrupt Mask + 1 + 1 + read-write + + + AHBErrMsk + AHB Error Mask + 2 + 2 + read-write + + + TimeOUTMsk + Timeout Condition Mask + 3 + 3 + read-write + + + INTknTXFEmpMsk + IN Token Received When TxFIFO Empty Mask + 4 + 4 + read-write + + + INEPNakEffMsk + IN Endpoint NAK Effective Mask + 6 + 6 + read-write + + + TxfifoUndrnMsk + Fifo Underrun Mask + 8 + 8 + read-write + + + BNAInIntrMsk + BNA Interrupt Mask + 9 + 9 + read-write + + + NAKMsk + NAK interrupt Mask + 13 + 13 + read-write + + + + + DOEPMSK + Device OUT Endpoint Common Interrupt Mask Register + 0x814 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferComplMsk + Transfer Completed Interrupt Mask + 0 + 0 + read-write + + + EPDisbldMsk + Endpoint Disabled Interrupt Mask + 1 + 1 + read-write + + + AHBErrMsk + AHB Error + 2 + 2 + read-write + + + SetUPMsk + SETUP Phase Done Mask + 3 + 3 + read-write + + + OUTTknEPdisMsk + OUT Token Received when Endpoint Disabled Mask + 4 + 4 + read-write + + + Back2BackSETup + Back-to-Back SETUP Packets Received Mask + 6 + 6 + read-write + + + OutPktErrMsk + OUT Packet Error Mask + 8 + 8 + read-write + + + BnaOutIntrMsk + BNA interrupt Mask + 9 + 9 + read-write + + + BbleErrMsk + Babble Interrupt Mask + 12 + 12 + read-write + + + NAKMsk + NAK Interrupt Mask + 13 + 13 + read-write + + + NYETMsk + NYET Interrupt Mask + 14 + 14 + read-write + + + + + DAINT + Device All Endpoints Interrupt Register + 0x818 + 32 + 0x00000000 + 0xFFFFFFFF + + + InEpInt + IN Endpoint Interrupt Bits + 0 + 15 + read-only + + + OutEPInt + OUT Endpoint Interrupt Bits + 16 + 31 + read-only + + + + + DAINTMSK + Device All Endpoints Interrupt Mask Register + 0x81C + 32 + 0x00000000 + 0xFFFFFFFF + + + InEpMsk + IN EP Interrupt Mask Bits + 0 + 15 + read-write + + + OutEpMsk + OUT EP Interrupt Mask Bits + 16 + 31 + read-write + + + + + DVBUSDIS + Device VBUS Discharge Time Register + 0x828 + 32 + 0x000017D7 + 0xFFFFFFFF + + + DVBUSDis + Device Vbus Discharge Time + 0 + 15 + read-write + + + + + DVBUSPULSE + Device VBUS Pulsing Time Register + 0x82C + 32 + 0x000005B8 + 0xFFFFFFFF + + + DVBUSPulse + Device Vbus Pulsing Time + 0 + 11 + read-write + + + + + DIEPEMPMSK + Device IN Endpoint FIFO Empty Interrupt Mask Register + 0x834 + 32 + 0x00000000 + 0xFFFFFFFF + + + InEpTxfEmpMsk + IN EP Tx FIFO Empty Interrupt Mask Bits + 0 + 15 + read-write + + + + + PCGCCTL + Power and Clock Gating Control Register + 0xE00 + 32 + 0x00000100 + 0xFFFFFFFF + + + StopPclk + Stop Pclk + 0 + 0 + read-write + + + GateHclk + Gate Hclk + 1 + 1 + read-write + + + + + + + USB0_EP0 + Universal Serial Bus + USB + 0x50040900 + + 0x0 + 0x0400 + registers + + + + DIEPCTL0 + Device Control IN Endpoint Control Register + 0x000 + 32 + 0x00008000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 1 + read-write + + + value1 + 64 bytes + #00 + + + value2 + 32 bytes + #01 + + + value3 + 16 bytes + #10 + + + value4 + 8 bytes + #11 + + + + + USBActEP + USB Active Endpoint + 15 + 15 + read-only + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-only + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DIEPINT0 + Device Endpoint Interrupt Register + 0x008 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + TimeOUT + Timeout Condition + 3 + 3 + read-write + + + INTknTXFEmp + IN Token Received When TxFIFO is Empty + 4 + 4 + read-write + + + INEPNakEff + IN Endpoint NAK Effective + 6 + 6 + read-write + + + TxFEmp + Transmit FIFO Empty + 7 + 7 + read-only + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + + + DIEPTSIZ0 + Device IN Endpoint Transfer Size Register + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 6 + read-write + + + PktCnt + Packet Count + 19 + 20 + read-write + + + + + DIEPDMA0 + Device Endpoint DMA Address Register + 0x014 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DTXFSTS0 + Device IN Endpoint Transmit FIFO Status Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + INEPTxFSpcAvail + IN Endpoint TxFIFO Space Avail + 0 + 15 + read-only + + + value1 + Endpoint TxFIFO is full + 0x0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + + + DIEPDMAB0 + Device Endpoint DMA Buffer Address Register + 0x01C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + DOEPCTL0 + Device Control OUT Endpoint Control Register + 0x200 + 32 + 0x00008000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 1 + read-only + + + value1 + 64 bytes + #00 + + + value2 + 32 bytes + #01 + + + value3 + 16 bytes + #10 + + + value4 + 8 bytes + #11 + + + + + USBActEP + USB Active Endpoint + 15 + 15 + read-only + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-only + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-only + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DOEPINT0 + Device Endpoint Interrupt Register + 0x208 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + SetUp + SETUP Phase Done + 3 + 3 + read-write + + + OUTTknEPdis + OUT Token Received When Endpoint Disabled + 4 + 4 + read-write + + + StsPhseRcvd + Status Phase Received For Control Write + 5 + 5 + read-write + + + Back2BackSETup + Back-to-Back SETUP Packets Received + 6 + 6 + read-write + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + PktDrpSts + Packet Dropped Status + 11 + 11 + read-write + + + BbleErrIntrpt + BbleErr (Babble Error) interrupt + 12 + 12 + read-write + + + NAKIntrpt + NAK interrupt + 13 + 13 + read-write + + + NYETIntrpt + NYET interrupt + 14 + 14 + read-write + + + + + DOEPTSIZ0 + Device OUT Endpoint Transfer Size Register + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 6 + read-write + + + PktCnt + Packet Count + 19 + 20 + read-write + + + SUPCnt + SETUP Packet Count + 29 + 30 + read-write + + + value1 + 1 packet + #01 + + + value2 + 2 packets + #10 + + + value3 + 3 packets + #11 + + + + + + + DOEPDMA0 + Device Endpoint DMA Address Register + 0x214 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DOEPDMAB0 + Device Endpoint DMA Buffer Address Register + 0x21C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + + + USB0_EP1 + Universal Serial Bus + USB + USB_EP + 0x50040920 + + 0x0 + 0x0400 + registers + + + + DIEPCTL_ISOCONT + Device Endpoint Control Register [ISOCONT] + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + EO_FrNum + Even/Odd Frame + 16 + 16 + read-only + + + value1 + Even frame + #0 + + + value2 + Odd rame + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetEvenFr + In non-Scatter/Gather DMA mode: Set Even frame + 28 + 28 + write-only + + + SetOddFr + Set Odd frame + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DIEPCTL_INTBULK + Device Endpoint Control Register [INTBULK] + DIEPCTL_ISOCONT + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + DPID + Endpoint Data PID + 16 + 16 + read-only + + + value1 + DATA0 + #0 + + + value2 + DATA1 + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetD0PID + Set DATA0 PID + 28 + 28 + write-only + + + SetD1PID + 29 Set DATA1 PID + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DIEPINT + Device Endpoint Interrupt Register + 0x008 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + TimeOUT + Timeout Condition + 3 + 3 + read-write + + + INTknTXFEmp + IN Token Received When TxFIFO is Empty + 4 + 4 + read-write + + + INEPNakEff + IN Endpoint NAK Effective + 6 + 6 + read-write + + + TxFEmp + Transmit FIFO Empty + 7 + 7 + read-only + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + + + DIEPTSIZ + Device Endpoint Transfer Size Register + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + + + DIEPDMA + Device Endpoint DMA Address Register + 0x014 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DTXFSTS + Device IN Endpoint Transmit FIFO Status Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + INEPTxFSpcAvail + IN Endpoint TxFIFO Space Avail + 0 + 15 + read-only + + + value1 + Endpoint TxFIFO is full + 0x0 + + + value2 + 1 word available + 0x1 + + + value3 + 2 words available + 0x2 + + + + + + + DIEPDMAB + Device Endpoint DMA Buffer Address Register + 0x01C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + DOEPCTL_ISOCONT + Device Endpoint Control Register [ISOCONT] + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + EO_FrNum + Even/Odd Frame + 16 + 16 + read-only + + + value1 + Even frame + #0 + + + value2 + Odd rame + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetEvenFr + In non-Scatter/Gather DMA mode: Set Even frame + 28 + 28 + write-only + + + SetOddFr + Set Odd frame + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DOEPCTL_INTBULK + Device Endpoint Control Register [INTBULK] + DOEPCTL_ISOCONT + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + USBActEP + USB Active Endpoint + 15 + 15 + read-write + + + DPID + Endpoint Data PID + 16 + 16 + read-only + + + value1 + DATA0 + #0 + + + value2 + DATA1 + #1 + + + + + NAKSts + NAK Status + 17 + 17 + read-only + + + value1 + The core is transmitting non-NAK handshakes based on the FIFO status. + #0 + + + value2 + The core is transmitting NAK handshakes on this endpoint. + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + Snp + Snoop Mode + 20 + 20 + read-write + + + Stall + STALL Handshake + 21 + 21 + read-write + + + TxFNum + TxFIFO Number + 22 + 25 + read-write + + + CNAK + Clear NAK + 26 + 26 + write-only + + + SNAK + Set NAK + 27 + 27 + write-only + + + SetD0PID + Set DATA0 PID + 28 + 28 + write-only + + + SetD1PID + 29 Set DATA1 PID + 29 + 29 + write-only + + + EPDis + Endpoint Disable + 30 + 30 + read-write + + + EPEna + Endpoint Enable + 31 + 31 + read-write + + + + + DOEPINT + Device Endpoint Interrupt Register + 0x208 + 32 + 0x00000080 + 0xFFFFFFFF + + + XferCompl + Transfer Completed Interrupt + 0 + 0 + read-write + + + EPDisbld + Endpoint Disabled Interrupt + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + SetUp + SETUP Phase Done + 3 + 3 + read-write + + + OUTTknEPdis + OUT Token Received When Endpoint Disabled + 4 + 4 + read-write + + + StsPhseRcvd + Status Phase Received For Control Write + 5 + 5 + read-write + + + Back2BackSETup + Back-to-Back SETUP Packets Received + 6 + 6 + read-write + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 9 + 9 + read-write + + + PktDrpSts + Packet Dropped Status + 11 + 11 + read-write + + + BbleErrIntrpt + BbleErr (Babble Error) interrupt + 12 + 12 + read-write + + + NAKIntrpt + NAK interrupt + 13 + 13 + read-write + + + NYETIntrpt + NYET interrupt + 14 + 14 + read-write + + + + + DOEPTSIZ_ISO + Device Endpoint Transfer Size Register [ISO] + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + RxDPID + Received Data PID + 29 + 30 + read-only + + + value1 + DATA0 + #00 + + + value2 + DATA2 + #01 + + + value3 + DATA1 + #10 + + + value4 + MDATA + #11 + + + + + + + DOEPTSIZ_CONTROL + Device Endpoint Transfer Size Register [CONT] + DOEPTSIZ_ISO + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + SUPCnt + SETUP Packet Count: 0b00=1 packet, 0b00=2 packets, 0b00=3 packets, + 29 + 30 + read-write + + + + + DOEPDMA + Device Endpoint DMA Address Register + 0x214 + 32 + 0x00000000 + 0x00000000 + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + DOEPDMAB + Device Endpoint DMA Buffer Address Register + 0x21C + 32 + 0x00000000 + 0x00000000 + + + DMABufferAddr + DMA Buffer Address + 0 + 31 + read-only + + + + + + + USB0_EP2 + Universal Serial Bus + USB + 0x50040940 + + 0x0 + 0x0400 + registers + + + + USB0_EP3 + Universal Serial Bus + USB + 0x50040960 + + 0x0 + 0x0400 + registers + + + + USB0_EP4 + Universal Serial Bus + USB + 0x50040980 + + 0x0 + 0x0400 + registers + + + + USB0_EP5 + Universal Serial Bus + USB + 0x500409A0 + + 0x0 + 0x0400 + registers + + + + USB0_EP6 + Universal Serial Bus + USB + 0x500409C0 + + 0x0 + 0x0400 + registers + + + + USB0_CH0 + Universal Serial Bus + USB + USB_CH + 0x50040500 + + 0x0 + 0x20 + registers + + + + HCCHAR + Host Channel Characteristics Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + MPS + Maximum Packet Size + 0 + 10 + read-write + + + EPNum + Endpoint Number + 11 + 14 + read-write + + + EPDir + Endpoint Direction + 15 + 15 + read-write + + + value1 + OUT + #0 + + + value2 + IN + #1 + + + + + EPType + Endpoint Type + 18 + 19 + read-write + + + value1 + Control + #00 + + + value2 + Isochronous + #01 + + + value3 + Bulk + #10 + + + value4 + Interrupt + #11 + + + + + MC_EC + Multi Count / Error Count + 20 + 21 + read-write + + + value2 + 1 transaction + #01 + + + value3 + 2 transactions to be issued for this endpoint per frame + #10 + + + value4 + 3 transactions to be issued for this endpoint per frame + #11 + + + + + DevAddr + Device Address + 22 + 28 + read-write + + + OddFrm + Odd Frame + 29 + 29 + read-write + + + value1 + Even frame + #0 + + + value2 + Odd frame + #1 + + + + + ChDis + Channel Disable + 30 + 30 + read-write + + + ChEna + Channel Enable + 31 + 31 + read-write + + + value1 + Scatter/Gather mode enabled: Indicates that the descriptor structure is not yet ready. Scatter/Gather mode disabled: Channel disabled + #0 + + + value2 + Scatter/Gather mode enabled: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor. Scatter/Gather mode disabled: Channel enabled + #1 + + + + + + + HCINT + Host Channel Interrupt Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferCompl + Transfer Completed + 0 + 0 + read-write + + + ChHltd + Channel Halted + 1 + 1 + read-write + + + AHBErr + AHB Error + 2 + 2 + read-write + + + STALL + STALL Response Received Interrupt + 3 + 3 + read-write + + + NAK + NAK Response Received Interrupt + 4 + 4 + read-write + + + ACK + ACK Response Received/Transmitted Interrupt + 5 + 5 + read-write + + + NYET + NYET Response Received Interrupt + 6 + 6 + read-write + + + XactErr + Transaction Error + 7 + 7 + read-write + + + BblErr + Babble Error + 8 + 8 + read-write + + + FrmOvrun + Frame Overrun + 9 + 9 + read-write + + + DataTglErr + Data Toggle Error + 10 + 10 + read-write + + + BNAIntr + BNA (Buffer Not Available) Interrupt + 11 + 11 + read-write + + + XCS_XACT_ERR + Excessive Transaction Error + 12 + 12 + read-write + + + DESC_LST_ROLLIntr + Descriptor rollover interrupt + 13 + 13 + read-write + + + + + HCINTMSK + Host Channel Interrupt Mask Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + XferComplMsk + Transfer Completed Mask + 0 + 0 + read-write + + + ChHltdMsk + Channel Halted Mask + 1 + 1 + read-write + + + AHBErrMsk + AHB Error Mask + 2 + 2 + read-write + + + StallMsk + STALL Response Received Interrupt Mask + 3 + 3 + read-write + + + NakMsk + NAK Response Received Interrupt Mask + 4 + 4 + read-write + + + AckMsk + ACK Response Received/Transmitted Interrupt Mask + 5 + 5 + read-write + + + NyetMsk + NYET Response Received Interrupt Mask + 6 + 6 + read-write + + + XactErrMsk + Transaction Error Mask + 7 + 7 + read-write + + + BblErrMsk + Babble Error Mask + 8 + 8 + read-write + + + FrmOvrunMsk + Frame Overrun Mask + 9 + 9 + read-write + + + DataTglErrMsk + Data Toggle Error Mask + 10 + 10 + read-write + + + BNAIntrMsk + BNA (Buffer Not Available) Interrupt mask register + 11 + 11 + read-write + + + DESC_LST_ROLLIntrMsk + Descriptor rollover interrupt Mask register + 13 + 13 + read-write + + + + + HCTSIZ_BUFFERMODE + Host Channel Transfer Size Register [BUFFERMODE] + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XferSize + Transfer Size + 0 + 18 + read-write + + + PktCnt + Packet Count + 19 + 28 + read-write + + + Pid + PID + 29 + 30 + read-write + + + value1 + DATA0 + #00 + + + value2 + DATA2 + #01 + + + value3 + DATA1 + #10 + + + value4 + MDATA (non-control)/SETUP (control) + #11 + + + + + + + HCTSIZ_SCATGATHER + Host Channel Transfer Size Register [SCATGATHER] + HCTSIZ_BUFFERMODE + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCHED_INFO + Schedule information + 0 + 7 + read-write + + + NTD + Number of Transfer Descriptors: 0=1 descriptor, 63=64 descriptors, 1=2 descriptors, 3=4 descriptors, 7=8 descriptors, 15=16 descriptors, 31=32 descriptors, 63=64 descriptors, + 8 + 15 + read-write + + + Pid + PID + 29 + 30 + read-write + + + value1 + DATA0 + #00 + + + value2 + DATA2 + #01 + + + value3 + DATA1 + #10 + + + value4 + MDATA (non-control) + #11 + + + + + + + HCDMA_BUFFERMODE + Host Channel DMA Address Register [BUFFERMODE] + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + DMAAddr + DMA Address + 0 + 31 + read-write + + + + + HCDMA_SCATGATHER + Host Channel DMA Address Register [SCATGATHER] + HCDMA_BUFFERMODE + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CTD + Current Transfer Desc: + 3 + 8 + read-write + + + value1 + 1 descriptor + 0 + + + value2 + 64 descriptors + 63 + + + + + DMAAddr + DMA Address + 9 + 31 + read-write + + + + + HCDMAB + Host Channel DMA Buffer Address Register + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + Buffer_Address + Buffer Address + 0 + 31 + read-only + + + + + + + USB0_CH1 + Universal Serial Bus + USB + 0x50040520 + + 0x0 + 0x20 + registers + + + + USB0_CH2 + Universal Serial Bus + USB + 0x50040540 + + 0x0 + 0x20 + registers + + + + USB0_CH3 + Universal Serial Bus + USB + 0x50040560 + + 0x0 + 0x20 + registers + + + + USB0_CH4 + Universal Serial Bus + USB + 0x50040580 + + 0x0 + 0x20 + registers + + + + USB0_CH5 + Universal Serial Bus + USB + 0x500405A0 + + 0x0 + 0x20 + registers + + + + USB0_CH6 + Universal Serial Bus + USB + 0x500405C0 + + 0x0 + 0x20 + registers + + + + USB0_CH7 + Universal Serial Bus + USB + 0x500405E0 + + 0x0 + 0x20 + registers + + + + USB0_CH8 + Universal Serial Bus + USB + 0x50040600 + + 0x0 + 0x20 + registers + + + + USB0_CH9 + Universal Serial Bus + USB + 0x50040620 + + 0x0 + 0x20 + registers + + + + USB0_CH10 + Universal Serial Bus + USB + 0x50040640 + + 0x0 + 0x20 + registers + + + + USB0_CH11 + Universal Serial Bus + USB + 0x50040660 + + 0x0 + 0x20 + registers + + + + USB0_CH12 + Universal Serial Bus + USB + 0x50040680 + + 0x0 + 0x20 + registers + + + + USB0_CH13 + Universal Serial Bus + USB + 0x500406A0 + + 0x0 + 0x20 + registers + + + + USIC0 + Universal Serial Interface Controller 0 + USIC + USIC + 0x40030008 + + 0 + 4 + registers + + + USIC0_0 + Universal Serial Interface Channel (Module 0) + 84 + + + USIC0_1 + Universal Serial Interface Channel (Module 0) + 85 + + + USIC0_2 + Universal Serial Interface Channel (Module 0) + 86 + + + USIC0_3 + Universal Serial Interface Channel (Module 0) + 87 + + + USIC0_4 + Universal Serial Interface Channel (Module 0) + 88 + + + USIC0_5 + Universal Serial Interface Channel (Module 0) + 89 + + + + ID + Module Identification Register + 0 + 32 + 0x00AAC000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + + + USIC1 + Universal Serial Interface Controller 1 + USIC + 0x48020008 + + 0 + 4 + registers + + + USIC1_0 + Universal Serial Interface Channel (Module 1) + 90 + + + USIC1_1 + Universal Serial Interface Channel (Module 1) + 91 + + + USIC1_2 + Universal Serial Interface Channel (Module 1) + 92 + + + USIC1_3 + Universal Serial Interface Channel (Module 1) + 93 + + + USIC1_4 + Universal Serial Interface Channel (Module 1) + 94 + + + USIC1_5 + Universal Serial Interface Channel (Module 1) + 95 + + + + USIC2 + Universal Serial Interface Controller 2 + USIC + 0x48024008 + + 0 + 4 + registers + + + USIC2_0 + Universal Serial Interface Channel (Module 2) + 96 + + + USIC2_1 + Universal Serial Interface Channel (Module 2) + 97 + + + USIC2_2 + Universal Serial Interface Channel (Module 2) + 98 + + + USIC2_3 + Universal Serial Interface Channel (Module 2) + 99 + + + USIC2_4 + Universal Serial Interface Channel (Module 2) + 100 + + + USIC2_5 + Universal Serial Interface Channel (Module 2) + 101 + + + + USIC0_CH0 + Universal Serial Interface Controller 0 + USIC + USIC_CH + 0x40030000 + + 0x0 + 0x0200 + registers + + + + CCFG + Channel Configuration Register + 0x004 + 32 + 0x000000CF + 0xFFFFFFFF + + + SSC + SSC Protocol Available + 0 + 0 + read-only + + + value1 + The SSC protocol is not available. + #0 + + + value2 + The SSC protocol is available. + #1 + + + + + ASC + ASC Protocol Available + 1 + 1 + read-only + + + value1 + The ASC protocol is not available. + #0 + + + value2 + The ASC protocol is available. + #1 + + + + + IIC + IIC Protocol Available + 2 + 2 + read-only + + + value1 + The IIC protocol is not available. + #0 + + + value2 + The IIC protocol is available. + #1 + + + + + IIS + IIS Protocol Available + 3 + 3 + read-only + + + value1 + The IIS protocol is not available. + #0 + + + value2 + The IIS protocol is available. + #1 + + + + + RB + Receive FIFO Buffer Available + 6 + 6 + read-only + + + value1 + A receive FIFO buffer is not available. + #0 + + + value2 + A receive FIFO buffer is available. + #1 + + + + + TB + Transmit FIFO Buffer Available + 7 + 7 + read-only + + + value1 + A transmit FIFO buffer is not available. + #0 + + + value2 + A transmit FIFO buffer is available. + #1 + + + + + + + KSCFG + Kernel State Configuration Register + 0x00C + 32 + 0x00000000 + 0xFFFFFFFF + + + MODEN + Module Enable + 0 + 0 + read-write + + + value1 + The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). + #0 + + + value2 + The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other Service Request Processing registers. + #1 + + + + + BPMODEN + Bit Protection for MODEN + 1 + 1 + write-only + + + value1 + MODEN is not changed. + #0 + + + value2 + MODEN is updated with the written value. + #1 + + + + + NOMCFG + Normal Operation Mode Configuration + 4 + 5 + read-write + + + value1 + Run mode 0 is selected. + #00 + + + value2 + Run mode 1 is selected. + #01 + + + value3 + Stop mode 0 is selected. + #10 + + + value4 + Stop mode 1 is selected. + #11 + + + + + BPNOM + Bit Protection for NOMCFG + 7 + 7 + write-only + + + value1 + NOMCFG is not changed. + #0 + + + value2 + NOMCFG is updated with the written value. + #1 + + + + + SUMCFG + Suspend Mode Configuration + 8 + 9 + read-write + + + BPSUM + Bit Protection for SUMCFG + 11 + 11 + write-only + + + value1 + SUMCFG is not changed. + #0 + + + value2 + SUMCFG is updated with the written value. + #1 + + + + + + + FDR + Fractional Divider Register + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + STEP + Step Value + 0 + 9 + read-write + + + DM + Divider Mode + 14 + 15 + read-write + + + value1 + The divider is switched off, fFD = 0. + #00 + + + value2 + Normal divider mode selected. + #01 + + + value3 + Fractional divider mode selected. + #10 + + + value4 + The divider is switched off, fFD = 0. + #11 + + + + + RESULT + Result Value + 16 + 25 + read-only + + + + + BRG + Baud Rate Generator Register + 0x014 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLKSEL + Clock Selection + 0 + 1 + read-write + + + value1 + The fractional divider frequency fFD is selected. + #00 + + + value3 + The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. + #10 + + + value4 + Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. + #11 + + + + + TMEN + Timing Measurement Enable + 3 + 3 + read-write + + + value1 + Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored. + #0 + + + value2 + Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. + #1 + + + + + PPPEN + Enable 2:1 Divider for fPPP + 4 + 4 + read-write + + + value1 + The 2:1 divider for fPPP is disabled. fPPP = fPIN + #0 + + + value2 + The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. + #1 + + + + + CTQSEL + Input Selection for CTQ + 6 + 7 + read-write + + + value1 + fCTQIN = fPDIV + #00 + + + value2 + fCTQIN = fPPP + #01 + + + value3 + fCTQIN = fSCLK + #10 + + + value4 + fCTQIN = fMCLK + #11 + + + + + PCTQ + Pre-Divider for Time Quanta Counter + 8 + 9 + read-write + + + DCTQ + Denominator for Time Quanta Counter + 10 + 14 + read-write + + + PDIV + Divider Mode: Divider Factor to Generate fPDIV + 16 + 25 + read-write + + + SCLKOSEL + Shift Clock Output Select + 28 + 28 + read-write + + + value1 + SCLK from the baud rate generator is selected as the SCLKOUT input source. + #0 + + + value2 + The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. + #1 + + + + + MCLKCFG + Master Clock Configuration + 29 + 29 + read-write + + + value1 + The passive level is 0. + #0 + + + value2 + The passive level is 1. + #1 + + + + + SCLKCFG + Shift Clock Output Configuration + 30 + 31 + read-write + + + value1 + The passive level is 0 and the delay is disabled. + #00 + + + value2 + The passive level is 1 and the delay is disabled. + #01 + + + value3 + The passive level is 0 and the delay is enabled. + #10 + + + value4 + The passive level is 1 and the delay is enabled. + #11 + + + + + + + INPR + Interrupt Node Pointer Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSINP + Transmit Shift Interrupt Node Pointer + 0 + 2 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + TBINP + Transmit Buffer Interrupt Node Pointer + 4 + 6 + read-write + + + RINP + Receive Interrupt Node Pointer + 8 + 10 + read-write + + + AINP + Alternative Receive Interrupt Node Pointer + 12 + 14 + read-write + + + PINP + Transmit Shift Interrupt Node Pointer + 16 + 18 + read-write + + + + + DX0CR + Input Control Register 0 + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX1CR + Input Control Register 1 + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DX1A is selected. + #000 + + + value2 + The data input DX1B is selected. + #001 + + + value3 + The data input DX1C is selected. + #010 + + + value4 + The data input DX1D is selected. + #011 + + + value5 + The data input DX1E is selected. + #100 + + + value6 + The data input DX1F is selected. + #101 + + + value7 + The data input DX1G is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + DCEN + Delay Compensation Enable + 3 + 3 + read-write + + + value1 + The receive shift clock is dependent on INSW selection. + #0 + + + value2 + The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. + #1 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DX1T. + #01 + + + value3 + A falling edge activates DX1T. + #10 + + + value4 + Both edges activate DX1T. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DX1S is 0. + #0 + + + value2 + The current value of DX1S is 1. + #1 + + + + + + + DX2CR + Input Control Register 2 + 0x024 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX3CR + Input Control Register 3 + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX4CR + Input Control Register 4 + 0x02C + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + DX5CR + Input Control Register 5 + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSEL + Data Selection for Input Signal + 0 + 2 + read-write + + + value1 + The data input DXnA is selected. + #000 + + + value2 + The data input DXnB is selected. + #001 + + + value3 + The data input DXnC is selected. + #010 + + + value4 + The data input DXnD is selected. + #011 + + + value5 + The data input DXnE is selected. + #100 + + + value6 + The data input DXnF is selected. + #101 + + + value7 + The data input DXnG is selected. + #110 + + + value8 + The data input is always 1. + #111 + + + + + INSW + Input Switch + 4 + 4 + read-write + + + value1 + The input of the data shift unit is controlled by the protocol pre-processor. + #0 + + + value2 + The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. + #1 + + + + + DFEN + Digital Filter Enable + 5 + 5 + read-write + + + value1 + The input signal is not digitally filtered. + #0 + + + value2 + The input signal is digitally filtered. + #1 + + + + + DSEN + Data Synchronization Enable + 6 + 6 + read-write + + + value1 + The un-synchronized signal can be taken as input for the data shift unit. + #0 + + + value2 + The synchronized signal can be taken as input for the data shift unit. + #1 + + + + + DPOL + Data Polarity for DXn + 8 + 8 + read-write + + + value1 + The input signal is not inverted. + #0 + + + value2 + The input signal is inverted. + #1 + + + + + SFSEL + Sampling Frequency Selection + 9 + 9 + read-write + + + value1 + The sampling frequency is fPB. + #0 + + + value2 + The sampling frequency is fFD. + #1 + + + + + CM + Combination Mode + 10 + 11 + read-write + + + value1 + The trigger activation is disabled. + #00 + + + value2 + A rising edge activates DXnT. + #01 + + + value3 + A falling edge activates DXnT. + #10 + + + value4 + Both edges activate DXnT. + #11 + + + + + DXS + Synchronized Data Value + 15 + 15 + read-only + + + value1 + The current value of DXnS is 0. + #0 + + + value2 + The current value of DXnS is 1. + #1 + + + + + + + SCTR + Shift Control Register + 0x034 + 32 + 0x00000000 + 0xFFFFFFFF + + + SDIR + Shift Direction + 0 + 0 + read-write + + + value1 + Shift LSB first. The first data bit of a data word is located at bit position 0. + #0 + + + value2 + Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE. + #1 + + + + + PDL + Passive Data Level + 1 + 1 + read-write + + + value1 + The passive data level is 0. + #0 + + + value2 + The passive data level is 1. + #1 + + + + + DSM + Data Shift Mode + 2 + 3 + read-write + + + value1 + Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0. + #00 + + + value3 + Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively. + #10 + + + value4 + Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively. + #11 + + + + + HPCDIR + Port Control Direction + 4 + 4 + read-write + + + value1 + The pin(s) with hardware pin control enabled are selected to be in input mode. + #0 + + + value2 + The pin(s) with hardware pin control enabled are selected to be in output mode. + #1 + + + + + DOCFG + Data Output Configuration + 6 + 7 + read-write + + + value1 + DOUTx = shift data value + #00 + + + value2 + DOUTx = inverted shift data value + #01 + + + + + TRM + Transmission Mode + 8 + 9 + read-write + + + value1 + The shift control signal is considered as inactive and data frame transfers are not possible. + #00 + + + value2 + The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. + #01 + + + value3 + The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. + #10 + + + value4 + The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. + #11 + + + + + FLE + Frame Length + 16 + 21 + read-write + + + WLE + Word Length + 24 + 27 + read-write + + + value1 + The data word contains 1 data bit located at bit position 0. + 0x0 + + + value2 + The data word contains 2 data bits located at bit positions [1:0]. + 0x1 + + + value3 + The data word contains 15 data bits located at bit positions [14:0]. + 0xE + + + value4 + The data word contains 16 data bits located at bit positions [15:0]. + 0xF + + + + + + + TCSR + Transmit Control/Status Register + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLEMD + WLE Mode + 0 + 0 + read-write + + + value1 + The automatic update of SCTR.WLE and TCSR.EOF is disabled. + #0 + + + value2 + The automatic update of SCTR.WLE and TCSR.EOF is enabled. + #1 + + + + + SELMD + Select Mode + 1 + 1 + read-write + + + value1 + The automatic update of PCR.CTR[23:16] is disabled. + #0 + + + value2 + The automatic update of PCR.CTR[23:16] is disabled. + #1 + + + + + FLEMD + FLE Mode + 2 + 2 + read-write + + + value1 + The automatic update of FLE is disabled. + #0 + + + value2 + The automatic update of FLE is enabled. + #1 + + + + + WAMD + WA Mode + 3 + 3 + read-write + + + value1 + The automatic update of bit WA is disabled. + #0 + + + value2 + The automatic update of bit WA is enabled. + #1 + + + + + HPCMD + Hardware Port Control Mode + 4 + 4 + read-write + + + value1 + The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled. + #0 + + + value2 + The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled. + #1 + + + + + SOF + Start Of Frame + 5 + 5 + read-write + + + value1 + The data word in TBUF is not considered as first word of a frame. + #0 + + + value2 + The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). + #1 + + + + + EOF + End Of Frame + 6 + 6 + read-write + + + value1 + The data word in TBUF is not considered as last word of an SSC frame. + #0 + + + value2 + The data word in TBUF is considered as last word of an SSC frame. + #1 + + + + + TDV + Transmit Data Valid + 7 + 7 + read-only + + + value1 + The data word in TBUF is not valid for transmission. + #0 + + + value2 + The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. + #1 + + + + + TDSSM + TBUF Data Single Shot Mode + 8 + 8 + read-write + + + value1 + The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. + #0 + + + value2 + The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. + #1 + + + + + TDEN + TBUF Data Enable + 10 + 11 + read-write + + + value1 + A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. + #00 + + + value2 + A transmission of the data word in TBUF can be started if TDV = 1. + #01 + + + value3 + A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. + #10 + + + value4 + A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. + #11 + + + + + TDVTR + TBUF Data Valid Trigger + 12 + 12 + read-write + + + value1 + Bit TCSR.TE is permanently set. + #0 + + + value2 + Bit TCSR.TE is set if DX2T becomes active while TDV = 1. + #1 + + + + + WA + Word Address + 13 + 13 + read-write + + + value1 + The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA). + #0 + + + value2 + The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA). + #1 + + + + + TSOF + Transmitted Start Of Frame + 24 + 24 + read-only + + + value1 + The latest data word transmission has not been started for the first word of a data frame. + #0 + + + value2 + The latest data word transmission has been started for the first word of a data frame. + #1 + + + + + TV + Transmission Valid + 26 + 26 + read-only + + + value1 + The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started. + #0 + + + value2 + The latest start of a data word transmission has taken place with valid data from TBUF. + #1 + + + + + TVC + Transmission Valid Cumulated + 27 + 27 + read-only + + + value1 + Since TVC has been set, at least one data buffer underflow condition has occurred. + #0 + + + value2 + Since TVC has been set, no data buffer underflow condition has occurred. + #1 + + + + + TE + Trigger Event + 28 + 28 + read-only + + + value1 + The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started. + #0 + + + value2 + The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can not be started. + #1 + + + + + + + PCR + Protocol Control Register + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + CTR0 + Protocol Control Bit 0 + 0 + 0 + read-write + + + CTR1 + Protocol Control Bit 1 + 1 + 1 + read-write + + + CTR2 + Protocol Control Bit 2 + 2 + 2 + read-write + + + CTR3 + Protocol Control Bit 3 + 3 + 3 + read-write + + + CTR4 + Protocol Control Bit 4 + 4 + 4 + read-write + + + CTR5 + Protocol Control Bit 5 + 5 + 5 + read-write + + + CTR6 + Protocol Control Bit 6 + 6 + 6 + read-write + + + CTR7 + Protocol Control Bit 7 + 7 + 7 + read-write + + + CTR8 + Protocol Control Bit 8 + 8 + 8 + read-write + + + CTR9 + Protocol Control Bit 9 + 9 + 9 + read-write + + + CTR10 + Protocol Control Bit 10 + 10 + 10 + read-write + + + CTR11 + Protocol Control Bit 11 + 11 + 11 + read-write + + + CTR12 + Protocol Control Bit 12 + 12 + 12 + read-write + + + CTR13 + Protocol Control Bit 13 + 13 + 13 + read-write + + + CTR14 + Protocol Control Bit 14 + 14 + 14 + read-write + + + CTR15 + Protocol Control Bit 15 + 15 + 15 + read-write + + + CTR16 + Protocol Control Bit 16 + 16 + 16 + read-write + + + CTR17 + Protocol Control Bit 17 + 17 + 17 + read-write + + + CTR18 + Protocol Control Bit 18 + 18 + 18 + read-write + + + CTR19 + Protocol Control Bit 19 + 19 + 19 + read-write + + + CTR20 + Protocol Control Bit 20 + 20 + 20 + read-write + + + CTR21 + Protocol Control Bit 21 + 21 + 21 + read-write + + + CTR22 + Protocol Control Bit 22 + 22 + 22 + read-write + + + CTR23 + Protocol Control Bit 23 + 23 + 23 + read-write + + + CTR24 + Protocol Control Bit 24 + 24 + 24 + read-write + + + CTR25 + Protocol Control Bit 25 + 25 + 25 + read-write + + + CTR26 + Protocol Control Bit 26 + 26 + 26 + read-write + + + CTR27 + Protocol Control Bit 27 + 27 + 27 + read-write + + + CTR28 + Protocol Control Bit 28 + 28 + 28 + read-write + + + CTR29 + Protocol Control Bit 29 + 29 + 29 + read-write + + + CTR30 + Protocol Control Bit 30 + 30 + 30 + read-write + + + CTR31 + Protocol Control Bit 31 + 31 + 31 + read-write + + + + + PCR_ASCMode + Protocol Control Register [ASC Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + SMD + Sample Mode + 0 + 0 + read-write + + + value1 + Only one sample is taken per bit time. The current input value is sampled. + #0 + + + value2 + Three samples are taken per bit time and a majority decision is made. + #1 + + + + + STPB + Stop Bits + 1 + 1 + read-write + + + value1 + The number of stop bits is 1. + #0 + + + value2 + The number of stop bits is 2. + #1 + + + + + IDM + Idle Detection Mode + 2 + 2 + read-write + + + value1 + The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. + #0 + + + value2 + The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). + #1 + + + + + SBIEN + Synchronization Break Interrupt Enable + 3 + 3 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + CDEN + Collision Detection Enable + 4 + 4 + read-write + + + value1 + The collision detection is disabled. + #0 + + + value2 + If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software. + #1 + + + + + RNIEN + Receiver Noise Detection Interrupt Enable + 5 + 5 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + FEIEN + Format Error Interrupt Enable + 6 + 6 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + FFIEN + Frame Finished Interrupt Enable + 7 + 7 + read-write + + + value1 + The interrupt generation is disabled. + #0 + + + value2 + The interrupt generation is enabled. + #1 + + + + + SP + Sample Point + 8 + 12 + read-write + + + PL + Pulse Length + 13 + 15 + read-write + + + value1 + The pulse length is equal to the bit length (no shortened 0). + #000 + + + value2 + The pulse length of a 0 bit is 2 time quanta. + #001 + + + value3 + The pulse length of a 0 bit is 3 time quanta. + #010 + + + value4 + The pulse length of a 0 bit is 8 time quanta. + #111 + + + + + RSTEN + Receiver Status Enable + 16 + 16 + read-write + + + value1 + Flag PSR[9] is not modified depending on the receiver status. + #0 + + + value2 + Flag PSR[9] is set during the complete reception of a frame. + #1 + + + + + TSTEN + Transmitter Status Enable + 17 + 17 + read-write + + + value1 + Flag PSR[9] is not modified depending on the transmitter status. + #0 + + + value2 + Flag PSR[9] is set during the complete transmission of a frame. + #1 + + + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and the MCLK signal is 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + PCR_SSCMode + Protocol Control Register [SSC Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + MSLSEN + MSLS Enable + 0 + 0 + read-write + + + value1 + The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. + #0 + + + value2 + The MSLS generation is enabled. This is the setting for SSC master mode. + #1 + + + + + SELCTR + Select Control + 1 + 1 + read-write + + + value1 + The coded select mode is enabled. + #0 + + + value2 + The direct select mode is enabled. + #1 + + + + + SELINV + Select Inversion + 2 + 2 + read-write + + + value1 + The SELO outputs have the same polarity as the MSLS signal (active high). + #0 + + + value2 + The SELO outputs have the inverted polarity to the MSLS signal (active low). + #1 + + + + + FEM + Frame End Mode + 3 + 3 + read-write + + + value1 + The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). + #0 + + + value2 + The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. + #1 + + + + + CTQSEL1 + Input Frequency Selection + 4 + 5 + read-write + + + value1 + fCTQIN = fPDIV + #00 + + + value2 + fCTQIN = fPPP + #01 + + + value3 + fCTQIN = fSCLK + #10 + + + value4 + fCTQIN = fMCLK + #11 + + + + + PCTQ1 + Divider Factor PCTQ1 for Tiw and Tnf + 6 + 7 + read-write + + + DCTQ1 + Divider Factor DCTQ1 for Tiw and Tnf + 8 + 12 + read-write + + + PARIEN + Parity Error Interrupt Enable + 13 + 13 + read-write + + + value1 + A protocol interrupt is not generated with the detection of a parity error. + #0 + + + value2 + A protocol interrupt is generated with the detection of a parity error. + #1 + + + + + MSLSIEN + MSLS Interrupt Enable + 14 + 14 + read-write + + + value1 + A protocol interrupt is not generated if a change of signal MSLS is detected. + #0 + + + value2 + A protocol interrupt is generated if a change of signal MSLS is detected. + #1 + + + + + DX2TIEN + DX2T Interrupt Enable + 15 + 15 + read-write + + + value1 + A protocol interrupt is not generated if DX2T is activated. + #0 + + + value2 + A protocol interrupt is generated if DX2T is activated. + #1 + + + + + SELO + Select Output + 16 + 23 + read-write + + + value1 + The corresponding SELOx line cannot be activated. + #0 + + + value2 + The corresponding SELOx line can be activated (according to the mode selected by SELCTR). + #1 + + + + + TIWEN + Enable Inter-Word Delay Tiw + 24 + 24 + read-write + + + value1 + No delay between data words of the same frame. + #0 + + + value2 + The inter-word delay Tiw is enabled and introduced between data words of the same frame. + #1 + + + + + SLPHSEL + Slave Mode Clock Phase Select + 25 + 25 + read-write + + + value1 + Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge. + 0b0 + + + value2 + The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge. + 0b1 + + + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and output MCLK = 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + PCR_IICMode + Protocol Control Register [IIC Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + SLAD + Slave Address + 0 + 15 + read-write + + + ACK00 + Acknowledge 00H + 16 + 16 + read-write + + + value1 + The slave device is not sensitive to this address. + #0 + + + value2 + The slave device is sensitive to this address. + #1 + + + + + STIM + Symbol Timing + 17 + 17 + read-write + + + value1 + A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud). + #0 + + + value2 + A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud). + #1 + + + + + SCRIEN + Start Condition Received Interrupt Enable + 18 + 18 + read-write + + + value1 + The start condition interrupt is disabled. + #0 + + + value2 + The start condition interrupt is enabled. + #1 + + + + + RSCRIEN + Repeated Start Condition Received Interrupt Enable + 19 + 19 + read-write + + + value1 + The repeated start condition interrupt is disabled. + #0 + + + value2 + The repeated start condition interrupt is enabled. + #1 + + + + + PCRIEN + Stop Condition Received Interrupt Enable + 20 + 20 + read-write + + + value1 + The stop condition interrupt is disabled. + #0 + + + value2 + The stop condition interrupt is enabled. + #1 + + + + + NACKIEN + Non-Acknowledge Interrupt Enable + 21 + 21 + read-write + + + value1 + The non-acknowledge interrupt is disabled. + #0 + + + value2 + The non-acknowledge interrupt is enabled. + #1 + + + + + ARLIEN + Arbitration Lost Interrupt Enable + 22 + 22 + read-write + + + value1 + The arbitration lost interrupt is disabled. + #0 + + + value2 + The arbitration lost interrupt is enabled. + #1 + + + + + SRRIEN + Slave Read Request Interrupt Enable + 23 + 23 + read-write + + + value1 + The slave read request interrupt is disabled. + #0 + + + value2 + The slave read request interrupt is enabled. + #1 + + + + + ERRIEN + Error Interrupt Enable + 24 + 24 + read-write + + + value1 + The error interrupt is disabled. + #0 + + + value2 + The error interrupt is enabled. + #1 + + + + + SACKDIS + Slave Acknowledge Disable + 25 + 25 + read-write + + + value1 + The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received). + #0 + + + value2 + The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped). + #1 + + + + + HDEL + Hardware Delay + 26 + 29 + read-write + + + ACKIEN + Acknowledge Interrupt Enable + 30 + 30 + read-write + + + value1 + The acknowledge interrupt is disabled. + #0 + + + value2 + The acknowledge interrupt is enabled. + #1 + + + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and MCLK is 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + PCR_IISMode + Protocol Control Register [IIS Mode] + PCR + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + WAGEN + WA Generation Enable + 0 + 0 + read-write + + + value1 + The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. + #0 + + + value2 + The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. + #1 + + + + + DTEN + Data Transfers Enable + 1 + 1 + read-write + + + value1 + The changes of the WA input signal are ignored and no transfers take place. + #0 + + + value2 + Transfers are enabled. + #1 + + + + + SELINV + Select Inversion + 2 + 2 + read-write + + + value1 + The SELOx outputs have the same polarity as the WA signal. + #0 + + + value2 + The SELOx outputs have the inverted polarity to the WA signal. + #1 + + + + + WAFEIEN + WA Falling Edge Interrupt Enable + 4 + 4 + read-write + + + value1 + A protocol interrupt is not activated if a falling edge of WA is generated. + #0 + + + value2 + A protocol interrupt is activated if a falling edge of WA is generated. + #1 + + + + + WAREIEN + WA Rising Edge Interrupt Enable + 5 + 5 + read-write + + + value1 + A protocol interrupt is not activated if a rising edge of WA is generated. + #0 + + + value2 + A protocol interrupt is activated if a rising edge of WA is generated. + #1 + + + + + ENDIEN + END Interrupt Enable + 6 + 6 + read-write + + + value1 + A protocol interrupt is not activated. + #0 + + + value2 + A protocol interrupt is activated. + #1 + + + + + DX2TIEN + DX2T Interrupt Enable + 15 + 15 + read-write + + + value1 + A protocol interrupt is not generated if DX2T is active. + #0 + + + value2 + A protocol interrupt is generated if DX2T is active. + #1 + + + + + TDEL + Transfer Delay + 16 + 21 + read-write + + + MCLK + Master Clock Enable + 31 + 31 + read-write + + + value1 + The MCLK generation is disabled and MCLK is 0. + #0 + + + value2 + The MCLK generation is enabled. + #1 + + + + + + + CCR + Channel Control Register + 0x040 + 32 + 0x00000000 + 0xFFFFFFFF + + + MODE + Operating Mode + 0 + 3 + read-write + + + value1 + The USIC channel is disabled. All protocol-related state machines are set to an idle state. + 0x0 + + + value2 + The SSC (SPI) protocol is selected. + 0x1 + + + value3 + The ASC (SCI, UART) protocol is selected. + 0x2 + + + value4 + The IIS protocol is selected. + 0x3 + + + value5 + The IIC protocol is selected. + 0x4 + + + + + HPCEN + Hardware Port Control Enable + 6 + 7 + read-write + + + value1 + The hardware port control is disabled. + #00 + + + value2 + The hardware port control is enabled for DX0 and DOUT0. + #01 + + + value3 + The hardware port control is enabled for DX3, DX0 and DOUT[1:0]. + #10 + + + value4 + The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0]. + #11 + + + + + PM + Parity Mode + 8 + 9 + read-write + + + value1 + The parity generation is disabled. + #00 + + + value3 + Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). + #10 + + + value4 + Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). + #11 + + + + + RSIEN + Receiver Start Interrupt Enable + 10 + 10 + read-write + + + value1 + The receiver start interrupt is disabled. + #0 + + + value2 + The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated. + #1 + + + + + DLIEN + Data Lost Interrupt Enable + 11 + 11 + read-write + + + value1 + The data lost interrupt is disabled. + #0 + + + value2 + The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated. + #1 + + + + + TSIEN + Transmit Shift Interrupt Enable + 12 + 12 + read-write + + + value1 + The transmit shift interrupt is disabled. + #0 + + + value2 + The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated. + #1 + + + + + TBIEN + Transmit Buffer Interrupt Enable + 13 + 13 + read-write + + + value1 + The transmit buffer interrupt is disabled. + #0 + + + value2 + The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated. + #1 + + + + + RIEN + Receive Interrupt Enable + 14 + 14 + read-write + + + value1 + The receive interrupt is disabled. + #0 + + + value2 + The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated. + #1 + + + + + AIEN + Alternative Receive Interrupt Enable + 15 + 15 + read-write + + + value1 + The alternative receive interrupt is disabled. + #0 + + + value2 + The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated. + #1 + + + + + BRGIEN + Baud Rate Generator Interrupt Enable + 16 + 16 + read-write + + + value1 + The baud rate generator interrupt is disabled. + #0 + + + value2 + The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated. + #1 + + + + + + + CMTR + Capture Mode Timer Register + 0x044 + 32 + 0x00000000 + 0xFFFFFFFF + + + CTV + Captured Timer Value + 0 + 9 + read-write + + + + + PSR + Protocol Status Register + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + ST0 + Protocol Status Flag 0 + 0 + 0 + read-write + + + ST1 + Protocol Status Flag 1 + 1 + 1 + read-write + + + ST2 + Protocol Status Flag 2 + 2 + 2 + read-write + + + ST3 + Protocol Status Flag 3 + 3 + 3 + read-write + + + ST4 + Protocol Status Flag 4 + 4 + 4 + read-write + + + ST5 + Protocol Status Flag 5 + 5 + 5 + read-write + + + ST6 + Protocol Status Flag 6 + 6 + 6 + read-write + + + ST7 + Protocol Status Flag 7 + 7 + 7 + read-write + + + ST8 + Protocol Status Flag 8 + 8 + 8 + read-write + + + ST9 + Protocol Status Flag 9 + 9 + 9 + read-write + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_ASCMode + Protocol Status Register [ASC Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXIDLE + Transmission Idle + 0 + 0 + read-write + + + value1 + The transmitter line has not yet been idle. + #0 + + + value2 + The transmitter line has been idle and frame transmission is possible. + #1 + + + + + RXIDLE + Reception Idle + 1 + 1 + read-write + + + value1 + The receiver line has not yet been idle. + #0 + + + value2 + The receiver line has been idle and frame reception is possible. + #1 + + + + + SBD + Synchronization Break Detected + 2 + 2 + read-write + + + value1 + A synchronization break has not yet been detected. + #0 + + + value2 + A synchronization break has been detected. + #1 + + + + + COL + Collision Detected + 3 + 3 + read-write + + + value1 + A collision has not yet been detected and frame transmission is possible. + #0 + + + value2 + A collision has been detected and frame transmission is not possible. + #1 + + + + + RNS + Receiver Noise Detected + 4 + 4 + read-write + + + value1 + Receiver noise has not been detected. + #0 + + + value2 + Receiver noise has been detected. + #1 + + + + + FER0 + Format Error in Stop Bit 0 + 5 + 5 + read-write + + + value1 + A format error 0 has not been detected. + #0 + + + value2 + A format error 0 has been detected. + #1 + + + + + FER1 + Format Error in Stop Bit 1 + 6 + 6 + read-write + + + value1 + A format error 1 has not been detected. + #0 + + + value2 + A format error 1 has been detected. + #1 + + + + + RFF + Receive Frame Finished + 7 + 7 + read-write + + + value1 + The received frame is not yet finished. + #0 + + + value2 + The received frame is finished. + #1 + + + + + TFF + Transmitter Frame Finished + 8 + 8 + read-write + + + value1 + The transmitter frame is not yet finished. + #0 + + + value2 + The transmitter frame is finished. + #1 + + + + + BUSY + Transfer Status BUSY + 9 + 9 + read-only + + + value1 + A data transfer does not take place. + #0 + + + value2 + A data transfer currently takes place. + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_SSCMode + Protocol Status Register [SSC Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + MSLS + MSLS Status + 0 + 0 + read-write + + + value1 + The internal signal MSLS is inactive (0). + #0 + + + value2 + The internal signal MSLS is active (1). + #1 + + + + + DX2S + DX2S Status + 1 + 1 + read-write + + + value1 + DX2S is 0. + #0 + + + value2 + DX2S is 1. + #1 + + + + + MSLSEV + MSLS Event Detected + 2 + 2 + read-write + + + value1 + The MSLS signal has not changed its state. + #0 + + + value2 + The MSLS signal has changed its state. + #1 + + + + + DX2TEV + DX2T Event Detected + 3 + 3 + read-write + + + value1 + The DX2T signal has not been activated. + #0 + + + value2 + The DX2T signal has been activated. + #1 + + + + + PARERR + Parity Error Event Detected + 4 + 4 + read-write + + + value1 + A parity error event has not been activated. + #0 + + + value2 + A parity error event has been activated. + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_IICMode + Protocol Status Register [IIC Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLSEL + Slave Select + 0 + 0 + read-write + + + value1 + The device is not selected as slave. + #0 + + + value2 + The device is selected as slave. + #1 + + + + + WTDF + Wrong TDF Code Found + 1 + 1 + read-write + + + value1 + A wrong TDF code has not been found. + #0 + + + value2 + A wrong TDF code has been found. + #1 + + + + + SCR + Start Condition Received + 2 + 2 + read-write + + + value1 + A start condition has not yet been detected. + #0 + + + value2 + A start condition has been detected. + #1 + + + + + RSCR + Repeated Start Condition Received + 3 + 3 + read-write + + + value1 + A repeated start condition has not yet been detected. + #0 + + + value2 + A repeated start condition has been detected. + #1 + + + + + PCR + Stop Condition Received + 4 + 4 + read-write + + + value1 + A stop condition has not yet been detected. + #0 + + + value2 + A stop condition has been detected. + #1 + + + + + NACK + Non-Acknowledge Received + 5 + 5 + read-write + + + value1 + A non-acknowledge has not been received. + #0 + + + value2 + A non-acknowledge has been received. + #1 + + + + + ARL + Arbitration Lost + 6 + 6 + read-write + + + value1 + An arbitration has not been lost. + #0 + + + value2 + An arbitration has been lost. + #1 + + + + + SRR + Slave Read Request + 7 + 7 + read-write + + + value1 + A slave read request has not been detected. + #0 + + + value2 + A slave read request has been detected. + #1 + + + + + ERR + Error + 8 + 8 + read-write + + + value1 + An IIC error has not been detected. + #0 + + + value2 + An IIC error has been detected. + #1 + + + + + ACK + Acknowledge Received + 9 + 9 + read-write + + + value1 + An acknowledge has not been received. + #0 + + + value2 + An acknowledge has been received. + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSR_IISMode + Protocol Status Register [IIS Mode] + PSR + 0x048 + 32 + 0x00000000 + 0xFFFFFFFF + + + WA + Word Address + 0 + 0 + read-write + + + value1 + WA has been sampled 0. + #0 + + + value2 + WA has been sampled 1. + #1 + + + + + DX2S + DX2S Status + 1 + 1 + read-write + + + value1 + DX2S is 0. + #0 + + + value2 + DX2S is 1. + #1 + + + + + DX2TEV + DX2T Event Detected + 3 + 3 + read-write + + + value1 + The DX2T signal has not been activated. + #0 + + + value2 + The DX2T signal has been activated. + #1 + + + + + WAFE + WA Falling Edge Event + 4 + 4 + read-write + + + value1 + A WA falling edge has not been generated. + #0 + + + value2 + A WA falling edge has been generated. + #1 + + + + + WARE + WA Rising Edge Event + 5 + 5 + read-write + + + value1 + A WA rising edge has not been generated. + #0 + + + value2 + A WA rising edge has been generated. + #1 + + + + + END + WA Generation End + 6 + 6 + read-write + + + value1 + The WA generation has not yet ended (if it is running and WAGEN has been cleared). + #0 + + + value2 + The WA generation has ended (if it has been running). + #1 + + + + + RSIF + Receiver Start Indication Flag + 10 + 10 + read-write + + + value1 + A receiver start event has not occurred. + #0 + + + value2 + A receiver start event has occurred. + #1 + + + + + DLIF + Data Lost Indication Flag + 11 + 11 + read-write + + + value1 + A data lost event has not occurred. + #0 + + + value2 + A data lost event has occurred. + #1 + + + + + TSIF + Transmit Shift Indication Flag + 12 + 12 + read-write + + + value1 + A transmit shift event has not occurred. + #0 + + + value2 + A transmit shift event has occurred. + #1 + + + + + TBIF + Transmit Buffer Indication Flag + 13 + 13 + read-write + + + value1 + A transmit buffer event has not occurred. + #0 + + + value2 + A transmit buffer event has occurred. + #1 + + + + + RIF + Receive Indication Flag + 14 + 14 + read-write + + + value1 + A receive event has not occurred. + #0 + + + value2 + A receive event has occurred. + #1 + + + + + AIF + Alternative Receive Indication Flag + 15 + 15 + read-write + + + value1 + An alternative receive event has not occurred. + #0 + + + value2 + An alternative receive event has occurred. + #1 + + + + + BRGIF + Baud Rate Generator Indication Flag + 16 + 16 + read-write + + + value1 + A baud rate generator event has not occurred. + #0 + + + value2 + A baud rate generator event has occurred. + #1 + + + + + + + PSCR + Protocol Status Clear Register + 0x04C + 32 + 0x00000000 + 0xFFFFFFFF + + + CST0 + Clear Status Flag 0 in PSR + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST1 + Clear Status Flag 1 in PSR + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST2 + Clear Status Flag 2 in PSR + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST3 + Clear Status Flag 3 in PSR + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST4 + Clear Status Flag 4 in PSR + 4 + 4 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST5 + Clear Status Flag 5 in PSR + 5 + 5 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST6 + Clear Status Flag 6 in PSR + 6 + 6 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST7 + Clear Status Flag 7 in PSR + 7 + 7 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST8 + Clear Status Flag 8 in PSR + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CST9 + Clear Status Flag 9 in PSR + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.STx is cleared. + #1 + + + + + CRSIF + Clear Receiver Start Indication Flag + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.RSIF is cleared. + #1 + + + + + CDLIF + Clear Data Lost Indication Flag + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.DLIF is cleared. + #1 + + + + + CTSIF + Clear Transmit Shift Indication Flag + 12 + 12 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.TSIF is cleared. + #1 + + + + + CTBIF + Clear Transmit Buffer Indication Flag + 13 + 13 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.TBIF is cleared. + #1 + + + + + CRIF + Clear Receive Indication Flag + 14 + 14 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.RIF is cleared. + #1 + + + + + CAIF + Clear Alternative Receive Indication Flag + 15 + 15 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.AIF is cleared. + #1 + + + + + CBRGIF + Clear Baud Rate Generator Indication Flag + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Flag PSR.BRGIF is cleared. + #1 + + + + + + + RBUFSR + Receiver Buffer Status Register + 0x050 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLEN + Received Data Word Length in RBUF or RBUFD + 0 + 3 + read-only + + + SOF + Start of Frame in RBUF or RBUFD + 6 + 6 + read-only + + + PAR + Protocol-Related Argument in RBUF or RBUFD + 8 + 8 + read-only + + + PERR + Protocol-related Error in RBUF or RBUFD + 9 + 9 + read-only + + + RDV0 + Receive Data Valid in RBUF or RBUFD + 13 + 13 + read-only + + + RDV1 + Receive Data Valid in RBUF or RBUFD + 14 + 14 + read-only + + + DS + Data Source of RBUF or RBUFD + 15 + 15 + read-only + + + + + RBUF + Receiver Buffer Register + 0x054 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + DSR + Received Data + 0 + 15 + read-only + + + + + RBUFD + Receiver Buffer Register for Debugger + 0x058 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR + Data from Shift Register + 0 + 15 + read-only + + + + + RBUF0 + Receiver Buffer Register 0 + 0x05C + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR0 + Data of Shift Registers 0[3:0] + 0 + 15 + read-only + + + + + RBUF1 + Receiver Buffer Register 1 + 0x060 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR1 + Data of Shift Registers 1[3:0] + 0 + 15 + read-only + + + + + RBUF01SR + Receiver Buffer 01 Status Register + 0x064 + 32 + 0x00000000 + 0xFFFFFFFF + + + WLEN0 + Received Data Word Length in RBUF0 + 0 + 3 + read-only + + + SOF0 + Start of Frame in RBUF0 + 6 + 6 + read-only + + + value1 + The data in RBUF0 has not been the first data word of a data frame. + #0 + + + value2 + The data in RBUF0 has been the first data word of a data frame. + #1 + + + + + PAR0 + Protocol-Related Argument in RBUF0 + 8 + 8 + read-only + + + PERR0 + Protocol-related Error in RBUF0 + 9 + 9 + read-only + + + value1 + The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. + #0 + + + value2 + The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. + #1 + + + + + RDV00 + Receive Data Valid in RBUF0 + 13 + 13 + read-only + + + value1 + Register RBUF0 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF0 contains data that has not yet been read out. + #1 + + + + + RDV01 + Receive Data Valid in RBUF1 + 14 + 14 + read-only + + + value1 + Register RBUF1 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF1 contains data that has not yet been read out. + #1 + + + + + DS0 + Data Source + 15 + 15 + read-only + + + value1 + The register RBUF contains the data of RBUF0 (same for associated status information). + #0 + + + value2 + The register RBUF contains the data of RBUF1 (same for associated status information). + #1 + + + + + WLEN1 + Received Data Word Length in RBUF1 + 16 + 19 + read-only + + + value1 + One bit has been received. + 0x0 + + + value2 + Sixteen bits have been received. + 0xF + + + + + SOF1 + Start of Frame in RBUF1 + 22 + 22 + read-only + + + value1 + The data in RBUF1 has not been the first data word of a data frame. + #0 + + + value2 + The data in RBUF1 has been the first data word of a data frame. + #1 + + + + + PAR1 + Protocol-Related Argument in RBUF1 + 24 + 24 + read-only + + + PERR1 + Protocol-related Error in RBUF1 + 25 + 25 + read-only + + + value1 + The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. + #0 + + + value2 + The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. + #1 + + + + + RDV10 + Receive Data Valid in RBUF0 + 29 + 29 + read-only + + + value1 + Register RBUF0 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF0 contains data that has not yet been read out. + #1 + + + + + RDV11 + Receive Data Valid in RBUF1 + 30 + 30 + read-only + + + value1 + Register RBUF1 does not contain data that has not yet been read out. + #0 + + + value2 + Register RBUF1 contains data that has not yet been read out. + #1 + + + + + DS1 + Data Source + 31 + 31 + read-only + + + value1 + The register RBUF contains the data of RBUF0 (same for associated status information). + #0 + + + value2 + The register RBUF contains the data of RBUF1 (same for associated status information). + #1 + + + + + + + FMR + Flag Modification Register + 0x068 + 32 + 0x00000000 + 0xFFFFFFFF + + + MTDV + Modify Transmit Data Valid + 0 + 1 + write-only + + + value1 + No action. + #00 + + + value2 + Bit TDV is set, TE is unchanged. + #01 + + + value3 + Bits TDV and TE are cleared. + #10 + + + + + ATVC + Activate Bit TVC + 4 + 4 + write-only + + + value1 + No action. + #0 + + + value2 + Bit TCSR.TVC is set. + #1 + + + + + CRDV0 + Clear Bits RDV for RBUF0 + 14 + 14 + write-only + + + value1 + No action. + #0 + + + value2 + Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared. + #1 + + + + + CRDV1 + Clear Bit RDV for RBUF1 + 15 + 15 + write-only + + + value1 + No action. + #0 + + + value2 + Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared. + #1 + + + + + SIO0 + Set Interrupt Output SRx + 16 + 16 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO1 + Set Interrupt Output SRx + 17 + 17 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO2 + Set Interrupt Output SRx + 18 + 18 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO3 + Set Interrupt Output SRx + 19 + 19 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO4 + Set Interrupt Output SRx + 20 + 20 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + SIO5 + Set Interrupt Output SRx + 21 + 21 + write-only + + + value1 + No action. + #0 + + + value2 + The service request output SRx is activated. + #1 + + + + + + + 32 + 4 + TBUF[%s] + Transmit Buffer + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDATA + Transmit Data + 0 + 15 + read-write + + + + + BYP + Bypass Data Register + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + BDATA + Bypass Data + 0 + 15 + read-write + + + + + BYPCR + Bypass Control Register + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + BWLE + Bypass Word Length + 0 + 3 + read-write + + + BDSSM + Bypass Data Single Shot Mode + 8 + 8 + read-write + + + value1 + The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. + #0 + + + value2 + The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV. + #1 + + + + + BDEN + Bypass Data Enable + 10 + 11 + read-write + + + value1 + The transfer of bypass data is disabled. + #00 + + + value2 + The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. + #01 + + + value3 + Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. + #10 + + + value4 + Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. + #11 + + + + + BDVTR + Bypass Data Valid Trigger + 12 + 12 + read-write + + + value1 + Bit BDV is not influenced by DX2T. + #0 + + + value2 + Bit BDV is set if DX2T is active. + #1 + + + + + BPRIO + Bypass Priority + 13 + 13 + read-write + + + value1 + The transmit FIFO data has a higher priority than the bypass data. + #0 + + + value2 + The bypass data has a higher priority than the transmit FIFO data. + #1 + + + + + BDV + Bypass Data Valid + 15 + 15 + read-only + + + value1 + The bypass data is not valid. + #0 + + + value2 + The bypass data is valid. + #1 + + + + + BSELO + Bypass Select Outputs + 16 + 20 + read-write + + + BHPC + Bypass Hardware Port Control + 21 + 23 + read-write + + + + + TBCTR + Transmitter Buffer Control Register + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPTR + Data Pointer + 0 + 5 + write-only + + + LIMIT + Limit For Interrupt Generation + 8 + 13 + read-write + + + STBTM + Standard Transmit Buffer Trigger Mode + 14 + 14 + read-write + + + value1 + Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT. + #0 + + + value2 + Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE. + #1 + + + + + STBTEN + Standard Transmit Buffer Trigger Enable + 15 + 15 + read-write + + + value1 + The standard transmit buffer event trigger through bit TRBSR.STBT is disabled. + #0 + + + value2 + The standard transmit buffer event trigger through bit TRBSR.STBT is enabled. + #1 + + + + + STBINP + Standard Transmit Buffer Interrupt Node Pointer + 16 + 18 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + ATBINP + Alternative Transmit Buffer Interrupt Node Pointer + 19 + 21 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + SIZE + Buffer Size + 24 + 26 + read-write + + + value1 + The FIFO mechanism is disabled. The buffer does not accept any request for data. + #000 + + + value2 + The FIFO buffer contains 2 entries. + #001 + + + value3 + The FIFO buffer contains 4 entries. + #010 + + + value4 + The FIFO buffer contains 8 entries. + #011 + + + value5 + The FIFO buffer contains 16 entries. + #100 + + + value6 + The FIFO buffer contains 32 entries. + #101 + + + value7 + The FIFO buffer contains 64 entries. + #110 + + + + + LOF + Buffer Event on Limit Overflow + 28 + 28 + read-write + + + value1 + A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word. + #0 + + + value2 + A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. + #1 + + + + + STBIEN + Standard Transmit Buffer Interrupt Enable + 30 + 30 + read-write + + + value1 + The standard transmit buffer interrupt generation is disabled. + #0 + + + value2 + The standard transmit buffer interrupt generation is enabled. + #1 + + + + + TBERIEN + Transmit Buffer Error Interrupt Enable + 31 + 31 + read-write + + + value1 + The transmit buffer error interrupt generation is disabled. + #0 + + + value2 + The transmit buffer error interrupt generation is enabled. + #1 + + + + + + + RBCTR + Receiver Buffer Control Register + 0x10C + 32 + 0x00000000 + 0xFFFFFFFF + + + DPTR + Data Pointer + 0 + 5 + write-only + + + LIMIT + Limit For Interrupt Generation + 8 + 13 + read-write + + + SRBTM + Standard Receive Buffer Trigger Mode + 14 + 14 + read-write + + + value1 + Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. + #0 + + + value2 + Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. + #1 + + + + + SRBTEN + Standard Receive Buffer Trigger Enable + 15 + 15 + read-write + + + value1 + The standard receive buffer event trigger through bit TRBSR.SRBT is disabled. + #0 + + + value2 + The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. + #1 + + + + + SRBINP + Standard Receive Buffer Interrupt Node Pointer + 16 + 18 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + ARBINP + Alternative Receive Buffer Interrupt Node Pointer + 19 + 21 + read-write + + + value1 + Output SR0 becomes activated. + #000 + + + value2 + Output SR1 becomes activated. + #001 + + + value3 + Output SR2 becomes activated. + #010 + + + value4 + Output SR3 becomes activated. + #011 + + + value5 + Output SR4 becomes activated. + #100 + + + value6 + Output SR5 becomes activated. + #101 + + + + + RCIM + Receiver Control Information Mode + 22 + 23 + read-write + + + value1 + RCI[4] = PERR, RCI[3:0] = WLEN + #00 + + + value2 + RCI[4] = SOF, RCI[3:0] = WLEN + #01 + + + value3 + RCI[4] = 0, RCI[3:0] = WLEN + #10 + + + value4 + RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF + #11 + + + + + SIZE + Buffer Size + 24 + 26 + read-write + + + value1 + The FIFO mechanism is disabled. The buffer does not accept any request for data. + #000 + + + value2 + The FIFO buffer contains 2 entries. + #001 + + + value3 + The FIFO buffer contains 4 entries. + #010 + + + value4 + The FIFO buffer contains 8 entries. + #011 + + + value5 + The FIFO buffer contains 16 entries. + #100 + + + value6 + The FIFO buffer contains 32 entries. + #101 + + + value7 + The FIFO buffer contains 64 entries. + #110 + + + + + RNM + Receiver Notification Mode + 27 + 27 + read-write + + + value1 + Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). + #0 + + + value2 + RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. + #1 + + + + + LOF + Buffer Event on Limit Overflow + 28 + 28 + read-write + + + value1 + A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR. + #0 + + + value2 + A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. + #1 + + + + + ARBIEN + Alternative Receive Buffer Interrupt Enable + 29 + 29 + read-write + + + value1 + The alternative receive buffer interrupt generation is disabled. + #0 + + + value2 + The alternative receive buffer interrupt generation is enabled. + #1 + + + + + SRBIEN + Standard Receive Buffer Interrupt Enable + 30 + 30 + read-write + + + value1 + The standard receive buffer interrupt generation is disabled. + #0 + + + value2 + The standard receive buffer interrupt generation is enabled. + #1 + + + + + RBERIEN + Receive Buffer Error Interrupt Enable + 31 + 31 + read-write + + + value1 + The receive buffer error interrupt generation is disabled. + #0 + + + value2 + The receive buffer error interrupt generation is enabled. + #1 + + + + + + + TRBPTR + Transmit/Receive Buffer Pointer Register + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDIPTR + Transmitter Data Input Pointer + 0 + 5 + read-only + + + TDOPTR + Transmitter Data Output Pointer + 8 + 13 + read-only + + + RDIPTR + Receiver Data Input Pointer + 16 + 21 + read-only + + + RDOPTR + Receiver Data Output Pointer + 24 + 29 + read-only + + + + + TRBSR + Transmit/Receive Buffer Status Register + 0x114 + 32 + 0x00000808 + 0xFFFFFFFF + + + SRBI + Standard Receive Buffer Event + 0 + 0 + read-write + + + value1 + A standard receive buffer event has not been detected. + #0 + + + value2 + A standard receive buffer event has been detected. + #1 + + + + + RBERI + Receive Buffer Error Event + 1 + 1 + read-write + + + value1 + A receive buffer error event has not been detected. + #0 + + + value2 + A receive buffer error event has been detected. + #1 + + + + + ARBI + Alternative Receive Buffer Event + 2 + 2 + read-write + + + value1 + An alternative receive buffer event has not been detected. + #0 + + + value2 + An alternative receive buffer event has been detected. + #1 + + + + + REMPTY + Receive Buffer Empty + 3 + 3 + read-only + + + value1 + The receive buffer is not empty. + #0 + + + value2 + The receive buffer is empty. + #1 + + + + + RFULL + Receive Buffer Full + 4 + 4 + read-only + + + value1 + The receive buffer is not full. + #0 + + + value2 + The receive buffer is full. + #1 + + + + + RBUS + Receive Buffer Busy + 5 + 5 + read-only + + + value1 + The receive buffer information has been completely updated. + #0 + + + value2 + The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. + #1 + + + + + SRBT + Standard Receive Buffer Event Trigger + 6 + 6 + read-only + + + value1 + A standard receive buffer event is not triggered using this bit. + #0 + + + value2 + A standard receive buffer event is triggered using this bit. + #1 + + + + + STBI + Standard Transmit Buffer Event + 8 + 8 + read-write + + + value1 + A standard transmit buffer event has not been detected. + #0 + + + value2 + A standard transmit buffer event has been detected. + #1 + + + + + TBERI + Transmit Buffer Error Event + 9 + 9 + read-write + + + value1 + A transmit buffer error event has not been detected. + #0 + + + value2 + A transmit buffer error event has been detected. + #1 + + + + + TEMPTY + Transmit Buffer Empty + 11 + 11 + read-only + + + value1 + The transmit buffer is not empty. + #0 + + + value2 + The transmit buffer is empty. + #1 + + + + + TFULL + Transmit Buffer Full + 12 + 12 + read-only + + + value1 + The transmit buffer is not full. + #0 + + + value2 + The transmit buffer is full. + #1 + + + + + TBUS + Transmit Buffer Busy + 13 + 13 + read-only + + + value1 + The transmit buffer information has been completely updated. + #0 + + + value2 + The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. + #1 + + + + + STBT + Standard Transmit Buffer Event Trigger + 14 + 14 + read-only + + + value1 + A standard transmit buffer event is not triggered using this bit. + #0 + + + value2 + A standard transmit buffer event is triggered using this bit. + #1 + + + + + RBFLVL + Receive Buffer Filling Level + 16 + 22 + read-only + + + TBFLVL + Transmit Buffer Filling Level + 24 + 30 + read-only + + + + + TRBSCR + Transmit/Receive Buffer Status Clear Register + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + CSRBI + Clear Standard Receive Buffer Event + 0 + 0 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.SRBI. + #1 + + + + + CRBERI + Clear Receive Buffer Error Event + 1 + 1 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.RBERI. + #1 + + + + + CARBI + Clear Alternative Receive Buffer Event + 2 + 2 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.ARBI. + #1 + + + + + CSTBI + Clear Standard Transmit Buffer Event + 8 + 8 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.STBI. + #1 + + + + + CTBERI + Clear Transmit Buffer Error Event + 9 + 9 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear TRBSR.TBERI. + #1 + + + + + CBDV + Clear Bypass Data Valid + 10 + 10 + write-only + + + value1 + No effect. + #0 + + + value2 + Clear BYPCR.BDV. + #1 + + + + + FLUSHRB + Flush Receive Buffer + 14 + 14 + write-only + + + value1 + No effect. + #0 + + + value2 + The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. + #1 + + + + + FLUSHTB + Flush Transmit Buffer + 15 + 15 + write-only + + + value1 + No effect. + #0 + + + value2 + The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. + #1 + + + + + + + OUTR + Receiver Buffer Output Register + 0x11C + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + DSR + Received Data + 0 + 15 + read-only + + + RCI + Receiver Control Information + 16 + 20 + read-only + + + + + OUTDR + Receiver Buffer Output Register L for Debugger + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSR + Data from Shift Register + 0 + 15 + read-only + + + RCI + Receive Control Information from Shift Register + 16 + 20 + read-only + + + + + 32 + 4 + IN[%s] + Transmit FIFO Buffer + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDATA + Transmit Data + 0 + 15 + write-only + + + + + + + USIC0_CH1 + Universal Serial Interface Controller 0 + USIC + 0x40030200 + + 0x0 + 0x0200 + registers + + + + USIC1_CH0 + Universal Serial Interface Controller 0 + USIC + 0x48020000 + + 0x0 + 0x0200 + registers + + + + USIC1_CH1 + Universal Serial Interface Controller 0 + USIC + 0x48020200 + + 0x0 + 0x0200 + registers + + + + USIC2_CH0 + Universal Serial Interface Controller 0 + USIC + 0x48024000 + + 0x0 + 0x0200 + registers + + + + USIC2_CH1 + Universal Serial Interface Controller 0 + USIC + 0x48024200 + + 0x0 + 0x0200 + registers + + + + CAN + Controller Area Networks + CAN + 0x48014000 + + 0x0 + 0x200 + registers + + + CAN0_0 + MultiCAN + 76 + + + CAN0_1 + MultiCAN + 77 + + + CAN0_2 + MultiCAN + 78 + + + CAN0_3 + MultiCAN + 79 + + + CAN0_4 + MultiCAN + 80 + + + CAN0_5 + MultiCAN + 81 + + + CAN0_6 + MultiCAN + 82 + + + CAN0_7 + MultiCAN + 83 + + + + CLC + CAN Clock Control Register + 0x0000 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + EDIS + Sleep Mode Enable Control + 3 + 3 + read-write + + + + + ID + Module Identification Register + 0x0008 + 32 + 0x00B5C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision Number + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + value1 + Define the module as a 32-bit module. + 0xC0 + + + + + MOD_NUMBER + Module Number Value + 16 + 31 + read-only + + + + + FDR + CAN Fractional Divider Register + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + STEP + Step Value + 0 + 9 + read-write + + + DM + Divider Mode + 14 + 15 + read-write + + + + + 16 + 4 + LIST[%s] + List Register + 0x0100 + 32 + 0x00000000 + 0x00000000 + + + BEGIN + List Begin + 0 + 7 + read-only + + + END + List End + 8 + 15 + read-only + + + SIZE + List Size + 16 + 23 + read-only + + + EMPTY + List Empty Indication + 24 + 24 + read-only + + + value1 + At least one message object is allocated to list i. + #0 + + + value2 + No message object is allocated to the list i. List i is empty. + #1 + + + + + + + 8 + 4 + MSPND[%s] + Message Pending Register + 0x0140 + 32 + 0x00000000 + 0xFFFFFFFF + + + PND + Message Pending + 0 + 31 + read-write + + + + + 8 + 4 + MSID[%s] + Message Index Register + 0x0180 + 32 + 0x00000020 + 0xFFFFFFFF + + + INDEX + Message Pending Index + 0 + 5 + read-only + + + + + MSIMASK + Message Index Mask Register + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IM + Message Index Mask + 0 + 31 + read-write + + + + + PANCTR + Panel Control Register + 0x01C4 + 32 + 0x00000301 + 0xFFFFFFFF + + + PANCMD + Panel Command + 0 + 7 + read-write + + + BUSY + Panel Busy Flag + 8 + 8 + read-only + + + value1 + Panel has finished command and is ready to accept a new command. + #0 + + + value2 + Panel operation is in progress. + #1 + + + + + RBUSY + Result Busy Flag + 9 + 9 + read-only + + + value1 + No update of PANAR1 and PANAR2 is scheduled by the list controller. + #0 + + + value2 + A list command is running (BUSY = 1) that will write results to PANAR1 and PANAR2, but the results are not yet available. + #1 + + + + + PANAR1 + Panel Argument 1 + 16 + 23 + read-write + + + PANAR2 + Panel Argument 2 + 24 + 31 + read-write + + + + + MCR + Module Control Register + 0x01C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CLKSEL + Baud Rate Logic Clock Select + 0 + 3 + read-write + + + value1 + No clock supplied + #0000 + + + value2 + fPERIPH + #0001 + + + value3 + fOHP + #0010 + + + value4 + hard wired to 0 + #0100 + + + value5 + hard wired to 0 + #1000 + + + + + MPSEL + Message Pending Selector + 12 + 15 + read-write + + + + + MITR + Module Interrupt Trigger Register + 0x01CC + 32 + 0x00000000 + 0xFFFFFFFF + + + IT + Interrupt Trigger + 0 + 7 + write-only + + + + + + + CAN_NODE0 + Controller Area Networks + CAN + CAN_NODE + 0x48014200 + + 0x0 + 0x100 + registers + + + + NCR + Node Control Register + 0x00 + 32 + 0x00000041 + 0xFFFFFFFF + + + INIT + Node Initialization + 0 + 0 + read-write + + + value1 + Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic. + #0 + + + value2 + Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set. + #1 + + + + + TRIE + Transfer Interrupt Enable + 1 + 1 + read-write + + + value1 + Transfer interrupt is disabled. + #0 + + + value2 + Transfer interrupt is enabled. + #1 + + + + + LECIE + LEC Indicated Error Interrupt Enable + 2 + 2 + read-write + + + value1 + Last error code interrupt is disabled. + #0 + + + value2 + Last error code interrupt is enabled. + #1 + + + + + ALIE + Alert Interrupt Enable + 3 + 3 + read-write + + + value1 + Alert interrupt is disabled. + #0 + + + value2 + Alert interrupt is enabled. + #1 + + + + + CANDIS + CAN Disable + 4 + 4 + read-write + + + TXDIS + Transmit Disable + 5 + 5 + read-write + + + CCE + Configuration Change Enable + 6 + 6 + read-write + + + value1 + The Bit Timing Register, the Port Control Register, Error Counter Register may only be read. All attempts to modify them are ignored. + #0 + + + value2 + The Bit Timing Register, the Port Control Register, Error Counter Register may be read and written. + #1 + + + + + CALM + CAN Analyzer Mode + 7 + 7 + read-write + + + + + NSR + Node Status Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + LEC + Last Error Code + 0 + 2 + read-write + + + TXOK + Message Transmitted Successfully + 3 + 3 + read-write + + + value1 + No successful transmission since last (most recent) flag reset. + #0 + + + value2 + A message has been transmitted successfully (error-free and acknowledged by at least another node). + #1 + + + + + RXOK + Message Received Successfully + 4 + 4 + read-write + + + value1 + No successful reception since last (most recent) flag reset. + #0 + + + value2 + A message has been received successfully. + #1 + + + + + ALERT + Alert Warning + 5 + 5 + read-write + + + EWRN + Error Warning Status + 6 + 6 + read-only + + + value1 + No warning limit exceeded. + #0 + + + value2 + One of the error counters REC or TEC reached the warning limit EWRNLVL. + #1 + + + + + BOFF + Bus-off Status + 7 + 7 + read-only + + + value1 + CAN controller is not in the bus-off state. + #0 + + + value2 + CAN controller is in the bus-off state. + #1 + + + + + LLE + List Length Error + 8 + 8 + read-write + + + value1 + No List Length Error since last (most recent) flag reset. + #0 + + + value2 + A List Length Error has been detected during message acceptance filtering. The number of elements in the list that belongs to this CAN node differs from the list SIZE given in the list termination pointer. + #1 + + + + + LOE + List Object Error + 9 + 9 + read-write + + + value1 + No List Object Error since last (most recent) flag reset. + #0 + + + value2 + A List Object Error has been detected during message acceptance filtering. A message object with wrong LIST index entry in the Message Object Status Register has been detected. + #1 + + + + + + + NIPR + Node Interrupt Pointer Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALINP + Alert Interrupt Node Pointer + 0 + 3 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + LECINP + Last Error Code Interrupt Node Pointer + 4 + 7 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + TRINP + Transfer OK Interrupt Node Pointer + 8 + 11 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + CFCINP + Frame Counter Interrupt Node Pointer + 12 + 15 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + + + NPCR + Node Port Control Register + 0x0C + 32 + 0x00000000 + 0xFFFFFFFF + + + RXSEL + Receive Select + 0 + 2 + read-write + + + LBM + Loop-Back Mode + 8 + 8 + read-write + + + value1 + Loop-Back Mode is disabled. + #0 + + + value2 + Loop-Back Mode is enabled. This node is connected to an internal (virtual) loop-back CAN bus. All CAN nodes which are in Loop-Back Mode are connected to this virtual CAN bus so that they can communicate with each other internally. The external transmit line is forced recessive in Loop-Back Mode. + #1 + + + + + + + NBTR + Node Bit Timing Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + BRP + Baud Rate Prescaler + 0 + 5 + read-write + + + SJW + (Re) Synchronization Jump Width + 6 + 7 + read-write + + + TSEG1 + Time Segment Before Sample Point + 8 + 11 + read-write + + + TSEG2 + Time Segment After Sample Point + 12 + 14 + read-write + + + DIV8 + Divide Prescaler Clock by 8 + 15 + 15 + read-write + + + value1 + A time quantum lasts (BRP+1) clock cycles. + #0 + + + value2 + A time quantum lasts 8 (BRP+1) clock cycles. + #1 + + + + + + + NECNT + Node Error Counter Register + 0x14 + 32 + 0x00600000 + 0xFFFFFFFF + + + REC + Receive Error Counter + 0 + 7 + read-write + + + TEC + Transmit Error Counter + 8 + 15 + read-write + + + EWRNLVL + Error Warning Level + 16 + 23 + read-write + + + LETD + Last Error Transfer Direction + 24 + 24 + read-only + + + value1 + The last error occurred while the CAN node x was receiver (REC has been incremented). + #0 + + + value2 + The last error occurred while the CAN node x was transmitter (TEC has been incremented). + #1 + + + + + LEINC + Last Error Increment + 25 + 25 + read-only + + + value1 + The last error led to an error counter increment of 1. + #0 + + + value2 + The last error led to an error counter increment of 8. + #1 + + + + + + + NFCR + Node Frame Counter Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFC + CAN Frame Counter + 0 + 15 + read-write + + + CFSEL + CAN Frame Count Selection + 16 + 18 + read-write + + + CFMOD + CAN Frame Counter Mode + 19 + 20 + read-write + + + value1 + Frame Count Mode: The frame counter is incremented upon the reception and transmission of frames. + #00 + + + value2 + Time Stamp Mode: The frame counter is used to count bit times. + #01 + + + value3 + Bit Timing Mode: The frame counter is used for analysis of the bit timing. + #10 + + + value4 + Error Count Mode: The frame counter is used for counting when an error frame is received or an error is detected by the node. + #11 + + + + + CFCIE + CAN Frame Count Interrupt Enable + 22 + 22 + read-write + + + value1 + CAN frame counter overflow interrupt is disabled. + #0 + + + value2 + CAN frame counter overflow interrupt is enabled. + #1 + + + + + CFCOV + CAN Frame Counter Overflow Flag + 23 + 23 + read-write + + + value1 + No overflow has occurred since last flag reset. + #0 + + + value2 + An overflow has occurred since last flag reset. + #1 + + + + + + + + + CAN_NODE1 + Controller Area Networks + CAN + 0x48014300 + + 0x0 + 0x100 + registers + + + + CAN_NODE2 + Controller Area Networks + CAN + 0x48014400 + + 0x0 + 0x100 + registers + + + + CAN_NODE3 + Controller Area Networks + CAN + 0x48014500 + + 0x0 + 0x100 + registers + + + + CAN_NODE4 + Controller Area Networks + CAN + 0x48014600 + + 0x0 + 0x100 + registers + + + + CAN_NODE5 + Controller Area Networks + CAN + 0x48014700 + + 0x0 + 0x100 + registers + + + + CAN_MO + Controller Area Networks + CAN + CAN_MO_CLUSTER + 0x48015000 + + 0x0 + 0x2000 + registers + + + + 256 + 0x20 + MO[%s] + Message Object Registers + CAN_MO + 0 + + MOFCR + Message Object Function Control Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + MMC + Message Mode Control + 0 + 3 + read-write + + + value1 + Standard Message Object + #0000 + + + value2 + Receive FIFO Base Object + #0001 + + + value3 + Transmit FIFO Base Object + #0010 + + + value4 + Transmit FIFO Slave Object + #0011 + + + value5 + Gateway Source Object + #0100 + + + + + RXTOE + Receive Time-Out Enable + 4 + 4 + read-write + + + value1 + Message does not take part in receive time-out check + #0 + + + value2 + Message takes part in receive time-out check + #1 + + + + + GDFS + Gateway Data Frame Send + 8 + 8 + read-write + + + value1 + TXRQ is unchanged in the destination object. + #0 + + + value2 + TXRQ is set in the gateway destination object after the internal transfer from the gateway source to the gateway destination object. + #1 + + + + + IDC + Identifier Copy + 9 + 9 + read-write + + + value1 + The identifier of the gateway source object is not copied. + #0 + + + value2 + The identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. + #1 + + + + + DLCC + Data Length Code Copy + 10 + 10 + read-write + + + value1 + Data length code is not copied. + #0 + + + value2 + Data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. + #1 + + + + + DATC + Data Copy + 11 + 11 + read-write + + + value1 + Data fields are not copied. + #0 + + + value2 + Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) are copied to the gateway destination. + #1 + + + + + RXIE + Receive Interrupt Enable + 16 + 16 + read-write + + + value1 + Message receive interrupt is disabled. + #0 + + + value2 + Message receive interrupt is enabled. + #1 + + + + + TXIE + Transmit Interrupt Enable + 17 + 17 + read-write + + + value1 + Message transmit interrupt is disabled. + #0 + + + value2 + Message transmit interrupt is enabled. + #1 + + + + + OVIE + Overflow Interrupt Enable + 18 + 18 + read-write + + + value1 + FIFO full interrupt is disabled. + #0 + + + value2 + FIFO full interrupt is enabled. + #1 + + + + + FRREN + Foreign Remote Request Enable + 20 + 20 + read-write + + + value1 + TXRQ of message object n is set on reception of a matching Remote Frame. + #0 + + + value2 + TXRQ of the message object referenced by the pointer CUR is set on reception of a matching Remote Frame. + #1 + + + + + RMM + Transmit Object Remote Monitoring + 21 + 21 + read-write + + + value1 + Remote monitoring is disabled: Identifier, IDE bit, and DLC of message object n remain unchanged upon the reception of a matching Remote Frame. + #0 + + + value2 + Remote monitoring is enabled: Identifier, IDE bit, and DLC of a matching Remote Frame are copied to transmit object n in order to monitor incoming Remote Frames. + #1 + + + + + SDT + Single Data Transfer + 22 + 22 + read-write + + + STT + Single Transmit Trial + 23 + 23 + read-write + + + DLC + Data Length Code + 24 + 27 + read-write + + + + + MOFGPR + Message Object FIFO/Gateway Pointer Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOT + Bottom Pointer + 0 + 7 + read-write + + + TOP + Top Pointer + 8 + 15 + read-write + + + CUR + Current Object Pointer + 16 + 23 + read-write + + + SEL + Object Select Pointer + 24 + 31 + read-write + + + + + MOIPR + Message Object Interrupt Pointer Register + 0x08 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXINP + Receive Interrupt Node Pointer + 0 + 3 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + TXINP + Transmit Interrupt Node Pointer + 4 + 7 + read-write + + + value1 + Interrupt output line INT_O0 is selected. + #0000 + + + value2 + Interrupt output line INT_O1 is selected. + #0001 + + + value3 + Interrupt output line INT_O14 is selected. + #1110 + + + value4 + Interrupt output line INT_O15 is selected. + #1111 + + + + + MPN + Message Pending Number + 8 + 15 + read-write + + + CFCVAL + CAN Frame Counter Value + 16 + 31 + read-write + + + + + MOAMR + Message Object Acceptance Mask Register + 0x0C + 32 + 0x3FFFFFFF + 0xFFFFFFFF + + + AM + Acceptance Mask for Message Identifier + 0 + 28 + read-write + + + MIDE + Acceptance Mask Bit for Message IDE Bit + 29 + 29 + read-write + + + value1 + Message object n accepts the reception of both, standard and extended frames. + #0 + + + value2 + Message object n receives frames only with matching IDE bit. + #1 + + + + + + + MODATAL + Message Object Data Register Low + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DB0 + Data Byte 0 of Message Object n + 0 + 7 + read-write + + + DB1 + Data Byte 1 of Message Object n + 8 + 15 + read-write + + + DB2 + Data Byte 2 of Message Object n + 16 + 23 + read-write + + + DB3 + Data Byte 3 of Message Object n + 24 + 31 + read-write + + + + + MODATAH + Message Object Data Register High + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + DB4 + Data Byte 4 of Message Object n + 0 + 7 + read-write + + + DB5 + Data Byte 5 of Message Object n + 8 + 15 + read-write + + + DB6 + Data Byte 6 of Message Object n + 16 + 23 + read-write + + + DB7 + Data Byte 7 of Message Object n + 24 + 31 + read-write + + + + + MOAR + Message Object Arbitration Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ID + CAN Identifier of Message Object n + 0 + 28 + read-write + + + IDE + Identifier Extension Bit of Message Object n + 29 + 29 + read-write + + + value1 + Message object n handles standard frames with 11-bit identifier. + #0 + + + value2 + Message object n handles extended frames with 29-bit identifier. + #1 + + + + + PRI + Priority Class + 30 + 31 + read-write + + + value2 + Transmit acceptance filtering is based on the list order. This means that message object n is considered for transmission only if there is no other message object with valid transmit request (MSGVAL & TXEN0 & TXEN1 = 1) somewhere before this object in the list. + #01 + + + value3 + Transmit acceptance filtering is based on the CAN identifier. This means, message object n is considered for transmission only if there is no other message object with higher priority identifier + IDE + DIR (with respect to CAN arbitration rules) somewhere in the list (see ). + #10 + + + value4 + Transmit acceptance filtering is based on the list order (as PRI = 01B). + #11 + + + + + + + MOCTR + Message Object Control Register + 0x1C + 32 + 0x00000000 + 0x0000FFFF + + + RESRXPND + Reset/Set Receive Pending + 0 + 0 + write-only + + + SETRXPND + Reset/Set Receive Pending + 16 + 16 + write-only + + + RESTXPND + Reset/Set Transmit Pending + 1 + 1 + write-only + + + SETTXPND + Reset/Set Transmit Pending + 17 + 17 + write-only + + + RESRXUPD + Reset/Set Receive Updating + 2 + 2 + write-only + + + SETRXUPD + Reset/Set Receive Updating + 18 + 18 + write-only + + + RESNEWDAT + Reset/Set New Data + 3 + 3 + write-only + + + SETNEWDAT + Reset/Set New Data + 19 + 19 + write-only + + + RESMSGLST + Reset/Set Message Lost + 4 + 4 + write-only + + + SETMSGLST + Reset/Set Message Lost + 20 + 20 + write-only + + + RESMSGVAL + Reset/Set Message Valid + 5 + 5 + write-only + + + SETMSGVAL + Reset/Set Message Valid + 21 + 21 + write-only + + + RESRTSEL + Reset/Set Receive/Transmit Selected + 6 + 6 + write-only + + + SETRTSEL + Reset/Set Receive/Transmit Selected + 22 + 22 + write-only + + + RESRXEN + Reset/Set Receive Enable + 7 + 7 + write-only + + + SETRXEN + Reset/Set Receive Enable + 23 + 23 + write-only + + + RESTXRQ + Reset/Set Transmit Request + 8 + 8 + write-only + + + SETTXRQ + Reset/Set Transmit Request + 24 + 24 + write-only + + + RESTXEN0 + Reset/Set Transmit Enable 0 + 9 + 9 + write-only + + + SETTXEN0 + Reset/Set Transmit Enable 0 + 25 + 25 + write-only + + + RESTXEN1 + Reset/Set Transmit Enable 1 + 10 + 10 + write-only + + + SETTXEN1 + Reset/Set Transmit Enable 1 + 26 + 26 + write-only + + + RESDIR + Reset/Set Message Direction + 11 + 11 + write-only + + + SETDIR + Reset/Set Message Direction + 27 + 27 + write-only + + + + + MOSTAT + Message Object Status Register + MOCTR + 0x1C + 32 + 0x00000000 + 0x0000FFFF + + + RXPND + Receive Pending + 0 + 0 + read-only + + + value1 + No CAN message has been received. + #0 + + + value2 + A CAN message has been received by the message object n, either directly or via gateway copy action. + #1 + + + + + TXPND + Transmit Pending + 1 + 1 + read-only + + + value1 + No CAN message has been transmitted. + #0 + + + value2 + A CAN message from message object n has been transmitted successfully over the CAN bus. + #1 + + + + + RXUPD + Receive Updating + 2 + 2 + read-only + + + value1 + No receive update ongoing. + #0 + + + value2 + Message identifier, DLC, and data of the message object are currently updated. + #1 + + + + + NEWDAT + New Data + 3 + 3 + read-only + + + value1 + No update of the message object n since last flag reset. + #0 + + + value2 + Message object n has been updated. + #1 + + + + + MSGLST + Message Lost + 4 + 4 + read-only + + + value1 + No CAN message is lost. + #0 + + + value2 + A CAN message is lost because NEWDAT has become set again when it has already been set. + #1 + + + + + MSGVAL + Message Valid + 5 + 5 + read-only + + + value1 + Message object n is not valid. + #0 + + + value2 + Message object n is valid. + #1 + + + + + RTSEL + Receive/Transmit Selected + 6 + 6 + read-only + + + value1 + Message object n is not selected for receive or transmit operation. + #0 + + + value2 + Message object n is selected for receive or transmit operation. + #1 + + + + + RXEN + Receive Enable + 7 + 7 + read-only + + + value1 + Message object n is not enabled for frame reception. + #0 + + + value2 + Message object n is enabled for frame reception. + #1 + + + + + TXRQ + Transmit Request + 8 + 8 + read-only + + + value1 + No transmission of message object n is requested. + #0 + + + value2 + Transmission of message object n on the CAN bus is requested. + #1 + + + + + TXEN0 + Transmit Enable 0 + 9 + 9 + read-only + + + value1 + Message object n is not enabled for frame transmission. + #0 + + + value2 + Message object n is enabled for frame transmission. + #1 + + + + + TXEN1 + Transmit Enable 1 + 10 + 10 + read-only + + + value1 + Message object n is not enabled for frame transmission. + #0 + + + value2 + Message object n is enabled for frame transmission. + #1 + + + + + DIR + Message Direction + 11 + 11 + read-only + + + value1 + Receive Object selected: With TXRQ = 1, a Remote Frame with the identifier of message object n is scheduled for transmission. On reception of a Data Frame with matching identifier, the message is stored in message object n. + #0 + + + value2 + Transmit Object selected: If TXRQ = 1, message object n is scheduled for transmission of a Data Frame. On reception of a Remote Frame with matching identifier, bit TXRQ is set. + #1 + + + + + LIST + List Allocation + 12 + 15 + read-only + + + PPREV + Pointer to Previous Message Object + 16 + 23 + read-only + + + PNEXT + Pointer to Next Message Object + 24 + 31 + read-only + + + + + + + + VADC + Analog to Digital Converter + VADC + 0x40004000 + + 0x0 + 0x400 + registers + + + VADC0_C0_0 + Analog to Digital Converter Common Block 0 + 14 + + + VADC0_C0_1 + Analog to Digital Converter Common Block 0 + 15 + + + VADC0_C0_2 + Analog to Digital Converter Common Block 0 + 16 + + + VADC0_C0_3 + Analog to Digital Converter Common Block 0 + 17 + + + + CLC + Clock Control Register + 0x0000 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + value1 + On request: enable the module clock + #0 + + + value2 + Off request: stop the module clock + #1 + + + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + value1 + Module clock is enabled + #0 + + + value2 + Off: module is not clocked + #1 + + + + + EDIS + Sleep Mode Enable Control + 3 + 3 + read-write + + + value1 + Sleep mode request is enabled and functional + #0 + + + value2 + Module disregards the sleep mode control signal + #1 + + + + + + + ID + Module Identification Register + 0x0008 + 32 + 0x00C5C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + OCS + OCDS Control and Status Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + TGS + Trigger Set for OTGB0/1 + 0 + 1 + read-write + + + value1 + No Trigger Set output + #00 + + + value2 + Trigger Set 1: TS16_SSIG, input sample signals + #01 + + + + + TGB + OTGB0/1 Bus Select + 2 + 2 + read-write + + + value1 + Trigger Set is output on OTGB0 + #0 + + + value2 + Trigger Set is output on OTGB1 + #1 + + + + + TG_P + TGS, TGB Write Protection + 3 + 3 + write-only + + + SUS + OCDS Suspend Control + 24 + 27 + read-write + + + value1 + Will not suspend + #0000 + + + value2 + Hard suspend: Clock is switched off immediately. + #0001 + + + value3 + Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter. + #0010 + + + value4 + Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round. + #0011 + + + + + SUS_P + SUS Write Protection + 28 + 28 + write-only + + + SUSSTA + Suspend State + 29 + 29 + read-only + + + value1 + Module is not (yet) suspended + #0 + + + value2 + Module is suspended + #1 + + + + + + + GLOBCFG + Global Configuration Register + 0x0080 + 32 + 0x0000000F + 0xFFFFFFFF + + + DIVA + Divider Factor for the Analog Internal Clock + 0 + 4 + read-write + + + value1 + fADCI = fADC / 2 + 0x00 + + + value2 + fADCI = fADC / 2 + 0x01 + + + value3 + fADCI = fADC / 3 + 0x02 + + + value4 + fADCI = fADC / 32 + 0x1F + + + + + DCMSB + Double Clock for the MSB Conversion + 7 + 7 + read-write + + + value1 + 1 clock cycles for the MSB (standard) + #0 + + + value2 + 2 clock cycles for the MSB (fADCI > 20 MHz) + #1 + + + + + DIVD + Divider Factor for the Arbiter Clock + 8 + 9 + read-write + + + value1 + fADCD = fADC + #00 + + + value2 + fADCD = fADC / 2 + #01 + + + value3 + fADCD = fADC / 3 + #10 + + + value4 + fADCD = fADC / 4 + #11 + + + + + DIVWC + Write Control for Divider Parameters + 15 + 15 + write-only + + + value1 + No write access to divider parameters + #0 + + + value2 + Bitfields DIVA, DCMSB, DIVD can be written + #1 + + + + + DPCAL0 + Disable Post-Calibration + 16 + 16 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + DPCAL1 + Disable Post-Calibration + 17 + 17 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + DPCAL2 + Disable Post-Calibration + 18 + 18 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + DPCAL3 + Disable Post-Calibration + 19 + 19 + read-write + + + value1 + Automatic post-calibration after each conversion of group x + #0 + + + value2 + No post-calibration + #1 + + + + + SUCAL + Start-Up Calibration + 31 + 31 + write-only + + + value1 + No action + #0 + + + value2 + Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL) + #1 + + + + + + + 2 + 4 + GLOBICLASS[%s] + Input Class Register, Global + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + STCS + Sample Time Control for Standard Conversions + 0 + 4 + read-write + + + CMS + Conversion Mode for Standard Conversions + 8 + 10 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + STCE + Sample Time Control for EMUX Conversions + 16 + 20 + read-write + + + CME + Conversion Mode for EMUX Conversions + 24 + 26 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + + + GLOBBOUND + Global Boundary Select Register + 0x00B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOUNDARY0 + Boundary Value 0 for Limit Checking + 0 + 11 + read-write + + + BOUNDARY1 + Boundary Value 1 for Limit Checking + 16 + 27 + read-write + + + + + GLOBEFLAG + Global Event Flag Register + 0x00E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEVGLB + Source Event (Background) + 0 + 0 + read-write + + + value1 + No source event + #0 + + + value2 + A source event has occurred + #1 + + + + + REVGLB + Global Result Event + 8 + 8 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GLOBRES + #1 + + + + + SEVGLBCLR + Clear Source Event (Background) + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Clear the source event flag SEVGLB + #1 + + + + + REVGLBCLR + Clear Global Result Event + 24 + 24 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag REVGLB + #1 + + + + + + + GLOBEVNP + Global Event Node Pointer Register + 0x0140 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0NP + Service Request Node Pointer Backgr. Source + 0 + 3 + read-write + + + value1 + Select shared service request line 0 of common service request group 0 + #0000 + + + value2 + Select shared service request line 3 of common service request group 0 + #0011 + + + value3 + Select shared service request line 0 of common service request group 1 + #0100 + + + value4 + Select shared service request line 3 of common service request group 1 + #0111 + + + + + REV0NP + Service Request Node Pointer Backgr. Result + 16 + 19 + read-write + + + value1 + Select shared service request line 0 of common service request group 0 + #0000 + + + value2 + Select shared service request line 3 of common service request group 0 + #0011 + + + value3 + Select shared service request line 0 of common service request group 1 + #0100 + + + value4 + Select shared service request line 3 of common service request group 1 + #0111 + + + + + + + GLOBTF + Global Test Functions Register + 0x0160 + 32 + 0x00000000 + 0xFFFFFFFF + + + CDGR + Converter Diagnostics Group + 4 + 7 + read-write + + + CDEN + Converter Diagnostics Enable + 8 + 8 + read-write + + + value1 + All diagnostic pull devices are disconnected + #0 + + + value2 + Diagnostic pull devices connected as selected by bitfield CDSEL + #1 + + + + + CDSEL + Converter Diagnostics Pull-Devices Select + 9 + 10 + read-write + + + value1 + Connected to VAREF + #00 + + + value2 + Connected to VAGND + #01 + + + value3 + Connected to 1/3rd VAREF + #10 + + + value4 + Connected to 2/3rd VAREF + #11 + + + + + CDWC + Write Control for Conversion Diagnostics + 15 + 15 + write-only + + + value1 + No write access to parameters + #0 + + + value2 + Bitfields CDSEL, CDEN, CDGR can be written + #1 + + + + + PDD + Pull-Down Diagnostics Enable + 16 + 16 + read-write + + + value1 + Disconnected + #0 + + + value2 + The pull-down diagnostics device is active + #1 + + + + + MDWC + Write Control for Multiplexer Diagnostics + 23 + 23 + write-only + + + value1 + No write access to parameters + #0 + + + value2 + Bitfield PDD can be written + #1 + + + + + + + 4 + 4 + BRSSEL[%s] + Background Request Source Channel Select Register + 0x0180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHSELG0 + Channel Selection Group x + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG1 + Channel Selection Group x + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG2 + Channel Selection Group x + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG3 + Channel Selection Group x + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG4 + Channel Selection Group x + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG5 + Channel Selection Group x + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG6 + Channel Selection Group x + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSELG7 + Channel Selection Group x + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + + + 4 + 4 + BRSPND[%s] + Background Request Source Pending Register + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHPNDG0 + Channels Pending Group x + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG1 + Channels Pending Group x + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG2 + Channels Pending Group x + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG3 + Channels Pending Group x + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG4 + Channels Pending Group x + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG5 + Channels Pending Group x + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG6 + Channels Pending Group x + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPNDG7 + Channels Pending Group x + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + + + BRSCTRL + Background Request Source Control Register + 0x0200 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCRESREG + Source-specific Result Register + 0 + 3 + read-write + + + value1 + Use GxCHCTRy.RESREG to select a group result register + #0000 + + + value2 + Store result in group result register GxRES1 + #0001 + + + value3 + Store result in group result register GxRES15 + #1111 + + + + + XTSEL + External Trigger Input Selection + 8 + 11 + read-write + + + XTLVL + External Trigger Level + 12 + 12 + read-only + + + XTMODE + Trigger Operating Mode + 13 + 14 + read-write + + + value1 + No external trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon any edge + #11 + + + + + XTWC + Write Control for Trigger Configuration + 15 + 15 + write-only + + + value1 + No write access to trigger configuration + #0 + + + value2 + Bitfields XTMODE and XTSEL can be written + #1 + + + + + GTSEL + Gate Input Selection + 16 + 19 + read-write + + + GTLVL + Gate Input Level + 20 + 20 + read-only + + + GTWC + Write Control for Gate Configuration + 23 + 23 + write-only + + + value1 + No write access to gate configuration + #0 + + + value2 + Bitfield GTSEL can be written + #1 + + + + + + + BRSMR + Background Request Source Mode Register + 0x0204 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENGT + Enable Gate + 0 + 1 + read-write + + + value1 + No conversion requests are issued + #00 + + + value2 + Conversion requests are issued if at least one pending bit is set + #01 + + + value3 + Conversion requests are issued if at least one pending bit is set and REQGTx = 1. + #10 + + + value4 + Conversion requests are issued if at least one pending bit is set and REQGTx = 0. + #11 + + + + + ENTR + Enable External Trigger + 2 + 2 + read-write + + + value1 + External trigger disabled + #0 + + + value2 + The selected edge at the selected trigger input signal REQTR generates the load event + #1 + + + + + ENSI + Enable Source Interrupt + 3 + 3 + read-write + + + value1 + No request source interrupt + #0 + + + value2 + A request source interrupt is generated upon a request source event (last pending conversion is finished) + #1 + + + + + SCAN + Autoscan Enable + 4 + 4 + read-write + + + value1 + No autoscan + #0 + + + value2 + Autoscan functionality enabled: a request source event automatically generates a load event + #1 + + + + + LDM + Autoscan Source Load Event Mode + 5 + 5 + read-write + + + value1 + Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event + #0 + + + value2 + Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) + #1 + + + + + REQGT + Request Gate Level + 7 + 7 + read-only + + + value1 + The gate input is low + #0 + + + value2 + The gate input is high + #1 + + + + + CLRPND + Clear Pending Bits + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + The bits in registers BRSPNDx are cleared + #1 + + + + + LDEV + Generate Load Event + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + A load event is generated + #1 + + + + + RPTDIS + Repeat Disable + 16 + 16 + read-write + + + value1 + A cancelled conversion is repeated + #0 + + + value2 + A cancelled conversion is discarded + #1 + + + + + + + GLOBRCR + Global Result Control Register + 0x0280 + 32 + 0x00000000 + 0xFFFFFFFF + + + DRCTR + Data Reduction Control + 16 + 19 + read-write + + + value1 + Data reduction disabled + #0000 + + + + + WFR + Wait-for-Read Mode Enable + 24 + 24 + read-write + + + value1 + Overwrite mode + #0 + + + value2 + Wait-for-read mode enabled for this register + #1 + + + + + SRGEN + Service Request Generation Enable + 31 + 31 + read-write + + + value1 + No service request + #0 + + + value2 + Service request after a result event + #1 + + + + + + + GLOBRES + Global Result Register + 0x0300 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + RESULT + Result of most recent conversion + 0 + 15 + read-write + + + GNR + Group Number + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) + #1 + + + + + + + GLOBRESD + Global Result Register, Debug + 0x0380 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-write + + + GNR + Group Number + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) + #1 + + + + + + + EMUXSEL + External Multiplexer Select Register + 0x03F0 + 32 + 0x00000000 + 0xFFFFFFFF + + + EMUXGRP0 + External Multiplexer Group for Interface x + 0 + 3 + read-write + + + EMUXGRP1 + External Multiplexer Group for Interface x + 4 + 7 + read-write + + + + + + + VADC_G0 + Analog to Digital Converter + VADC + VADC_G + 0x40004400 + + 0x0 + 0x400 + registers + + + VADC0_G0_0 + Analog to Digital Converter Group 0 + 18 + + + VADC0_G0_1 + Analog to Digital Converter Group 0 + 19 + + + VADC0_G0_2 + Analog to Digital Converter Group 0 + 20 + + + VADC0_G0_3 + Analog to Digital Converter Group 0 + 21 + + + + ARBCFG + Arbitration Configuration Register + 0x0080 + 32 + 0x00000000 + 0xFFFFFFFF + + + ANONC + Analog Converter Control + 0 + 1 + read-write + + + ARBRND + Arbitration Round Length + 4 + 5 + read-write + + + value1 + 4 arbitration slots per round (tARB = 4 / fADCD) + #00 + + + value2 + 8 arbitration slots per round (tARB = 8 / fADCD) + #01 + + + value3 + 16 arbitration slots per round (tARB = 16 / fADCD) + #10 + + + value4 + 20 arbitration slots per round (tARB = 20 / fADCD) + #11 + + + + + ARBM + Arbitration Mode + 7 + 7 + read-write + + + value1 + The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ). + #0 + + + value2 + The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported. + #1 + + + + + ANONS + Analog Converter Control Status + 16 + 17 + read-only + + + value1 + Analog converter off + #00 + + + value4 + Normal operation (permanently on) + #11 + + + + + CAL + Start-Up Calibration Active Indication + 28 + 28 + read-only + + + value1 + Completed or not yet started + #0 + + + value2 + Start-up calibration phase is active + #1 + + + + + BUSY + Converter Busy Flag + 30 + 30 + read-only + + + value1 + Not busy + #0 + + + value2 + Converter is busy with a conversion + #1 + + + + + SAMPLE + Sample Phase Flag + 31 + 31 + read-only + + + value1 + Converting or idle + #0 + + + value2 + Input signal is currently sampled + #1 + + + + + + + ARBPR + Arbitration Priority Register + 0x0084 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIO0 + Priority of Request Source x + 0 + 1 + read-write + + + value1 + Lowest priority is selected. + #00 + + + value2 + Highest priority is selected. + #11 + + + + + PRIO1 + Priority of Request Source x + 4 + 5 + read-write + + + value1 + Lowest priority is selected. + #00 + + + value2 + Highest priority is selected. + #11 + + + + + PRIO2 + Priority of Request Source x + 8 + 9 + read-write + + + value1 + Lowest priority is selected. + #00 + + + value2 + Highest priority is selected. + #11 + + + + + CSM0 + Conversion Start Mode of Request Source x + 3 + 3 + read-write + + + value1 + Wait-for-start mode + #0 + + + value2 + Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. + #1 + + + + + CSM1 + Conversion Start Mode of Request Source x + 7 + 7 + read-write + + + value1 + Wait-for-start mode + #0 + + + value2 + Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. + #1 + + + + + CSM2 + Conversion Start Mode of Request Source x + 11 + 11 + read-write + + + value1 + Wait-for-start mode + #0 + + + value2 + Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. + #1 + + + + + ASEN0 + Arbitration Slot 0 Enable + 24 + 24 + read-write + + + value1 + The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. + #0 + + + value2 + The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. + #1 + + + + + ASEN1 + Arbitration Slot 1 Enable + 25 + 25 + read-write + + + value1 + The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. + #0 + + + value2 + The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. + #1 + + + + + ASEN2 + Arbitration Slot 2 Enable + 26 + 26 + read-write + + + value1 + The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. + #0 + + + value2 + The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. + #1 + + + + + + + CHASS + Channel Assignment Register + 0x0088 + 32 + 0x00000000 + 0xFFFFFFFF + + + ASSCH0 + Assignment for Channel 0 + 0 + 0 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH1 + Assignment for Channel 1 + 1 + 1 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH2 + Assignment for Channel 2 + 2 + 2 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH3 + Assignment for Channel 3 + 3 + 3 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH4 + Assignment for Channel 4 + 4 + 4 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH5 + Assignment for Channel 5 + 5 + 5 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH6 + Assignment for Channel 6 + 6 + 6 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + ASSCH7 + Assignment for Channel 7 + 7 + 7 + read-write + + + value1 + Channel y can be a background channel converted with lowest priority + #0 + + + value2 + Channel y is a priority channel within group x + #1 + + + + + + + 2 + 4 + ICLASS[%s] + Input Class Register + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + STCS + Sample Time Control for Standard Conversions + 0 + 4 + read-write + + + CMS + Conversion Mode for Standard Conversions + 8 + 10 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + STCE + Sample Time Control for EMUX Conversions + 16 + 20 + read-write + + + CME + Conversion Mode for EMUX Conversions + 24 + 26 + read-write + + + value1 + 12-bit conversion + #000 + + + value2 + 10-bit conversion + #001 + + + value3 + 8-bit conversion + #010 + + + value6 + 10-bit fast compare mode + #101 + + + + + + + ALIAS + Alias Register + 0x00B0 + 32 + 0x00000100 + 0xFFFFFFFF + + + ALIAS0 + Alias Value for CH0 Conversion Requests + 0 + 4 + read-write + + + ALIAS1 + Alias Value for CH1 Conversion Requests + 8 + 12 + read-write + + + + + BOUND + Boundary Select Register + 0x00B8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOUNDARY0 + Boundary Value 0 for Limit Checking + 0 + 11 + read-write + + + BOUNDARY1 + Boundary Value 1 for Limit Checking + 16 + 27 + read-write + + + + + SYNCTR + Synchronization Control Register + 0x00C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + STSEL + Start Selection + 0 + 1 + read-write + + + value1 + Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC + #00 + + + value2 + Kernel is synchronization slave: Control information from input CI1 + #01 + + + value3 + Kernel is synchronization slave: Control information from input CI2 + #10 + + + value4 + Kernel is synchronization slave: Control information from input CI3 + #11 + + + + + EVALR1 + Evaluate Ready Input Rx + 4 + 4 + read-write + + + value1 + No ready input control + #0 + + + value2 + Ready input Rx is considered for the start of a parallel conversion of this conversion group + #1 + + + + + EVALR2 + Evaluate Ready Input Rx + 5 + 5 + read-write + + + value1 + No ready input control + #0 + + + value2 + Ready input Rx is considered for the start of a parallel conversion of this conversion group + #1 + + + + + EVALR3 + Evaluate Ready Input Rx + 6 + 6 + read-write + + + value1 + No ready input control + #0 + + + value2 + Ready input Rx is considered for the start of a parallel conversion of this conversion group + #1 + + + + + + + BFL + Boundary Flag Register + 0x00C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + BFL0 + Boundary Flag 0 + 0 + 0 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFL1 + Boundary Flag 1 + 1 + 1 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFL2 + Boundary Flag 2 + 2 + 2 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFL3 + Boundary Flag 3 + 3 + 3 + read-only + + + value1 + Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled + #0 + + + value2 + Active state: result has crossed the activation boundary + #1 + + + + + BFA0 + Boundary Flag 0 Activation Select + 8 + 8 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFA1 + Boundary Flag 1 Activation Select + 9 + 9 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFA2 + Boundary Flag 2 Activation Select + 10 + 10 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFA3 + Boundary Flag 3 Activation Select + 11 + 11 + read-write + + + value1 + Set boundary flag BFLy if result is above the defined band or compare value, clear if below + #0 + + + value2 + Set boundary flag BFLy if result is below the defined band or compare value, clear if above + #1 + + + + + BFI0 + Boundary Flag 0 Inversion Control + 16 + 16 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + BFI1 + Boundary Flag 1 Inversion Control + 17 + 17 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + BFI2 + Boundary Flag 2 Inversion Control + 18 + 18 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + BFI3 + Boundary Flag 3 Inversion Control + 19 + 19 + read-write + + + value1 + Use BFLy directly + #0 + + + value2 + Invert value and use BFLy + #1 + + + + + + + BFLS + Boundary Flag Software Register + 0x00CC + 32 + 0x00000000 + 0xFFFFFFFF + + + BFC0 + Boundary Flag 0 Clear + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFC1 + Boundary Flag 1 Clear + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFC2 + Boundary Flag 2 Clear + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFC3 + Boundary Flag 3 Clear + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit BFLy + #1 + + + + + BFS0 + Boundary Flag 0 Set + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + BFS1 + Boundary Flag 1 Set + 17 + 17 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + BFS2 + Boundary Flag 2 Set + 18 + 18 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + BFS3 + Boundary Flag 3 Set + 19 + 19 + write-only + + + value1 + No action + #0 + + + value2 + Set bit BFLy + #1 + + + + + + + BFLC + Boundary Flag Control Register + 0x00D0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BFM0 + Boundary Flag y Mode Control + 0 + 3 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + BFM1 + Boundary Flag y Mode Control + 4 + 7 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + BFM2 + Boundary Flag y Mode Control + 8 + 11 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + BFM3 + Boundary Flag y Mode Control + 12 + 15 + read-write + + + value1 + Disable boundary flag, BFLy is not changed + #0000 + + + value2 + Always enable boundary flag (follow compare results) + #0001 + + + value3 + Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive + #0010 + + + value4 + Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive + #0011 + + + + + + + BFLNP + Boundary Flag Node Pointer Register + 0x00D4 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + BFL0NP + Boundary Flag y Node Pointer + 0 + 3 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + BFL1NP + Boundary Flag y Node Pointer + 4 + 7 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + BFL2NP + Boundary Flag y Node Pointer + 8 + 11 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + BFL3NP + Boundary Flag y Node Pointer + 12 + 15 + read-write + + + value1 + Select common bondary flag output 0 + #0000 + + + value2 + Select common bondary flag output 3 + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + value5 + Disabled, no common output signal + #1111 + + + + + + + QCTRL0 + Queue 0 Source Control Register + 0x0100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCRESREG + Source-specific Result Register + 0 + 3 + read-write + + + value1 + Use GxCHCTRy.RESREG to select a group result register + #0000 + + + value2 + Store result in group result register GxRES1 + #0001 + + + value3 + Store result in group result register GxRES15 + #1111 + + + + + XTSEL + External Trigger Input Selection + 8 + 11 + read-write + + + XTLVL + External Trigger Level + 12 + 12 + read-only + + + XTMODE + Trigger Operating Mode + 13 + 14 + read-write + + + value1 + No external trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon any edge + #11 + + + + + XTWC + Write Control for Trigger Configuration + 15 + 15 + write-only + + + value1 + No write access to trigger configuration + #0 + + + value2 + Bitfields XTMODE and XTSEL can be written + #1 + + + + + GTSEL + Gate Input Selection + 16 + 19 + read-write + + + GTLVL + Gate Input Level + 20 + 20 + read-only + + + GTWC + Write Control for Gate Configuration + 23 + 23 + write-only + + + value1 + No write access to gate configuration + #0 + + + value2 + Bitfield GTSEL can be written + #1 + + + + + TMEN + Timer Mode Enable + 28 + 28 + read-write + + + value1 + No timer mode: standard gating mechanism can be used + #0 + + + value2 + Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled + #1 + + + + + TMWC + Write Control for Timer Mode + 31 + 31 + write-only + + + value1 + No write access to timer mode + #0 + + + value2 + Bitfield TMEN can be written + #1 + + + + + + + QMR0 + Queue 0 Mode Register + 0x0104 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENGT + Enable Gate + 0 + 1 + read-write + + + value1 + No conversion requests are issued + #00 + + + value2 + Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register + #01 + + + value3 + Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1 + #10 + + + value4 + Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0 + #11 + + + + + ENTR + Enable External Trigger + 2 + 2 + read-write + + + value1 + External trigger disabled + #0 + + + value2 + The selected edge at the selected trigger input signal REQTR generates the trigger event + #1 + + + + + CLRV + Clear Valid Bit + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. + #1 + + + + + TREV + Trigger Event + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Generate a trigger event by software + #1 + + + + + FLUSH + Flush Queue + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry. + #1 + + + + + CEV + Clear Event Flag + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit EV + #1 + + + + + RPTDIS + Repeat Disable + 16 + 16 + read-write + + + value1 + A cancelled conversion is repeated + #0 + + + value2 + A cancelled conversion is discarded + #1 + + + + + + + QSR0 + Queue 0 Status Register + 0x0108 + 32 + 0x00000020 + 0xFFFFFFFF + + + FILL + Filling Level for Queue 2 + 0 + 3 + read-only + + + value1 + There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue + #0000 + + + value2 + There are 2 valid entries in the queue + #0001 + + + value3 + There are 3 valid entries in the queue + #0010 + + + value4 + There are 8 valid entries in the queue + #0111 + + + + + EMPTY + Queue Empty + 5 + 5 + read-only + + + value1 + There are valid entries in the queue (see FILL) + #0 + + + value2 + No valid entries (queue is empty) + #1 + + + + + REQGT + Request Gate Level + 7 + 7 + read-only + + + value1 + The gate input is low + #0 + + + value2 + The gate input is high + #1 + + + + + EV + Event Detected + 8 + 8 + read-only + + + value1 + No trigger event + #0 + + + value2 + A trigger event has been detected + #1 + + + + + + + Q0R0 + Queue 0 Register 0 + 0x010C + 32 + 0x00000000 + 0xFFFFFFFF + + + REQCHNR + Request Channel Number + 0 + 4 + read-only + + + RF + Refill + 5 + 5 + read-only + + + value1 + The request is discarded after the conversion start. + #0 + + + value2 + The request is automatically refilled into the queue after the conversion start. + #1 + + + + + ENSI + Enable Source Interrupt + 6 + 6 + read-only + + + value1 + No request source interrupt + #0 + + + value2 + A request source event interrupt is generated upon a request source event (related conversion is finished) + #1 + + + + + EXTR + External Trigger + 7 + 7 + read-only + + + value1 + A valid queue entry immediately leads to a conversion request + #0 + + + value2 + The request handler waits for a trigger event + #1 + + + + + V + Request Channel Number Valid + 8 + 8 + read-only + + + value1 + No valid queue entry + #0 + + + value2 + The queue entry is valid and leads to a conversion request + #1 + + + + + + + QINR0 + Queue 0 Input Register + 0x0110 + 32 + 0x00000000 + 0xFFFFFFFF + + + REQCHNR + Request Channel Number + 0 + 4 + write-only + + + RF + Refill + 5 + 5 + write-only + + + value1 + No refill: this queue entry is converted once and then invalidated + #0 + + + value2 + Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started + #1 + + + + + ENSI + Enable Source Interrupt + 6 + 6 + write-only + + + value1 + No request source interrupt + #0 + + + value2 + A request source event interrupt is generated upon a request source event (related conversion is finished) + #1 + + + + + EXTR + External Trigger + 7 + 7 + write-only + + + value1 + A valid queue entry immediately leads to a conversion request. + #0 + + + value2 + A valid queue entry waits for a trigger event to occur before issuing a conversion request. + #1 + + + + + + + QBUR0 + Queue 0 Backup Register + QINR0 + 0x0110 + 32 + 0x00000000 + 0xFFFFFFFF + + + REQCHNR + Request Channel Number + 0 + 4 + read-only + + + RF + Refill + 5 + 5 + read-only + + + ENSI + Enable Source Interrupt + 6 + 6 + read-only + + + EXTR + External Trigger + 7 + 7 + read-only + + + V + Request Channel Number Valid + 8 + 8 + read-only + + + value1 + Backup register not valid + #0 + + + value2 + Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested. + #1 + + + + + + + ASCTRL + Autoscan Source Control Register + 0x0120 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCRESREG + Source-specific Result Register + 0 + 3 + read-write + + + value1 + Use GxCHCTRy.RESREG to select a group result register + #0000 + + + value2 + Store result in group result register GxRES1 + #0001 + + + value3 + Store result in group result register GxRES15 + #1111 + + + + + XTSEL + External Trigger Input Selection + 8 + 11 + read-write + + + XTLVL + External Trigger Level + 12 + 12 + read-only + + + XTMODE + Trigger Operating Mode + 13 + 14 + read-write + + + value1 + No external trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon any edge + #11 + + + + + XTWC + Write Control for Trigger Configuration + 15 + 15 + write-only + + + value1 + No write access to trigger configuration + #0 + + + value2 + Bitfields XTMODE and XTSEL can be written + #1 + + + + + GTSEL + Gate Input Selection + 16 + 19 + read-write + + + GTLVL + Gate Input Level + 20 + 20 + read-only + + + GTWC + Write Control for Gate Configuration + 23 + 23 + write-only + + + value1 + No write access to gate configuration + #0 + + + value2 + Bitfield GTSEL can be written + #1 + + + + + TMEN + Timer Mode Enable + 28 + 28 + read-write + + + value1 + No timer mode: standard gating mechanism can be used + #0 + + + value2 + Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled + #1 + + + + + TMWC + Write Control for Timer Mode + 31 + 31 + write-only + + + value1 + No write access to timer mode + #0 + + + value2 + Bitfield TMEN can be written + #1 + + + + + + + ASMR + Autoscan Source Mode Register + 0x0124 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENGT + Enable Gate + 0 + 1 + read-write + + + value1 + No conversion requests are issued + #00 + + + value2 + Conversion requests are issued if at least one pending bit is set + #01 + + + value3 + Conversion requests are issued if at least one pending bit is set and REQGTx = 1. + #10 + + + value4 + Conversion requests are issued if at least one pending bit is set and REQGTx = 0. + #11 + + + + + ENTR + Enable External Trigger + 2 + 2 + read-write + + + value1 + External trigger disabled + #0 + + + value2 + The selected edge at the selected trigger input signal REQTR generates the load event + #1 + + + + + ENSI + Enable Source Interrupt + 3 + 3 + read-write + + + value1 + No request source interrupt + #0 + + + value2 + A request source interrupt is generated upon a request source event (last pending conversion is finished) + #1 + + + + + SCAN + Autoscan Enable + 4 + 4 + read-write + + + value1 + No autoscan + #0 + + + value2 + Autoscan functionality enabled: a request source event automatically generates a load event + #1 + + + + + LDM + Autoscan Source Load Event Mode + 5 + 5 + read-write + + + value1 + Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event + #0 + + + value2 + Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) + #1 + + + + + REQGT + Request Gate Level + 7 + 7 + read-only + + + value1 + The gate input is low + #0 + + + value2 + The gate input is high + #1 + + + + + CLRPND + Clear Pending Bits + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + The bits in register GxASPNDx are cleared + #1 + + + + + LDEV + Generate Load Event + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + A load event is generated + #1 + + + + + RPTDIS + Repeat Disable + 16 + 16 + read-write + + + value1 + A cancelled conversion is repeated + #0 + + + value2 + A cancelled conversion is discarded + #1 + + + + + + + ASSEL + Autoscan Source Channel Select Register + 0x0128 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHSEL0 + Channel Selection + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL1 + Channel Selection + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL2 + Channel Selection + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL3 + Channel Selection + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL4 + Channel Selection + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL5 + Channel Selection + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL6 + Channel Selection + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + CHSEL7 + Channel Selection + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + This channel is part of the scan sequence + #1 + + + + + + + ASPND + Autoscan Source Pending Register + 0x012C + 32 + 0x00000000 + 0xFFFFFFFF + + + CHPND0 + Channels Pending + 0 + 0 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND1 + Channels Pending + 1 + 1 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND2 + Channels Pending + 2 + 2 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND3 + Channels Pending + 3 + 3 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND4 + Channels Pending + 4 + 4 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND5 + Channels Pending + 5 + 5 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND6 + Channels Pending + 6 + 6 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + CHPND7 + Channels Pending + 7 + 7 + read-write + + + value1 + Ignore this channel + #0 + + + value2 + Request conversion of this channel + #1 + + + + + + + CEFLAG + Channel Event Flag Register + 0x0180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CEV0 + Channel Event for Channel 0 + 0 + 0 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV1 + Channel Event for Channel 1 + 1 + 1 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV2 + Channel Event for Channel 2 + 2 + 2 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV3 + Channel Event for Channel 3 + 3 + 3 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV4 + Channel Event for Channel 4 + 4 + 4 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV5 + Channel Event for Channel 5 + 5 + 5 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV6 + Channel Event for Channel 6 + 6 + 6 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + CEV7 + Channel Event for Channel 7 + 7 + 7 + read-write + + + value1 + No channel event + #0 + + + value2 + A channel event has occurred + #1 + + + + + + + REFLAG + Result Event Flag Register + 0x0184 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV0 + Result Event for Result Register 0 + 0 + 0 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV1 + Result Event for Result Register 1 + 1 + 1 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV2 + Result Event for Result Register 2 + 2 + 2 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV3 + Result Event for Result Register 3 + 3 + 3 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV4 + Result Event for Result Register 4 + 4 + 4 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV5 + Result Event for Result Register 5 + 5 + 5 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV6 + Result Event for Result Register 6 + 6 + 6 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV7 + Result Event for Result Register 7 + 7 + 7 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV8 + Result Event for Result Register 8 + 8 + 8 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV9 + Result Event for Result Register 9 + 9 + 9 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV10 + Result Event for Result Register 10 + 10 + 10 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV11 + Result Event for Result Register 11 + 11 + 11 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV12 + Result Event for Result Register 12 + 12 + 12 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV13 + Result Event for Result Register 13 + 13 + 13 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV14 + Result Event for Result Register 14 + 14 + 14 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + REV15 + Result Event for Result Register 15 + 15 + 15 + read-write + + + value1 + No result event + #0 + + + value2 + New result was stored in register GxRESy + #1 + + + + + + + SEFLAG + Source Event Flag Register + 0x0188 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0 + Source Event 0/1 + 0 + 0 + read-write + + + value1 + No source event + #0 + + + value2 + A source event has occurred + #1 + + + + + SEV1 + Source Event 0/1 + 1 + 1 + read-write + + + value1 + No source event + #0 + + + value2 + A source event has occurred + #1 + + + + + + + CEFCLR + Channel Event Flag Clear Register + 0x0190 + 32 + 0x00000000 + 0xFFFFFFFF + + + CEV0 + Clear Channel Event for Channel 0 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV1 + Clear Channel Event for Channel 1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV2 + Clear Channel Event for Channel 2 + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV3 + Clear Channel Event for Channel 3 + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV4 + Clear Channel Event for Channel 4 + 4 + 4 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV5 + Clear Channel Event for Channel 5 + 5 + 5 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV6 + Clear Channel Event for Channel 6 + 6 + 6 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + CEV7 + Clear Channel Event for Channel 7 + 7 + 7 + write-only + + + value1 + No action + #0 + + + value2 + Clear the channel event flag in GxCEFLAG + #1 + + + + + + + REFCLR + Result Event Flag Clear Register + 0x0194 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV0 + Clear Result Event for Result Register 0 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV1 + Clear Result Event for Result Register 1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV2 + Clear Result Event for Result Register 2 + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV3 + Clear Result Event for Result Register 3 + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV4 + Clear Result Event for Result Register 4 + 4 + 4 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV5 + Clear Result Event for Result Register 5 + 5 + 5 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV6 + Clear Result Event for Result Register 6 + 6 + 6 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV7 + Clear Result Event for Result Register 7 + 7 + 7 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV8 + Clear Result Event for Result Register 8 + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV9 + Clear Result Event for Result Register 9 + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV10 + Clear Result Event for Result Register 10 + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV11 + Clear Result Event for Result Register 11 + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV12 + Clear Result Event for Result Register 12 + 12 + 12 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV13 + Clear Result Event for Result Register 13 + 13 + 13 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV14 + Clear Result Event for Result Register 14 + 14 + 14 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + REV15 + Clear Result Event for Result Register 15 + 15 + 15 + write-only + + + value1 + No action + #0 + + + value2 + Clear the result event flag in GxREFLAG + #1 + + + + + + + SEFCLR + Source Event Flag Clear Register + 0x0198 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0 + Clear Source Event 0/1 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear the source event flag in GxSEFLAG + #1 + + + + + SEV1 + Clear Source Event 0/1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear the source event flag in GxSEFLAG + #1 + + + + + + + CEVNP0 + Channel Event Node Pointer Register 0 + 0x01A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CEV0NP + Service Request Node Pointer Channel Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV1NP + Service Request Node Pointer Channel Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV2NP + Service Request Node Pointer Channel Event i + 8 + 11 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV3NP + Service Request Node Pointer Channel Event i + 12 + 15 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV4NP + Service Request Node Pointer Channel Event i + 16 + 19 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV5NP + Service Request Node Pointer Channel Event i + 20 + 23 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV6NP + Service Request Node Pointer Channel Event i + 24 + 27 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + CEV7NP + Service Request Node Pointer Channel Event i + 28 + 31 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + REVNP0 + Result Event Node Pointer Register 0 + 0x01B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV0NP + Service Request Node Pointer Result Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV1NP + Service Request Node Pointer Result Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV2NP + Service Request Node Pointer Result Event i + 8 + 11 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV3NP + Service Request Node Pointer Result Event i + 12 + 15 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV4NP + Service Request Node Pointer Result Event i + 16 + 19 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV5NP + Service Request Node Pointer Result Event i + 20 + 23 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV6NP + Service Request Node Pointer Result Event i + 24 + 27 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV7NP + Service Request Node Pointer Result Event i + 28 + 31 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + REVNP1 + Result Event Node Pointer Register 1 + 0x01B4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV8NP + Service Request Node Pointer Result Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV9NP + Service Request Node Pointer Result Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV10NP + Service Request Node Pointer Result Event i + 8 + 11 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV11NP + Service Request Node Pointer Result Event i + 12 + 15 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV12NP + Service Request Node Pointer Result Event i + 16 + 19 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV13NP + Service Request Node Pointer Result Event i + 20 + 23 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV14NP + Service Request Node Pointer Result Event i + 24 + 27 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + REV15NP + Service Request Node Pointer Result Event i + 28 + 31 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + SEVNP + Source Event Node Pointer Register + 0x01C0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEV0NP + Service Request Node Pointer Source Event i + 0 + 3 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + SEV1NP + Service Request Node Pointer Source Event i + 4 + 7 + read-write + + + value1 + Select service request line 0 of group x + #0000 + + + value2 + Select service request line 3 of group x + #0011 + + + value3 + Select shared service request line 0 + #0100 + + + value4 + Select shared service request line 3 + #0111 + + + + + + + SRACT + Service Request Software Activation Trigger + 0x01C8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AGSR0 + Activate Group Service Request Node 0 + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + AGSR1 + Activate Group Service Request Node 1 + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + AGSR2 + Activate Group Service Request Node 2 + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + AGSR3 + Activate Group Service Request Node 3 + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR0 + Activate Shared Service Request Node 0 + 8 + 8 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR1 + Activate Shared Service Request Node 1 + 9 + 9 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR2 + Activate Shared Service Request Node 2 + 10 + 10 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + ASSR3 + Activate Shared Service Request Node 3 + 11 + 11 + write-only + + + value1 + No action + #0 + + + value2 + Activate the associated service request line + #1 + + + + + + + EMUXCTR + E0ternal Multiplexer Control Register + 0x01F0 + 32 + 0x00000000 + 0xFFFFFFFF + + + EMUXSET + External Multiplexer Start Selection + 0 + 2 + read-write + + + EMUXACT + External Multiplexer Actual Selection + 8 + 10 + read-only + + + EMUXCH + External Multiplexer Channel Select + 16 + 25 + read-write + + + EMUXMODE + External Multiplexer Mode + 26 + 27 + read-write + + + value1 + Software control (no hardware action) + #00 + + + value2 + Steady mode (use EMUXSET value) + #01 + + + value3 + Single-step mode + #10 + + + value4 + Sequence mode + #11 + + + + + EMXCOD + External Multiplexer Coding Scheme + 28 + 28 + read-write + + + value1 + Output the channel number in binary code + #0 + + + value2 + Output the channel number in Gray code + #1 + + + + + EMXST + External Multiplexer Sample Time Control + 29 + 29 + read-write + + + value1 + Use STCE whenever the setting changes + #0 + + + value2 + Use STCE for each conversion of an external channel + #1 + + + + + EMXCSS + External Multiplexer Channel Selection Style + 30 + 30 + read-only + + + value1 + Channel number: Bitfield EMUXCH selects an arbitrary channel + #0 + + + value2 + Channel enable: Each bit of bitfield EMUXCH selects the associated channel for EMUX control + #1 + + + + + EMXWC + Write Control for EMUX Configuration + 31 + 31 + write-only + + + value1 + No write access to EMUX cfg. + #0 + + + value2 + Bitfields EMXMODE, EMXCOD, EMXST, EMXCSS can be written + #1 + + + + + + + VFR + Valid Flag Register + 0x01F8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VF0 + Valid Flag of Result Register x + 0 + 0 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF1 + Valid Flag of Result Register x + 1 + 1 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF2 + Valid Flag of Result Register x + 2 + 2 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF3 + Valid Flag of Result Register x + 3 + 3 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF4 + Valid Flag of Result Register x + 4 + 4 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF5 + Valid Flag of Result Register x + 5 + 5 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF6 + Valid Flag of Result Register x + 6 + 6 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF7 + Valid Flag of Result Register x + 7 + 7 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF8 + Valid Flag of Result Register x + 8 + 8 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF9 + Valid Flag of Result Register x + 9 + 9 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF10 + Valid Flag of Result Register x + 10 + 10 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF11 + Valid Flag of Result Register x + 11 + 11 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF12 + Valid Flag of Result Register x + 12 + 12 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF13 + Valid Flag of Result Register x + 13 + 13 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF14 + Valid Flag of Result Register x + 14 + 14 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + VF15 + Valid Flag of Result Register x + 15 + 15 + read-write + + + value1 + Read access: No new valid data available Write access: No effect + #0 + + + value2 + Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) + #1 + + + + + + + 8 + 4 + CHCTR[%s] + Channel Ctrl. Reg. + 0x0200 + 32 + 0x00000000 + 0xFFFFFFFF + + + ICLSEL + Input Class Select + 0 + 1 + read-write + + + value1 + Use group-specific class 0 + #00 + + + value2 + Use group-specific class 1 + #01 + + + value3 + Use global class 0 + #10 + + + value4 + Use global class 1 + #11 + + + + + BNDSELL + Lower Boundary Select + 4 + 5 + read-write + + + value1 + Use group-specific boundary 0 + #00 + + + value2 + Use group-specific boundary 1 + #01 + + + value3 + Use global boundary 0 + #10 + + + value4 + Use global boundary 1 + #11 + + + + + BNDSELU + Upper Boundary Select + 6 + 7 + read-write + + + value1 + Use group-specific boundary 0 + #00 + + + value2 + Use group-specific boundary 1 + #01 + + + value3 + Use global boundary 0 + #10 + + + value4 + Use global boundary 1 + #11 + + + + + CHEVMODE + Channel Event Mode + 8 + 9 + read-write + + + value1 + Never + #00 + + + value2 + NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) + #01 + + + value3 + NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) + #10 + + + value4 + NCM: Always (ignore band) FCM: If result switches to either level + #11 + + + + + SYNC + Synchronization Request + 10 + 10 + read-write + + + value1 + No synchroniz. request, standalone operation + #0 + + + value2 + Request a synchronized conversion of this channel (only taken into account for a master) + #1 + + + + + REFSEL + Reference Input Selection + 11 + 11 + read-write + + + value1 + Standard reference input VAREF + #0 + + + value2 + Alternate reference input from CH0 + #1 + + + + + RESREG + Result Register + 16 + 19 + read-write + + + value1 + Store result in group result register GxRES0 + #0000 + + + value2 + Store result in group result register GxRES15 + #1111 + + + + + RESTBS + Result Target for Background Source + 20 + 20 + read-write + + + value1 + Store results in the selected group result register + #0 + + + value2 + Store results in the global result register + #1 + + + + + RESPOS + Result Position + 21 + 21 + read-write + + + value1 + Store results left-aligned + #0 + + + value2 + Store results right-aligned + #1 + + + + + BWDCH + Broken Wire Detection Channel + 28 + 29 + read-write + + + value1 + Select VAGND + #00 + + + value2 + Select VAREF + #01 + + + + + BWDEN + Broken Wire Detection Enable + 30 + 30 + read-write + + + value1 + Normal operation + #0 + + + value2 + Additional preparation phase is enabled + #1 + + + + + + + 16 + 4 + RCR[%s] + Result Control Register + 0x0280 + 32 + 0x00000000 + 0xFFFFFFFF + + + DRCTR + Data Reduction Control + 16 + 19 + read-write + + + DMM + Data Modification Mode + 20 + 21 + read-write + + + value1 + Standard data reduction (accumulation) + #00 + + + value2 + Result filtering mode + #01 + + + value3 + Difference mode + #10 + + + + + WFR + Wait-for-Read Mode Enable + 24 + 24 + read-write + + + value1 + Overwrite mode + #0 + + + value2 + Wait-for-read mode enabled for this register + #1 + + + + + FEN + FIFO Mode Enable + 25 + 26 + read-write + + + value1 + Separate result register + #00 + + + value2 + Part of a FIFO structure: copy each new valid result + #01 + + + + + SRGEN + Service Request Generation Enable + 31 + 31 + read-write + + + value1 + No service request + #0 + + + value2 + Service request after a result event + #1 + + + + + + + 16 + 4 + RES[%s] + Result Register + 0x0300 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + RESULT + Result of Most Recent Conversion + 0 + 15 + read-write + + + DRC + Data Reduction Counter + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + value1 + Request source 0 + #00 + + + value2 + Request source 1 + #01 + + + value3 + Request source 2 + #10 + + + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-only + + + value1 + No new result available + #0 + + + value2 + Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated + #1 + + + + + + + 16 + 4 + RESD[%s] + Result Register, Debug + 0x0380 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of Most Recent Conversion + 0 + 15 + read-only + + + DRC + Data Reduction Counter + 16 + 19 + read-only + + + CHNR + Channel Number + 20 + 24 + read-only + + + EMUX + External Multiplexer Setting + 25 + 27 + read-only + + + CRS + Converted Request Source + 28 + 29 + read-only + + + value1 + Request source 0 + #00 + + + value2 + Request source 1 + #01 + + + value3 + Request source 2 + #10 + + + + + FCR + Fast Compare Result + 30 + 30 + read-only + + + value1 + Signal level was below compare value + #0 + + + value2 + Signal level was above compare value + #1 + + + + + VF + Valid Flag + 31 + 31 + read-only + + + value1 + No new result available + #0 + + + value2 + Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated + #1 + + + + + + + + + VADC_G1 + Analog to Digital Converter + VADC + 0x40004800 + + 0x0 + 0x400 + registers + + + VADC0_G1_0 + Analog to Digital Converter Group 1 + 22 + + + VADC0_G1_1 + Analog to Digital Converter Group 1 + 23 + + + VADC0_G1_2 + Analog to Digital Converter Group 1 + 24 + + + VADC0_G1_3 + Analog to Digital Converter Group 1 + 25 + + + + VADC_G2 + Analog to Digital Converter + VADC + 0x40004C00 + + 0x0 + 0x400 + registers + + + VADC0_G2_0 + Analog to Digital Converter Group 2 + 26 + + + VADC0_G2_1 + Analog to Digital Converter Group 2 + 27 + + + VADC0_G2_2 + Analog to Digital Converter Group 2 + 28 + + + VADC0_G2_3 + Analog to Digital Converter Group 2 + 29 + + + + VADC_G3 + Analog to Digital Converter + VADC + 0x40005000 + + 0x0 + 0x400 + registers + + + VADC0_G3_0 + Analog to Digital Converter Group 3 + 30 + + + VADC0_G3_1 + Analog to Digital Converter Group 3 + 31 + + + VADC0_G3_2 + Analog to Digital Converter Group 3 + 32 + + + VADC0_G3_3 + Analog to Digital Converter Group 3 + 33 + + + + DSD + Delta Sigma Demodulator + DSD + 0x40008000 + + 0x0 + 0x100 + registers + + + + CLC + Clock Control Register + 0x0000 + 32 + 0x00000003 + 0xFFFFFFFF + + + DISR + Module Disable Request Bit + 0 + 0 + read-write + + + value1 + On request: enable the module clock + #0 + + + value2 + Off request: stop the module clock + #1 + + + + + DISS + Module Disable Status Bit + 1 + 1 + read-only + + + value1 + Module clock is enabled + #0 + + + value2 + Off: module is not clocked + #1 + + + + + EDIS + Sleep Mode Enable Control + 3 + 3 + read-write + + + value1 + Sleep mode request is enabled and functional + #0 + + + value2 + Module disregards the sleep mode control signal + #1 + + + + + + + ID + Module Identification Register + 0x0008 + 32 + 0x00A4C000 + 0xFFFFFF00 + + + MOD_REV + Module Revision + 0 + 7 + read-only + + + MOD_TYPE + Module Type + 8 + 15 + read-only + + + MOD_NUMBER + Module Number + 16 + 31 + read-only + + + + + OCS + OCDS Control and Status Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUS + OCDS Suspend Control + 24 + 27 + read-write + + + value1 + Will not suspend + #0000 + + + value2 + Hard suspend: Clock is switched off immediately. + #0001 + + + value3 + Soft suspend channel 0 + #0010 + + + value4 + Soft suspend channel 1 + #0011 + + + value5 + Soft suspend channel 3 + #0101 + + + + + SUS_P + SUS Write Protection + 28 + 28 + write-only + + + SUSSTA + Suspend State + 29 + 29 + read-only + + + value1 + Module is not (yet) suspended + #0 + + + value2 + Module is suspended + #1 + + + + + + + GLOBCFG + Global Configuration Register + 0x0080 + 32 + 0x00000000 + 0xFFFFFFFF + + + MCSEL + Modulator Clock Select + 0 + 2 + read-write + + + value1 + Internal clock off, no source selected + #000 + + + value2 + fDSD + #001 + + + + + + + GLOBRC + Global Run Control Register + 0x0088 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH0RUN + Channel 0 Run Control + 0 + 0 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + CH1RUN + Channel 1 Run Control + 1 + 1 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + CH2RUN + Channel 2 Run Control + 2 + 2 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + CH3RUN + Channel 3 Run Control + 3 + 3 + read-write + + + value1 + Stop channel x + #0 + + + value2 + Demodulator channel x is enabled and runs + #1 + + + + + + + CGCFG + Carrier Generator Configuration Register + 0x00A0 + 32 + 0x07100000 + 0xFFFFFFFF + + + CGMOD + Carrier Generator Operating Mode + 0 + 1 + read-write + + + value1 + Stopped + #00 + + + value2 + Square wave + #01 + + + value3 + Triangle + #10 + + + value4 + Sine wave + #11 + + + + + BREV + Bit-Reverse PWM Generation + 2 + 2 + read-write + + + value1 + Normal mode + #0 + + + value2 + Bit-reverse mode + #1 + + + + + SIGPOL + Signal Polarity + 3 + 3 + read-write + + + value1 + Normal: carrier signal begins with +1 + #0 + + + value2 + Inverted: carrier signal begins with -1 + #1 + + + + + DIVCG + Divider Factor for the PWM Pattern Signal Generator + 4 + 7 + read-write + + + value1 + fCG = fCLK / 2 + 0x0 + + + value2 + fCG = fCLK / 4 + 0x1 + + + value3 + fCG = fCLK / 6 + 0x2 + + + value4 + fCG = fCLK / 32 + 0xF + + + + + RUN + Run Indicator + 15 + 15 + read-only + + + value1 + Stopped (cleared at the end of a period) + #0 + + + value2 + Running + #1 + + + + + BITCOUNT + Bit Counter + 16 + 20 + read-only + + + STEPCOUNT + Step Counter + 24 + 27 + read-only + + + STEPS + Step Counter Sign + 28 + 28 + read-only + + + value1 + Step counter value is positive + #0 + + + value2 + Step counter value is negative + #1 + + + + + STEPD + Step Counter Direction + 29 + 29 + read-only + + + value1 + Step counter is counting up + #0 + + + value2 + Step counter is counting down + #1 + + + + + SGNCG + Sign Signal from Carrier Generator + 30 + 30 + read-only + + + value1 + Positive values + #0 + + + value2 + Negative values + #1 + + + + + + + EVFLAG + Event Flag Register + 0x00E0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESEV0 + Result Event + 0 + 0 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + RESEV1 + Result Event + 1 + 1 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + RESEV2 + Result Event + 2 + 2 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + RESEV3 + Result Event + 3 + 3 + read-write + + + value1 + No result event + #0 + + + value2 + A new result has been stored in register RESMx + #1 + + + + + ALEV0 + Alarm Event + 16 + 16 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + ALEV1 + Alarm Event + 17 + 17 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + ALEV2 + Alarm Event + 18 + 18 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + ALEV3 + Alarm Event + 19 + 19 + read-write + + + value1 + No alarm event + #0 + + + value2 + An alarm event has occurred + #1 + + + + + + + EVFLAGCLR + Event Flag Clear Register + 0x00E4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESEC0 + Result Event Clear + 0 + 0 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + RESEC1 + Result Event Clear + 1 + 1 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + RESEC2 + Result Event Clear + 2 + 2 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + RESEC3 + Result Event Clear + 3 + 3 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit RESEVx + #1 + + + + + ALEC0 + Alarm Event Clear + 16 + 16 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + ALEC1 + Alarm Event Clear + 17 + 17 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + ALEC2 + Alarm Event Clear + 18 + 18 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + ALEC3 + Alarm Event Clear + 19 + 19 + write-only + + + value1 + No action + #0 + + + value2 + Clear bit ALEVx + #1 + + + + + + + + + DSD_CH0 + Delta Sigma Demodulator + DSD + DSD_CH + 0x40008100 + + 0x0 + 0x100 + registers + + + DSD0_M_0 + Delta Sigma Demodulator Main + 34 + + + DSD0_A_4 + Delta Sigma Demodulator Auxiliary + 38 + + + + MODCFG + Modulator Configuration Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIVM + Divider Factor for Modulator Clock + 16 + 19 + read-write + + + value1 + fMOD = fCLK / 2 + 0x0 + + + value2 + fMOD = fCLK / 4 + 0x1 + + + value3 + fMOD = fCLK / 6 + 0x2 + + + value4 + fMOD = fCLK / 32 + 0xF + + + + + DWC + Write Control for Divider Factor + 23 + 23 + write-only + + + value1 + No write access to divider factor + #0 + + + value2 + Bitfield DIVM can be written + #1 + + + + + + + DICFG + Demodulator Input Configuration Register + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSRC + Input Data Source Select + 0 + 3 + read-write + + + value1 + Disconnected + #000X + + + value2 + External, from input A, direct + #0010 + + + value3 + External, from input A, inverted + #0011 + + + value4 + External, from input B, direct + #0100 + + + value5 + External, from input B, inverted + #0101 + + + + + DSWC + Write Control for Data Selection + 7 + 7 + write-only + + + value1 + No write access to data parameters + #0 + + + value2 + Bitfield DSRC can be written + #1 + + + + + ITRMODE + Integrator Trigger Mode + 8 + 9 + read-write + + + value1 + No integration trigger, integrator bypassed, INTEN = 0 all the time + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + No trigger, integrator active all the time, INTEN = 1 all the time + #11 + + + + + TSTRMODE + Timestamp Trigger Mode + 10 + 11 + read-write + + + value1 + No timestamp trigger + #00 + + + value2 + Trigger event upon a falling edge + #01 + + + value3 + Trigger event upon a rising edge + #10 + + + value4 + Trigger event upon each edge + #11 + + + + + TRSEL + Trigger Select + 12 + 14 + read-write + + + TRWC + Write Control for Trigger Parameters + 15 + 15 + write-only + + + value1 + No write access to trigger parameters + #0 + + + value2 + Bitfields TRSEL, TSTRMODE, ITRMODE can be written + #1 + + + + + CSRC + Sample Clock Source Select + 16 + 19 + read-write + + + value2 + External, from input A + #0001 + + + value3 + External, from input B + #0010 + + + value4 + External, from input C + #0011 + + + value5 + External, from input D + #0100 + + + value6 + Internal clock + #1111 + + + + + STROBE + Data Strobe Generatoion Mode + 20 + 23 + read-write + + + value1 + No data strobe + #0000 + + + value2 + Direct clock, a sample trigger is generated at each rising clock edge + #0001 + + + value3 + Direct clock, a sample trigger is generated at each falling clock edge + #0010 + + + value4 + Double data, a sample trigger is generated at each rising and falling clock edge + #0011 + + + value6 + Double clock, a sample trigger is generated at every 2nd rising clock edge + #0101 + + + value7 + Double clock, a sample trigger is generated at every 2nd falling clock edge + #0110 + + + + + SCWC + Write Control for Strobe/Clock Selection + 31 + 31 + write-only + + + value1 + No write access to strobe/clock parameters + #0 + + + value2 + Bitfields STROBE, CSRC can be written + #1 + + + + + + + FCFGC + Filter Configuration Register, Main CIC Filter + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFMDF + CIC Filter (Main Chain) Decimation Factor + 0 + 7 + read-write + + + CFMC + CIC Filter (Main Chain) Configuration + 8 + 9 + read-write + + + value1 + CIC1 + #00 + + + value2 + CIC2 + #01 + + + value3 + CIC3 + #10 + + + value4 + CICF + #11 + + + + + CFEN + CIC Filter Enable + 10 + 10 + read-write + + + value1 + CIC filter disabled and bypassed + #0 + + + value2 + Enable CIC filter + #1 + + + + + SRGM + Service Request Generation Main Chain + 14 + 15 + read-write + + + value1 + Never, service requests disabled + #00 + + + value4 + Always, for each new result value + #11 + + + + + CFMSV + CIC Filter (Main Chain) Start Value + 16 + 23 + read-write + + + CFMDCNT + CIC Filter (Main Chain) Decimation Counter + 24 + 31 + read-only + + + + + FCFGA + Filter Configuration Register, Auxiliary Filter + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFADF + CIC Filter (Auxiliary) Decimation Factor + 0 + 7 + read-write + + + CFAC + CIC Filter (Auxiliary) Configuration + 8 + 9 + read-write + + + value1 + CIC1 + #00 + + + value2 + CIC2 + #01 + + + value3 + CIC3 + #10 + + + value4 + CICF + #11 + + + + + SRGA + Service Request Generation Auxiliary Filter + 10 + 11 + read-write + + + value1 + Never, service requests disabled + #00 + + + value2 + Auxiliary filter: As selected by bitfields ESEL and EGT (if integrator enabled) + #01 + + + value3 + Alternate source: Capturing of a sign delay value to register CGSYNCx (x = 0 - 3) + #10 + + + + + ESEL + Event Select + 12 + 13 + read-write + + + value1 + Always, for each new result value + #00 + + + value2 + If result is inside the boundary band + #01 + + + value3 + If result is outside the boundary band + #10 + + + + + EGT + Event Gating + 14 + 14 + read-write + + + value1 + Separate: generate events according to ESEL + #0 + + + value2 + Coupled: generate events only when the integrator is enabled and after the discard phase defined by bitfield NVALDISWhile the integrator is bypassed, event gating is disabled, i.e. service requests are generated according to bitfield ESEL. The event gating suppresses service requests, result values are still stored in register RESAx. + #1 + + + + + CFADCNT + CIC Filter (Auxiliary) Decimation Counter + 24 + 31 + read-only + + + + + IWCTR + Integration Window Control Register + 0x0020 + 32 + 0x00000000 + 0xFFFFFFFF + + + NVALCNT + Number of Values Counted + 0 + 5 + read-only + + + INTEN + Integration Enable + 7 + 7 + read-only + + + value1 + Integration stopped. INTEN is cleared at the end of the integration window, i.e. upon the inverse trigger event transition of the external trigger signal. + #0 + + + value2 + Integration enabled. INTEN is set upon the defined trigger event. + #1 + + + + + REPCNT + Integration Cycle Counter + 8 + 11 + read-only + + + REPVAL + Number of Integration Cycles + 12 + 15 + read-write + + + NVALDIS + Number of Values Discarded + 16 + 21 + read-write + + + IWS + Integration Window SIze + 23 + 23 + read-write + + + value1 + Internal control: stop integrator after REPVAL+1 integration cycles + #0 + + + value2 + External control: stop integrator when bit INTEN becomes 0 + #1 + + + + + NVALINT + Number of Values Integrated + 24 + 29 + read-write + + + + + BOUNDSEL + Boundary Select Register + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + BOUNDARYL + Lower Boundary Value for Limit Checking + 0 + 15 + read-write + + + BOUNDARYU + Upper Boundary Value for Limit Checking + 16 + 31 + read-write + + + + + RESM + Result Register, Main Filter + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-only + + + + + OFFM + Offset Register, Main Filter + 0x0038 + 32 + 0x00000000 + 0xFFFFFFFF + + + OFFSET + Offset Value + 0 + 15 + read-write + + + + + RESA + Result Register, Auxiliary Filter + 0x0040 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-only + + + + + TSTMP + Time-Stamp Register + 0x0050 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + Result of most recent conversion + 0 + 15 + read-only + + + CFMDCNT + CIC Filter (Main Chain) Decimation Counter + 16 + 23 + read-only + + + NVALCNT + Number of Values Counted + 24 + 29 + read-only + + + + + CGSYNC + Carrier Generator Synchronization Register + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SDCOUNT + Sign Delay Counter + 0 + 7 + read-only + + + SDCAP + Sign Delay Capture Value + 8 + 15 + read-only + + + SDPOS + Sign Delay Value for Positive Halfwave + 16 + 23 + read-write + + + SDNEG + Sign Delay Value for Negative Halfwave + 24 + 31 + read-write + + + + + RECTCFG + Rectification Configuration Register + 0x00A8 + 32 + 0x80000000 + 0xFFFFFFFF + + + RFEN + Rectification Enable + 0 + 0 + read-write + + + value1 + No rectification, data not altered + #0 + + + value2 + Data are rectified according to SGND + #1 + + + + + SSRC + Sign Source + 4 + 5 + read-write + + + value1 + On-chip carrier generator + #00 + + + value2 + Sign of result of next channel + #01 + + + value3 + External sign signal A + #10 + + + value4 + External sign signal B + #11 + + + + + SDVAL + Valid Flag + 15 + 15 + read-only + + + value1 + No new result available + #0 + + + value2 + Bitfield SDCAP has been updated with a new captured value and has not yet been read + #1 + + + + + SGNCS + Selected Carrier Sign Signal + 30 + 30 + read-only + + + value1 + Positive values + #0 + + + value2 + Negative values + #1 + + + + + SGND + Sign Signal Delayed + 31 + 31 + read-only + + + value1 + Positive values + #0 + + + value2 + Negative values + #1 + + + + + + + + + DSD_CH1 + Delta Sigma Demodulator + DSD + 0x40008200 + + 0x0 + 0x100 + registers + + + DSD0_M_1 + Delta Sigma Demodulator Main + 35 + + + DSD0_A_5 + Delta Sigma Demodulator Auxiliary + 39 + + + + DSD_CH2 + Delta Sigma Demodulator + DSD + 0x40008300 + + 0x0 + 0x100 + registers + + + DSD0_M_2 + Delta Sigma Demodulator Main + 36 + + + DSD0_A_6 + Delta Sigma Demodulator Auxiliary + 40 + + + + DSD_CH3 + Delta Sigma Demodulator + DSD + 0x40008400 + + 0x0 + 0x100 + registers + + + DSD0_M_3 + Delta Sigma Demodulator Main + 37 + + + DSD0_A_7 + Delta Sigma Demodulator Auxiliary + 41 + + + + DAC + Digital to Analog Converter + 0x48018000 + + 0x0 + 0x4000 + registers + + + DAC0_0 + Digital to Analog Converter + 42 + + + DAC0_1 + Digital to Analog Converter + 43 + + + + ID + Module Identification Register + 0x000 + 32 + 0x00A5C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + DAC0CFG0 + DAC0 Configuration Register 0 + 0x004 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQ + Integer Frequency Divider Value + 0 + 19 + read-write + + + MODE + Enables and Sets the Mode for DAC0 + 20 + 22 + read-write + + + value1 + disable/switch-off DAC + #000 + + + value2 + Single Value Mode + #001 + + + value3 + Data Mode + #010 + + + value4 + Patgen Mode + #011 + + + value5 + Noise Mode + #100 + + + value6 + Ramp Mode + #101 + + + value7 + na + #110 + + + value8 + na + #111 + + + + + SIGN + Selects Between Signed and Unsigned DAC0 Mode + 23 + 23 + read-write + + + value1 + DAC expects unsigned input data + #0 + + + value2 + DAC expects signed input data + #1 + + + + + FIFOIND + Current write position inside the data FIFO + 24 + 25 + read-only + + + FIFOEMP + Indicate if the FIFO is empty + 26 + 26 + read-only + + + value1 + FIFO not empty + #0 + + + value2 + FIFO empty + #1 + + + + + FIFOFUL + Indicate if the FIFO is full + 27 + 27 + read-only + + + value1 + FIFO not full + #0 + + + value2 + FIFO full + #1 + + + + + NEGATE + Negates the DAC0 output + 28 + 28 + read-write + + + value1 + DAC output not negated + #0 + + + value2 + DAC output negated + #1 + + + + + SIGNEN + Enable Sign Output of DAC0 Pattern Generator + 29 + 29 + read-write + + + value1 + Disable + #0 + + + value2 + Enable + #1 + + + + + SREN + Enable DAC0 service request interrupt generation + 30 + 30 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + RUN + RUN indicates the current DAC0 operation status + 31 + 31 + read-only + + + value1 + DAC0 channel disabled + #0 + + + value2 + DAC0 channel in operation + #1 + + + + + + + DAC0CFG1 + DAC0 Configuration Register 1 + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCALE + Scale value for up- or downscale of the DAC0 input data in steps by the power of 2 (=shift operation) + 0 + 2 + read-write + + + value1 + no shift = multiplication/division by 1 + #000 + + + value2 + shift by 1 = multiplication/division by 2 + #001 + + + value3 + shift by 2 = multiplication/division by 4 + #010 + + + value4 + shift left by 3 = multiplication/division by 8 + #011 + + + value5 + shift left by 4 = multiplication/division by 16 + #100 + + + value6 + shift left by 5 = multiplication/division by 32 + #101 + + + value7 + shift left by 6 = multiplication/division by 64 + #110 + + + value8 + shift left by 7 = multiplication/division by 128 + #111 + + + + + MULDIV + Switch between up- and downscale of the DAC0 input data values + 3 + 3 + read-write + + + value1 + downscale = division (shift SCALE positions to the right) + #0 + + + value2 + upscale = multiplication (shift SCALE positions to the left) + #1 + + + + + OFFS + 8-bit offset value addition + 4 + 11 + read-write + + + TRIGSEL + Selects one of the eight external trigger sources for DAC0 + 12 + 14 + read-write + + + DATMOD + Switch between independent or simultaneous DAC mode and select the input data register for DAC0 and DAC1 + 15 + 15 + read-write + + + value1 + independent data handling - process data from DATA0 register (bits 11:0) to DAC0 and data from DATA1 register (bits 11:0) to DAC1 + #0 + + + value2 + simultaneous data handling - process data from DAC01 register to both DACs (bits 11:0 to DAC0 and bits 23:12 to DAC1). + #1 + + + + + SWTRIG + Software Trigger + 16 + 16 + read-write + + + TRIGMOD + Select the trigger source for channel 0 + 17 + 18 + read-write + + + value1 + internal Trigger (integer divided clock - see FREQ parameter) + #00 + + + value2 + external Trigger (preselected trigger by TRIGSEL parameter) + #01 + + + value3 + software Trigger (see SWTRIG parameter) + #10 + + + + + ANACFG + DAC0 analog configuration/calibration parameters + 19 + 23 + read-write + + + ANAEN + Enable analog DAC for channel 0 + 24 + 24 + read-write + + + value1 + DAC0 is set to standby (analog output only) + #0 + + + value2 + enable DAC0 (analog output only) + #1 + + + + + REFCFGL + Lower 4 band-gap configuration/calibration parameters + 28 + 31 + read-write + + + + + DAC1CFG0 + DAC1 Configuration Register 0 + 0x00C + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQ + Integer Frequency Divider Value + 0 + 19 + read-write + + + MODE + Enables and sets the Mode for DAC1 + 20 + 22 + read-write + + + value1 + disable/switch-off DAC + #000 + + + value2 + Single Value Mode + #001 + + + value3 + Data Mode + #010 + + + value4 + Patgen Mode + #011 + + + value5 + Noise Mode + #100 + + + value6 + Ramp Mode + #101 + + + value7 + na + #110 + + + value8 + na + #111 + + + + + SIGN + Selects between signed and unsigned DAC1 mode + 23 + 23 + read-write + + + value1 + DAC expects unsigned input data + #0 + + + value2 + DAC expects signed input data + #1 + + + + + FIFOIND + Current write position inside the data FIFO + 24 + 25 + read-only + + + FIFOEMP + Indicate if the FIFO is empty + 26 + 26 + read-only + + + value1 + FIFO not empty + #0 + + + value2 + FIFO empty + #1 + + + + + FIFOFUL + Indicate if the FIFO is full + 27 + 27 + read-only + + + value1 + FIFO not full + #0 + + + value2 + FIFO full + #1 + + + + + NEGATE + Negates the DAC1 output + 28 + 28 + read-write + + + value1 + DAC output not negated + #0 + + + value2 + DAC output negated + #1 + + + + + SIGNEN + Enable sign output of DAC1 pattern generator + 29 + 29 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + SREN + Enable DAC1 service request interrupt generation + 30 + 30 + read-write + + + value1 + disable + #0 + + + value2 + enable + #1 + + + + + RUN + RUN indicates the current DAC1 operation status + 31 + 31 + read-only + + + value1 + DAC1 channel disabled + #0 + + + value2 + DAC1 channel in operation + #1 + + + + + + + DAC1CFG1 + DAC1 Configuration Register 1 + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCALE + Scale value for up- or downscale of the DAC1 input data in steps by the power of 2 (=shift operation) + 0 + 2 + read-write + + + value1 + no shift = multiplication/division by 1 + #000 + + + value2 + shift by 1 = multiplication/division by 2 + #001 + + + value3 + shift by 2 = multiplication/division by 4 + #010 + + + value4 + shift left by 3 = multiplication/division by 8 + #011 + + + value5 + shift left by 4 = multiplication/division by 16 + #100 + + + value6 + shift left by 5 = multiplication/division by 32 + #101 + + + value7 + shift left by 6 = multiplication/division by 64 + #110 + + + value8 + shift left by 7 = multiplication/division by 128 + #111 + + + + + MULDIV + Switch between up- and downscale of the DAC1 input data values + 3 + 3 + read-write + + + value1 + downscale = division (shift SCALE positions to the right) + #0 + + + value2 + upscale = multiplication (shift SCALE positions to the left) + #1 + + + + + OFFS + 8-bit offset value addition + 4 + 11 + read-write + + + TRIGSEL + Selects one of the eight external trigger sources for DAC1 + 12 + 14 + read-write + + + SWTRIG + Software Trigger + 16 + 16 + read-write + + + TRIGMOD + Select the trigger source for channel 1 + 17 + 18 + read-write + + + value1 + internal Trigger (integer divided clock - see FREQ parameter) + #00 + + + value2 + external Trigger (preselected trigger by TRIGSEL parameter) + #01 + + + value3 + software Trigger (see SWTRIG parameter) + #10 + + + + + ANACFG + DAC1 analog configuration/calibration parameters + 19 + 23 + read-write + + + ANAEN + Enable analog DAC for channel 1 + 24 + 24 + read-write + + + value1 + DAC1 is set to standby (analog output only) + #0 + + + value2 + enable DAC1 (analog output only) + #1 + + + + + REFCFGH + Higher 4 band-gap configuration/calibration parameters + 28 + 31 + read-write + + + + + DAC0DATA + DAC0 Data Register + 0x014 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA0 + DAC0 Data Bits + 0 + 11 + read-write + + + + + DAC1DATA + DAC1 Data Register + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA1 + DAC1 Data Bits + 0 + 11 + read-write + + + + + DAC01DATA + DAC01 Data Register + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA0 + DAC0 Data Bits + 0 + 11 + read-write + + + DATA1 + DAC1 Data Bits + 16 + 27 + read-write + + + + + DAC0PATL + DAC0 Lower Pattern Register + 0x020 + 32 + 0x3568B0C0 + 0xFFFFFFFF + + + PAT0 + Pattern Number 0 for PATGEN of DAC0 + 0 + 4 + read-write + + + PAT1 + Pattern Number 1 for PATGEN of DAC0 + 5 + 9 + read-write + + + PAT2 + Pattern Number 2 for PATGEN of DAC0 + 10 + 14 + read-write + + + PAT3 + Pattern Number 3 for PATGEN of DAC0 + 15 + 19 + read-write + + + PAT4 + Pattern Number 4 for PATGEN of DAC0 + 20 + 24 + read-write + + + PAT5 + Pattern Number 5 for PATGEN of DAC0 + 25 + 29 + read-write + + + + + DAC0PATH + DAC0 Higher Pattern Register + 0x024 + 32 + 0x00007FDD + 0xFFFFFFFF + + + PAT6 + Pattern Number 6 for PATGEN of DAC0 + 0 + 4 + read-write + + + PAT7 + Pattern Number 7 for PATGEN of DAC0 + 5 + 9 + read-write + + + PAT8 + Pattern Number 8 for PATGEN of DAC0 + 10 + 14 + read-write + + + + + DAC1PATL + DAC1 Lower Pattern Register + 0x028 + 32 + 0x3568B0C0 + 0xFFFFFFFF + + + PAT0 + Pattern Number 0 for PATGEN of DAC1 + 0 + 4 + read-write + + + PAT1 + Pattern Number 1 for PATGEN of DAC1 + 5 + 9 + read-write + + + PAT2 + Pattern Number 2 for PATGEN of DAC1 + 10 + 14 + read-write + + + PAT3 + Pattern Number 3 for PATGEN of DAC1 + 15 + 19 + read-write + + + PAT4 + Pattern Number 4 for PATGEN of DAC1 + 20 + 24 + read-write + + + PAT5 + Pattern Number 5 for PATGEN of DAC1 + 25 + 29 + read-write + + + + + DAC1PATH + DAC1 Higher Pattern Register + 0x02C + 32 + 0x00007FDD + 0xFFFFFFFF + + + PAT6 + Pattern Number 6 for PATGEN of DAC1 + 0 + 4 + read-write + + + PAT7 + Pattern Number 7 for PATGEN of DAC1 + 5 + 9 + read-write + + + PAT8 + Pattern Number 8 for PATGEN of DAC1 + 10 + 14 + read-write + + + + + + + CCU40 + Capture Compare Unit 4 - Unit 0 + CCU4 + CCU4 + 0x4000C000 + + 0x0 + 0x100 + registers + + + CCU40_0 + Capture Compare Unit 4 (Module 0) + 44 + + + CCU40_1 + Capture Compare Unit 4 (Module 0) + 45 + + + CCU40_2 + Capture Compare Unit 4 (Module 0) + 46 + + + CCU40_3 + Capture Compare Unit 4 (Module 0) + 47 + + + + GCTRL + Global Control Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRBC + Prescaler Clear Configuration + 0 + 2 + read-write + + + value1 + SW only + #000 + + + value2 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared. + #001 + + + value3 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared. + #010 + + + value4 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared. + #011 + + + value5 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared. + #100 + + + + + PCIS + Prescaler Input Clock Selection + 4 + 5 + read-write + + + value1 + Module clock + #00 + + + value2 + CCU4x.ECLKA + #01 + + + value3 + CCU4x.ECLKB + #10 + + + value4 + CCU4x.ECLKC + #11 + + + + + SUSCFG + Suspend Mode Configuration + 8 + 9 + read-write + + + value1 + Suspend request ignored. The module never enters in suspend + #00 + + + value2 + Stops all the running slices immediately. Safe stop is not applied. + #01 + + + value3 + Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. + #10 + + + value4 + Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. + #11 + + + + + MSE0 + Slice 0 Multi Channel shadow transfer enable + 10 + 10 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSE1 + Slice 1 Multi Channel shadow transfer enable + 11 + 11 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSE2 + Slice 2 Multi Channel shadow transfer enable + 12 + 12 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSE3 + Slice 3 Multi Channel shadow transfer enable + 13 + 13 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU4x.MCSS input. + #1 + + + + + MSDE + Multi Channel shadow transfer request configuration + 14 + 15 + read-write + + + value1 + Only the shadow transfer for period and compare values is requested + #00 + + + value2 + Shadow transfer for the compare, period and prescaler compare values is requested + #01 + + + value4 + Shadow transfer for the compare, period, prescaler and dither compare values is requested + #11 + + + + + + + GSTAT + Global Status Register + 0x0004 + 32 + 0x0000000F + 0xFFFFFFFF + + + S0I + CC40 IDLE status + 0 + 0 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S1I + CC41 IDLE status + 1 + 1 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S2I + CC42 IDLE status + 2 + 2 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S3I + CC43 IDLE status + 3 + 3 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + PRB + Prescaler Run Bit + 8 + 8 + read-only + + + value1 + Prescaler is stopped + #0 + + + value2 + Prescaler is running + #1 + + + + + + + GIDLS + Global Idle Set + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SS0I + CC40 IDLE mode set + 0 + 0 + write-only + + + SS1I + CC41 IDLE mode set + 1 + 1 + write-only + + + SS2I + CC42 IDLE mode set + 2 + 2 + write-only + + + SS3I + CC43 IDLE mode set + 3 + 3 + write-only + + + CPRB + Prescaler Run Bit Clear + 8 + 8 + write-only + + + PSIC + Prescaler clear + 9 + 9 + write-only + + + + + GIDLC + Global Idle Clear + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + CS0I + CC40 IDLE mode clear + 0 + 0 + write-only + + + CS1I + CC41 IDLE mode clear + 1 + 1 + write-only + + + CS2I + CC42 IDLE mode clear + 2 + 2 + write-only + + + CS3I + CC43 IDLE mode clear + 3 + 3 + write-only + + + SPRB + Prescaler Run Bit Set + 8 + 8 + write-only + + + + + GCSS + Global Channel Set + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SE + Slice 0 shadow transfer set enable + 0 + 0 + write-only + + + S0DSE + Slice 0 Dither shadow transfer set enable + 1 + 1 + write-only + + + S0PSE + Slice 0 Prescaler shadow transfer set enable + 2 + 2 + write-only + + + S1SE + Slice 1 shadow transfer set enable + 4 + 4 + write-only + + + S1DSE + Slice 1 Dither shadow transfer set enable + 5 + 5 + write-only + + + S1PSE + Slice 1 Prescaler shadow transfer set enable + 6 + 6 + write-only + + + S2SE + Slice 2 shadow transfer set enable + 8 + 8 + write-only + + + S2DSE + Slice 2 Dither shadow transfer set enable + 9 + 9 + write-only + + + S2PSE + Slice 2 Prescaler shadow transfer set enable + 10 + 10 + write-only + + + S3SE + Slice 3 shadow transfer set enable + 12 + 12 + write-only + + + S3DSE + Slice 3 Dither shadow transfer set enable + 13 + 13 + write-only + + + S3PSE + Slice 3 Prescaler shadow transfer set enable + 14 + 14 + write-only + + + S0STS + Slice 0 status bit set + 16 + 16 + write-only + + + S1STS + Slice 1 status bit set + 17 + 17 + write-only + + + S2STS + Slice 2 status bit set + 18 + 18 + write-only + + + S3STS + Slice 3 status bit set + 19 + 19 + write-only + + + + + GCSC + Global Channel Clear + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SC + Slice 0 shadow transfer clear + 0 + 0 + write-only + + + S0DSC + Slice 0 Dither shadow transfer clear + 1 + 1 + write-only + + + S0PSC + Slice 0 Prescaler shadow transfer clear + 2 + 2 + write-only + + + S1SC + Slice 1 shadow transfer clear + 4 + 4 + write-only + + + S1DSC + Slice 1 Dither shadow transfer clear + 5 + 5 + write-only + + + S1PSC + Slice 1 Prescaler shadow transfer clear + 6 + 6 + write-only + + + S2SC + Slice 2 shadow transfer clear + 8 + 8 + write-only + + + S2DSC + Slice 2 Dither shadow transfer clear + 9 + 9 + write-only + + + S2PSC + Slice 2 Prescaler shadow transfer clear + 10 + 10 + write-only + + + S3SC + Slice 3 shadow transfer clear + 12 + 12 + write-only + + + S3DSC + Slice 3 Dither shadow transfer clear + 13 + 13 + write-only + + + S3PSC + Slice 3 Prescaler shadow transfer clear + 14 + 14 + write-only + + + S0STC + Slice 0 status bit clear + 16 + 16 + write-only + + + S1STC + Slice 1 status bit clear + 17 + 17 + write-only + + + S2STC + Slice 2 status bit clear + 18 + 18 + write-only + + + S3STC + Slice 3 status bit clear + 19 + 19 + write-only + + + + + GCST + Global Channel Status + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SS + Slice 0 shadow transfer status + 0 + 0 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S0DSS + Slice 0 Dither shadow transfer status + 1 + 1 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S0PSS + Slice 0 Prescaler shadow transfer status + 2 + 2 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S1SS + Slice 1 shadow transfer status + 4 + 4 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S1DSS + Slice 1 Dither shadow transfer status + 5 + 5 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S1PSS + Slice 1 Prescaler shadow transfer status + 6 + 6 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S2SS + Slice 2 shadow transfer status + 8 + 8 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S2DSS + Slice 2 Dither shadow transfer status + 9 + 9 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S2PSS + Slice 2 Prescaler shadow transfer status + 10 + 10 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S3SS + Slice 3 shadow transfer status + 12 + 12 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S3DSS + Slice 3 Dither shadow transfer status + 13 + 13 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S3PSS + Slice 3 Prescaler shadow transfer status + 14 + 14 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + CC40ST + Slice 0 status bit + 16 + 16 + read-only + + + CC41ST + Slice 1 status bit + 17 + 17 + read-only + + + CC42ST + Slice 2 status bit + 18 + 18 + read-only + + + CC43ST + Slice 3 status bit + 19 + 19 + read-only + + + + + MIDR + Module Identification + 0x0080 + 32 + 0x00A6C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + + + CCU41 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010000 + + 0x0 + 0x100 + registers + + + CCU41_0 + Capture Compare Unit 4 (Module 1) + 48 + + + CCU41_1 + Capture Compare Unit 4 (Module 1) + 49 + + + CCU41_2 + Capture Compare Unit 4 (Module 1) + 50 + + + CCU41_3 + Capture Compare Unit 4 (Module 1) + 51 + + + + CCU42 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014000 + + 0x0 + 0x100 + registers + + + CCU42_0 + Capture Compare Unit 4 (Module 2) + 52 + + + CCU42_1 + Capture Compare Unit 4 (Module 2) + 53 + + + CCU42_2 + Capture Compare Unit 4 (Module 2) + 54 + + + CCU42_3 + Capture Compare Unit 4 (Module 2) + 55 + + + + CCU43 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004000 + + 0x0 + 0x100 + registers + + + CCU43_0 + Capture Compare Unit 4 (Module 3) + 56 + + + CCU43_1 + Capture Compare Unit 4 (Module 3) + 57 + + + CCU43_2 + Capture Compare Unit 4 (Module 3) + 58 + + + CCU43_3 + Capture Compare Unit 4 (Module 3) + 59 + + + + CCU40_CC40 + Capture Compare Unit 4 - Unit 0 + CCU4 + CCU4_CC4 + 0x4000C100 + + 0x0 + 0x100 + registers + + + + INS + Input Selector Configuration + 0x000 + 32 + 0x00000000 + 0xFFFFFFFF + + + EV0IS + Event 0 signal selection + 0 + 3 + read-write + + + value1 + CCU4x.INyA + #0000 + + + value2 + CCU4x.INyB + #0001 + + + value3 + CCU4x.INyC + #0010 + + + value4 + CCU4x.INyD + #0011 + + + value5 + CCU4x.INyE + #0100 + + + value6 + CCU4x.INyF + #0101 + + + value7 + CCU4x.INyG + #0110 + + + value8 + CCU4x.INyH + #0111 + + + value9 + CCU4x.INyI + #1000 + + + value10 + CCU4x.INyJ + #1001 + + + value11 + CCU4x.INyK + #1010 + + + value12 + CCU4x.INyL + #1011 + + + value13 + CCU4x.INyM + #1100 + + + value14 + CCU4x.INyN + #1101 + + + value15 + CCU4x.INyO + #1110 + + + value16 + CCU4x.INyP + #1111 + + + + + EV1IS + Event 1 signal selection + 4 + 7 + read-write + + + value1 + CCU4x.INyA + #0000 + + + value2 + CCU4x.INyB + #0001 + + + value3 + CCU4x.INyC + #0010 + + + value4 + CCU4x.INyD + #0011 + + + value5 + CCU4x.INyE + #0100 + + + value6 + CCU4x.INyF + #0101 + + + value7 + CCU4x.INyG + #0110 + + + value8 + CCU4x.INyH + #0111 + + + value9 + CCU4x.INyI + #1000 + + + value10 + CCU4x.INyJ + #1001 + + + value11 + CCU4x.INyK + #1010 + + + value12 + CCU4x.INyL + #1011 + + + value13 + CCU4x.INyM + #1100 + + + value14 + CCU4x.INyN + #1101 + + + value15 + CCU4x.INyO + #1110 + + + value16 + CCU4x.INyP + #1111 + + + + + EV2IS + Event 2 signal selection + 8 + 11 + read-write + + + value1 + CCU4x.INyA + #0000 + + + value2 + CCU4x.INyB + #0001 + + + value3 + CCU4x.INyC + #0010 + + + value4 + CCU4x.INyD + #0011 + + + value5 + CCU4x.INyE + #0100 + + + value6 + CCU4x.INyF + #0101 + + + value7 + CCU4x.INyG + #0110 + + + value8 + CCU4x.INyH + #0111 + + + value9 + CCU4x.INyI + #1000 + + + value10 + CCU4x.INyJ + #1001 + + + value11 + CCU4x.INyK + #1010 + + + value12 + CCU4x.INyL + #1011 + + + value13 + CCU4x.INyM + #1100 + + + value14 + CCU4x.INyN + #1101 + + + value15 + CCU4x.INyO + #1110 + + + value16 + CCU4x.INyP + #1111 + + + + + EV0EM + Event 0 Edge Selection + 16 + 17 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV1EM + Event 1 Edge Selection + 18 + 19 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV2EM + Event 2 Edge Selection + 20 + 21 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV0LM + Event 0 Level Selection + 22 + 22 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV1LM + Event 1 Level Selection + 23 + 23 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV2LM + Event 2 Level Selection + 24 + 24 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + LPF0M + Event 0 Low Pass Filter Configuration + 25 + 26 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU4 + #01 + + + value3 + 5 clock cycles of fCCU4 + #10 + + + value4 + 7 clock cycles of fCCU4 + #11 + + + + + LPF1M + Event 1 Low Pass Filter Configuration + 27 + 28 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU4 + #01 + + + value3 + 5 clock cycles of fCCU4 + #10 + + + value4 + 7 clock cycles of fCCU4 + #11 + + + + + LPF2M + Event 2 Low Pass Filter Configuration + 29 + 30 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU4 + #01 + + + value3 + 5 clock cycles of fCCU4 + #10 + + + value4 + 7 clock cycles of fCCU4 + #11 + + + + + + + CMC + Connection Matrix Control + 0x004 + 32 + 0x00000000 + 0xFFFFFFFF + + + STRTS + External Start Functionality Selector + 0 + 1 + read-write + + + value1 + External Start Function deactivated + #00 + + + value2 + External Start Function triggered by Event 0 + #01 + + + value3 + External Start Function triggered by Event 1 + #10 + + + value4 + External Start Function triggered by Event 2 + #11 + + + + + ENDS + External Stop Functionality Selector + 2 + 3 + read-write + + + value1 + External Stop Function deactivated + #00 + + + value2 + External Stop Function triggered by Event 0 + #01 + + + value3 + External Stop Function triggered by Event 1 + #10 + + + value4 + External Stop Function triggered by Event 2 + #11 + + + + + CAP0S + External Capture 0 Functionality Selector + 4 + 5 + read-write + + + value1 + External Capture 0 Function deactivated + #00 + + + value2 + External Capture 0 Function triggered by Event 0 + #01 + + + value3 + External Capture 0 Function triggered by Event 1 + #10 + + + value4 + External Capture 0 Function triggered by Event 2 + #11 + + + + + CAP1S + External Capture 1 Functionality Selector + 6 + 7 + read-write + + + value1 + External Capture 1 Function deactivated + #00 + + + value2 + External Capture 1 Function triggered by Event 0 + #01 + + + value3 + External Capture 1 Function triggered by Event 1 + #10 + + + value4 + External Capture 1 Function triggered by Event 2 + #11 + + + + + GATES + External Gate Functionality Selector + 8 + 9 + read-write + + + value1 + External Gating Function deactivated + #00 + + + value2 + External Gating Function triggered by Event 0 + #01 + + + value3 + External Gating Function triggered by Event 1 + #10 + + + value4 + External Gating Function triggered by Event 2 + #11 + + + + + UDS + External Up/Down Functionality Selector + 10 + 11 + read-write + + + value1 + External Up/Down Function deactivated + #00 + + + value2 + External Up/Down Function triggered by Event 0 + #01 + + + value3 + External Up/Down Function triggered by Event 1 + #10 + + + value4 + External Up/Down Function triggered by Event 2 + #11 + + + + + LDS + External Timer Load Functionality Selector + 12 + 13 + read-write + + + CNTS + External Count Selector + 14 + 15 + read-write + + + value1 + External Count Function deactivated + #00 + + + value2 + External Count Function triggered by Event 0 + #01 + + + value3 + External Count Function triggered by Event 1 + #10 + + + value4 + External Count Function triggered by Event 2 + #11 + + + + + OFS + Override Function Selector + 16 + 16 + read-write + + + value1 + Override functionality disabled + #0 + + + value2 + Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 + #1 + + + + + TS + Trap Function Selector + 17 + 17 + read-write + + + value1 + Trap function disabled + #0 + + + value2 + TRAP function connected to Event 2 + #1 + + + + + MOS + External Modulation Functionality Selector + 18 + 19 + read-write + + + TCE + Timer Concatenation Enable + 20 + 20 + read-write + + + value1 + Timer concatenation is disabled + #0 + + + value2 + Timer concatenation is enabled + #1 + + + + + + + TCST + Slice Timer Status + 0x008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRB + Timer Run Bit + 0 + 0 + read-only + + + value1 + Timer is stopped + #0 + + + value2 + Timer is running + #1 + + + + + CDIR + Timer Counting Direction + 1 + 1 + read-only + + + value1 + Timer is counting up + #0 + + + value2 + Timer is counting down + #1 + + + + + + + TCSET + Slice Timer Run Set + 0x00C + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBS + Timer Run Bit set + 0 + 0 + write-only + + + + + TCCLR + Slice Timer Clear + 0x010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBC + Timer Run Bit Clear + 0 + 0 + write-only + + + TCC + Timer Clear + 1 + 1 + write-only + + + DITC + Dither Counter Clear + 2 + 2 + write-only + + + + + TC + Slice Timer Control + 0x014 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCM + Timer Counting Mode + 0 + 0 + read-write + + + value1 + Edge aligned mode + #0 + + + value2 + Center aligned mode + #1 + + + + + TSSM + Timer Single Shot Mode + 1 + 1 + read-write + + + value1 + Single shot mode is disabled + #0 + + + value2 + Single shot mode is enabled + #1 + + + + + CLST + Shadow Transfer on Clear + 2 + 2 + read-write + + + CMOD + Capture Compare Mode + 3 + 3 + read-only + + + value1 + Compare Mode + #0 + + + value2 + Capture Mode + #1 + + + + + ECM + Extended Capture Mode + 4 + 4 + read-write + + + value1 + Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. + #0 + + + value2 + Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared. + #1 + + + + + CAPC + Clear on Capture Control + 5 + 6 + read-write + + + value1 + Timer is never cleared on a capture event + #00 + + + value2 + Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) + #01 + + + value3 + Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) + #10 + + + value4 + Timer is always cleared in a capture event. + #11 + + + + + ENDM + Extended Stop Function Control + 8 + 9 + read-write + + + value1 + Clears the timer run bit only (default stop) + #00 + + + value2 + Clears the timer only (flush) + #01 + + + value3 + Clears the timer and run bit (flush/stop) + #10 + + + + + STRM + Extended Start Function Control + 10 + 10 + read-write + + + value1 + Sets run bit only (default start) + #0 + + + value2 + Clears the timer and sets run bit (flush/start) + #1 + + + + + SCE + Equal Capture Event enable + 11 + 11 + read-write + + + value1 + Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #0 + + + value2 + Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #1 + + + + + CCS + Continuous Capture Enable + 12 + 12 + read-write + + + value1 + The capture into a specific capture register is done with the rules linked with the full flags, described at . + #0 + + + value2 + The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). + #1 + + + + + DITHE + Dither Enable + 13 + 14 + read-write + + + value1 + Dither is disabled + #00 + + + value2 + Dither is applied to the Period + #01 + + + value3 + Dither is applied to the Compare + #10 + + + value4 + Dither is applied to the Period and Compare + #11 + + + + + DIM + Dither input selector + 15 + 15 + read-write + + + value1 + Slice is using its own dither unit + #0 + + + value2 + Slice is connected to the dither unit of slice 0. + #1 + + + + + FPE + Floating Prescaler enable + 16 + 16 + read-write + + + value1 + Floating prescaler mode is disabled + #0 + + + value2 + Floating prescaler mode is enabled + #1 + + + + + TRAPE + TRAP enable + 17 + 17 + read-write + + + value1 + TRAP functionality has no effect on the output + #0 + + + value2 + TRAP functionality affects the output + #1 + + + + + TRPSE + TRAP Synchronization Enable + 21 + 21 + read-write + + + value1 + Exiting from TRAP state isn't synchronized with the PWM signal + #0 + + + value2 + Exiting from TRAP state is synchronized with the PWM signal + #1 + + + + + TRPSW + TRAP State Clear Control + 22 + 22 + read-write + + + value1 + The slice exits the TRAP state automatically when the TRAP condition is not present + #0 + + + value2 + The TRAP state can only be exited by a SW request. + #1 + + + + + EMS + External Modulation Synchronization + 23 + 23 + read-write + + + value1 + External Modulation functionality is not synchronized with the PWM signal + #0 + + + value2 + External Modulation functionality is synchronized with the PWM signal + #1 + + + + + EMT + External Modulation Type + 24 + 24 + read-write + + + value1 + External Modulation functionality is clearing the CC4yST bit. + #0 + + + value2 + External Modulation functionality is gating the outputs. + #1 + + + + + MCME + Multi Channel Mode Enable + 25 + 25 + read-write + + + value1 + Multi Channel Mode is disabled + #0 + + + value2 + Multi Channel Mode is enabled + #1 + + + + + + + PSL + Passive Level Config + 0x018 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSL + Output Passive Level + 0 + 0 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + + + DIT + Dither Config + 0x01C + 32 + 0x00000000 + 0xFFFFFFFF + + + DCV + Dither compare Value + 0 + 3 + read-only + + + DCNT + Dither counter actual value + 8 + 11 + read-only + + + + + DITS + Dither Shadow Register + 0x020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCVS + Dither Shadow Compare Value + 0 + 3 + read-write + + + + + PSC + Prescaler Control + 0x024 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSIV + Prescaler Initial Value + 0 + 3 + read-write + + + + + FPC + Floating Prescaler Control + 0x028 + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Compare Value + 0 + 3 + read-only + + + PVAL + Actual Prescaler Value + 8 + 11 + read-write + + + + + FPCS + Floating Prescaler Shadow + 0x02C + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Shadow Compare Value + 0 + 3 + read-write + + + + + PR + Timer Period Value + 0x030 + 32 + 0x00000000 + 0xFFFFFFFF + + + PR + Period Register + 0 + 15 + read-only + + + + + PRS + Timer Shadow Period Value + 0x034 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRS + Period Register + 0 + 15 + read-write + + + + + CR + Timer Compare Value + 0x038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Compare Register + 0 + 15 + read-only + + + + + CRS + Timer Shadow Compare Value + 0x03C + 32 + 0x00000000 + 0xFFFFFFFF + + + CRS + Compare Register + 0 + 15 + read-write + + + + + TIMER + Timer Value + 0x070 + 32 + 0x00000000 + 0xFFFFFFFF + + + TVAL + Timer Value + 0 + 15 + read-write + + + + + C0V + Capture Register 0 + 0x074 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C1V + Capture Register 1 + 0x078 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C2V + Capture Register 2 + 0x07C + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C3V + Capture Register 3 + 0x080 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + INTS + Interrupt Status + 0x0A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PMUS + Period Match while Counting Up + 0 + 0 + read-only + + + value1 + Period match while counting up not detected + #0 + + + value2 + Period match while counting up detected + #1 + + + + + OMDS + One Match while Counting Down + 1 + 1 + read-only + + + value1 + One match while counting down not detected + #0 + + + value2 + One match while counting down detected + #1 + + + + + CMUS + Compare Match while Counting Up + 2 + 2 + read-only + + + value1 + Compare match while counting up not detected + #0 + + + value2 + Compare match while counting up detected + #1 + + + + + CMDS + Compare Match while Counting Down + 3 + 3 + read-only + + + value1 + Compare match while counting down not detected + #0 + + + value2 + Compare match while counting down detected + #1 + + + + + E0AS + Event 0 Detection Status + 8 + 8 + read-only + + + value1 + Event 0 not detected + #0 + + + value2 + Event 0 detected + #1 + + + + + E1AS + Event 1 Detection Status + 9 + 9 + read-only + + + value1 + Event 1 not detected + #0 + + + value2 + Event 1 detected + #1 + + + + + E2AS + Event 2 Detection Status + 10 + 10 + read-only + + + value1 + Event 2 not detected + #0 + + + value2 + Event 2 detected + #1 + + + + + TRPF + Trap Flag Status + 11 + 11 + read-only + + + + + INTE + Interrupt Enable Control + 0x0A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + PME + Period match while counting up enable + 0 + 0 + read-write + + + value1 + Period Match interrupt is disabled + #0 + + + value2 + Period Match interrupt is enabled + #1 + + + + + OME + One match while counting down enable + 1 + 1 + read-write + + + value1 + One Match interrupt is disabled + #0 + + + value2 + One Match interrupt is enabled + #1 + + + + + CMUE + Compare match while counting up enable + 2 + 2 + read-write + + + value1 + Compare Match while counting up interrupt is disabled + #0 + + + value2 + Compare Match while counting up interrupt is enabled + #1 + + + + + CMDE + Compare match while counting down enable + 3 + 3 + read-write + + + value1 + Compare Match while counting down interrupt is disabled + #0 + + + value2 + Compare Match while counting down interrupt is enabled + #1 + + + + + E0AE + Event 0 interrupt enable + 8 + 8 + read-write + + + value1 + Event 0 detection interrupt is disabled + #0 + + + value2 + Event 0 detection interrupt is enabled + #1 + + + + + E1AE + Event 1 interrupt enable + 9 + 9 + read-write + + + value1 + Event 1 detection interrupt is disabled + #0 + + + value2 + Event 1 detection interrupt is enabled + #1 + + + + + E2AE + Event 2 interrupt enable + 10 + 10 + read-write + + + value1 + Event 2 detection interrupt is disabled + #0 + + + value2 + Event 2 detection interrupt is enabled + #1 + + + + + + + SRS + Service Request Selector + 0x0A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSR + Period/One match Service request selector + 0 + 1 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + CMSR + Compare match Service request selector + 2 + 3 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + E0SR + Event 0 Service request selector + 8 + 9 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + E1SR + Event 1 Service request selector + 10 + 11 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + E2SR + Event 2 Service request selector + 12 + 13 + read-write + + + value1 + Forward to CC4ySR0 + #00 + + + value2 + Forward to CC4ySR1 + #01 + + + value3 + Forward to CC4ySR2 + #10 + + + value4 + Forward to CC4ySR3 + #11 + + + + + + + SWS + Interrupt Status Set + 0x0AC + 32 + 0x00000000 + 0xFFFFFFFF + + + SPM + Period match while counting up set + 0 + 0 + write-only + + + SOM + One match while counting down set + 1 + 1 + write-only + + + SCMU + Compare match while counting up set + 2 + 2 + write-only + + + SCMD + Compare match while counting down set + 3 + 3 + write-only + + + SE0A + Event 0 detection set + 8 + 8 + write-only + + + SE1A + Event 1 detection set + 9 + 9 + write-only + + + SE2A + Event 2 detection set + 10 + 10 + write-only + + + STRPF + Trap Flag status set + 11 + 11 + write-only + + + + + SWR + Interrupt Status Clear + 0x0B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPM + Period match while counting up clear + 0 + 0 + write-only + + + ROM + One match while counting down clear + 1 + 1 + write-only + + + RCMU + Compare match while counting up clear + 2 + 2 + write-only + + + RCMD + Compare match while counting down clear + 3 + 3 + write-only + + + RE0A + Event 0 detection clear + 8 + 8 + write-only + + + RE1A + Event 1 detection clear + 9 + 9 + write-only + + + RE2A + Event 2 detection clear + 10 + 10 + write-only + + + RTRPF + Trap Flag status clear + 11 + 11 + write-only + + + + + ECRD0 + Extended Read Back 0 + 0x0B8 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC40 + #00 + + + value2 + CC41 + #01 + + + value3 + CC42 + #10 + + + value4 + CC43 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + ECRD1 + Extended Read Back 1 + 0x0BC + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC40 + #00 + + + value2 + CC41 + #01 + + + value3 + CC42 + #10 + + + value4 + CC43 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + + + CCU40_CC41 + Capture Compare Unit 4 - Unit 0 + CCU4 + 0x4000C200 + + 0x0 + 0x100 + registers + + + + CCU40_CC42 + Capture Compare Unit 4 - Unit 0 + CCU4 + 0x4000C300 + + 0x0 + 0x100 + registers + + + + CCU40_CC43 + Capture Compare Unit 4 - Unit 0 + CCU4 + 0x4000C400 + + 0x0 + 0x100 + registers + + + + CCU41_CC40 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010100 + + 0x0 + 0x100 + registers + + + + CCU41_CC41 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010200 + + 0x0 + 0x100 + registers + + + + CCU41_CC42 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010300 + + 0x0 + 0x100 + registers + + + + CCU41_CC43 + Capture Compare Unit 4 - Unit 1 + CCU4 + 0x40010400 + + 0x0 + 0x100 + registers + + + + CCU42_CC40 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014100 + + 0x0 + 0x100 + registers + + + + CCU42_CC41 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014200 + + 0x0 + 0x100 + registers + + + + CCU42_CC42 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014300 + + 0x0 + 0x100 + registers + + + + CCU42_CC43 + Capture Compare Unit 4 - Unit 2 + CCU4 + 0x40014400 + + 0x0 + 0x100 + registers + + + + CCU43_CC40 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004100 + + 0x0 + 0x100 + registers + + + + CCU43_CC41 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004200 + + 0x0 + 0x100 + registers + + + + CCU43_CC42 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004300 + + 0x0 + 0x100 + registers + + + + CCU43_CC43 + Capture Compare Unit 4 - Unit 3 + CCU4 + 0x48004400 + + 0x0 + 0x100 + registers + + + + CCU80 + Capture Compare Unit 8 - Unit 0 + CCU8 + CCU8 + 0x40020000 + + 0x0 + 0x100 + registers + + + CCU80_0 + Capture Compare Unit 8 (Module 0) + 60 + + + CCU80_1 + Capture Compare Unit 8 (Module 0) + 61 + + + CCU80_2 + Capture Compare Unit 8 (Module 0) + 62 + + + CCU80_3 + Capture Compare Unit 8 (Module 0) + 63 + + + + GCTRL + Global Control Register + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRBC + Prescaler Clear Configuration + 0 + 2 + read-write + + + value1 + SW only + #000 + + + value2 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC80 is cleared. + #001 + + + value3 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC81 is cleared. + #010 + + + value4 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC82 is cleared. + #011 + + + value5 + GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC83 is cleared. + #100 + + + + + PCIS + Prescaler Input Clock Selection + 4 + 5 + read-write + + + value1 + Module clock + #00 + + + value2 + CCU8x.ECLKA + #01 + + + value3 + CCU8x.ECLKB + #10 + + + value4 + CCU8x.ECLKC + #11 + + + + + SUSCFG + Suspend Mode Configuration + 8 + 9 + read-write + + + value1 + Suspend request ignored. The module never enters in suspend + #00 + + + value2 + Stops all the running slices immediately. Safe stop is not applied. + #01 + + + value3 + Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. + #10 + + + value4 + Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. + #11 + + + + + MSE0 + Slice 0 Multi Channel shadow transfer enable + 10 + 10 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8x.MCSS input. + #1 + + + + + MSE1 + Slice 1 Multi Channel shadow transfer enable + 11 + 11 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8x.MCSS input. + #1 + + + + + MSE2 + Slice 2 Multi Channel shadow transfer enable + 12 + 12 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8xMCSS input. + #1 + + + + + MSE3 + Slice 3 Multi Channel shadow transfer enable + 13 + 13 + read-write + + + value1 + Shadow transfer can only be requested by SW + #0 + + + value2 + Shadow transfer can be requested via SW and via the CCU8x.MCSS input. + #1 + + + + + MSDE + Multi Channel shadow transfer request configuration + 14 + 15 + read-write + + + value1 + Only the shadow transfer for period and compare values is requested + #00 + + + value2 + Shadow transfer for the compare, period and prescaler compare values is requested + #01 + + + value4 + Shadow transfer for the compare, period, prescaler and dither compare values is requested + #11 + + + + + + + GSTAT + Global Status Register + 0x0004 + 32 + 0x0000000F + 0xFFFFFFFF + + + S0I + CC80 IDLE status + 0 + 0 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S1I + CC81 IDLE status + 1 + 1 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S2I + CC82 IDLE status + 2 + 2 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + S3I + CC83 IDLE status + 3 + 3 + read-only + + + value1 + Running + #0 + + + value2 + Idle + #1 + + + + + PRB + Prescaler Run Bit + 8 + 8 + read-only + + + value1 + Prescaler is stopped + #0 + + + value2 + Prescaler is running + #1 + + + + + PCRB + Parity Checker Run Bit + 10 + 10 + read-only + + + value1 + Parity Checker is stopped + #0 + + + value2 + Parity Checker is running + #1 + + + + + + + GIDLS + Global Idle Set + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SS0I + CC80 IDLE mode set + 0 + 0 + write-only + + + SS1I + CC81 IDLE mode set + 1 + 1 + write-only + + + SS2I + CC82 IDLE mode set + 2 + 2 + write-only + + + SS3I + CC83 IDLE mode set + 3 + 3 + write-only + + + CPRB + Prescaler# Run Bit Clear + 8 + 8 + write-only + + + PSIC + Prescaler clear + 9 + 9 + write-only + + + CPCH + Parity Checker Run bit clear + 10 + 10 + write-only + + + + + GIDLC + Global Idle Clear + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + CS0I + CC80 IDLE mode clear + 0 + 0 + write-only + + + CS1I + CC81 IDLE mode clear + 1 + 1 + write-only + + + CS2I + CC82 IDLE mode clear + 2 + 2 + write-only + + + CS3I + CC83 IDLE mode clear + 3 + 3 + write-only + + + SPRB + Prescaler Run Bit Set + 8 + 8 + write-only + + + SPCH + Parity Checker run bit set + 10 + 10 + write-only + + + + + GCSS + Global Channel Set + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SE + Slice 0 shadow transfer set enable + 0 + 0 + write-only + + + S0DSE + Slice 0 Dither shadow transfer set enable + 1 + 1 + write-only + + + S0PSE + Slice 0 Prescaler shadow transfer set enable + 2 + 2 + write-only + + + S1SE + Slice 1 shadow transfer set enable + 4 + 4 + write-only + + + S1DSE + Slice 1 Dither shadow transfer set enable + 5 + 5 + write-only + + + S1PSE + Slice 1 Prescaler shadow transfer set enable + 6 + 6 + write-only + + + S2SE + Slice 2 shadow transfer set enable + 8 + 8 + write-only + + + S2DSE + Slice 2 Dither shadow transfer set enable + 9 + 9 + write-only + + + S2PSE + Slice 2 Prescaler shadow transfer set enable + 10 + 10 + write-only + + + S3SE + Slice 3 shadow transfer set enable + 12 + 12 + write-only + + + S3DSE + Slice 3 Dither shadow transfer set enable + 13 + 13 + write-only + + + S3PSE + Slice 3 Prescaler shadow transfer set enable + 14 + 14 + write-only + + + S0ST1S + Slice 0 status bit 1 set + 16 + 16 + write-only + + + S1ST1S + Slice 1 status bit 1 set + 17 + 17 + write-only + + + S2ST1S + Slice 2 status bit 1 set + 18 + 18 + write-only + + + S3ST1S + Slice 3 status bit 1 set + 19 + 19 + write-only + + + S0ST2S + Slice 0 status bit 2 set + 20 + 20 + write-only + + + S1ST2S + Slice 1 status bit 2 set + 21 + 21 + write-only + + + S2ST2S + Slice 2 status bit 2 set + 22 + 22 + write-only + + + S3ST2S + Slice 3 status bit 2 set + 23 + 23 + write-only + + + + + GCSC + Global Channel Clear + 0x0014 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SC + Slice 0 shadow transfer request clear + 0 + 0 + write-only + + + S0DSC + Slice 0 Dither shadow transfer clear + 1 + 1 + write-only + + + S0PSC + Slice 0 Prescaler shadow transfer clear + 2 + 2 + write-only + + + S1SC + Slice 1 shadow transfer clear + 4 + 4 + write-only + + + S1DSC + Slice 1 Dither shadow transfer clear + 5 + 5 + write-only + + + S1PSC + Slice 1 Prescaler shadow transfer clear + 6 + 6 + write-only + + + S2SC + Slice 2 shadow transfer clear + 8 + 8 + write-only + + + S2DSC + Slice 2 Dither shadow transfer clear + 9 + 9 + write-only + + + S2PSC + Slice 2 Prescaler shadow transfer clear + 10 + 10 + write-only + + + S3SC + Slice 3 shadow transfer clear + 12 + 12 + write-only + + + S3DSC + Slice 3 Dither shadow transfer clear + 13 + 13 + write-only + + + S3PSC + Slice 3 Prescaler shadow transfer clear + 14 + 14 + write-only + + + S0ST1C + Slice 0 status bit 1 clear + 16 + 16 + write-only + + + S1ST1C + Slice 1 status bit 1 clear + 17 + 17 + write-only + + + S2ST1C + Slice 2 status bit 1 clear + 18 + 18 + write-only + + + S3ST1C + Slice 3 status bit 1 clear + 19 + 19 + write-only + + + S0ST2C + Slice 0 status bit 2 clear + 20 + 20 + write-only + + + S1ST2C + Slice 1 status bit 2 clear + 21 + 21 + write-only + + + S2ST2C + Slice 2 status bit 2 clear + 22 + 22 + write-only + + + S3ST2C + Slice 3 status bit 2 clear + 23 + 23 + write-only + + + + + GCST + Global Channel status + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + S0SS + Slice 0 shadow transfer status + 0 + 0 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S0DSS + Slice 0 Dither shadow transfer status + 1 + 1 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S0PSS + Slice 0 Prescaler shadow transfer status + 2 + 2 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S1SS + Slice 1 shadow transfer status + 4 + 4 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S1DSS + Slice 1 Dither shadow transfer status + 5 + 5 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S1PSS + Slice 1 Prescaler shadow transfer status + 6 + 6 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S2SS + Slice 2 shadow transfer status + 8 + 8 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S2DSS + Slice 2 Dither shadow transfer status + 9 + 9 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S2PSS + Slice 2 Prescaler shadow transfer status + 10 + 10 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + S3SS + Slice 3 shadow transfer status + 12 + 12 + read-only + + + value1 + Shadow transfer has not been requested + #0 + + + value2 + Shadow transfer has been requested + #1 + + + + + S3DSS + Slice 3 Dither shadow transfer status + 13 + 13 + read-only + + + value1 + Dither shadow transfer has not been requested + #0 + + + value2 + Dither shadow transfer has been requested + #1 + + + + + S3PSS + Slice 3 Prescaler shadow transfer status + 14 + 14 + read-only + + + value1 + Prescaler shadow transfer has not been requested + #0 + + + value2 + Prescaler shadow transfer has been requested + #1 + + + + + CC80ST1 + Slice 0 compare channel 1 status bit + 16 + 16 + read-only + + + CC81ST1 + Slice 1 compare channel 1 status bit + 17 + 17 + read-only + + + CC82ST1 + Slice 2 compare channel 1 status bit + 18 + 18 + read-only + + + CC83ST1 + Slice 3 compare channel 1 status bit + 19 + 19 + read-only + + + CC80ST2 + Slice 0 compare channel 2 status bit + 20 + 20 + read-only + + + CC81ST2 + Slice 1 compare channel 2 status bit + 21 + 21 + read-only + + + CC82ST2 + Slice 2 compare channel 2 status bit + 22 + 22 + read-only + + + CC83ST2 + Slice 3 compare channel 2 status bit + 23 + 23 + read-only + + + + + GPCHK + Parity Checker Configuration + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + PASE + Parity Checker Automatic start/stop + 0 + 0 + read-write + + + PACS + Parity Checker Automatic start/stop selector + 1 + 2 + read-write + + + value1 + CC80 + #00 + + + value2 + CC81 + #01 + + + value3 + CC82 + #10 + + + value4 + CC83 + #11 + + + + + PISEL + Driver Input signal selector + 3 + 4 + read-write + + + value1 + CC8x.GP01 - driver output is connected to event 1 of slice 0 + #00 + + + value2 + CC8x.GP11 - drive output is connected to event 1 of slice 1 + #01 + + + value3 + CC8x.GP21 - driver output is connected to event 1 of slice 2 + #10 + + + value4 + CC8x.GP31 - driver output is connected to event 1 of slice 3 + #11 + + + + + PCDS + Parity Checker Delay Input Selector + 5 + 6 + read-write + + + value1 + CCU8x.IGBTA + #00 + + + value2 + CCU8x.IGBTB + #01 + + + value3 + CCU8x.IGBTC + #10 + + + value4 + CCU8x.IGBTD + #11 + + + + + PCTS + Parity Checker type selector + 7 + 7 + read-write + + + value1 + Even parity enabled + #0 + + + value2 + Odd parity enabled + #1 + + + + + PCST + Parity Checker XOR status + 15 + 15 + read-only + + + PCSEL0 + Parity Checker Slice 0 output selection + 16 + 19 + read-write + + + PCSEL1 + Parity Checker Slice 1 output selection + 20 + 23 + read-write + + + PCSEL2 + Parity Checker Slice 2 output selection + 24 + 27 + read-write + + + PCSEL3 + Parity Checker Slice 3 output selection + 28 + 31 + read-write + + + + + MIDR + Module Identification + 0x0080 + 32 + 0x00A7C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + + + CCU81 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024000 + + 0x0 + 0x100 + registers + + + CCU81_0 + Capture Compare Unit 8 (Module 1) + 64 + + + CCU81_1 + Capture Compare Unit 8 (Module 1) + 65 + + + CCU81_2 + Capture Compare Unit 8 (Module 1) + 66 + + + CCU81_3 + Capture Compare Unit 8 (Module 1) + 67 + + + + CCU80_CC80 + Capture Compare Unit 8 - Unit 0 + CCU8 + CCU8_CC8 + 0x40020100 + + 0x0 + 0x100 + registers + + + + INS + Input Selector Configuration + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + EV0IS + Event 0 signal selection + 0 + 3 + read-write + + + value1 + CCU8x.INyA + #0000 + + + value2 + CCU8x.INyB + #0001 + + + value3 + CCU8x.INyC + #0010 + + + value4 + CCU8x.INyD + #0011 + + + value5 + CCU8x.INyE + #0100 + + + value6 + CCU8x.INyF + #0101 + + + value7 + CCU8x.INyG + #0110 + + + value8 + CCU8x.INyH + #0111 + + + value9 + CCU8x.INyI + #1000 + + + value10 + CCU8x.INyJ + #1001 + + + value11 + CCU8x.INyK + #1010 + + + value12 + CCU8x.INyL + #1011 + + + value13 + CCU8x.INyM + #1100 + + + value14 + CCU8x.INyN + #1101 + + + value15 + CCU8x.INyO + #1110 + + + value16 + CCU8x.INyP + #1111 + + + + + EV1IS + Event 1 signal selection + 4 + 7 + read-write + + + value1 + CCU8x.INyA + #0000 + + + value2 + CCU8x.INyB + #0001 + + + value3 + CCU8x.INyC + #0010 + + + value4 + CCU8x.INyD + #0011 + + + value5 + CCU8x.INyE + #0100 + + + value6 + CCU8x.INyF + #0101 + + + value7 + CCU8x.INyG + #0110 + + + value8 + CCU8x.INyH + #0111 + + + value9 + CCU8x.INyI + #1000 + + + value10 + CCU8x.INyJ + #1001 + + + value11 + CCU8x.INyK + #1010 + + + value12 + CCU8x.INyL + #1011 + + + value13 + CCU8x.INyM + #1100 + + + value14 + CCU8x.INyN + #1101 + + + value15 + CCU8x.INyO + #1110 + + + value16 + CCU8x.INyP + #1111 + + + + + EV2IS + Event 2 signal selection + 8 + 11 + read-write + + + value1 + CCU8x.INyA + #0000 + + + value2 + CCU8x.INyB + #0001 + + + value3 + CCU8x.INyC + #0010 + + + value4 + CCU8x.INyD + #0011 + + + value5 + CCU8x.INyE + #0100 + + + value6 + CCU8x.INyF + #0101 + + + value7 + CCU8x.INyG + #0110 + + + value8 + CCU8x.INyH + #0111 + + + value9 + CCU8x.INyI + #1000 + + + value10 + CCU8x.INyJ + #1001 + + + value11 + CCU8x.INyK + #1010 + + + value12 + CCU8x.INyL + #1011 + + + value13 + CCU8x.INyM + #1100 + + + value14 + CCU8x.INyN + #1101 + + + value15 + CCU8x.INyO + #1110 + + + value16 + CCU8x.INyP + #1111 + + + + + EV0EM + Event 0 Edge Selection + 16 + 17 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV1EM + Event 1 Edge Selection + 18 + 19 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV2EM + Event 2 Edge Selection + 20 + 21 + read-write + + + value1 + No action + #00 + + + value2 + Signal active on rising edge + #01 + + + value3 + Signal active on falling edge + #10 + + + value4 + Signal active on both edges + #11 + + + + + EV0LM + Event 0 Level Selection + 22 + 22 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV1LM + Event 1 Level Selection + 23 + 23 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + EV2LM + Event 2 Level Selection + 24 + 24 + read-write + + + value1 + Active on HIGH level + #0 + + + value2 + Active on LOW level + #1 + + + + + LPF0M + Event 0 Low Pass Filter Configuration + 25 + 26 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU8 + #01 + + + value3 + 5 clock cycles of fCCU8 + #10 + + + value4 + 7 clock cycles of fCCU8 + #11 + + + + + LPF1M + Event 1 Low Pass Filter Configuration + 27 + 28 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU8 + #01 + + + value3 + 5 clock cycles of fCCU8 + #10 + + + value4 + 7 clock cycles of fCCU8 + #11 + + + + + LPF2M + Event 2 Low Pass Filter Configuration + 29 + 30 + read-write + + + value1 + LPF is disabled + #00 + + + value2 + 3 clock cycles of fCCU8 + #01 + + + value3 + 5 clock cycles of fCCU8 + #10 + + + value4 + 7 clock cycles of fCCU8 + #11 + + + + + + + CMC + Connection Matrix Control + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + STRTS + External Start Functionality Selector + 0 + 1 + read-write + + + value1 + External Start Function deactivated + #00 + + + value2 + External Start Function triggered by Event 0 + #01 + + + value3 + External Start Function triggered by Event 1 + #10 + + + value4 + External Start Function triggered by Event 2 + #11 + + + + + ENDS + External Stop Functionality Selector + 2 + 3 + read-write + + + value1 + External Stop Function deactivated + #00 + + + value2 + External Stop Function triggered by Event 0 + #01 + + + value3 + External Stop Function triggered by Event 1 + #10 + + + value4 + External Stop Function triggered by Event 2 + #11 + + + + + CAP0S + External Capture 0 Functionality Selector + 4 + 5 + read-write + + + value1 + External Capture 0 Function deactivated + #00 + + + value2 + External Capture 0 Function triggered by Event 0 + #01 + + + value3 + External Capture 0 Function triggered by Event 1 + #10 + + + value4 + External Capture 0 Function triggered by Event 2 + #11 + + + + + CAP1S + External Capture 1 Functionality Selector + 6 + 7 + read-write + + + value1 + External Capture 1 Function deactivated + #00 + + + value2 + External Capture 1 Function triggered by Event 0 + #01 + + + value3 + External Capture 1 Function triggered by Event 1 + #10 + + + value4 + External Capture 1 Function triggered by Event 2 + #11 + + + + + GATES + External Gate Functionality Selector + 8 + 9 + read-write + + + value1 + External Gating Function deactivated + #00 + + + value2 + External Gating Function triggered by Event 0 + #01 + + + value3 + External Gating Function triggered by Event 1 + #10 + + + value4 + External Gating Function triggered by Event 2 + #11 + + + + + UDS + External Up/Down Functionality Selector + 10 + 11 + read-write + + + value1 + External Up/Down Function deactivated + #00 + + + value2 + External Up/Down Function triggered by Event 0 + #01 + + + value3 + External Up/Down Function triggered by Event 1 + #10 + + + value4 + External Up/Down Function triggered by Event 2 + #11 + + + + + LDS + External Timer Load Functionality Selector + 12 + 13 + read-write + + + CNTS + External Count Selector + 14 + 15 + read-write + + + value1 + External Count Function deactivated + #00 + + + value2 + External Count Function triggered by Event 0 + #01 + + + value3 + External Count Function triggered by Event 1 + #10 + + + value4 + External Count Function triggered by Event 2 + #11 + + + + + OFS + Override Function Selector + 16 + 16 + read-write + + + value1 + Override functionality disabled + #0 + + + value2 + Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 + #1 + + + + + TS + Trap Function Selector + 17 + 17 + read-write + + + value1 + Trap function disabled + #0 + + + value2 + TRAP function connected to Event 2 + #1 + + + + + MOS + External Modulation Functionality Selector + 18 + 19 + read-write + + + TCE + Timer Concatenation Enable + 20 + 20 + read-write + + + value1 + Timer concatenation is disabled + #0 + + + value2 + Timer concatenation is enabled + #1 + + + + + + + TCST + Slice Timer Status + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRB + Timer Run Bit + 0 + 0 + read-only + + + value1 + Timer is stopped + #0 + + + value2 + Timer is running + #1 + + + + + CDIR + Timer Counting Direction + 1 + 1 + read-only + + + value1 + Timer is counting up + #0 + + + value2 + Timer is counting down + #1 + + + + + DTR1 + Dead Time Counter 1 Run bit + 3 + 3 + read-only + + + value1 + Dead Time counter is idle + #0 + + + value2 + Dead Time counter is running + #1 + + + + + DTR2 + Dead Time Counter 2 Run bit + 4 + 4 + read-only + + + value1 + Dead Time counter is idle + #0 + + + value2 + Dead Time counter is running + #1 + + + + + + + TCSET + Slice Timer Run Set + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBS + Timer Run Bit set + 0 + 0 + write-only + + + + + TCCLR + Slice Timer Clear + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRBC + Timer Run Bit Clear + 0 + 0 + write-only + + + TCC + Timer Clear + 1 + 1 + write-only + + + DITC + Dither Counter Clear + 2 + 2 + write-only + + + DTC1C + Dead Time Counter 1 Clear + 3 + 3 + write-only + + + DTC2C + Dead Time Counter 2 Clear + 4 + 4 + write-only + + + + + TC + Slice Timer Control + 0x0014 + 32 + 0x18000000 + 0xFFFFFFFF + + + TCM + Timer Counting Mode + 0 + 0 + read-write + + + value1 + Edge aligned mode + #0 + + + value2 + Center aligned mode + #1 + + + + + TSSM + Timer Single Shot Mode + 1 + 1 + read-write + + + value1 + Single shot mode is disabled + #0 + + + value2 + Single shot mode is enabled + #1 + + + + + CLST + Shadow Transfer on Clear + 2 + 2 + read-write + + + CMOD + Capture Compare Mode + 3 + 3 + read-only + + + value1 + Compare Mode + #0 + + + value2 + Capture Mode + #1 + + + + + ECM + Extended Capture Mode + 4 + 4 + read-write + + + value1 + Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. + #0 + + + value2 + Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared + #1 + + + + + CAPC + Clear on Capture Control + 5 + 6 + read-write + + + value1 + Timer is never cleared on a capture event + #00 + + + value2 + Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) + #01 + + + value3 + Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) + #10 + + + value4 + Timer is always cleared in a capture event. + #11 + + + + + TLS + Timer Load selector + 7 + 7 + read-write + + + value1 + Timer is loaded with the value of CR1 + #0 + + + value2 + Timer is loaded with the value of CR2 + #1 + + + + + ENDM + Extended Stop Function Control + 8 + 9 + read-write + + + value1 + Clears the timer run bit only (default stop) + #00 + + + value2 + Clears the timer only (flush) + #01 + + + value3 + Clears the timer and run bit (flush/stop) + #10 + + + + + STRM + Extended Start Function Control + 10 + 10 + read-write + + + value1 + Sets run bit only (default start) + #0 + + + value2 + Clears the timer and sets run bit, if not set (flush/start) + #1 + + + + + SCE + Equal Capture Event enable + 11 + 11 + read-write + + + value1 + Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #0 + + + value2 + Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 + #1 + + + + + CCS + Continuous Capture Enable + 12 + 12 + read-write + + + value1 + The capture into a specific capture register is done with the rules linked with the full flags, described at . + #0 + + + value2 + The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). + #1 + + + + + DITHE + Dither Enable + 13 + 14 + read-write + + + value1 + Dither is disabled + #00 + + + value2 + Dither is applied to the Period + #01 + + + value3 + Dither is applied to the Compare + #10 + + + value4 + Dither is applied to the Period and Compare + #11 + + + + + DIM + Dither input selector + 15 + 15 + read-write + + + value1 + Slice is using it own dither unit + #0 + + + value2 + Slice is connected to the dither unit of slice 0. + #1 + + + + + FPE + Floating Prescaler enable + 16 + 16 + read-write + + + value1 + Floating prescaler mode is disabled + #0 + + + value2 + Floating prescaler mode is enabled + #1 + + + + + TRAPE0 + TRAP enable for CCU8x.OUTy0 + 17 + 17 + read-write + + + value1 + TRAP functionality has no effect on the CCU8x.OUTy0 output + #0 + + + value2 + TRAP functionality affects the CCU8x.OUTy0 output + #1 + + + + + TRAPE1 + TRAP enable for CCU8x.OUTy1 + 18 + 18 + read-write + + + TRAPE2 + TRAP enable for CCU8x.OUTy2 + 19 + 19 + read-write + + + TRAPE3 + TRAP enable for CCU8x.OUTy3 + 20 + 20 + read-write + + + TRPSE + TRAP Synchronization Enable + 21 + 21 + read-write + + + value1 + Exiting from TRAP state isn't synchronized with the PWM signal + #0 + + + value2 + Exiting from TRAP state is synchronized with the PWM signal + #1 + + + + + TRPSW + TRAP State Clear Control + 22 + 22 + read-write + + + value1 + The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW) + #0 + + + value2 + The TRAP state can only be exited by a SW request. + #1 + + + + + EMS + External Modulation Synchronization + 23 + 23 + read-write + + + value1 + External Modulation functionality is not synchronized with the PWM signal + #0 + + + value2 + External Modulation functionality is synchronized with the PWM signal + #1 + + + + + EMT + External Modulation Type + 24 + 24 + read-write + + + value1 + External Modulation functionality is clearing the CC8ySTx bits. + #0 + + + value2 + External Modulation functionality is gating the outputs. + #1 + + + + + MCME1 + Multi Channel Mode Enable for Channel 1 + 25 + 25 + read-write + + + value1 + Multi Channel Mode in Channel 1 is disabled + #0 + + + value2 + Multi Channel Mode in Channel 1 is enabled + #1 + + + + + MCME2 + Multi Channel Mode Enable for Channel 2 + 26 + 26 + read-write + + + value1 + Multi Channel Mode in Channel 2 is disabled + #0 + + + value2 + Multi Channel Mode in Channel 2 is enabled + #1 + + + + + EME + External Modulation Channel enable + 27 + 28 + read-write + + + value1 + External Modulation functionality doesn't affect any channel + #00 + + + value2 + External Modulation only applied on channel 1 + #01 + + + value3 + External Modulation only applied on channel 2 + #10 + + + value4 + External Modulation applied on both channels + #11 + + + + + STOS + Status bit output selector + 29 + 30 + read-write + + + value1 + CC8yST1 forward to CCU8x.STy + #00 + + + value2 + CC8yST2 forward to CCU8x.STy + #01 + + + value3 + CC8yST1 AND CC8yST2 forward to CCU8x.STy + #10 + + + value4 + CC8yST1 OR CC8yST2 forward to CCU8x.STy + #11 + + + + + + + PSL + Passive Level Config + 0x0018 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSL11 + Output Passive Level for CCU8x.OUTy0 + 0 + 0 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + PSL12 + Output Passive Level for CCU8x.OUTy1 + 1 + 1 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + PSL21 + Output Passive Level for CCU8x.OUTy2 + 2 + 2 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + PSL22 + Output Passive Level for CCU8x.OUTy3 + 3 + 3 + read-write + + + value1 + Passive Level is LOW + #0 + + + value2 + Passive Level is HIGH + #1 + + + + + + + DIT + Dither Config + 0x001C + 32 + 0x00000000 + 0xFFFFFFFF + + + DCV + Dither compare Value + 0 + 3 + read-only + + + DCNT + Dither counter actual value + 8 + 11 + read-only + + + + + DITS + Dither Shadow Register + 0x0020 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCVS + Dither Shadow Compare Value + 0 + 3 + read-write + + + + + PSC + Prescaler Control + 0x0024 + 32 + 0x00000000 + 0xFFFFFFFF + + + PSIV + Prescaler Initial Value + 0 + 3 + read-write + + + + + FPC + Floating Prescaler Control + 0x0028 + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Compare Value + 0 + 3 + read-only + + + PVAL + Actual Prescaler Value + 8 + 11 + read-write + + + + + FPCS + Floating Prescaler Shadow + 0x002C + 32 + 0x00000000 + 0xFFFFFFFF + + + PCMP + Floating Prescaler Shadow Compare Value + 0 + 3 + read-write + + + + + PR + Timer Period Value + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + PR + Period Register + 0 + 15 + read-only + + + + + PRS + Timer Shadow Period Value + 0x0034 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRS + Period Register + 0 + 15 + read-write + + + + + CR1 + Channel 1 Compare Value + 0x0038 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR1 + Compare Register for Channel 1 + 0 + 15 + read-only + + + + + CR1S + Channel 1 Compare Shadow Value + 0x003C + 32 + 0x00000000 + 0xFFFFFFFF + + + CR1S + Shadow Compare Register for Channel 1 + 0 + 15 + read-write + + + + + CR2 + Channel 2 Compare Value + 0x0040 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR2 + Compare Register for Channel 2 + 0 + 15 + read-only + + + + + CR2S + Channel 2 Compare Shadow Value + 0x0044 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR2S + Shadow Compare Register for Channel 2 + 0 + 15 + read-write + + + + + CHC + Channel Control + 0x0048 + 32 + 0x00000000 + 0xFFFFFFFF + + + ASE + Asymmetric PWM mode Enable + 0 + 0 + read-write + + + value1 + Asymmetric PWM is disabled + #0 + + + value2 + Asymmetric PWM is enabled + #1 + + + + + OCS1 + Output selector for CCU8x.OUTy0 + 1 + 1 + read-write + + + value1 + CC8yST1 signal path is connected to the CCU8x.OUTy0 + #0 + + + value2 + Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0 + #1 + + + + + OCS2 + Output selector for CCU8x.OUTy1 + 2 + 2 + read-write + + + value1 + Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1 + #0 + + + value2 + CC8yST1 signal path is connected to the CCU8x.OUTy1 + #1 + + + + + OCS3 + Output selector for CCU8x.OUTy2 + 3 + 3 + read-write + + + value1 + CC8yST2 signal path is connected to the CCU8x.OUTy2 + #0 + + + value2 + Inverted CCST2 signal path is connected to the CCU8x.OUTy2 + #1 + + + + + OCS4 + Output selector for CCU8x.OUTy3 + 4 + 4 + read-write + + + value1 + Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3 + #0 + + + value2 + CC8yST2 signal path is connected to the CCU8x.OUTy3 + #1 + + + + + + + DTC + Dead Time Control + 0x004C + 32 + 0x00000000 + 0xFFFFFFFF + + + DTE1 + Dead Time Enable for Channel 1 + 0 + 0 + read-write + + + value1 + Dead Time for channel 1 is disabled + #0 + + + value2 + Dead Time for channel 1 is enabled + #1 + + + + + DTE2 + Dead Time Enable for Channel 2 + 1 + 1 + read-write + + + value1 + Dead Time for channel 2 is disabled + #0 + + + value2 + Dead Time for channel 2 is enabled + #1 + + + + + DCEN1 + Dead Time Enable for CC8yST1 + 2 + 2 + read-write + + + value1 + Dead Time for CC8yST1 path is disabled + #0 + + + value2 + Dead Time for CC8yST1 path is enabled + #1 + + + + + DCEN2 + Dead Time Enable for inverted CC8yST1 + 3 + 3 + read-write + + + value1 + Dead Time for inverted CC8yST1 path is disabled + #0 + + + value2 + Dead Time for inverted CC8yST1 path is enabled + #1 + + + + + DCEN3 + Dead Time Enable for CC8yST2 + 4 + 4 + read-write + + + value1 + Dead Time for CC8yST2 path is disabled + #0 + + + value2 + Dead Time for CC8yST2 path is enabled + #1 + + + + + DCEN4 + Dead Time Enable for inverted CC8yST2 + 5 + 5 + read-write + + + value1 + Dead Time for inverted CC8yST2 path is disabled + #0 + + + value2 + Dead Time for inverted CC8yST2 path is enabled + #1 + + + + + DTCC + Dead Time clock control + 6 + 7 + read-write + + + value1 + ftclk + #00 + + + value2 + ftclk/2 + #01 + + + value3 + ftclk/4 + #10 + + + value4 + ftclk/8 + #11 + + + + + + + DC1R + Channel 1 Dead Time Values + 0x0050 + 32 + 0x00000000 + 0xFFFFFFFF + + + DT1R + Rise Value for Dead Time of Channel 1 + 0 + 7 + read-write + + + DT1F + Fall Value for Dead Time of Channel 1 + 8 + 15 + read-write + + + + + DC2R + Channel 2 Dead Time Values + 0x0054 + 32 + 0x00000000 + 0xFFFFFFFF + + + DT2R + Rise Value for Dead Time of Channel 2 + 0 + 7 + read-write + + + DT2F + Fall Value for Dead Time of Channel 2 + 8 + 15 + read-write + + + + + TIMER + Timer Value + 0x0070 + 32 + 0x00000000 + 0xFFFFFFFF + + + TVAL + Timer Value + 0 + 15 + read-write + + + + + C0V + Capture Register 0 + 0x0074 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C1V + Capture Register 1 + 0x0078 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C2V + Capture Register 2 + 0x007C + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + C3V + Capture Register 3 + 0x0080 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPTV + Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Value + 16 + 19 + read-only + + + FFL + Full Flag + 20 + 20 + read-only + + + value1 + No new value was captured into the specific capture register + #0 + + + value2 + A new value was captured into the specific register + #1 + + + + + + + INTS + Interrupt Status + 0x00A0 + 32 + 0x00000000 + 0xFFFFFFFF + + + PMUS + Period Match while Counting Up + 0 + 0 + read-only + + + value1 + Period match while counting up not detected + #0 + + + value2 + Period match while counting up detected + #1 + + + + + OMDS + One Match while Counting Down + 1 + 1 + read-only + + + value1 + One match while counting down not detected + #0 + + + value2 + One match while counting down detected + #1 + + + + + CMU1S + Channel 1 Compare Match while Counting Up + 2 + 2 + read-only + + + value1 + Compare match while counting up not detected + #0 + + + value2 + Compare match while counting up detected + #1 + + + + + CMD1S + Channel 1 Compare Match while Counting Down + 3 + 3 + read-only + + + value1 + Compare match while counting down not detected + #0 + + + value2 + Compare match while counting down detected + #1 + + + + + CMU2S + Channel 2 Compare Match while Counting Up + 4 + 4 + read-only + + + value1 + Compare match while counting up not detected + #0 + + + value2 + Compare match while counting up detected + #1 + + + + + CMD2S + Channel 2 Compare Match while Counting Down + 5 + 5 + read-only + + + value1 + Compare match while counting down not detected + #0 + + + value2 + Compare match while counting down detected + #1 + + + + + E0AS + Event 0 Detection Status + 8 + 8 + read-only + + + value1 + Event 0 not detected + #0 + + + value2 + Event 0 detected + #1 + + + + + E1AS + Event 1 Detection Status + 9 + 9 + read-only + + + value1 + Event 1 not detected + #0 + + + value2 + Event 1 detected + #1 + + + + + E2AS + Event 2 Detection Status + 10 + 10 + read-only + + + value1 + Event 2 not detected + #0 + + + value2 + Event 2 detected + #1 + + + + + TRPF + Trap Flag Status + 11 + 11 + read-only + + + + + INTE + Interrupt Enable Control + 0x00A4 + 32 + 0x00000000 + 0xFFFFFFFF + + + PME + Period match while counting up enable + 0 + 0 + read-write + + + value1 + Period Match interrupt is disabled + #0 + + + value2 + Period Match interrupt is enabled + #1 + + + + + OME + One match while counting down enable + 1 + 1 + read-write + + + value1 + One Match interrupt is disabled + #0 + + + value2 + One Match interrupt is enabled + #1 + + + + + CMU1E + Channel 1 Compare match while counting up enable + 2 + 2 + read-write + + + value1 + Compare Match while counting up interrupt is disabled + #0 + + + value2 + Compare Match while counting up interrupt is enabled + #1 + + + + + CMD1E + Channel 1 Compare match while counting down enable + 3 + 3 + read-write + + + value1 + Compare Match while counting down interrupt is disabled + #0 + + + value2 + Compare Match while counting down interrupt is enabled + #1 + + + + + CMU2E + Channel 2 Compare match while counting up enable + 4 + 4 + read-write + + + value1 + Compare Match while counting up interrupt is disabled + #0 + + + value2 + Compare Match while counting up interrupt is enabled + #1 + + + + + CMD2E + Channel 2 Compare match while counting down enable + 5 + 5 + read-write + + + value1 + Compare Match while counting down interrupt is disabled + #0 + + + value2 + Compare Match while counting down interrupt is enabled + #1 + + + + + E0AE + Event 0 interrupt enable + 8 + 8 + read-write + + + value1 + Event 0 detection interrupt is disabled + #0 + + + value2 + Event 0 detection interrupt is enabled + #1 + + + + + E1AE + Event 1 interrupt enable + 9 + 9 + read-write + + + value1 + Event 1 detection interrupt is disabled + #0 + + + value2 + Event 1 detection interrupt is enabled + #1 + + + + + E2AE + Event 2 interrupt enable + 10 + 10 + read-write + + + value1 + Event 2 detection interrupt is disabled + #0 + + + value2 + Event 2 detection interrupt is enabled + #1 + + + + + + + SRS + Service Request Selector + 0x00A8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSR + Period/One match Service request selector + 0 + 1 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + CM1SR + Channel 1 Compare match Service request selector + 2 + 3 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + CM2SR + Channel 2 Compare match Service request selector + 4 + 5 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + E0SR + Event 0 Service request selector + 8 + 9 + read-write + + + value1 + Forward to CCvySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + E1SR + Event 1 Service request selector + 10 + 11 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CC8ySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + E2SR + Event 2 Service request selector + 12 + 13 + read-write + + + value1 + Forward to CC8ySR0 + #00 + + + value2 + Forward to CCvySR1 + #01 + + + value3 + Forward to CC8ySR2 + #10 + + + value4 + Forward to CC8ySR3 + #11 + + + + + + + SWS + Interrupt Status Set + 0x00AC + 32 + 0x00000000 + 0xFFFFFFFF + + + SPM + Period match while counting up set + 0 + 0 + write-only + + + SOM + One match while counting down set + 1 + 1 + write-only + + + SCM1U + Channel 1 Compare match while counting up set + 2 + 2 + write-only + + + SCM1D + Channel 1 Compare match while counting down set + 3 + 3 + write-only + + + SCM2U + Compare match while counting up set + 4 + 4 + write-only + + + SCM2D + Compare match while counting down set + 5 + 5 + write-only + + + SE0A + Event 0 detection set + 8 + 8 + write-only + + + SE1A + Event 1 detection set + 9 + 9 + write-only + + + SE2A + Event 2 detection set + 10 + 10 + write-only + + + STRPF + Trap Flag status set + 11 + 11 + write-only + + + + + SWR + Interrupt Status Clear + 0x00B0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPM + Period match while counting up clear + 0 + 0 + write-only + + + ROM + One match while counting down clear + 1 + 1 + write-only + + + RCM1U + Channel 1 Compare match while counting up clear + 2 + 2 + write-only + + + RCM1D + Channel 1 Compare match while counting down clear + 3 + 3 + write-only + + + RCM2U + Channel 2 Compare match while counting up clear + 4 + 4 + write-only + + + RCM2D + Channel 2 Compare match while counting down clear + 5 + 5 + write-only + + + RE0A + Event 0 detection clear + 8 + 8 + write-only + + + RE1A + Event 1 detection clear + 9 + 9 + write-only + + + RE2A + Event 2 detection clear + 10 + 10 + write-only + + + RTRPF + Trap Flag status clear + 11 + 11 + write-only + + + + + STC + Shadow transfer control + 0x00B4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CSE + Cascaded shadow transfer enable + 0 + 0 + read-write + + + value1 + Cascaded shadow transfer disabled + #0 + + + value2 + Cascaded shadow transfer enabled + #1 + + + + + STM + Shadow transfer mode + 1 + 2 + read-write + + + value1 + Shadow transfer is done in Period Match and One match. + #00 + + + value2 + Shadow transfer is done only in Period Match. + #01 + + + value3 + Shadow transfer is done only in One Match. + #10 + + + + + + + ECRD0 + Extended Read Back 0 + 0x00B8 + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC80 + #00 + + + value2 + CC81 + #01 + + + value3 + CC82 + #10 + + + value4 + CC83 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + ECRD1 + Extended Read Back 1 + 0x00BC + 32 + 0x00000000 + 0xFFFFFFFF + modifyExternal + + + CAPV + Timer Capture Value + 0 + 15 + read-only + + + FPCV + Prescaler Capture value + 16 + 19 + read-only + + + SPTR + Slice pointer + 20 + 21 + read-only + + + value1 + CC80 + #00 + + + value2 + CC81 + #01 + + + value3 + CC82 + #10 + + + value4 + CC83 + #11 + + + + + VPTR + Capture register pointer + 22 + 23 + read-only + + + value1 + Capture register 0 + #00 + + + value2 + Capture register 1 + #01 + + + value3 + Capture register 2 + #10 + + + value4 + Capture register 3 + #11 + + + + + FFL + Full Flag + 24 + 24 + read-only + + + value1 + No new value was captured into this register + #0 + + + value2 + A new value has been captured into this register + #1 + + + + + LCV + Lost Capture Value + 25 + 25 + read-only + + + value1 + No capture was lost + #0 + + + value2 + A capture was lost + #1 + + + + + + + + + CCU80_CC81 + Capture Compare Unit 8 - Unit 0 + CCU8 + 0x40020200 + + 0x0 + 0x100 + registers + + + + CCU80_CC82 + Capture Compare Unit 8 - Unit 0 + CCU8 + 0x40020300 + + 0x0 + 0x100 + registers + + + + CCU80_CC83 + Capture Compare Unit 8 - Unit 0 + CCU8 + 0x40020400 + + 0x0 + 0x100 + registers + + + + CCU81_CC80 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024100 + + 0x0 + 0x100 + registers + + + + CCU81_CC81 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024200 + + 0x0 + 0x100 + registers + + + + CCU81_CC82 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024300 + + 0x0 + 0x100 + registers + + + + CCU81_CC83 + Capture Compare Unit 8 - Unit 1 + CCU8 + 0x40024400 + + 0x0 + 0x100 + registers + + + + POSIF0 + Position Interface 0 + POSIF + POSIF + 0x40028000 + + 0x0 + 0x4000 + registers + + + POSIF0_0 + Position Interface (Module 0) + 68 + + + POSIF0_1 + Position Interface (Module 0) + 69 + + + + PCONF + POSIF configuration + 0x0000 + 32 + 0x00000000 + 0xFFFFFFFF + + + FSEL + Function Selector + 0 + 1 + read-write + + + value1 + Hall Sensor Mode enabled + #00 + + + value2 + Quadrature Decoder Mode enabled + #01 + + + value3 + stand-alone Multi-Channel Mode enabled + #10 + + + value4 + Quadrature Decoder and stand-alone Multi-Channel Mode enabled + #11 + + + + + QDCM + Position Decoder Mode selection + 2 + 2 + read-write + + + value1 + Position encoder is in Quadrature Mode + #0 + + + value2 + Position encoder is in Direction Count Mode. + #1 + + + + + HIDG + Idle generation enable + 4 + 4 + read-write + + + MCUE + Multi-Channel Pattern SW update enable + 5 + 5 + read-write + + + value1 + Multi-Channel pattern update is controlled via HW + #0 + + + value2 + Multi-Channel pattern update is controlled via SW + #1 + + + + + INSEL0 + PhaseA/Hal input 1 selector + 8 + 9 + read-write + + + value1 + POSIFx.IN0A + #00 + + + value2 + POSIFx.IN0B + #01 + + + value3 + POSIFx.IN0C + #10 + + + value4 + POSIFx.IN0D + #11 + + + + + INSEL1 + PhaseB/Hall input 2 selector + 10 + 11 + read-write + + + value1 + POSIFx.IN1A + #00 + + + value2 + POSIFx.IN1B + #01 + + + value3 + POSIFx.IN1C + #10 + + + value4 + POSIFx.IN1D + #11 + + + + + INSEL2 + Index/Hall input 3 selector + 12 + 13 + read-write + + + value1 + POSIFx.IN2A + #00 + + + value2 + POSIFx.IN2B + #01 + + + value3 + POSIFx.IN2C + #10 + + + value4 + POSIFx.IN2D + #11 + + + + + DSEL + Delay Pin selector + 16 + 16 + read-write + + + value1 + POSIFx.HSDA + #0 + + + value2 + POSIFx.HSDB + #1 + + + + + SPES + Edge selector for the sampling trigger + 17 + 17 + read-write + + + value1 + Rising edge + #0 + + + value2 + Falling edge + #1 + + + + + MSETS + Pattern update signal select + 18 + 20 + read-write + + + value1 + POSIFx.MSETA + #000 + + + value2 + POSIFx.MSETB + #001 + + + value3 + POSIFx.MSETC + #010 + + + value4 + POSIFx.MSETD + #011 + + + value5 + POSIFx.MSETE + #100 + + + value6 + POSIFx.MSETF + #101 + + + value7 + POSIFx.MSETG + #110 + + + value8 + POSIFx.MSETH + #111 + + + + + MSES + Multi-Channel pattern update trigger edge + 21 + 21 + read-write + + + value1 + The signal used to enable a pattern update is active on the rising edge + #0 + + + value2 + The signal used to enable a pattern update is active on the falling edge + #1 + + + + + MSYNS + PWM synchronization signal selector + 22 + 23 + read-write + + + value1 + POSIFx.MSYNCA + #00 + + + value2 + POSIFx.MSYNCB + #01 + + + value3 + POSIFx.MSYNCC + #10 + + + value4 + POSIFx.MSYNCD + #11 + + + + + EWIS + Wrong Hall Event selection + 24 + 25 + read-write + + + value1 + POSIFx.EWHEA + #00 + + + value2 + POSIFx.EWHEB + #01 + + + value3 + POSIFx.EWHEC + #10 + + + value4 + POSIFx.EWHED + #11 + + + + + EWIE + External Wrong Hall Event enable + 26 + 26 + read-write + + + value1 + External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled + #0 + + + value2 + External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled. + #1 + + + + + EWIL + External Wrong Hall Event active level + 27 + 27 + read-write + + + value1 + POSIFx.EWHE[D...A] signal is active HIGH + #0 + + + value2 + POSIFx.EWHE[D...A] signal is active LOW + #1 + + + + + LPC + Low Pass Filters Configuration + 28 + 30 + read-write + + + value1 + Low pass filter disabled + #000 + + + value2 + Low pass of 1 clock cycle + #001 + + + value3 + Low pass of 2 clock cycles + #010 + + + value4 + Low pass of 4 clock cycles + #011 + + + value5 + Low pass of 8 clock cycles + #100 + + + value6 + Low pass of 16 clock cycles + #101 + + + value7 + Low pass of 32 clock cycles + #110 + + + value8 + Low pass of 64 clock cycles + #111 + + + + + + + PSUS + POSIF Suspend Config + 0x0004 + 32 + 0x00000000 + 0xFFFFFFFF + + + QSUS + Quadrature Mode Suspend Config + 0 + 1 + read-write + + + value1 + Suspend request ignored + #00 + + + value2 + Stop immediately + #01 + + + value3 + Suspend in the next index occurrence + #10 + + + value4 + Suspend in the next phase (PhaseA or PhaseB) occurrence + #11 + + + + + MSUS + Multi-Channel Mode Suspend Config + 2 + 3 + read-write + + + value1 + Suspend request ignored + #00 + + + value2 + Stop immediately. Multi-Channel pattern is not set to the reset value. + #01 + + + value3 + Stop immediately. Multi-Channel pattern is set to the reset value. + #10 + + + value4 + Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization. + #11 + + + + + + + PRUNS + POSIF Run Bit Set + 0x0008 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRB + Set Run bit + 0 + 0 + write-only + + + + + PRUNC + POSIF Run Bit Clear + 0x000C + 32 + 0x00000000 + 0xFFFFFFFF + + + CRB + Clear Run bit + 0 + 0 + write-only + + + CSM + Clear Current internal status + 1 + 1 + write-only + + + + + PRUN + POSIF Run Bit Status + 0x0010 + 32 + 0x00000000 + 0xFFFFFFFF + + + RB + Run Bit + 0 + 0 + read-only + + + value1 + IDLE + #0 + + + value2 + Running + #1 + + + + + + + MIDR + Module Identification register + 0x0020 + 32 + 0x00A8C000 + 0xFFFFFF00 + + + MODR + Module Revision + 0 + 7 + read-only + + + MODT + Module Type + 8 + 15 + read-only + + + MODN + Module Number + 16 + 31 + read-only + + + + + HALP + Hall Sensor Patterns + 0x0030 + 32 + 0x00000000 + 0xFFFFFFFF + + + HCP + Hall Current Pattern + 0 + 2 + read-only + + + HEP + Hall Expected Pattern + 3 + 5 + read-only + + + + + HALPS + Hall Sensor Shadow Patterns + 0x0034 + 32 + 0x00000000 + 0xFFFFFFFF + + + HCPS + Shadow Hall Current Pattern + 0 + 2 + read-write + + + HEPS + Shadow Hall expected Pattern + 3 + 5 + read-write + + + + + MCM + Multi-Channel Pattern + 0x0040 + 32 + 0x00000000 + 0xFFFFFFFF + + + MCMP + Multi-Channel Pattern + 0 + 15 + read-only + + + + + MCSM + Multi-Channel Shadow Pattern + 0x0044 + 32 + 0x00000000 + 0xFFFFFFFF + + + MCMPS + Shadow Multi-Channel Pattern + 0 + 15 + read-write + + + + + MCMS + Multi-Channel Pattern Control set + 0x0048 + 32 + 0x00000000 + 0xFFFFFFFF + + + MNPS + Multi-Channel Pattern Update Enable Set + 0 + 0 + write-only + + + STHR + Hall Pattern Shadow Transfer Request + 1 + 1 + write-only + + + STMR + Multi-Channel Shadow Transfer Request + 2 + 2 + write-only + + + + + MCMC + Multi-Channel Pattern Control clear + 0x004C + 32 + 0x00000000 + 0xFFFFFFFF + + + MNPC + Multi-Channel Pattern Update Enable Clear + 0 + 0 + write-only + + + MPC + Multi-Channel Pattern clear + 1 + 1 + write-only + + + + + MCMF + Multi-Channel Pattern Control flag + 0x0050 + 32 + 0x00000000 + 0xFFFFFFFF + + + MSS + Multi-Channel Pattern update status + 0 + 0 + read-only + + + value1 + Update of the Multi-Channel pattern is set + #0 + + + value2 + Update of the Multi-Channel pattern is not set + #1 + + + + + + + QDC + Quadrature Decoder Control + 0x0060 + 32 + 0x00000000 + 0xFFFFFFFF + + + PALS + Phase A Level selector + 0 + 0 + read-write + + + value1 + Phase A is active HIGH + #0 + + + value2 + Phase A is active LOW + #1 + + + + + PBLS + Phase B Level selector + 1 + 1 + read-write + + + value1 + Phase B is active HIGH + #0 + + + value2 + Phase B is active LOW + #1 + + + + + PHS + Phase signals swap + 2 + 2 + read-write + + + value1 + Phase A is the leading signal for clockwise rotation + #0 + + + value2 + Phase B is the leading signal for clockwise rotation + #1 + + + + + ICM + Index Marker generations control + 4 + 5 + read-write + + + value1 + No index marker generation on POSIFx.OUT3 + #00 + + + value2 + Only first index occurrence generated on POSIFx.OUT3 + #01 + + + value3 + All index occurrences generated on POSIFx.OUT3 + #10 + + + + + DVAL + Current rotation direction + 8 + 8 + read-only + + + value1 + Counterclockwise rotation + #0 + + + value2 + Clockwise rotation + #1 + + + + + + + PFLG + POSIF Interrupt Flags + 0x0070 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHES + Correct Hall Event Status + 0 + 0 + read-only + + + value1 + Correct Hall Event not detected + #0 + + + value2 + Correct Hall Event detected + #1 + + + + + WHES + Wrong Hall Event Status + 1 + 1 + read-only + + + value1 + Wrong Hall Event not detected + #0 + + + value2 + Wrong Hall Event detected + #1 + + + + + HIES + Hall Inputs Update Status + 2 + 2 + read-only + + + value1 + Transition on the Hall Inputs not detected + #0 + + + value2 + Transition on the Hall Inputs detected + #1 + + + + + MSTS + Multi-Channel pattern shadow transfer status + 4 + 4 + read-only + + + value1 + Shadow transfer not done + #0 + + + value2 + Shadow transfer done + #1 + + + + + INDXS + Quadrature Index Status + 8 + 8 + read-only + + + value1 + Index event not detected + #0 + + + value2 + Index event detected + #1 + + + + + ERRS + Quadrature Phase Error Status + 9 + 9 + read-only + + + value1 + Phase Error event not detected + #0 + + + value2 + Phase Error event detected + #1 + + + + + CNTS + Quadrature CLK Status + 10 + 10 + read-only + + + value1 + Quadrature clock not generated + #0 + + + value2 + Quadrature clock generated + #1 + + + + + DIRS + Quadrature Direction Change + 11 + 11 + read-only + + + value1 + Change on direction not detected + #0 + + + value2 + Change on direction detected + #1 + + + + + PCLKS + Quadrature Period Clk Status + 12 + 12 + read-only + + + value1 + Period clock not generated + #0 + + + value2 + Period clock generated + #1 + + + + + + + PFLGE + POSIF Interrupt Enable + 0x0074 + 32 + 0x00000000 + 0xFFFFFFFF + + + ECHE + Correct Hall Event Enable + 0 + 0 + read-write + + + value1 + Correct Hall Event interrupt disabled + #0 + + + value2 + Correct Hall Event interrupt enabled + #1 + + + + + EWHE + Wrong Hall Event Enable + 1 + 1 + read-write + + + value1 + Wrong Hall Event interrupt disabled + #0 + + + value2 + Wrong Hall Event interrupt enabled + #1 + + + + + EHIE + Hall Input Update Enable + 2 + 2 + read-write + + + value1 + Update of the Hall Inputs interrupt is disabled + #0 + + + value2 + Update of the Hall Inputs interrupt is enabled + #1 + + + + + EMST + Multi-Channel pattern shadow transfer enable + 4 + 4 + read-write + + + value1 + Shadow transfer event interrupt disabled + #0 + + + value2 + Shadow transfer event interrupt enabled + #1 + + + + + EINDX + Quadrature Index Event Enable + 8 + 8 + read-write + + + value1 + Index event interrupt disabled + #0 + + + value2 + Index event interrupt enabled + #1 + + + + + EERR + Quadrature Phase Error Enable + 9 + 9 + read-write + + + value1 + Phase error event interrupt disabled + #0 + + + value2 + Phase error event interrupt enabled + #1 + + + + + ECNT + Quadrature CLK interrupt Enable + 10 + 10 + read-write + + + value1 + Quadrature CLK event interrupt disabled + #0 + + + value2 + Quadrature CLK event interrupt enabled + #1 + + + + + EDIR + Quadrature direction change interrupt Enable + 11 + 11 + read-write + + + value1 + Direction change event interrupt disabled + #0 + + + value2 + Direction change event interrupt enabled + #1 + + + + + EPCLK + Quadrature Period CLK interrupt Enable + 12 + 12 + read-write + + + value1 + Quadrature Period CLK event interrupt disabled + #0 + + + value2 + Quadrature Period CLK event interrupt enabled + #1 + + + + + CHESEL + Correct Hall Event Service Request Selector + 16 + 16 + read-write + + + value1 + Correct Hall Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Correct Hall Event interrupt forward to POSIFx.SR1 + #1 + + + + + WHESEL + Wrong Hall Event Service Request Selector + 17 + 17 + read-write + + + value1 + Wrong Hall Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Wrong Hall Event interrupt forward to POSIFx.SR1 + #1 + + + + + HIESEL + Hall Inputs Update Event Service Request Selector + 18 + 18 + read-write + + + value1 + Hall Inputs Update Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Hall Inputs Update Event interrupt forward to POSIFx.SR1 + #1 + + + + + MSTSEL + Multi-Channel pattern Update Event Service Request Selector + 20 + 20 + read-write + + + value1 + Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1 + #1 + + + + + INDSEL + Quadrature Index Event Service Request Selector + 24 + 24 + read-write + + + value1 + Quadrature Index Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Index Event interrupt forward to POSIFx.SR1 + #1 + + + + + ERRSEL + Quadrature Phase Error Event Service Request Selector + 25 + 25 + read-write + + + value1 + Quadrature Phase error Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Phase error Event interrupt forward to POSIFx.SR1 + #1 + + + + + CNTSEL + Quadrature Clock Event Service Request Selector + 26 + 26 + read-write + + + value1 + Quadrature Clock Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Clock Event interrupt forward to POSIFx.SR1 + #1 + + + + + DIRSEL + Quadrature Direction Update Event Service Request Selector + 27 + 27 + read-write + + + value1 + Quadrature Direction Update Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Direction Update Event interrupt forward to POSIFx.SR1 + #1 + + + + + PCLSEL + Quadrature Period clock Event Service Request Selector + 28 + 28 + read-write + + + value1 + Quadrature Period clock Event interrupt forward to POSIFx.SR0 + #0 + + + value2 + Quadrature Period clock Event interrupt forward to POSIFx.SR1 + #1 + + + + + + + SPFLG + POSIF Interrupt Set + 0x0078 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCHE + Correct Hall Event flag set + 0 + 0 + write-only + + + SWHE + Wrong Hall Event flag set + 1 + 1 + write-only + + + SHIE + Hall Inputs Update Event flag set + 2 + 2 + write-only + + + SMST + Multi-Channel Pattern shadow transfer flag set + 4 + 4 + write-only + + + SINDX + Quadrature Index flag set + 8 + 8 + write-only + + + SERR + Quadrature Phase Error flag set + 9 + 9 + write-only + + + SCNT + Quadrature CLK flag set + 10 + 10 + write-only + + + SDIR + Quadrature Direction flag set + 11 + 11 + write-only + + + SPCLK + Quadrature period clock flag set + 12 + 12 + write-only + + + + + RPFLG + POSIF Interrupt Clear + 0x007C + 32 + 0x00000000 + 0xFFFFFFFF + + + RCHE + Correct Hall Event flag clear + 0 + 0 + write-only + + + RWHE + Wrong Hall Event flag clear + 1 + 1 + write-only + + + RHIE + Hall Inputs Update Event flag clear + 2 + 2 + write-only + + + RMST + Multi-Channel Pattern shadow transfer flag clear + 4 + 4 + write-only + + + RINDX + Quadrature Index flag clear + 8 + 8 + write-only + + + RERR + Quadrature Phase Error flag clear + 9 + 9 + write-only + + + RCNT + Quadrature CLK flag clear + 10 + 10 + write-only + + + RDIR + Quadrature Direction flag clear + 11 + 11 + write-only + + + RPCLK + Quadrature period clock flag clear + 12 + 12 + write-only + + + + + PDBG + POSIF Debug register + 0x0100 + 32 + 0x00000000 + 0xFFFFFFFF + + + QCSV + Quadrature Decoder Current state + 0 + 1 + read-only + + + QPSV + Quadrature Decoder Previous state + 2 + 3 + read-only + + + IVAL + Current Index Value + 4 + 4 + read-only + + + HSP + Hall Current Sampled Pattern + 5 + 7 + read-only + + + LPP0 + Actual count of the Low Pass Filter for POSI0 + 8 + 13 + read-only + + + LPP1 + Actual count of the Low Pass Filter for POSI1 + 16 + 21 + read-only + + + LPP2 + Actual count of the Low Pass Filter for POSI2 + 22 + 27 + read-only + + + + + + + POSIF1 + Position Interface 1 + POSIF + 0x4002C000 + + 0x0 + 0x4000 + registers + + + POSIF1_0 + Position Interface (Module 1) + 70 + + + POSIF1_1 + Position Interface (Module 1) + 71 + + + + PORT0 + Port 0 + PORTS + 0x48028000 + + 0x0 + 0x0100 + registers + + + + OUT + Port 0 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 0 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 0 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 0 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 0 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 0 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 0 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 0 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDR1 + Port 0 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDISC + Port 0 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 0 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 0 Pin Hardware Select Register + 0x74 + 32 + 0x00014000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT1 + Port 1 + PORTS + 0x48028100 + + 0x0 + 0x0100 + registers + + + + OUT + Port 1 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 1 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 1 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 1 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 1 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 1 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 1 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 1 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDR1 + Port 1 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 1 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 1 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 1 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT2 + Port 2 + PORTS + 0x48028200 + + 0x0 + 0x0100 + registers + + + + OUT + Port 2 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 2 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 2 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 2 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 2 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 2 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 2 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 2 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 2 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 2 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 2 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 2 Pin Hardware Select Register + 0x74 + 32 + 0x00000004 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT3 + Port 3 + PORTS + 0x48028300 + + 0x0 + 0x0100 + registers + + + + OUT + Port 3 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 3 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 3 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 3 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 3 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 3 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 3 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 3 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 3 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDISC + Port 3 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 3 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 3 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT4 + Port 4 + PORTS + 0x48028400 + + 0x0 + 0x0100 + registers + + + + OUT + Port 4 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 4 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 4 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 4 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 4 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 4 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDISC + Port 4 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 4 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 4 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT5 + Port 5 + PORTS + 0x48028500 + + 0x0 + 0x0100 + registers + + + + OUT + Port 5 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 5 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 5 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 5 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 5 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 5 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 5 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 5 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 5 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 5 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 5 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT6 + Port 6 + PORTS + 0x48028600 + + 0x0 + 0x0100 + registers + + + + OUT + Port 6 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 6 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 6 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 6 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 6 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 6 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 6 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 6 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 6 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT7 + Port 7 + PORTS + 0x48028700 + + 0x0 + 0x0100 + registers + + + + OUT + Port 7 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 7 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 7 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 7 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 7 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 7 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 7 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 7 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 7 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 7 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 7 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT8 + Port 8 + PORTS + 0x48028800 + + 0x0 + 0x0100 + registers + + + + OUT + Port 8 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 8 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 8 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 8 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 8 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 8 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 8 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 8 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 8 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 8 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 8 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT9 + Port 9 + PORTS + 0x48028900 + + 0x0 + 0x0100 + registers + + + + OUT + Port 9 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 9 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 9 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 5 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 9 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 9 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDR0 + Port 9 Pad Driver Mode 0 Register + 0x40 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD0 + Pad Driver Mode for Pn.0 + 0 + 2 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD1 + Pad Driver Mode for Pn.1 + 4 + 6 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD2 + Pad Driver Mode for Pn.2 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD3 + Pad Driver Mode for Pn.3 + 12 + 14 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD4 + Pad Driver Mode for Pn.4 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD5 + Pad Driver Mode for Pn.5 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD6 + Pad Driver Mode for Pn.6 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD7 + Pad Driver Mode for Pn.7 + 28 + 30 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + + + PDR1 + Port 9 Pad Driver Mode 1 Register + 0x44 + 32 + 0x22222222 + 0xFFFFFFFF + + + PD8 + Pad Driver Mode for Pn.8 + 0 + 2 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD9 + Pad Driver Mode for Pn.9 + 4 + 6 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD10 + Pad Driver Mode for Pn.10 + 8 + 10 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD11 + Pad Driver Mode for Pn.11 + 12 + 14 + read-write + + + sd_soe + A1+ strong driver, soft edge + #010 + + + sd_sle + A1+ strong driver, slow edge + #011 + + + md + A1+ medium driver + #100 + + + wd + A1+ weak driver + #111 + + + sd_soe_alt + A1+ strong driver, soft edge (alternate value) + #000 + + + sd_sle_alt + A1+ strong driver, slow edge (alternate value) + #001 + + + md_alt + A1+ medium driver (alternate value) + #110 + + + wd_alt + A1+ weak driver (alternate value) + #101 + + + + + PD12 + Pad Driver Mode for Pn.12 + 16 + 18 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD13 + Pad Driver Mode for Pn.13 + 20 + 22 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD14 + Pad Driver Mode for Pn.14 + 24 + 26 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + PD15 + Pad Driver Mode for Pn.15 + 28 + 30 + read-write + + + sd_she + A2 strong driver, sharp edge + #000 + + + sd_mee + A2 strong driver, medium edge + #001 + + + sd_soe + A2 strong driver, soft edge + #010 + + + md + A2 medium driver + #100 + + + wd + A2 weak driver + #111 + + + + + + + PDISC + Port 9 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port n Pin 0 + 0 + 0 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS1 + Pad Disable for Port n Pin 1 + 1 + 1 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS2 + Pad Disable for Port n Pin 2 + 2 + 2 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS3 + Pad Disable for Port n Pin 3 + 3 + 3 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS4 + Pad Disable for Port n Pin 4 + 4 + 4 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS5 + Pad Disable for Port n Pin 5 + 5 + 5 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS6 + Pad Disable for Port n Pin 6 + 6 + 6 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS7 + Pad Disable for Port n Pin 7 + 7 + 7 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS8 + Pad Disable for Port n Pin 8 + 8 + 8 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS9 + Pad Disable for Port n Pin 9 + 9 + 9 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS10 + Pad Disable for Port n Pin 10 + 10 + 10 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS11 + Pad Disable for Port n Pin 11 + 11 + 11 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS12 + Pad Disable for Port n Pin 12 + 12 + 12 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS13 + Pad Disable for Port n Pin 13 + 13 + 13 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS14 + Pad Disable for Port n Pin 14 + 14 + 14 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + PDIS15 + Pad Disable for Port n Pin 15 + 15 + 15 + read-only + + + value1 + Pad Pn.x is enabled. + #0 + + + value2 + Pad Pn.x is disabled. + #1 + + + + + + + PPS + Port 9 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 9 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT14 + Port 14 + PORTS + 0x48028E00 + + 0x0 + 0x0100 + registers + + + + OUT + Port 14 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 14 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 14 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 14 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 14 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 14 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 14 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDISC + Port 14 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS0 + Pad Disable for Port 14 Pin 0 + 0 + 0 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 0 selected. + #1 + + + + + PDIS1 + Pad Disable for Port 14 Pin 1 + 1 + 1 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 1 selected. + #1 + + + + + PDIS2 + Pad Disable for Port 14 Pin 2 + 2 + 2 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 and ADC 1 analog input 2 selected. + #1 + + + + + PDIS3 + Pad Disable for Port 14 Pin 3 + 3 + 3 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 and ADC 1 analog input 3 selected. + #1 + + + + + PDIS4 + Pad Disable for Port 14 Pin 4 + 4 + 4 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 4 and ADC 2 analog input 0 and DAC Reference selected. + #1 + + + + + PDIS5 + Pad Disable for Port 14 Pin 5 + 5 + 5 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 5 and ADC 2 analog input 1 selected. + #1 + + + + + PDIS6 + Pad Disable for Port 14 Pin 6 + 6 + 6 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 0 analog input 6 selected. + #1 + + + + + PDIS7 + Pad Disable for Port 14 Pin 7 + 7 + 7 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC0 analog input 7 selected. + #1 + + + + + PDIS8 + Pad Disable for Port 14 Pin 8 + 8 + 8 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 0 and ADC 2 analog input 4 and DAC output 0 selected. + #1 + + + + + PDIS9 + Pad Disable for Port 14 Pin 9 + 9 + 9 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 1 and ADC 2 analog input 5 and DAC output 1 selected. + #1 + + + + + PDIS12 + Pad Disable for Port 14 Pin 12 + 12 + 12 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 4 selected. + #1 + + + + + PDIS13 + Pad Disable for Port 14 Pin 13 + 13 + 13 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 5 selected. + #1 + + + + + PDIS14 + Pad Disable for Port 14 Pin 14 + 14 + 14 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 6 selected. + #1 + + + + + PDIS15 + Pad Disable for Port 14 Pin 15 + 15 + 15 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 1 analog input 7 selected. + #1 + + + + + + + PPS + Port 14 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 14 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + PORT15 + Port 15 + PORTS + 0x48028F00 + + 0x0 + 0x0100 + registers + + + + OUT + Port 15 Output Register + 0x00 + 32 + 0x00000000 + 0xFFFFFFFF + + + P0 + Port n Output Bit 0 + 0 + 0 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P1 + Port n Output Bit 1 + 1 + 1 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P2 + Port n Output Bit 2 + 2 + 2 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P3 + Port n Output Bit 3 + 3 + 3 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P4 + Port n Output Bit 4 + 4 + 4 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P5 + Port n Output Bit 5 + 5 + 5 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P6 + Port n Output Bit 6 + 6 + 6 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P7 + Port n Output Bit 7 + 7 + 7 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P8 + Port n Output Bit 8 + 8 + 8 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P9 + Port n Output Bit 9 + 9 + 9 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P10 + Port n Output Bit 10 + 10 + 10 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P11 + Port n Output Bit 11 + 11 + 11 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P12 + Port n Output Bit 12 + 12 + 12 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P13 + Port n Output Bit 13 + 13 + 13 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P14 + Port n Output Bit 14 + 14 + 14 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + P15 + Port n Output Bit 15 + 15 + 15 + read-write + + + value1 + The output level of Pn.x is 0. + #0 + + + value2 + The output level of Pn.x is 1. + #1 + + + + + + + OMR + Port 15 Output Modification Register + 0x04 + 32 + 0x00000000 + 0xFFFFFFFF + + + PS0 + Port n Set Bit 0 + 0 + 0 + write-only + + + PS1 + Port n Set Bit 1 + 1 + 1 + write-only + + + PS2 + Port n Set Bit 2 + 2 + 2 + write-only + + + PS3 + Port n Set Bit 3 + 3 + 3 + write-only + + + PS4 + Port n Set Bit 4 + 4 + 4 + write-only + + + PS5 + Port n Set Bit 5 + 5 + 5 + write-only + + + PS6 + Port n Set Bit 6 + 6 + 6 + write-only + + + PS7 + Port n Set Bit 7 + 7 + 7 + write-only + + + PS8 + Port n Set Bit 8 + 8 + 8 + write-only + + + PS9 + Port n Set Bit 9 + 9 + 9 + write-only + + + PS10 + Port n Set Bit 10 + 10 + 10 + write-only + + + PS11 + Port n Set Bit 11 + 11 + 11 + write-only + + + PS12 + Port n Set Bit 12 + 12 + 12 + write-only + + + PS13 + Port n Set Bit 13 + 13 + 13 + write-only + + + PS14 + Port n Set Bit 14 + 14 + 14 + write-only + + + PS15 + Port n Set Bit 15 + 15 + 15 + write-only + + + PR0 + Port n Reset Bit 0 + 16 + 16 + write-only + + + PR1 + Port n Reset Bit 1 + 17 + 17 + write-only + + + PR2 + Port n Reset Bit 2 + 18 + 18 + write-only + + + PR3 + Port n Reset Bit 3 + 19 + 19 + write-only + + + PR4 + Port n Reset Bit 4 + 20 + 20 + write-only + + + PR5 + Port n Reset Bit 5 + 21 + 21 + write-only + + + PR6 + Port n Reset Bit 6 + 22 + 22 + write-only + + + PR7 + Port n Reset Bit 7 + 23 + 23 + write-only + + + PR8 + Port n Reset Bit 8 + 24 + 24 + write-only + + + PR9 + Port n Reset Bit 9 + 25 + 25 + write-only + + + PR10 + Port n Reset Bit 10 + 26 + 26 + write-only + + + PR11 + Port n Reset Bit 11 + 27 + 27 + write-only + + + PR12 + Port n Reset Bit 12 + 28 + 28 + write-only + + + PR13 + Port n Reset Bit 13 + 29 + 29 + write-only + + + PR14 + Port n Reset Bit 14 + 30 + 30 + write-only + + + PR15 + Port n Reset Bit 15 + 31 + 31 + write-only + + + + + IOCR0 + Port 15 Input/Output Control Register 0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC0 + Port Control for Port n Pin 0 to 3 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC1 + Port Control for Port n Pin 0 to 3 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC2 + Port Control for Port n Pin 0 to 3 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC3 + Port Control for Port n Pin 0 to 3 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR4 + Port 15 Input/Output Control Register 4 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC4 + Port Control for Port n Pin 4 to 7 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC5 + Port Control for Port n Pin 4 to 7 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC6 + Port Control for Port n Pin 4 to 7 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC7 + Port Control for Port n Pin 4 to 7 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR8 + Port 15 Input/Output Control Register 8 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + PC8 + Port Control for Port n Pin 8 to 11 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC9 + Port Control for Port n Pin 8 to 11 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC10 + Port Control for Port n Pin 8 to 11 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC11 + Port Control for Port n Pin 8 to 11 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IOCR12 + Port 15 Input/Output Control Register 12 + 0x1C + 32 + 0x00000000 + 0xFFFFFFFF + + + PC12 + Port Control for Port n Pin 12 to 15 + 3 + 7 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC13 + Port Control for Port n Pin 12 to 15 + 11 + 15 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC14 + Port Control for Port n Pin 12 to 15 + 19 + 23 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + PC15 + Port Control for Port n Pin 12 to 15 + 27 + 31 + read-write + + + value1 + Input - No internal pull device active + #00000 + + + value2 + Input - Internal pull-down device active + #00001 + + + value3 + Input - Internal pull-up device active + #00010 + + + value4 + Input - No internal pull device, Pn_OUTx = input value + #00011 + + + value5 + Input inverted - No internal pull device active + #00100 + + + value6 + Input inverted - Internal pull-down device active + #00101 + + + value7 + Input inverted - Internal pull-up device active + #00110 + + + value8 + Input inverted - No internal pull device, Pn_OUTx = input value + #00111 + + + value9 + Output Push-Pull - General-purpose output + #10000 + + + value10 + Output Push-Pull - Alternate output function 1 + #10001 + + + value11 + Output Push-Pull - Alternate output function 2 + #10010 + + + value12 + Output Push-Pull - Alternate output function 3 + #10011 + + + value13 + Output Push-Pull - Alternate output function 4 + #10100 + + + value14 + Output Open Drain - General-purpose output + #11000 + + + value15 + Output Open Drain - Alternate output function 1 + #11001 + + + value16 + Output Open Drain - Alternate output function 2 + #11010 + + + value17 + Output Open Drain - Alternate output function 3 + #11011 + + + value18 + Output Open Drain - Alternate output function 4 + #11100 + + + + + + + IN + Port 15 Input Register + 0x24 + 32 + 0x00000000 + 0xFFFF0000 + + + P0 + Port n Input Bit 0 + 0 + 0 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P1 + Port n Input Bit 1 + 1 + 1 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P2 + Port n Input Bit 2 + 2 + 2 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P3 + Port n Input Bit 3 + 3 + 3 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P4 + Port n Input Bit 4 + 4 + 4 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P5 + Port n Input Bit 5 + 5 + 5 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P6 + Port n Input Bit 6 + 6 + 6 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P7 + Port n Input Bit 7 + 7 + 7 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P8 + Port n Input Bit 8 + 8 + 8 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P9 + Port n Input Bit 9 + 9 + 9 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P10 + Port n Input Bit 10 + 10 + 10 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P11 + Port n Input Bit 11 + 11 + 11 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P12 + Port n Input Bit 12 + 12 + 12 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P13 + Port n Input Bit 13 + 13 + 13 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P14 + Port n Input Bit 14 + 14 + 14 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + P15 + Port n Input Bit 15 + 15 + 15 + read-only + + + value1 + The input level of Pn.x is 0. + #0 + + + value2 + The input level of Pn.x is 1. + #1 + + + + + + + PDISC + Port 15 Pin Function Decision Control Register + 0x60 + 32 + 0x00000000 + 0xFFFF0000 + + + PDIS2 + Pad Disable for Port 15 Pin 2 + 2 + 2 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 2. + #1 + + + + + PDIS3 + Pad Disable for Port 15 Pin 3 + 3 + 3 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 3. + #1 + + + + + PDIS4 + Pad Disable for Port 15 Pin 4 + 4 + 4 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 4. + #1 + + + + + PDIS5 + Pad Disable for Port 15 Pin 5 + 5 + 5 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 5. + #1 + + + + + PDIS6 + Pad Disable for Port 15 Pin 6 + 6 + 6 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 6. + #1 + + + + + PDIS7 + Pad Disable for Port 15 Pin 7 + 7 + 7 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 2 analog input 7. + #1 + + + + + PDIS8 + Pad Disable for Port 15 Pin 8 + 8 + 8 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 0. + #1 + + + + + PDIS9 + Pad Disable for Port 15 Pin 9 + 9 + 9 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 1. + #1 + + + + + PDIS12 + Pad Disable for Port 15 Pin 12 + 12 + 12 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 4. + #1 + + + + + PDIS13 + Pad Disable for Port 15 Pin 13 + 13 + 13 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 5. + #1 + + + + + PDIS14 + Pad Disable for Port 15 Pin 14 + 14 + 14 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 6. + #1 + + + + + PDIS15 + Pad Disable for Port 15 Pin 15 + 15 + 15 + read-write + + + value1 + Pad is enabled, digital input selected. + #0 + + + value2 + Pad is disabled, ADC 3 analog input 7. + #1 + + + + + + + PPS + Port 15 Pin Power Save Register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPS0 + Port n Pin Power Save Bit 0 + 0 + 0 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS1 + Port n Pin Power Save Bit 1 + 1 + 1 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS2 + Port n Pin Power Save Bit 2 + 2 + 2 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS3 + Port n Pin Power Save Bit 3 + 3 + 3 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS4 + Port n Pin Power Save Bit 4 + 4 + 4 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS5 + Port n Pin Power Save Bit 5 + 5 + 5 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS6 + Port n Pin Power Save Bit 6 + 6 + 6 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS7 + Port n Pin Power Save Bit 7 + 7 + 7 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS8 + Port n Pin Power Save Bit 8 + 8 + 8 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS9 + Port n Pin Power Save Bit 9 + 9 + 9 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS10 + Port n Pin Power Save Bit 10 + 10 + 10 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS11 + Port n Pin Power Save Bit 11 + 11 + 11 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS12 + Port n Pin Power Save Bit 12 + 12 + 12 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS13 + Port n Pin Power Save Bit 13 + 13 + 13 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS14 + Port n Pin Power Save Bit 14 + 14 + 14 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + PPS15 + Port n Pin Power Save Bit 15 + 15 + 15 + read-write + + + value1 + Pin Power Save of Pn.x is disabled. + #0 + + + value2 + Pin Power Save of Pn.x is enabled. + #1 + + + + + + + HWSEL + Port 15 Pin Hardware Select Register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + HW0 + Port n Pin Hardware Select Bit 0 + 0 + 1 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW1 + Port n Pin Hardware Select Bit 1 + 2 + 3 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW2 + Port n Pin Hardware Select Bit 2 + 4 + 5 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW3 + Port n Pin Hardware Select Bit 3 + 6 + 7 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW4 + Port n Pin Hardware Select Bit 4 + 8 + 9 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW5 + Port n Pin Hardware Select Bit 5 + 10 + 11 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW6 + Port n Pin Hardware Select Bit 6 + 12 + 13 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW7 + Port n Pin Hardware Select Bit 7 + 14 + 15 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW8 + Port n Pin Hardware Select Bit 8 + 16 + 17 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW9 + Port n Pin Hardware Select Bit 9 + 18 + 19 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW10 + Port n Pin Hardware Select Bit 10 + 20 + 21 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW11 + Port n Pin Hardware Select Bit 11 + 22 + 23 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW12 + Port n Pin Hardware Select Bit 12 + 24 + 25 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW13 + Port n Pin Hardware Select Bit 13 + 26 + 27 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW14 + Port n Pin Hardware Select Bit 14 + 28 + 29 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + HW15 + Port n Pin Hardware Select Bit 15 + 30 + 31 + read-write + + + value1 + Software control only. + #00 + + + value2 + HW0 control path can override the software configuration. + #01 + + + value3 + HW1 control path can override the software configuration. + #10 + + + + + + + + + diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.depend b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.depend index c1120a61..9bb1dd58 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.depend +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.depend @@ -1013,10 +1013,11 @@ 1452185952 source:c:\users\voorburg\documents\embedded\infineon\apps\xmc4700_relax_kit\xmc4700_emblocks_os\src\os\os.c "os.h" -1477055058 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\boot.c +1477219350 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\boot.c "header.h" - "xmc_uart.h" "xmc_gpio.h" + "xmc_uart.h" + "xmc_can.h" 1477053802 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\header.h "../Boot/blt_conf.h" @@ -1025,45 +1026,45 @@ "led.h" "timer.h" -1477061178 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\blt_conf.h +1477217517 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\boot\blt_conf.h -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmc4700.h +1473064960 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmc4700.h "core_cm4.h" "system_XMC4700.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cm4.h +1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cm4.h "core_cmInstr.h" "core_cmFunc.h" "core_cmSimd.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cminstr.h - - - +1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cminstr.h + "cmsis_armcc.h" + "cmsis_armcc_V6.h" + "cmsis_gcc.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\cmsis_gcc.h +1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\cmsis_gcc.h -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cmfunc.h - - - +1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cmfunc.h + "cmsis_armcc.h" + "cmsis_armcc_V6.h" + "cmsis_gcc.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cmsimd.h - - - +1465289978 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\cmsis\core_cmsimd.h + "cmsis_armcc.h" + "cmsis_armcc_V6.h" + "cmsis_gcc.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\system_xmc4700.h +1468487305 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\system_xmc4700.h 1477053763 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\boot.h @@ -1072,21 +1073,21 @@ 1477054079 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\timer.h -1477085557 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\system_xmc4700.c +1477088447 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\system_xmc4700.c "system_XMC4700.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_eru.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_eru.c "xmc_eru.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_eru.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_eru.h "xmc_common.h" "xmc1_eru_map.h" "xmc4_eru_map.h" -1477054406 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_common.h +1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_common.h @@ -1094,9 +1095,10 @@ "xmc_device.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_device.h +1469781874 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_device.h "XMC4500.h" "XMC4400.h" + "XMC4300.h" "XMC4200.h" "XMC4100.h" "XMC4700.h" @@ -1106,255 +1108,255 @@ "XMC1300.h" "XMC1400.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_eru_map.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_eru_map.h -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_scu.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_scu.h -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_scu.h +1467383079 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_scu.h "xmc_common.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_flash.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_flash.c "xmc_flash.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_flash.h +1471242129 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_flash.h "xmc_common.h" "xmc1_flash.h" "xmc4_flash.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_flash.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_flash.h "xmc_common.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_gpio.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_gpio.c "xmc_gpio.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_gpio.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_gpio.h "xmc_common.h" "xmc1_gpio.h" "xmc4_gpio.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_gpio.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_gpio.h "xmc_common.h" "xmc4_gpio_map.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_gpio_map.h +1471903247 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_gpio_map.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_rtc.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_rtc.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_rtc.h +1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_rtc.h "xmc1_rtc.h" "xmc4_rtc.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_rtc.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_rtc.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_scu.c +1467379907 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc4_scu.c -1477085088 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\led.c +1477089099 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\led.c "header.h" "xmc_gpio.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_can.c +1467378878 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_can.c "xmc_can.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_can.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_can.h "xmc_common.h" "xmc_scu.h" "xmc_can_map.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_can_map.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_can_map.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_ccu4.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_ccu4.c "xmc_ccu4.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_ccu4.h +1467378878 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_ccu4.h "xmc_common.h" "xmc1_ccu4_map.h" "xmc4_ccu4_map.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_ccu4_map.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_ccu4_map.h -1447665730 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source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_common.c "xmc_common.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_dac.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_dac.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dac.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dac.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_dma.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_dma.c "xmc_dma.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dma.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dma.h "xmc_common.h" "xmc_dma_map.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dma_map.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dma_map.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_dsd.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_dsd.c "xmc_dsd.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dsd.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_dsd.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_ebu.c +1470204177 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source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_gpio.c -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_hrpwm.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_hrpwm.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_hrpwm.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_hrpwm.h -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_hrpwm_map.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_hrpwm_map.h "xmc_hrpwm.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_i2c.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_i2c.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_i2c.h +1471939947 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_i2c.h "xmc_usic.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usic.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usic.h "xmc_common.h" "xmc1_usic_map.h" "xmc4_usic_map.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_usic_map.h +1469014921 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc4_usic_map.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_i2s.c +1469450032 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_i2s.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_i2s.h +1468425037 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_i2s.h "xmc_usic.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_ledts.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_ledts.c "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_ledts.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_ledts.h "xmc_scu.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_posif.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_posif.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_posif.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_posif.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_rtc.c +1467378878 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_rtc.c "xmc_scu.h" "xmc_rtc.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_sdmmc.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_sdmmc.c "xmc_sdmmc.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_sdmmc.h +1470204177 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c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_uart.h "xmc_usic.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_usbd.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_usbd.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usbd.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usbd.h "xmc_common.h" "xmc_usbd_regs.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usbd_regs.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usbd_regs.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_usic.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_usic.c "xmc_usic.h" "xmc_scu.h" -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_vadc.c +1470204802 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_vadc.c -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_vadc.h +1470205055 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_vadc.h -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_vadc_map.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_vadc_map.h -1447665730 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_wdt.c +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_wdt.c "xmc_wdt.h" "xmc_scu.h" -1447665730 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_wdt.h +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_wdt.h "xmc_common.h" "xmc_scu.h" @@ -1366,3 +1368,56 @@ 1477054062 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\timer.c "header.h" +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_acmp.c + + +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_acmp.h + + +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_bccu.c + + + +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_bccu.h + + +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_ecat.c + + + +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_ecat.h + "xmc_common.h" + "xmc_ecat_map.h" + +1469014958 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_ecat_map.h + +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_math.c + + +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_math.h + + + +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_pau.c + "xmc_pau.h" + +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_pau.h + "xmc_common.h" + +1470204177 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_prng.c + "xmc_prng.h" + +1470204177 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_prng.h + "xmc_common.h" + +1473236602 source:c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\src\xmc_usbh.c + + + "xmc_usbh.h" + +1473236602 c:\work\software\openblt\target\demo\armcm4_xmc4_xcm4700_relax_kit_gcc\prog\lib\xmclib\inc\xmc_usbh.h + + "xmc_common.h" + "xmc_scu.h" + "xmc_gpio.h" + diff --git a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.ebp b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.ebp index 6e153fe8..42dd4577 100644 --- a/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.ebp +++ b/Target/Demo/ARMCM4_XMC4_XCM4700_Relax_Kit_GCC/Prog/ide/xmc4700.ebp @@ -420,7 +420,7 @@ - +