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Refs #311. Reworked compiler specific parts in the STM32F4 port. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@333 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2017-08-16 08:17:23 +00:00
parent 5a6eba22d1
commit ff6ce18750
22 changed files with 8543 additions and 7695 deletions
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BIN
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/bin/openblt_olimex_stm32e407.out
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5587
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/bin/openblt_olimex_stm32e407.srec
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File diff suppressed because it is too large Load Diff

10
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dbgdt
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@ -39,7 +39,7 @@
<Wnd2>
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@ -55,7 +55,7 @@
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@ -67,20 +67,20 @@
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2
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dni
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@ -9,7 +9,7 @@ TriggerName=main
LimitSize=0
ByteLimit=50
[DebugChecksum]
Checksum=-1563361147
Checksum=-1075250955
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0

8
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.wsdt
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@ -30,7 +30,7 @@
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@ -42,20 +42,20 @@
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4308
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/ide/stm32f407.dep
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11
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/ide/stm32f407.ewp
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@ -744,7 +744,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32F4\IAR\memory.x</state>
<state>$PROJ_DIR$\..\stm32f4xx_flash.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@ -2249,6 +2249,9 @@
<file>
<name>$PROJ_DIR$\..\main.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\startup_stm32f40xx.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\usb_bsp.c</name>
</file>
@ -2283,12 +2286,6 @@
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32F4\IAR\cpu_comp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32F4\IAR\cstart.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32F4\IAR\vectors.c</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32F4\can.c</name>

636
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/startup_stm32f40xx.s Normal file
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@ -0,0 +1,636 @@
;/******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f40xx.s
;* Author : MCD Application Team
;* Version : V1.1.0
;* Date : 11-January-2013
;* Description : STM32F40xx/41xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************/
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
Target/Source/ARMCM4_STM32F4/IAR/memory.x → Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Boot/stm32f4xx_flash.icf
View File

@ -4,13 +4,12 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800BFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20005FFF;
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
@ -28,5 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
block CSTACK, block HEAP };

BIN
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/bin/demoprog_olimex_stm32e407.out
View File

Binary file not shown.

1689
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/bin/demoprog_olimex_stm32e407.srec
View File

File diff suppressed because it is too large Load Diff

64
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/cstart.s
View File

@ -1,64 +0,0 @@
/****************************************************************************************
| Description: Demo program C startup source file
| File Name: cstart.s
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
MODULE ?cstartup
; Forward declaration of section.
SECTION CSTACK:DATA:NOROOT(3)
PUBLIC __iar_program_start
EXTERN __cmain
EXTERN __vector_table
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
/****************************************************************************************
** NAME: __iar_program_start
** PARAMETER: none
** RETURN VALUE: none
** DESCRIPTION: Reset interrupt service routine. Configures the stack, initializes RAM
** and jumps to function main.
**
****************************************************************************************/
SECTION .text:CODE:REORDER(2)
THUMB
__iar_program_start:
; Initialize the stack pointer
LDR R3, =sfe(CSTACK)
MOV SP, R3
BL __iar_init_core
BL __iar_init_vfp
BL __cmain
REQUIRE __vector_table
END
/*********************************** end of cstart.s ***********************************/

6
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/ide/settings/stm32f407.wsdt
View File

@ -25,7 +25,7 @@
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>stm32f407</ExpandedNode><ExpandedNode>stm32f407/Output</ExpandedNode><ExpandedNode>stm32f407/Prog</ExpandedNode><ExpandedNode>stm32f407/Prog/lib</ExpandedNode><ExpandedNode>stm32f407/Prog/lib/ethernetlib</ExpandedNode><ExpandedNode>stm32f407/Prog/lib/uip</ExpandedNode></NodeDict></Session>
<NodeDict><ExpandedNode>stm32f407</ExpandedNode><ExpandedNode>stm32f407/Output</ExpandedNode><ExpandedNode>stm32f407/Prog</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
@ -35,14 +35,14 @@
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>42</YPos2><SelStart2>3162</SelStart2><SelEnd2>3162</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>40</YPos2><SelStart2>2989</SelStart2><SelEnd2>2989</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-047EDDB8><key>iaridepm.enu1</key></Toolbar-047EDDB8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>764</Bottom><Right>379</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>198610</sizeHorzCY><sizeVertCX>198438</sizeVertCX><sizeVertCY>760675</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>200</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>198610</sizeHorzCY><sizeVertCX>104167</sizeVertCX><sizeVertCY>198610</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
<Top><Row0><Sizes><Toolbar-04C2DDB8><key>iaridepm.enu1</key></Toolbar-04C2DDB8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>764</Bottom><Right>379</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>198610</sizeHorzCY><sizeVertCX>198438</sizeVertCX><sizeVertCY>760675</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>200</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>198610</sizeHorzCY><sizeVertCX>104167</sizeVertCX><sizeVertCY>198610</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

2833
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/ide/stm32f407.dep
View File

File diff suppressed because it is too large Load Diff

11
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/ide/stm32f407.ewp
View File

@ -735,7 +735,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\..\memory.x</state>
<state>$PROJ_DIR$\..\stm32f4xx_flash.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@ -2234,9 +2234,6 @@
<file>
<name>$PROJ_DIR$\..\boot.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\cstart.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\header.h</name>
</file>
@ -2255,15 +2252,15 @@
<file>
<name>$PROJ_DIR$\..\net.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\startup_stm32f40xx.s</name>
</file>
<file>
<name>$PROJ_DIR$\..\timer.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\timer.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\vectors.c</name>
</file>
</group>
</project>

639
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/startup_stm32f40xx.s Normal file
View File

@ -0,0 +1,639 @@
;/******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f40xx.s
;* Author : MCD Application Team
;* Version : V1.1.0
;* Date : 11-January-2013
;* Description : STM32F40xx/41xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************/
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD 0x55AA11EE ; Reserved for OpenBLT checksum
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
; Initialize the stack pointer
LDR R0, =sfe(CSTACK)
MOV SP, R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/memory.x → Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/stm32f4xx_flash.icf
View File

@ -8,9 +8,8 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x800;
define memory mem with size = 4G;
@ -28,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
block CSTACK, block HEAP };

4
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/timer.c
View File

@ -96,11 +96,11 @@ unsigned long TimerGet(void)
** \return none.
**
****************************************************************************************/
void TimerISRHandler(void)
void SysTick_Handler(void)
{
/* increment the millisecond counter */
millisecond_counter++;
} /*** end of TimerISRHandler ***/
} /*** end of SysTick_Handler ***/
/*********************************** end of timer.c ************************************/

1
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/timer.h
View File

@ -35,7 +35,6 @@ void TimerInit(void);
void TimerDeinit(void);
void TimerSet(unsigned long timer_value);
unsigned long TimerGet(void);
void TimerISRHandler(void);
#endif /* TIMER_H */
/*********************************** end of timer.h ************************************/

177
Target/Demo/ARMCM4_STM32F4_Olimex_STM32E407_IAR/Prog/vectors.c
View File

@ -1,177 +0,0 @@
/************************************************************************************//**
* \file Demo\ARMCM4_STM32F4_Olimex_STM32E407_IAR\Prog\vectors.c
* \brief Demo program interrupt vectors source file.
* \ingroup Prog_ARMCM4_STM32F4_Olimex_STM32E407_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* External functions
****************************************************************************************/
extern void __iar_program_start( void );
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for vector table entries. */
typedef union
{
void (*func)(void); /**< for ISR function pointers */
void *ptr; /**< for stack pointer entry */
}tIsrFunc;
/************************************************************************************//**
** \brief Catch-all for unused interrrupt service routines.
** \return none.
**
****************************************************************************************/
void UnusedISR(void)
{
/* unexpected interrupt occured, so halt the system */
while (1) { ; }
} /*** end of UnusedISR ***/
/****************************************************************************************
* I N T E R R U P T V E C T O R T A B L E
****************************************************************************************/
#pragma language=extended /* enable IAR extensions */
#pragma segment="CSTACK"
/** \brief Interrupt vector table. */
__root const tIsrFunc __vector_table[] @ ".intvec" =
{
{ .ptr = __sfe( "CSTACK" ) }, /* the initial stack pointer */
{ &__iar_program_start }, /* the reset handler */
{ UnusedISR }, /* NMI Handler */
{ UnusedISR }, /* Hard Fault Handler */
{ UnusedISR }, /* MPU Fault Handler */
{ UnusedISR }, /* Bus Fault Handler */
{ UnusedISR }, /* Usage Fault Handler */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* SVCall Handler */
{ UnusedISR }, /* Debug Monitor Handler */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* PendSV Handler */
{ TimerISRHandler }, /* SysTick Handler */
{ UnusedISR }, /* Window Watchdog */
{ UnusedISR }, /* PVD through EXTI Line detect */
{ UnusedISR }, /* Tamper */
{ UnusedISR }, /* RTC */
{ UnusedISR }, /* Flash */
{ UnusedISR }, /* RCC */
{ UnusedISR }, /* EXTI Line 0 */
{ UnusedISR }, /* EXTI Line 1 */
{ UnusedISR }, /* EXTI Line 2 */
{ UnusedISR }, /* EXTI Line 3 */
{ UnusedISR }, /* EXTI Line 4 */
{ UnusedISR }, /* DMA1 Channel 0 */
{ UnusedISR }, /* DMA1 Channel 1 */
{ UnusedISR }, /* DMA1 Channel 2 */
{ UnusedISR }, /* DMA1 Channel 3 */
{ UnusedISR }, /* DMA1 Channel 4 */
{ UnusedISR }, /* DMA1 Channel 5 */
{ UnusedISR }, /* DMA1 Channel 6 */
{ UnusedISR }, /* ADC1 and ADC2, ADC3s */
{ UnusedISR }, /* CAN1 TX */
{ UnusedISR }, /* CAN1 RX0 */
{ UnusedISR }, /* CAN1 RX1 */
{ UnusedISR }, /* CAN1 SCE */
{ UnusedISR }, /* EXTI Line 9..5 */
{ UnusedISR }, /* TIM1 Break and TIM9 */
{ UnusedISR }, /* TIM1 Update and TIM10 */
{ UnusedISR }, /* TIM1 Trigger/Comm. and TIM11 */
{ UnusedISR }, /* TIM1 Capture Compare */
{ UnusedISR }, /* TIM2 */
{ UnusedISR }, /* TIM3 */
{ UnusedISR }, /* TIM4 */
{ UnusedISR }, /* I2C1 Event */
{ UnusedISR }, /* I2C1 Error */
{ UnusedISR }, /* I2C2 Event */
{ UnusedISR }, /* I2C1 Error */
{ UnusedISR }, /* SPI1 */
{ UnusedISR }, /* SPI2 */
{ UnusedISR }, /* USART1 */
{ UnusedISR }, /* USART2 */
{ UnusedISR }, /* USART3 */
{ UnusedISR }, /* EXTI Line 15..10 */
{ UnusedISR }, /* RTC alarm through EXTI line */
{ UnusedISR }, /* USB OTG FS Wakeup */
{ UnusedISR }, /* TIM8 Break and TIM12 */
{ UnusedISR }, /* TIM8 Update and TIM13 */
{ UnusedISR }, /* TIM8 Trigger/Comm. and TIM14 */
{ UnusedISR }, /* TIM8 Capture Compare */
{ UnusedISR }, /* DMA1 Stream7 */
{ UnusedISR }, /* FSMC */
{ UnusedISR }, /* SDIO */
{ UnusedISR }, /* TIM5 */
{ UnusedISR }, /* SPI3 */
{ UnusedISR }, /* UART4 */
{ UnusedISR }, /* UART5 */
{ UnusedISR }, /* TIM6 and DAC1&2 underrun err. */
{ UnusedISR }, /* TIM7 */
{ UnusedISR }, /* DMA2 Stream 0 */
{ UnusedISR }, /* DMA2 Stream 1 */
{ UnusedISR }, /* DMA2 Stream 2 */
{ UnusedISR }, /* DMA2 Stream 3 */
{ UnusedISR }, /* DMA2 Stream 4 */
{ UnusedISR }, /* Ethernet */
{ UnusedISR }, /* Ethernet Wakeup */
{ UnusedISR }, /* CAN2 TX */
{ UnusedISR }, /* CAN2 RX0 */
{ UnusedISR }, /* CAN2 RX1 */
{ UnusedISR }, /* CAN2 SCE */
{ UnusedISR }, /* USB OTG FS */
{ UnusedISR }, /* DMA2 Stream 5 */
{ UnusedISR }, /* DMA2 Stream 6 */
{ UnusedISR }, /* DMA2 Stream 7 */
{ UnusedISR }, /* USART6 */
{ UnusedISR }, /* I2C3 event */
{ UnusedISR }, /* I2C3 error */
{ UnusedISR }, /* USB OTG HS End Point 1 Out */
{ UnusedISR }, /* USB OTG HS End Point 1 In */
{ UnusedISR }, /* USB OTG HS Wakeup through EXTI*/
{ UnusedISR }, /* USB OTG HS */
{ UnusedISR }, /* DCMI */
{ UnusedISR }, /* CRYP crypto */
{ UnusedISR }, /* Hash and Rng */
{ UnusedISR }, /* FPU */
{ .ptr = (void*)0x55AA11EE } /* Reserved for OpenBLT checksum */
};
/************************************ end of vectors.c *********************************/

63
Target/Source/ARMCM4_STM32F4/IAR/cstart.s
View File

@ -1,63 +0,0 @@
/****************************************************************************************
| Description: bootloader C startup source file
| File Name: cstart.s
|
|----------------------------------------------------------------------------------------
| C O P Y R I G H T
|----------------------------------------------------------------------------------------
| Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
|
|----------------------------------------------------------------------------------------
| L I C E N S E
|----------------------------------------------------------------------------------------
| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
| modify it under the terms of the GNU General Public License as published by the Free
| Software Foundation, either version 3 of the License, or (at your option) any later
| version.
|
| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
| PURPOSE. See the GNU General Public License for more details.
|
| You have received a copy of the GNU General Public License along with OpenBLT. It
| should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
****************************************************************************************/
MODULE ?cstartup
; Forward declaration of section.
SECTION CSTACK:DATA:NOROOT(3)
PUBLIC reset_handler
EXTERN __cmain
EXTERN __vector_table
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
/****************************************************************************************
** NAME: reset_handler
** PARAMETER: none
** RETURN VALUE: none
** DESCRIPTION: Reset interrupt service routine. Configures the stack, initializes RAM
** and jumps to function main.
**
****************************************************************************************/
SECTION .text:CODE:REORDER(2)
THUMB
reset_handler:
; Initialize the stack pointer
LDR R3, =sfe(CSTACK)
MOV SP, R3
BL __iar_init_core
BL __iar_init_vfp
BL __cmain
REQUIRE __vector_table
END
/************************************ end of cstart.s **********************************/

176
Target/Source/ARMCM4_STM32F4/IAR/vectors.c
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@ -1,176 +0,0 @@
/************************************************************************************//**
* \file Source\ARMCM4_STM32F4\IAR\vectors.c
* \brief Bootloader interrupt vector table source file.
* \ingroup Target_ARMCM4_STM32F4
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
/****************************************************************************************
* External functions
****************************************************************************************/
extern void reset_handler(void);
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for vector table entries. */
typedef union
{
void (*func)(void); /**< for ISR function pointers */
void *ptr; /**< for stack pointer entry */
} tIsrFunc;
/************************************************************************************//**
** \brief Catch-all for unused interrrupt service routines.
** \return none.
**
****************************************************************************************/
void UnusedISR(void)
{
/* unexpected interrupt occured, so trigger an assertion to halt the system */
ASSERT_RT(BLT_FALSE);
} /*** end of UnusedISR ***/
/****************************************************************************************
* I N T E R R U P T V E C T O R T A B L E
****************************************************************************************/
#pragma language=extended /* enable IAR extensions */
#pragma segment="CSTACK"
/** \brief Interrupt vector table. */
__root const tIsrFunc __vector_table[] @ ".intvec" =
{
{ .ptr = __sfe("CSTACK") }, /* the initial stack pointer */
{ &reset_handler }, /* the reset handler */
{ UnusedISR }, /* NMI Handler */
{ UnusedISR }, /* Hard Fault Handler */
{ UnusedISR }, /* MPU Fault Handler */
{ UnusedISR }, /* Bus Fault Handler */
{ UnusedISR }, /* Usage Fault Handler */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* SVCall Handler */
{ UnusedISR }, /* Debug Monitor Handler */
{ UnusedISR }, /* Reserved */
{ UnusedISR }, /* PendSV Handler */
{ UnusedISR }, /* SysTick Handler */
{ UnusedISR }, /* Window Watchdog */
{ UnusedISR }, /* PVD through EXTI Line detect */
{ UnusedISR }, /* Tamper */
{ UnusedISR }, /* RTC */
{ UnusedISR }, /* Flash */
{ UnusedISR }, /* RCC */
{ UnusedISR }, /* EXTI Line 0 */
{ UnusedISR }, /* EXTI Line 1 */
{ UnusedISR }, /* EXTI Line 2 */
{ UnusedISR }, /* EXTI Line 3 */
{ UnusedISR }, /* EXTI Line 4 */
{ UnusedISR }, /* DMA1 Channel 0 */
{ UnusedISR }, /* DMA1 Channel 1 */
{ UnusedISR }, /* DMA1 Channel 2 */
{ UnusedISR }, /* DMA1 Channel 3 */
{ UnusedISR }, /* DMA1 Channel 4 */
{ UnusedISR }, /* DMA1 Channel 5 */
{ UnusedISR }, /* DMA1 Channel 6 */
{ UnusedISR }, /* ADC1 and ADC2, ADC3s */
{ UnusedISR }, /* CAN1 TX */
{ UnusedISR }, /* CAN1 RX0 */
{ UnusedISR }, /* CAN1 RX1 */
{ UnusedISR }, /* CAN1 SCE */
{ UnusedISR }, /* EXTI Line 9..5 */
{ UnusedISR }, /* TIM1 Break and TIM9 */
{ UnusedISR }, /* TIM1 Update and TIM10 */
{ UnusedISR }, /* TIM1 Trigger/Comm. and TIM11 */
{ UnusedISR }, /* TIM1 Capture Compare */
{ UnusedISR }, /* TIM2 */
{ UnusedISR }, /* TIM3 */
{ UnusedISR }, /* TIM4 */
{ UnusedISR }, /* I2C1 Event */
{ UnusedISR }, /* I2C1 Error */
{ UnusedISR }, /* I2C2 Event */
{ UnusedISR }, /* I2C1 Error */
{ UnusedISR }, /* SPI1 */
{ UnusedISR }, /* SPI2 */
{ UnusedISR }, /* USART1 */
{ UnusedISR }, /* USART2 */
{ UnusedISR }, /* USART3 */
{ UnusedISR }, /* EXTI Line 15..10 */
{ UnusedISR }, /* RTC alarm through EXTI line */
{ UnusedISR }, /* USB OTG FS Wakeup */
{ UnusedISR }, /* TIM8 Break and TIM12 */
{ UnusedISR }, /* TIM8 Update and TIM13 */
{ UnusedISR }, /* TIM8 Trigger/Comm. and TIM14 */
{ UnusedISR }, /* TIM8 Capture Compare */
{ UnusedISR }, /* DMA1 Stream7 */
{ UnusedISR }, /* FSMC */
{ UnusedISR }, /* SDIO */
{ UnusedISR }, /* TIM5 */
{ UnusedISR }, /* SPI3 */
{ UnusedISR }, /* UART4 */
{ UnusedISR }, /* UART5 */
{ UnusedISR }, /* TIM6 and DAC1&2 underrun err. */
{ UnusedISR }, /* TIM7 */
{ UnusedISR }, /* DMA2 Stream 0 */
{ UnusedISR }, /* DMA2 Stream 1 */
{ UnusedISR }, /* DMA2 Stream 2 */
{ UnusedISR }, /* DMA2 Stream 3 */
{ UnusedISR }, /* DMA2 Stream 4 */
{ UnusedISR }, /* Ethernet */
{ UnusedISR }, /* Ethernet Wakeup */
{ UnusedISR }, /* CAN2 TX */
{ UnusedISR }, /* CAN2 RX0 */
{ UnusedISR }, /* CAN2 RX1 */
{ UnusedISR }, /* CAN2 SCE */
{ UnusedISR }, /* USB OTG FS */
{ UnusedISR }, /* DMA2 Stream 5 */
{ UnusedISR }, /* DMA2 Stream 6 */
{ UnusedISR }, /* DMA2 Stream 7 */
{ UnusedISR }, /* USART6 */
{ UnusedISR }, /* I2C3 event */
{ UnusedISR }, /* I2C3 error */
{ UnusedISR }, /* USB OTG HS End Point 1 Out */
{ UnusedISR }, /* USB OTG HS End Point 1 In */
{ UnusedISR }, /* USB OTG HS Wakeup through EXTI*/
{ UnusedISR }, /* USB OTG HS */
{ UnusedISR }, /* DCMI */
{ UnusedISR }, /* CRYP crypto */
{ UnusedISR }, /* Hash and Rng */
{ UnusedISR } /* FPU */
};
/************************************ end of vectors.c *********************************/