/* * Copyright 2018 NXP * All rights reserved. * * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ /*! * @file S32K118_features.h * @brief Chip specific module features * * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, Global typedef not referenced. * Type used only in some modules of the SDK. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.4, tag unused outside of typedefs * Tag defined specifically for typedef * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. * The macros defined are used to define features for each driver, so this might be reported * when the analysis is made only on one driver. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are very simple macros used for abstracting hw implementation. * They help make the code easy to understand. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * */ #if !defined(S32K118_FEATURES_H) #define S32K118_FEATURES_H /* ERRATA sections*/ /* @brief Errata workaround: System clock status register may be a erroneous status during the system clock switch. * Read system clock source twice. */ #define ERRATA_E10777 /* @brief E10792: LPI2C: Slave Transmit Data Flag may incorrectly read as one when TXCFG is zero. * Interrupts for transfer data should be enabled after the address valid event is detected and * disabled at the end of the transfer. */ #define ERRATA_E10792 /* @brief Number of cores. */ #define NUMBER_OF_CORES (1u) /* SOC module features */ /* @brief PORT availability on the SoC. */ #define FEATURE_SOC_PORT_COUNT (5) #define FEATURE_SOC_SCG_COUNT (1) /* @brief Slow IRC high range clock frequency. */ #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U) /* @brief Fast IRC trimmed clock frequency(48MHz). */ #define FEATURE_SCG_FIRC_FREQ0 (48000000U) /* @brief VECTKEY value so that AIRCR register write is not ignored. */ #define FEATURE_SCB_VECTKEY (0x05FAU) /* FLASH module features */ /* @brief Is of type FTFA. */ #define FEATURE_FLS_IS_FTFA (0u) /* @brief Is of type FTFC. */ #define FEATURE_FLS_IS_FTFC (1u) /* @brief Is of type FTFE. */ #define FEATURE_FLS_IS_FTFE (0u) /* @brief Is of type FTFL. */ #define FEATURE_FLS_IS_FTFL (0u) /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u) /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u) /* @brief Has EEPROM region protection (register FEPROT). */ #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u) /* @brief Has data flash region protection (register FDPROT). */ #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u) /* @brief P-Flash block count. */ #define FEATURE_FLS_PF_BLOCK_COUNT (1u) /* @brief P-Flash block size. */ #define FEATURE_FLS_PF_BLOCK_SIZE (0x40000U) /* @brief P-Flash sector size. */ #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (2048u) /* @brief P-Flash write unit size. */ #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u) /* @brief P-Flash block swap feature. */ #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u) /* @brief Has FlexNVM memory. */ #define FEATURE_FLS_HAS_FLEX_NVM (1u) /* @brief FlexNVM block count. */ #define FEATURE_FLS_DF_BLOCK_COUNT (1u) /* @brief FlexNVM block size. */ #define FEATURE_FLS_DF_BLOCK_SIZE (32768u) /* @brief FlexNVM sector size. */ #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u) /* @brief FlexNVM write unit size. */ #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u) /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u) /* @brief Has FlexRAM memory. */ #define FEATURE_FLS_HAS_FLEX_RAM (1u) /* @brief FlexRAM size. */ #define FEATURE_FLS_FLEX_RAM_SIZE (2048u) /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u) /* @brief Has 0x00 Read 1s Block command. */ #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u) /* @brief Has 0x01 Read 1s Section command. */ #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u) /* @brief Has 0x02 Program Check command. */ #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u) /* @brief Has 0x03 Read Resource command. */ #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u) /* @brief Has 0x06 Program Longword command. */ #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u) /* @brief Has 0x07 Program Phrase command. */ #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u) /* @brief Has 0x08 Erase Flash Block command. */ #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u) /* @brief Has 0x09 Erase Flash Sector command. */ #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u) /* @brief Has 0x0B Program Section command. */ #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u) /* @brief Has 0x40 Read 1s All Blocks command. */ #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u) /* @brief Has 0x41 Read Once command. */ #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u) /* @brief Has 0x43 Program Once command. */ #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u) /* @brief Has 0x44 Erase All Blocks command. */ #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u) /* @brief Has 0x45 Verify Backdoor Access Key command. */ #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u) /* @brief Has 0x46 Swap Control command. */ #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u) /* @brief Has 0x49 Erase All Blocks unsecure command. */ #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u) /* @brief Has 0x80 Program Partition command. */ #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u) /* @brief Has 0x81 Set FlexRAM Function command. */ #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u) /* @brief P-Flash Erase/Read 1st all block command address alignment. */ #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (8u) /* @brief P-Flash Erase sector command address alignment. */ #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (8u) /* @brief P-Flash Program/Verify section command address alignment. */ #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (8u) /* @brief P-Flash Read resource command address alignment. */ #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u) /* @brief P-Flash Program check command address alignment. */ #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u) /* @brief P-Flash Program check command address alignment. */ #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u) /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u) /* @brief FlexNVM Erase sector command address alignment. */ #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u) /* @brief FlexNVM Program/Verify section command address alignment. */ #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u) /* @brief FlexNVM Read resource command address alignment. */ #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u) /* @brief FlexNVM Program check command address alignment. */ #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u) /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0000 (0x00008000u) /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu) /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu) /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0011 (0x00000000u) /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0100 (0xFFFFFFFFu) /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu) /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu) /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu) /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u) /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1001 (0x00002000u) /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1010 (0xFFFFFFFFu) /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u) /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1100 (0xFFFFFFFFu) /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu) /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu) /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FEATURE_FLS_DF_SIZE_1111 (0x00008000u) /* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu) /* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu) /* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0010 (0xFFFFu) /* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0011 (0x0800u) /* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0100 (0xFFFFu) /* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0101 (0xFFFFu) /* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0110 (0xFFFFu) /* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_0111 (0xFFFFu) /* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1000 (0xFFFFu) /* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1001 (0xFFFFu) /* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu) /* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu) /* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu) /* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu) /* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu) /* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */ #define FEATURE_FLS_EE_SIZE_1111 (0x0000u) /* @brief Has the detection of uncorrected ECC errors. */ #define FEATURE_FLS_HAS_DETECT_ECC_ERROR (1) /* @brief Has the interrupt double bit fault detect. */ #define FEATURE_FLS_HAS_INTERRUPT_DOUBLE_BIT_FAULT_IRQ (0) /* SMC module features */ /* @brief Has stop option (register bit STOPCTRL[STOPO]). */ #define FEATURE_SMC_HAS_STOPO (1) /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ #define FEATURE_SMC_HAS_PSTOPO (0) /* @brief Has WAIT and VLPW options. */ #define FEATURE_SMC_HAS_WAIT_VLPW (0) /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) /* RCM module feature */ /* @brief Has existence of CMU loss of clock as reset source */ #define FEATURE_RCM_HAS_EXISTENCE_CMU_LOSS_OF_CLOCK (1) /* @brief Has CMU loss of clock as reset source */ #define FEATURE_RCM_HAS_CMU_LOSS_OF_CLOCK (1) /* @brief Has sticky CMU loss of clock as reset source */ #define FEATURE_RCM_HAS_STICKY_CMU_LOSS_OF_CLOCK (1) /* WDOG module features */ /* @brief The 32-bit value used for unlocking the WDOG. */ #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U) /* @brief The 32-bit value used for resetting the WDOG counter. */ #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U) /* @brief The reset value of the timeout register. */ #define FEATURE_WDOG_TO_RESET_VALUE (0x400U) /* @brief The value minimum of the timeout register. */ #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U) /* @brief The reset value of the window register. */ #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U) /* @brief The mask of the reserved bit in the CS register. */ #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U) /* @brief The value used to set WDOG source clock from LPO. */ #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL) /* @brief The first 16-bit value used for unlocking the WDOG. */ #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U) /* @brief The second 16-bit value used for unlocking the WDOG. */ #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U) /* @brief The first 16-bit value used for resetting the WDOG counter. */ #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U) /* @brief The second 16-bit value used for resetting the WDOG counter. */ #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U) /* @brief Default reset value of the CS register. */ #define FEATURE_WDOG_CS_RESET_VALUE (0x2520U) /* Interrupt module features */ /* @brief Lowest interrupt request number. */ #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn) /* @brief Highest interrupt request number. */ #define FEATURE_INTERRUPT_IRQ_MAX (LPUART0_RxTx_IRQn) /**< Number of priority bits implemented in the NVIC */ #define FEATURE_NVIC_PRIO_BITS (2U) /* @brief Has software interrupt. */ #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u) /* @brief Has pending interrupt state. */ #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u) /* @brief Has active interrupt state. */ #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (0u) /* @brief Multicore support for interrupts */ #define FEATURE_INTERRUPT_MULTICORE_SUPPORT (0u) /* @brief Registers in which the start of interrupt vector table needs to be configured */ #define FEATURE_INTERRUPT_INT_VECTORS {&S32_SCB->VTOR} /* FTM module features */ /* @brief Number of PWM channels */ #define FEATURE_FTM_CHANNEL_COUNT (8U) /* @brief Number of fault channels */ #define FTM_FEATURE_FAULT_CHANNELS (4U) /* @brief Width of control channel */ #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) /* @brief Output channel offset */ #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) /* @brief Max counter value */ #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) /* @brief Input capture for single shot */ #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) /* @brief Dithering has supported on the generated PWM signals */ #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U) /* @brief Number of interrupt vector for channels of the FTM module. */ #define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U) /* LPIT module features */ /*! @brief Number of interrupt vector for channels of the LPIT module. */ #define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1U) /*! @brief Clock names for LPIT. */ #define LPIT_CLOCK_NAMES {LPIT0_CLK} /* LPI2C module features */ /* @brief DMA instance used for LPI2C module */ #define LPI2C_DMA_INSTANCE 0U /* @brief EDMA requests for LPI2C module. */ #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} /* @brief PCC clocks for LPI2C module. */ #define LPI2C_PCC_CLOCKS {LPI2C0_CLK} /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ #define LPI2C_HAS_FAST_PLUS_MODE (0U) #define LPI2C_HAS_HIGH_SPEED_MODE (0U) #define LPI2C_HAS_ULTRA_FAST_MODE (0U) /* LPI2C module features */ /* @brief DMA instance used for LPI2C module */ #define LPI2C_DMA_INSTANCE 0U /* @brief EDMA requests for LPI2C module. */ #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} /* @brief PCC clocks for LPI2C module. */ #define LPI2C_PCC_CLOCKS {LPI2C0_CLK} /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ #define LPI2C_HAS_FAST_PLUS_MODE (0U) #define LPI2C_HAS_HIGH_SPEED_MODE (0U) #define LPI2C_HAS_ULTRA_FAST_MODE (0U) /* MSCM module features */ /* @brief Has interrupt router control registers (IRSPRCn). */ #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) /* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) /* CSEc module features */ /*! @brief CSE_PRAM offset of the page length parameter used by the following commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) /*! @brief CSE_PRAM offset of the message length parameter used by the following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) /*! @brief CSE_PRAM offset of the MAC length parameter used by the following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) /*! @brief CSE_PRAM offset of the boot size parameter used by the following commands: CMD_BOOT_DEFINE */ #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) /*! @brief CSE_PRAM offset of the boot flavor parameter used by the following commands: CMD_BOOT_DEFINE */ #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) /*! @brief CSE_PRAM offset of the Flash start address parameter used by the following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) /*! @brief CSE_PRAM offset of the verification status parameter used by the following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) /*! @brief CSE_PRAM offset of the error bits field contained by all commands */ #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) /*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: CMD_GET_ID */ #define FEATURE_CSEC_SREG_OFFSET (0x2FU) /*! @brief CSE_PRAM offset of page 0 */ #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) /*! @brief CSE_PRAM offset of page 1 */ #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) /*! @brief CSE_PRAM offset of page 2 */ #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) /*! @brief CSE_PRAM offset of page 3 */ #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) /*! @brief CSE_PRAM offset of page 4 */ #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) /*! @brief CSE_PRAM offset of page 5 */ #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) /*! @brief CSE_PRAM offset of page 6 */ #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) /*! @brief CSE_PRAM offset of page 7 */ #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) /* CRC module features */ /* @brief CRC module use for S32K. */ #define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL /* @brief Default CRC bit width */ #define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16 /* @brief Default CRC read transpose */ #define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE /* @brief Default CRC write transpose */ #define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE /* @brief Default polynomial 0x1021U */ #define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U) /* @brief Default seed value is 0xFFFFU */ #define FEATURE_CRC_DEFAULT_SEED (0xFFFFU) /* PORT module features */ /*! @brief PORT Used for setting Pins */ #define FEATURE_PINS_DRIVER_USING_PORT (1) /* @brief Has control lock (register bit PCR[LK]). */ #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) /* @brief Has open drain control (register bit PCR[ODE]). */ #define FEATURE_PINS_HAS_OPEN_DRAIN (0) /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ #define FEATURE_PORT_HAS_DIGITAL_FILTER (1) /* @brief Has trigger output to trigger other peripherals (register bit field PCR[IRQC] values). */ #define FEATURE_PORT_HAS_TRIGGER_OUT (0) /* @brief Has setting flag only (register bit field PCR[IRQC] values). */ #define FEATURE_PORT_HAS_FLAG_SET_ONLY (0) /* @brief Has over-current feature (register bit field PCR[OCIE] values). */ #define FEATURE_PINS_HAS_OVER_CURRENT (0) /* @brief Has pull resistor selection available. */ #define FEATURE_PINS_HAS_PULL_SELECTION (1) /* @brief Has slew rate control (register bit PCR[SRE]). */ #define FEATURE_PINS_HAS_SLEW_RATE (0) /* @brief Has passive filter (register bit field PCR[PFE]). */ #define FEATURE_PORT_HAS_PASSIVE_FILTER (1) /* @brief Has drive strength (register bit PCR[DSE]). */ #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1) /* @brief Has drive strength control bits*/ #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0) /* @brief Has port input disable control bits*/ #define FEATURE_PORT_HAS_INPUT_DISABLE (0) /* @brief SIM_CHIPCTL_ADC_INTERLEAVE_EN bit is not available */ #define FEATURE_PINS_HAS_ADC_INTERLEAVE_EN (0) /* MPU module features */ /* @brief Specifies hardware revision level. */ #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) /* @brief Has process identifier support. */ #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) /* @brief Specifies total number of bus masters. */ #define FEATURE_MPU_MASTER_COUNT (3U) /* @brief Specifies maximum number of masters which have separated privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx). */ #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) /* @brief Specifies maximum number of masters which have only read and write permissions (e.g. master4~7 in S32K1xx). */ #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) /* @brief Specifies number of set access control right bits for masters which have separated privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx). */ #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) /* @brief Specifies number of set access control right bits for masters which have only read and write permissions(e.g. master4~7 in S32K1xx). */ #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) /* @brief The MPU Logical Bus Master Number for core bus master. */ #define FEATURE_MPU_MASTER_CORE (0U) /* @brief The MPU Logical Bus Master Number for Debugger master. */ #define FEATURE_MPU_MASTER_DEBUGGER (1U) /* @brief The MPU Logical Bus Master Number for DMA master. */ #define FEATURE_MPU_MASTER_DMA (2U) /* @brief Specifies master number. */ #define FEATURE_MPU_MASTER \ { \ FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ } /* @brief Specifies total number of slave ports. */ #define FEATURE_MPU_SLAVE_COUNT (2U) /* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) /* @brief The MPU Slave Port Assignment for SRAM, MTB, DWT and MCM. */ #define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U) /* @brief The MPU Slave Port mask. */ #define FEATURE_MPU_SLAVE_MASK (0xC0000000U) #define FEATURE_MPU_SLAVE_SHIFT (30u) #define FEATURE_MPU_SLAVE_WIDTH (2u) #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) /* @brief DMA virtual channel to channel */ #define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) /* @brief DMA supports the following particular channel priorities: */ #define FEATURE_DMA_4_CH_PRIORITIES /* @brief DMA supports bus bandwidth control. */ #define FEATURE_DMA_ENGINE_STALL /* DMAMUX module features */ /* @brief DMAMUX peripheral is available in silicon. */ #define FEATURE_DMAMUX_AVAILABLE /* @brief Number of DMA channels. */ #define FEATURE_DMAMUX_CHANNELS (4U) /* @brief Has the periodic trigger capability */ #define FEATURE_DMAMUX_HAS_TRIG (1) /* @brief Conversion from request source to the actual DMAMUX channel */ #define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) /* @brief Mapping between request source and DMAMUX instance */ #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) /* @brief Conversion from eDMA channel index to DMAMUX channel. */ #define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) /* @brief Conversion from DMAMUX channel DMAMUX register index. */ #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) /* @brief Clock names for DMAMUX. */ #define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} /*! * @brief Structure for the DMA hardware request * * Defines the structure for the DMA hardware request collections. The user can configure the * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index * of the hardware request varies according to the to SoC. */ typedef enum { EDMA_REQ_DISABLED = 0U, EDMA_REQ_LPUART0_RX = 2U, EDMA_REQ_LPUART0_TX = 3U, EDMA_REQ_LPUART1_RX = 4U, EDMA_REQ_LPUART1_TX = 5U, EDMA_REQ_FLEXIO_SHIFTER0 = 10U, EDMA_REQ_FLEXIO_SHIFTER1 = 11U, EDMA_REQ_FLEXIO_SHIFTER2 = 12U, EDMA_REQ_FLEXIO_SHIFTER3 = 13U, EDMA_REQ_LPSPI0_RX = 14U, EDMA_REQ_LPSPI0_TX = 15U, EDMA_REQ_LPSPI1_RX = 16U, EDMA_REQ_LPSPI1_TX = 17U, EDMA_REQ_FTM1_CHANNEL_0 = 20U, EDMA_REQ_FTM1_CHANNEL_1 = 21U, EDMA_REQ_FTM1_CHANNEL_2 = 22U, EDMA_REQ_FTM1_CHANNEL_3 = 23U, EDMA_REQ_FTM1_CHANNEL_4 = 24U, EDMA_REQ_FTM1_CHANNEL_5 = 25U, EDMA_REQ_FTM1_CHANNEL_6 = 26U, EDMA_REQ_FTM1_CHANNEL_7 = 27U, EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, EDMA_REQ_ADC0 = 42U, EDMA_REQ_LPI2C0_RX = 44U, EDMA_REQ_LPI2C0_TX = 45U, EDMA_REQ_PDB0 = 46U, EDMA_REQ_CMP0 = 48U, EDMA_REQ_PORTA = 49U, EDMA_REQ_PORTB = 50U, EDMA_REQ_PORTC = 51U, EDMA_REQ_PORTD = 52U, EDMA_REQ_PORTE = 53U, EDMA_REQ_FLEXCAN0 = 54U, EDMA_REQ_LPTMR0 = 59U, EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U } dma_request_source_t; /* TRGMUX module features */ /*! * @brief Enumeration for trigger source module of TRGMUX * * Describes all possible inputs (trigger sources) of the TRGMUX IP * This enumeration depends on the supported instances in device */ enum trgmux_trigger_source_e { TRGMUX_TRIG_SOURCE_DISABLED = 0U, TRGMUX_TRIG_SOURCE_VDD = 1U, TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U, }; /*! * @brief Enumeration for target module of TRGMUX * * Describes all possible outputs (target modules) of the TRGMUX IP * This enumeration depends on the supported instances in device */ enum trgmux_target_module_e { TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U, }; /* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ #define FEATURE_TRGMUX_TARGET_MODULE \ { \ TRGMUX_TARGET_MODULE_DMA_CH0, \ TRGMUX_TARGET_MODULE_DMA_CH1, \ TRGMUX_TARGET_MODULE_DMA_CH2, \ TRGMUX_TARGET_MODULE_DMA_CH3, \ TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ TRGMUX_TARGET_MODULE_LPUART0_TRG, \ TRGMUX_TARGET_MODULE_LPUART1_TRG, \ TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ } /* LPSPI module features */ /* @brief Initial value for state structure */ #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL} /* @brief Clock indexes for LPSPI clock */ #define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK}; /* FlexIO module features */ /* @brief Define the maximum number of shifters for any FlexIO instance. */ #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) /* @brief Define DMA request names for Flexio. */ #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 /* LPUART module features */ /* @brief Has extended data register ED. */ #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FEATURE_LPUART_FIFO_SIZE (4U) /* @brief Supports two match addresses to filter incoming frames. */ #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits. */ #define FEATURE_LPUART_HAS_DMA_ENABLE (1) /* @brief Flag clearance mask for STAT register. */ #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) /* @brief Flag clearance mask for FIFO register. */ #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) /* @brief Reset mask for FIFO register. */ #define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) /* @brief Default oversampling ratio. */ #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) /* @brief Default baud rate modulo divisor. */ #define FEATURE_LPUART_DEFAULT_SBR (0x04UL) /* @brief Clock names for LPUART. */ #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK} /* ADC module features */ /*! @brief ADC feature flag for extended number of SC1 and R registers, * generically named 'alias registers' */ #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) #define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1 /*! @brief ADC feature flag for defining number of external ADC channels. * If each ADC instance has different number of external channels, then * this define is set with the maximum value. */ #define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) #define FEATURE_ADC_HAS_CHANNEL_2 (1) #define FEATURE_ADC_HAS_CHANNEL_8 (1) #define ADC_CLOCKS {ADC0_CLK} /*! @brief ADC number of control channels */ #if FEATURE_ADC_HAS_EXTRA_NUM_REGS #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT #else #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT #endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ /*! @brief ADC default Sample Time from RM */ #define ADC_DEFAULT_SAMPLE_TIME (0x0CU) /*! @brief ADC default User Gain from RM */ #define ADC_DEFAULT_USER_GAIN (0x04U) /* @brief Max of adc clock frequency */ #define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) /* @brief Min of adc clock frequency */ #define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) /* CAN module features */ /* @brief Frames available in Rx FIFO flag shift */ #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U) /* @brief Rx FIFO warning flag shift */ #define FEATURE_CAN_RXFIFO_WARNING (6U) /* @brief Rx FIFO overflow flag shift */ #define FEATURE_CAN_RXFIFO_OVERFLOW (7U) /* @brief Has Flexible Data Rate for CAN0 */ #define FEATURE_CAN0_HAS_FD (1) /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */ #define FEATURE_CAN0_MAX_MB_NUM (32U) /* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */ #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1) /* @brief Has DMA enable (bit field MCR[DMA]). */ #define FEATURE_CAN_HAS_DMA_ENABLE (1) /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ #define FEATURE_CAN_MAX_MB_NUM (32U) /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */ #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM } /* @brief Has Pretending Networking mode */ #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1) /* @brief Has Stuff Bit Count Enable Bit */ #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0) /* @brief Has ISO CAN FD Enable Bit */ #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1) /* @brief Has Message Buffer Data Size Region 1 */ #define FEATURE_CAN_HAS_MBDSR1 (0) /* @brief Has Message Buffer Data Size Region 2 */ #define FEATURE_CAN_HAS_MBDSR2 (0) /* @brief DMA hardware requests for all FlexCAN instances */ #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 } /* @brief Maximum number of Message Buffers IRQs */ #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U) /* @brief Message Buffers IRQs */ #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \ CAN_ORed_16_31_MB_IRQS } /* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */ #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) /* @brief Has Self Wake Up mode */ #define FEATURE_CAN_HAS_SELF_WAKE_UP (0) /* @brief Has Flexible Data Rate */ #define FEATURE_CAN_HAS_FD (1) /* @brief Clock name for the PE oscillator clock source */ #define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK /* @bried FlexCAN has Detection And Correction of Memory Errors */ #define FEATURE_CAN_HAS_MEM_ERR_DET (0) /* LPTMR module features */ /* @brief LPTMR pulse counter input options */ #define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) /* OSIF module features */ #define FEATURE_OSIF_USE_SYSTICK (1) #define FEATURE_OSIF_USE_PIT (0) #define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ /* PDB module features */ /* @brief PDB has back-to-back at instance level */ #define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (0) #endif /* S32K118_FEATURES_H */ /******************************************************************************* * EOF ******************************************************************************/