/********************************************************************************************************************* * Copyright (c) 2015-2016, Infineon Technologies AG * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials provided with the distribution. * * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote * products derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with * Infineon Technologies AG dave@infineon.com). *********************************************************************************************************************/ /****************************************************************************************************//** * @file XMC1400.h * * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for * XMC1400 from Infineon. * * @version V1.1.0 (Reference Manual v1.1) * @date 30. August 2016 * * @note Generated with SVDConv V2.87l * from CMSIS SVD File 'XMC1400_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1), *******************************************************************************************************/ /** @addtogroup Infineon * @{ */ /** @addtogroup XMC1400 * @{ */ #ifndef XMC1400_H #define XMC1400_H #ifdef __cplusplus extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ /* --------------------- XMC1400 Specific Interrupt Numbers --------------------- */ IRQ0_IRQn = 0, IRQ1_IRQn = 1, IRQ2_IRQn = 2, IRQ3_IRQn = 3, IRQ4_IRQn = 4, IRQ5_IRQn = 5, IRQ6_IRQn = 6, IRQ7_IRQn = 7, IRQ8_IRQn = 8, IRQ9_IRQn = 9, IRQ10_IRQn = 10, IRQ11_IRQn = 11, IRQ12_IRQn = 12, IRQ13_IRQn = 13, IRQ14_IRQn = 14, IRQ15_IRQn = 15, IRQ16_IRQn = 16, IRQ17_IRQn = 17, IRQ18_IRQn = 18, IRQ19_IRQn = 19, IRQ20_IRQn = 20, IRQ21_IRQn = 21, IRQ22_IRQn = 22, IRQ23_IRQn = 23, IRQ24_IRQn = 24, IRQ25_IRQn = 25, IRQ26_IRQn = 26, IRQ27_IRQn = 27, IRQ28_IRQn = 28, IRQ29_IRQn = 29, IRQ30_IRQn = 30, IRQ31_IRQn = 31 } IRQn_Type; /** @addtogroup Configuration_of_CMSIS * @{ */ /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ #include "system_XMC1400.h" /*!< XMC1400 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ /* Macro to modify desired bitfields of a register */ #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ ((uint32_t)mask)) | \ (reg & ((uint32_t)~((uint32_t)mask))) /* Macro to modify desired bitfields of a register */ #define WR_REG_SIZE(reg, mask, pos, val, size) { \ uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ reg = (uint##size##_t) (VAL2 | VAL4);\ } /** Macro to read bitfields from a register */ #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) /** Macro to read bitfields from a register */ #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ (uint32_t)mask) >> pos) ) /** Macro to set a bit in register */ #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<