/* ** ################################################################### ** Processor: S32K144 ** Reference manual: S32K1XXRM Rev. 9, 09/2018 ** Version: rev. 4.2, 2019-02-19 ** Build: b190219 ** ** Abstract: ** Peripheral Access Layer for S32K144 ** ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2019 NXP ** All rights reserved. ** ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ** THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-04-09) - Iulian Talpiga ** Initial version. ** - rev. 1.1 (2015-05-19) - Bogdan Nitu ** Updated interrupts table ** Removed SIM_CHIPCTL_DAC2CMP ** Compacted PORT_PCR registers ** Compacted PCC registers ** - rev. 1.2 (2015-06-02) - Bogdan Nitu ** Added 'U' suffix to all integer constants ** Use "" instead of <> for Platform type inclusion ** CNT register from WDOG module is RW ** - rev. 1.3 (2015-08-05) - Iulian Talpiga ** Synchronized with latest RDP ** Removed OSC32 module ** Removed reserved registers ** Incorporated bit band acces macros ** Switched to standard C99 data types ** Added 'u' to constants ** Added size defines for register arrays ** Define peripheral instance count ** - rev. 1.4 (2015-08-10) - Iulian Talpiga ** Compacted TRGMUX registers ** Defined array index offsets for PCC and TRGMUX ** Added FPU registers ** Group FTM channel registers ** Added interrupt information to peripherals ** Renamed CAN interrupts according to the reference manual ** Added author information to revisions ** - rev. 1.5 (2015-09-16) - Iulian Talpiga ** Renamed NVIC and SCB to avoid conflict ** Compacted CAN Wake-up Message buffers ** Added CAN embedded RAM ** Updated interrupts: LPIT, FTFE, LPUART,ACMP ** Corrected ADC_SC1_ADCH_WIDTH ** Compacted PDB registers ** Corrected CAN, FTM, and PDB count defines ** Guarding register acces macro against redefintion ** - rev. 1.6 (2015-09-29) - Iulian Talpiga ** Added WATER and FIFO registers to LPUART. ** - rev. 1.7 (2015-10-21) - Iulian Talpiga ** Updated ADC, AIPS, CMP, LMEM, LPTMR, PMC, PORT, RCM, RTC, SCG, SIM ** Compacted MPU and LPIT ** Added FSL_SysTick ** Updated doxygen documentation grouping ** Updated interrupts: RCM ** - rev. 1.8 (2016-01-06) - Iulian Talpiga ** Updated DMA, compacted TCD registers ** Updated SCG, removed SC2P - SC16P ** Added 8 and 16 bit access to DATA register, CRC module ** - rev. 1.9 (2016-02-15) - Iulian Talpiga ** Updated CRC, renamed DATA union ** Updated PMC, added CLKBIASDIS bitfield ** Added FSL_NVIC registers to SVD ** - rev. 2.0 (2016-04-07) - Iulian Talpiga ** Updated support for Rev2.0 silicon (0N47T) ** Updated ADC, AIPS, DMA, FlexIO, FTM, GPIO, LPI2C, LPIT, LPSPI, MCM, MPU, MSCM, PMC, RTC, RCM, PCC, RTC, SCG, SIM, TRGMUX and WDOG module ** Updated interrupts ** Added EIM and ERM modules ** Added EIM and ERM modules ** - rev. 2.1 (2016-06-10) - Iulian Talpiga ** Updated to latest RM ** Minor changes to: CAN, EIM, LPI2C, MPU, PCC, PMC, RTC, SIM and TRGMUX ** - rev. 2.2 (2016-08-02) - Iulian Talpiga ** Updated to latest RM ** Minor changes to: ADC, CAN, CRC, FTFC, LMEM, LPI2C, MCM, MSCM, PCC, RTC, SIM ** Added CSE_PRAM ** - rev. 2.3 (2016-09-09) - Iulian Talpiga ** Updated to latest RM ** Minor changes to: PCC, FSL_NVIC and FTM ** - rev. 2.4 (2016-09-28) - Iulian Talpiga ** Fix RAMn array size in FlexCAN ** Fix FCSESTAT bit order ** Added CP0CFG0, CP0CFG1,CP0CFG2 and CP0CFG3 in MSCM ** Fixed STIR register in FSL_NVIC ** Fixed SHPR3 and ACTLR registers in FSL_SCB ** - rev. 2.5 (2016-11-25) - Iulian Talpiga ** Fix FRAC bit-field in PCC module ** Removed BITBAND_ACCESS macros ** Added MISRA declarations ** Updated copyright ** Changed prefix of NVIC, SCB and SysTick to S32_ ** - rev. 2.6 (2017-01-09) - Iulian Talpiga ** Fix interrupts for CAN, LPUART, FTFC ** - rev. 2.7 (2017-02-22) - Iulian Talpiga ** Update header as per rev S32K14XRM Rev. 2, 02/2017 ** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM ** - rev. 2.8 (2017-03-27) - Iulian Talpiga ** Synchronized PCC_FlexIO on S32K Family ** - rev. 3.0 (2017-08-04) - Mihai Volmer ** Update header as per rev S32K1XXRM Rev. 4, 06/2017 ** Updated modules CAN, MCM and PORTn ** - rev. 3.1 (2017-09-25) - Andrei Bolojan ** Update NVIC Size of Registers Arrays ** - rev. 4.0 (2018-02-28) - Mihai Volmer ** Updated header as per rev S32K1XXRM Rev. 6, 12/2017 ** Updated modules ERM, I2C, MSCM and SIM ** - rev. 4.1 (2018-07-19) - Dan Nastasa ** Updated the header based on S32K1XXRM Rev. 8, 06/2018. ** - rev. 4.2 (2019-02-19) - Ionut Pavel ** Updated the header based on S32K1XXRM Rev. 9, 09/2018. ** ** ################################################################### */ /*! * @file S32K144.h * @version 4.2 * @date 2019-02-19 * @brief Peripheral Access Layer for S32K144 * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(S32K144_H_) /* Check if memory map has not been already included */ #define S32K144_H_ #define MCU_S32K144 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error S32K144 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0400u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0002u /* ---------------------------------------------------------------------------- -- Generic macros ---------------------------------------------------------------------------- */ /* IO definitions (access restrictions to peripheral registers) */ /** * IO Type Qualifiers are used * \li to specify the access to peripheral variables. * \li for automatic generation of peripheral register debug information. */ #ifndef __IO #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ #endif /** * @brief 32 bits memory read macro. */ #if !defined(REG_READ32) #define REG_READ32(address) (*(volatile uint32_t*)(address)) #endif /** * @brief 32 bits memory write macro. */ #if !defined(REG_WRITE32) #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) #endif /** * @brief 32 bits bits setting macro. */ #if !defined(REG_BIT_SET32) #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) #endif /** * @brief 32 bits bits clearing macro. */ #if !defined(REG_BIT_CLEAR32) #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) #endif /** * @brief 32 bit clear bits and set with new value * @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 */ #if !defined(REG_RMW32) #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) #endif /* ---------------------------------------------------------------------------- -- Interrupt vector numbers for S32K144 ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers_S32K144 Interrupt vector numbers for S32K144 * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 139u /**< Number of interrupts in the Vector table */ /** * @brief Defines the Interrupt Numbers definitions * * This enumeration is used to configure the interrupts. * * Implements : IRQn_Type_Class */ typedef enum { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ DMA4_IRQn = 4u, /**< DMA channel 4 transfer complete */ DMA5_IRQn = 5u, /**< DMA channel 5 transfer complete */ DMA6_IRQn = 6u, /**< DMA channel 6 transfer complete */ DMA7_IRQn = 7u, /**< DMA channel 7 transfer complete */ DMA8_IRQn = 8u, /**< DMA channel 8 transfer complete */ DMA9_IRQn = 9u, /**< DMA channel 9 transfer complete */ DMA10_IRQn = 10u, /**< DMA channel 10 transfer complete */ DMA11_IRQn = 11u, /**< DMA channel 11 transfer complete */ DMA12_IRQn = 12u, /**< DMA channel 12 transfer complete */ DMA13_IRQn = 13u, /**< DMA channel 13 transfer complete */ DMA14_IRQn = 14u, /**< DMA channel 14 transfer complete */ DMA15_IRQn = 15u, /**< DMA channel 15 transfer complete */ DMA_Error_IRQn = 16u, /**< DMA error interrupt channels 0-15 */ MCM_IRQn = 17u, /**< FPU sources */ FTFC_IRQn = 18u, /**< FTFC Command complete */ Read_Collision_IRQn = 19u, /**< FTFC Read collision */ LVD_LVW_IRQn = 20u, /**< PMC Low voltage detect interrupt */ FTFC_Fault_IRQn = 21u, /**< FTFC Double bit fault detect */ WDOG_EWM_IRQn = 22u, /**< Single interrupt vector for WDOG and EWM */ RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ LPI2C0_Master_IRQn = 24u, /**< LPI2C0 Master Interrupt */ LPI2C0_Slave_IRQn = 25u, /**< LPI2C0 Slave Interrupt */ LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ LPSPI2_IRQn = 28u, /**< LPSPI2 Interrupt */ LPUART0_RxTx_IRQn = 31u, /**< LPUART0 Transmit / Receive Interrupt */ LPUART1_RxTx_IRQn = 33u, /**< LPUART1 Transmit / Receive Interrupt */ LPUART2_RxTx_IRQn = 35u, /**< LPUART2 Transmit / Receive Interrupt */ ADC0_IRQn = 39u, /**< ADC0 interrupt request. */ ADC1_IRQn = 40u, /**< ADC1 interrupt request. */ CMP0_IRQn = 41u, /**< CMP0 interrupt request */ ERM_single_fault_IRQn = 44u, /**< ERM single bit error correction */ ERM_double_fault_IRQn = 45u, /**< ERM double bit error non-correctable */ RTC_IRQn = 46u, /**< RTC alarm interrupt */ RTC_Seconds_IRQn = 47u, /**< RTC seconds interrupt */ LPIT0_Ch0_IRQn = 48u, /**< LPIT0 channel 0 overflow interrupt */ LPIT0_Ch1_IRQn = 49u, /**< LPIT0 channel 1 overflow interrupt */ LPIT0_Ch2_IRQn = 50u, /**< LPIT0 channel 2 overflow interrupt */ LPIT0_Ch3_IRQn = 51u, /**< LPIT0 channel 3 overflow interrupt */ PDB0_IRQn = 52u, /**< PDB0 interrupt */ SCG_IRQn = 57u, /**< SCG bus interrupt request */ LPTMR0_IRQn = 58u, /**< LPTIMER interrupt request */ PORTA_IRQn = 59u, /**< Port A pin detect interrupt */ PORTB_IRQn = 60u, /**< Port B pin detect interrupt */ PORTC_IRQn = 61u, /**< Port C pin detect interrupt */ PORTD_IRQn = 62u, /**< Port D pin detect interrupt */ PORTE_IRQn = 63u, /**< Port E pin detect interrupt */ SWI_IRQn = 64u, /**< Software interrupt */ PDB1_IRQn = 68u, /**< PDB1 interrupt */ FLEXIO_IRQn = 69u, /**< FlexIO Interrupt */ CAN0_ORed_IRQn = 78u, /**< CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ CAN0_Error_IRQn = 79u, /**< CAN0 Interrupt indicating that errors were detected on the CAN bus */ CAN0_Wake_Up_IRQn = 80u, /**< CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ CAN0_ORed_0_15_MB_IRQn = 81u, /**< CAN0 OR'ed Message buffer (0-15) */ CAN0_ORed_16_31_MB_IRQn = 82u, /**< CAN0 OR'ed Message buffer (16-31) */ CAN1_ORed_IRQn = 85u, /**< CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ CAN1_Error_IRQn = 86u, /**< CAN1 Interrupt indicating that errors were detected on the CAN bus */ CAN1_ORed_0_15_MB_IRQn = 88u, /**< CAN1 OR'ed Interrupt for Message buffer (0-15) */ CAN2_ORed_IRQn = 92u, /**< CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ CAN2_Error_IRQn = 93u, /**< CAN2 Interrupt indicating that errors were detected on the CAN bus */ CAN2_ORed_0_15_MB_IRQn = 95u, /**< CAN2 OR'ed Message buffer (0-15) */ FTM0_Ch0_Ch1_IRQn = 99u, /**< FTM0 Channel 0 and 1 interrupt */ FTM0_Ch2_Ch3_IRQn = 100u, /**< FTM0 Channel 2 and 3 interrupt */ FTM0_Ch4_Ch5_IRQn = 101u, /**< FTM0 Channel 4 and 5 interrupt */ FTM0_Ch6_Ch7_IRQn = 102u, /**< FTM0 Channel 6 and 7 interrupt */ FTM0_Fault_IRQn = 103u, /**< FTM0 Fault interrupt */ FTM0_Ovf_Reload_IRQn = 104u, /**< FTM0 Counter overflow and Reload interrupt */ FTM1_Ch0_Ch1_IRQn = 105u, /**< FTM1 Channel 0 and 1 interrupt */ FTM1_Ch2_Ch3_IRQn = 106u, /**< FTM1 Channel 2 and 3 interrupt */ FTM1_Ch4_Ch5_IRQn = 107u, /**< FTM1 Channel 4 and 5 interrupt */ FTM1_Ch6_Ch7_IRQn = 108u, /**< FTM1 Channel 6 and 7 interrupt */ FTM1_Fault_IRQn = 109u, /**< FTM1 Fault interrupt */ FTM1_Ovf_Reload_IRQn = 110u, /**< FTM1 Counter overflow and Reload interrupt */ FTM2_Ch0_Ch1_IRQn = 111u, /**< FTM2 Channel 0 and 1 interrupt */ FTM2_Ch2_Ch3_IRQn = 112u, /**< FTM2 Channel 2 and 3 interrupt */ FTM2_Ch4_Ch5_IRQn = 113u, /**< FTM2 Channel 4 and 5 interrupt */ FTM2_Ch6_Ch7_IRQn = 114u, /**< FTM2 Channel 6 and 7 interrupt */ FTM2_Fault_IRQn = 115u, /**< FTM2 Fault interrupt */ FTM2_Ovf_Reload_IRQn = 116u, /**< FTM2 Counter overflow and Reload interrupt */ FTM3_Ch0_Ch1_IRQn = 117u, /**< FTM3 Channel 0 and 1 interrupt */ FTM3_Ch2_Ch3_IRQn = 118u, /**< FTM3 Channel 2 and 3 interrupt */ FTM3_Ch4_Ch5_IRQn = 119u, /**< FTM3 Channel 4 and 5 interrupt */ FTM3_Ch6_Ch7_IRQn = 120u, /**< FTM3 Channel 6 and 7 interrupt */ FTM3_Fault_IRQn = 121u, /**< FTM3 Fault interrupt */ FTM3_Ovf_Reload_IRQn = 122u /**< FTM3 Counter overflow and Reload interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers_S32K144 */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer for S32K144 ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer_S32K144 Device Peripheral Access Layer for S32K144 * @{ */ /* @brief This module covers memory mapped registers available on SoC */ /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Size of Registers Arrays */ #define ADC_SC1_COUNT 16u #define ADC_R_COUNT 16u #define ADC_CV_COUNT 2u /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ } ADC_Type, *ADC_MemMapPtr; /** Number of instances of the ADC module. */ #define ADC_INSTANCE_COUNT (2u) /* ADC - Peripheral instance base addresses */ /** Peripheral ADC0 base address */ #define ADC0_BASE (0x4003B000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) /** Peripheral ADC1 base address */ #define ADC1_BASE (0x40027000u) /** Peripheral ADC1 base pointer */ #define ADC1 ((ADC_Type *)ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0, ADC1 } /** Number of interrupt vector arrays for the ADC module. */ #define ADC_IRQS_ARR_COUNT (1u) /** Number of interrupt channels for the ADC module. */ #define ADC_IRQS_CH_COUNT (1u) /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* SC1 Bit Fields */ #define ADC_SC1_ADCH_MASK 0x1Fu #define ADC_SC1_ADCH_SHIFT 0u #define ADC_SC1_ADCH_WIDTH 5u #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<