/********************************************************************************************************************* * Copyright (c) 2015-2016, Infineon Technologies AG * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the * following conditions are met: * * Redistributions of source code must retain the above copyright notice, this list of conditions and the following * disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials provided with the distribution. * * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote * products derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with * Infineon Technologies AG dave@infineon.com). *********************************************************************************************************************/ /****************************************************************************************************//** * @file XMC4700.h * * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for * XMC4700 from Infineon. * * @version V1.3.0 (Reference Manual v1.3) * @date 30. August 2016 * * @note Generated with SVDConv V2.87l * from CMSIS SVD File 'XMC4700_Processed_SVD.xml' Version 1.3.0 (Reference Manual v1.3), *******************************************************************************************************/ /** @addtogroup Infineon * @{ */ /** @addtogroup XMC4700 * @{ */ #ifndef XMC4700_H #define XMC4700_H #ifdef __cplusplus extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ /* --------------------- XMC4700 Specific Interrupt Numbers --------------------- */ SCU_0_IRQn = 0, /*!< 0 System Control */ ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ VADC0_G2_0_IRQn = 26, /*!< 26 Analog to Digital Converter Group 2 */ VADC0_G2_1_IRQn = 27, /*!< 27 Analog to Digital Converter Group 2 */ VADC0_G2_2_IRQn = 28, /*!< 28 Analog to Digital Converter Group 2 */ VADC0_G2_3_IRQn = 29, /*!< 29 Analog to Digital Converter Group 2 */ VADC0_G3_0_IRQn = 30, /*!< 30 Analog to Digital Converter Group 3 */ VADC0_G3_1_IRQn = 31, /*!< 31 Analog to Digital Converter Group 3 */ VADC0_G3_2_IRQn = 32, /*!< 32 Analog to Digital Converter Group 3 */ VADC0_G3_3_IRQn = 33, /*!< 33 Analog to Digital Converter Group 3 */ DSD0_M_0_IRQn = 34, /*!< 34 Delta Sigma Demodulator Main */ DSD0_M_1_IRQn = 35, /*!< 35 Delta Sigma Demodulator Main */ DSD0_M_2_IRQn = 36, /*!< 36 Delta Sigma Demodulator Main */ DSD0_M_3_IRQn = 37, /*!< 37 Delta Sigma Demodulator Main */ DSD0_A_4_IRQn = 38, /*!< 38 Delta Sigma Demodulator Auxiliary */ DSD0_A_5_IRQn = 39, /*!< 39 Delta Sigma Demodulator Auxiliary */ DSD0_A_6_IRQn = 40, /*!< 40 Delta Sigma Demodulator Auxiliary */ DSD0_A_7_IRQn = 41, /*!< 41 Delta Sigma Demodulator Auxiliary */ DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ CCU42_0_IRQn = 52, /*!< 52 Capture Compare Unit 4 (Module 2) */ CCU42_1_IRQn = 53, /*!< 53 Capture Compare Unit 4 (Module 2) */ CCU42_2_IRQn = 54, /*!< 54 Capture Compare Unit 4 (Module 2) */ CCU42_3_IRQn = 55, /*!< 55 Capture Compare Unit 4 (Module 2) */ CCU43_0_IRQn = 56, /*!< 56 Capture Compare Unit 4 (Module 3) */ CCU43_1_IRQn = 57, /*!< 57 Capture Compare Unit 4 (Module 3) */ CCU43_2_IRQn = 58, /*!< 58 Capture Compare Unit 4 (Module 3) */ CCU43_3_IRQn = 59, /*!< 59 Capture Compare Unit 4 (Module 3) */ CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ CCU81_0_IRQn = 64, /*!< 64 Capture Compare Unit 8 (Module 1) */ CCU81_1_IRQn = 65, /*!< 65 Capture Compare Unit 8 (Module 1) */ CCU81_2_IRQn = 66, /*!< 66 Capture Compare Unit 8 (Module 1) */ CCU81_3_IRQn = 67, /*!< 67 Capture Compare Unit 8 (Module 1) */ POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ POSIF1_0_IRQn = 70, /*!< 70 Position Interface (Module 1) */ POSIF1_1_IRQn = 71, /*!< 71 Position Interface (Module 1) */ CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ USIC2_0_IRQn = 96, /*!< 96 Universal Serial Interface Channel (Module 2) */ USIC2_1_IRQn = 97, /*!< 97 Universal Serial Interface Channel (Module 2) */ USIC2_2_IRQn = 98, /*!< 98 Universal Serial Interface Channel (Module 2) */ USIC2_3_IRQn = 99, /*!< 99 Universal Serial Interface Channel (Module 2) */ USIC2_4_IRQn = 100, /*!< 100 Universal Serial Interface Channel (Module 2) */ USIC2_5_IRQn = 101, /*!< 101 Universal Serial Interface Channel (Module 2) */ LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ SDMMC0_0_IRQn = 106, /*!< 106 Multi Media Card Interface */ USB0_0_IRQn = 107, /*!< 107 Universal Serial Bus (Module 0) */ ETH0_0_IRQn = 108, /*!< 108 Ethernet (Module 0) */ GPDMA1_0_IRQn = 110 /*!< 110 General Purpose DMA Unit 1 */ } IRQn_Type; /** @addtogroup Configuration_of_CMSIS * @{ */ /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ #define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ #define __MPU_PRESENT 1 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present or not */ /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #include "system_XMC4700.h" /*!< XMC4700 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ /* Macro to modify desired bitfields of a register */ #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ ((uint32_t)mask)) | \ (reg & ((uint32_t)~((uint32_t)mask))) /* Macro to modify desired bitfields of a register */ #define WR_REG_SIZE(reg, mask, pos, val, size) { \ uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ reg = (uint##size##_t) (VAL2 | VAL4);\ } /** Macro to read bitfields from a register */ #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) /** Macro to read bitfields from a register */ #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ (uint32_t)mask) >> pos) ) /** Macro to set a bit in register */ #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<