// <<< Use Configuration Wizard in Context Menu >>> // Debug MCU Configuration // DBG_SLEEP // Debug Sleep Mode // 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled // 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK // DBG_STOP // Debug Stop Mode // 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks // 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active // DBG_STANDBY // Debug Standby Mode // 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. // 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active // DBG_IWDG_STOP // Debug independent watchdog stopped when core is halted // 0: The watchdog counter clock continues even if the core is halted // 1: The watchdog counter clock is stopped when the core is halted // DBG_WWDG_STOP // Debug window watchdog stopped when core is halted // 0: The window watchdog counter clock continues even if the core is halted // 1: The window watchdog counter clock is stopped when the core is halted // DBG_TIM1_STOP // Timer 1 counter stopped when core is halted // 0: The clock of the involved Timer Counter is fed even if the core is halted // 1: The clock of the involved Timer counter is stopped when the core is halted // DBG_TIM2_STOP // Timer 2 counter stopped when core is halted // 0: The clock of the involved Timer Counter is fed even if the core is halted // 1: The clock of the involved Timer counter is stopped when the core is halted // DBG_TIM3_STOP // Timer 3 counter stopped when core is halted // 0: The clock of the involved Timer Counter is fed even if the core is halted // 1: The clock of the involved Timer counter is stopped when the core is halted // DBG_TIM4_STOP // Timer 4 counter stopped when core is halted // 0: The clock of the involved Timer Counter is fed even if the core is halted // 1: The clock of the involved Timer counter is stopped when the core is halted // DBG_CAN1_STOP // Debug CAN1 stopped when Core is halted // 0: Same behavior as in normal mode // 1: CAN1 receive registers are frozen // DBG_I2C1_SMBUS_TIMEOUT // I2C1 SMBUS timeout mode stopped when Core is halted // 0: Same behavior as in normal mode // 1: The SMBUS timeout is frozen // DBG_I2C2_SMBUS_TIMEOUT // I2C2 SMBUS timeout mode stopped when Core is halted // 0: Same behavior as in normal mode // 1: The SMBUS timeout is frozen // DBG_TIM8_STOP // Timer 8 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM5_STOP // Timer 5 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM6_STOP // Timer 6 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM7_STOP // Timer 7 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_CAN2_STOP // Debug CAN2 stopped when Core is halted // 0: Same behavior as in normal mode // 1: CAN2 receive registers are frozen // DBG_TIM12_STOP // Timer 12 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM13_STOP // Timer 13 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM14_STOP // Timer 14 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM9_STOP // Timer 9 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM10_STOP // Timer 10 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DBG_TIM11_STOP // Timer 11 counter stopped when core is halted // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). // DbgMCU_CR = 0x00000007; // <<< end of configuration section >>>