380 lines
16 KiB
ArmAsm
380 lines
16 KiB
ArmAsm
/*********************************************************************************************************************
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* @file startup_XMC1400.S
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* @brief CMSIS Core Device Startup File for Infineon XMC1400 Device Series
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* @version V1.1
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* @date 05 Jan 2016
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*
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* @cond
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*********************************************************************************************************************
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* Copyright (c) 2015-2016, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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**************************** Change history ********************************
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* V1.0, Sep, 03, 2015 JFT:Initial version
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* MCLK=8MHz, PCLK=16MHz
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* V1.1, Jan, 05, 2016 JFT:Fix .reset section attributes
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*
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* @endcond
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*/
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/*****************************************************************************
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* <h> Clock system handling by SSW
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* <h> CLK_VAL1 Configuration
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* <o0.0..9> FDIV Fractional Divider Selection <0-1023>
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* <i> Deafult: 0. Fractional part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024))
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* <o0.10..17> IDIV Divider Selection <1-16>
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* <i> Deafult: 6. Interger part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024) = 8MHz)
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* <o0.18> PCLKSEL PCLK Clock Select
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* <0=> PCLK = MCLK
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* <1=> PCLK = 2 x MCLK
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* <i> Deafult: 2 x MCLK
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* <o0.19..21> RTCCLKSEL RTC Clock Select
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* <0=> 32.768kHz standby clock
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* <1=> 32.768kHz external clock from ERU0.IOUT0
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* <2=> 32.768kHz external clock from ACMP0.OUT
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* <3=> 32.768kHz external clock from ACMP1.OUT
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* <4=> 32.768kHz external clock from ACMP2.OUT
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* <5=> 32.768kHz XTAL clock via OSC_LP
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* <6=> Reserved
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* <7=> Reserved
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* <i> Deafult: 32.768kHz standby clock
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* <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]
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* </h>
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*****************************************************************************/
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#define CLKVAL1_SSW 0x00041800
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/*****************************************************************************
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* <h> CLK_VAL2 Configuration
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* <o0.0> disable VADC and SHS Gating
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* <o0.1> disable CCU80 Gating
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* <o0.2> disable CCU40 Gating
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* <o0.3> disable USIC0 Gating
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* <o0.4> disable BCCU0 Gating
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* <o0.5> disable LEDTS0 Gating
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* <o0.6> disable LEDTS1 Gating
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* <o0.7> disable POSIF0 Gating
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* <o0.8> disable MATH Gating
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* <o0.9> disable WDT Gating
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* <o0.10> disable RTC Gating
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* <o0.16> disable CCU81 Gating
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* <o0.17> disable CCU41 Gating
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* <o0.18> disable USIC1 Gating
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* <o0.19> disable LEDTS2 Gating
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* <o0.20> disable POSIF1 Gating
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* <o0.21> disable MCAN0 Gating
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* <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
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* </h>
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*****************************************************************************/
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#define CLKVAL2_SSW 0x00000100
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/* A couple of macros to ease definition of the various handlers */
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.macro Insert_InterruptHandler Interrupt
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.weak \Interrupt\()_Handler
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.thumb_set \Interrupt\()_Handler, Default_Handler
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.endm
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.macro Insert_InterruptVeener Interrupt
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.globl \Interrupt\()_Veener
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\Interrupt\()_Veener:
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LDR R0, =\Interrupt\()_Handler
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BX R0
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.endm
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/* ================== START OF VECTOR TABLE DEFINITION ====================== */
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/* Vector Table - This is indirectly branched to through the veneers */
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.syntax unified
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.cpu cortex-m0
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.section .reset, "a", %progbits
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.align 2
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.globl __Vectors
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.type __Vectors, %object
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__Vectors:
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.long __initial_sp /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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/*
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* All entries below are redundant for M0, but are retained because they can
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* in the future be directly ported to M0 Plus devices.
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*/
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.long 0 /* Reserved */
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.long HardFault_Handler /* Hard Fault Handler */
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.long CLKVAL1_SSW /* Reserved */
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.long CLKVAL2_SSW /* Reserved */
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.long 0x55AA11EE /* Reserved for OpenBLT checksum*/
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#ifdef RETAIN_VECTOR_TABLE
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* Interrupt Handlers for Service Requests (SR) from XMC1400 Peripherals */
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.long IRQ0_Handler /* SCU.SR0, CAN0.SR0, CCU40.SR0, SCU.SR0 | CAN0.SR0 */
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.long IRQ1_Handler /* SCU.SR1, CAN0.SR1, CCU80.SR0, SCU.SR1 | CAN0.SR1 */
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.long IRQ2_Handler /* SCU.SR2, CAN0.SR2, CCU80.SR1, SCU.SR2 | CAN0.SR2 */
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.long IRQ3_Handler /* ERU0.SR0, ERU1.SR0, CAN0.SR0, ERU0.SR0 | ERU1.SR0 */
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.long IRQ4_Handler /* ERU0.SR1, ERU1.SR1, CAN0.SR1, ERU0.SR1 | ERU1.SR1 */
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.long IRQ5_Handler /* ERU0.SR2, ERU1.SR2, CAN0.SR2, ERU0.SR2 | ERU1.SR2 */
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.long IRQ6_Handler /* ERU0.SR3, ERU1.SR3, CAN0.SR3, ERU0.SR3 | ERU1.SR3 */
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.long IRQ7_Handler /* MATH.SR0, CAN0.SR3, CCU40.SR1, MATH.SR0 | CAN0.SR3 */
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.long IRQ8_Handler /* LEDTS2.SR0, CCU40.SR0, CCU80.SR0, LEDTS2.SR0 | CCU40.SR0 */
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.long IRQ9_Handler /* USIC0.SR0, USIC1.SR0, ERU0.SR0, USIC0.SR0 | USIC1.SR0 */
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.long IRQ10_Handler /* USIC0.SR1, USIC1.SR1, ERU0.SR1, USIC0.SR1 | USIC1.SR1 */
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.long IRQ11_Handler /* USIC0.SR2, USIC1.SR2, ERU0.SR2, USIC0.SR2 | USIC1.SR2 */
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.long IRQ12_Handler /* USIC0.SR3, USIC1.SR3, ERU0.SR3, USIC0.SR3 | USIC1.SR3 */
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.long IRQ13_Handler /* USIC0.SR4, USIC1.SR4, CCU80.SR1, USIC0.SR4 | USIC1.SR4 */
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.long IRQ14_Handler /* USIC0.SR5, USIC1.SR5, POSIF0.SR0, USIC0.SR5 | USIC1.SR5 */
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.long IRQ15_Handler /* VADC0.C0SR0, USIC0.SR0, POSIF0.SR1, VADC0.C0SR0 | USIC0.SR0 */
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.long IRQ16_Handler /* VADC0.C0SR1, USIC0.SR1, CCU40.SR2, VADC0.C0SR1 | USIC0.SR1 */
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.long IRQ17_Handler /* VADC0.G0SR0, USIC0.SR2, CAN0.SR0, VADC0.G0SR0 | USIC0.SR2 */
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.long IRQ18_Handler /* VADC0.G0SR1, USIC0.SR3, CAN0.SR1, VADC0.G0SR1 | USIC0.SR3 */
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.long IRQ19_Handler /* VADC0.G1SR0, USIC0.SR4, CAN0.SR2, VADC0.G1SR0 | USIC0.SR4 */
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.long IRQ20_Handler /* VADC0.G1SR1, USIC0.SR5, CAN0.SR3, VADC0.G1SR1 | USIC0.SR5 */
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.long IRQ21_Handler /* CCU40.SR0, CCU41.SR0, USIC0.SR0, CCU40.SR0 | CCU41.SR0 */
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.long IRQ22_Handler /* CCU40.SR1, CCU41.SR1, USIC0.SR1, CCU40.SR1 | CCU41.SR1 */
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.long IRQ23_Handler /* CCU40.SR2, CCU41.SR2, USIC0.SR2, CCU40.SR2 | CCU41.SR2 */
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.long IRQ24_Handler /* CCU40.SR3, CCU41.SR3, USIC0.SR3, CCU40.SR3 | CCU41.SR3 */
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.long IRQ25_Handler /* CCU80.SR0, CCU81.SR0, USIC0.SR4, CCU80.SR0 | CCU81.SR0 */
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.long IRQ26_Handler /* CCU80.SR1, CCU81.SR1, USIC0.SR5, CCU80.SR1 | CCU81.SR1 */
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.long IRQ27_Handler /* POSIF0.SR0, POSIF1.SR0, CCU40.SR3, POSIF0.SR0 | POSIF1.SR0 */
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.long IRQ28_Handler /* POSIF0.SR1, POSIF1.SR1, ERU0.SR0, POSIF0.SR1 | POSIF1.SR1 */
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.long IRQ29_Handler /* LEDTS0.SR0, CCU40.SR1, ERU0.SR1, LEDTS0.SR0 | CCU40.SR1 */
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.long IRQ30_Handler /* LEDTS1.SR0, CCU40.SR2, ERU0.SR2, LEDTS1.SR0 | CCU40.SR2 */
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.long IRQ31_Handler /* BCCU0.SR0, CCU40.SR3, ERU0.SR3, BCCU0.SR0 | CCU40.SR3 */
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#endif
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.size __Vectors, . - __Vectors
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/* ================== END OF VECTOR TABLE DEFINITION ======================= */
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/* ================== START OF VECTOR ROUTINES ============================= */
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.thumb
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.align 1
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/* Reset Handler */
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.thumb_func
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Initialize the stack pointer */
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ldr r0, =__initial_sp
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mov sp, r0
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/* Initialize interrupt veneer */
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ldr r1, =eROData
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ldr r2, =VeneerStart
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ldr r3, =VeneerEnd
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bl __copy_data
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ldr r0, =SystemInit
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blx r0
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/* Initialize data */
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ldr r1, =DataLoadAddr
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ldr r2, =__data_start
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ldr r3, =__data_end
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bl __copy_data
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/* RAM code */
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ldr r1, =__ram_code_load
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ldr r2, =__ram_code_start
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ldr r3, =__ram_code_end
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bl __copy_data
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/* Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup.
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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#ifndef __SKIP_BSS_CLEAR
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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movs r0, 0
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subs r2, r1
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ble .L_loop3_done
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.L_loop3:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop3
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.L_loop3_done:
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#endif /* __SKIP_BSS_CLEAR */
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#ifndef __SKIP_LIBC_INIT_ARRAY
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ldr r0, =__libc_init_array
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blx r0
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#endif
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ldr r0, =main
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blx r0
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.thumb_func
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.type __copy_data, %function
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__copy_data:
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/* The ranges of copy from/to are specified by following symbols
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* r1: start of the section to copy from.
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* r2: start of the section to copy to
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* r3: end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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* Uses r0
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*/
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subs r3, r2
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ble .L_loop_done
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.L_loop:
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subs r3, #4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .L_loop
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.L_loop_done:
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bx lr
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.pool
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.size Reset_Handler,.-Reset_Handler
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/* ======================================================================== */
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/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
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.align 1
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.thumb_func
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.weak Default_handler
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.type Default_handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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Insert_InterruptHandler HardFault
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Insert_InterruptHandler SVC
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Insert_InterruptHandler PendSV
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Insert_InterruptHandler SysTick
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Insert_InterruptHandler IRQ0
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Insert_InterruptHandler IRQ1
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Insert_InterruptHandler IRQ2
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Insert_InterruptHandler IRQ3
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Insert_InterruptHandler IRQ4
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Insert_InterruptHandler IRQ5
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Insert_InterruptHandler IRQ6
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Insert_InterruptHandler IRQ7
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Insert_InterruptHandler IRQ8
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Insert_InterruptHandler IRQ9
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Insert_InterruptHandler IRQ10
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Insert_InterruptHandler IRQ11
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Insert_InterruptHandler IRQ12
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Insert_InterruptHandler IRQ13
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Insert_InterruptHandler IRQ14
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Insert_InterruptHandler IRQ15
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Insert_InterruptHandler IRQ16
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Insert_InterruptHandler IRQ17
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Insert_InterruptHandler IRQ18
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Insert_InterruptHandler IRQ19
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Insert_InterruptHandler IRQ20
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Insert_InterruptHandler IRQ21
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Insert_InterruptHandler IRQ22
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Insert_InterruptHandler IRQ23
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Insert_InterruptHandler IRQ24
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Insert_InterruptHandler IRQ25
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Insert_InterruptHandler IRQ26
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Insert_InterruptHandler IRQ27
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Insert_InterruptHandler IRQ28
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Insert_InterruptHandler IRQ29
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Insert_InterruptHandler IRQ30
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Insert_InterruptHandler IRQ31
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/* ======================================================================== */
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/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
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.section ".XmcVeneerCode","ax",%progbits
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.align 1
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Insert_InterruptVeener HardFault
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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Insert_InterruptVeener SVC
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.long 0
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.long 0
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Insert_InterruptVeener PendSV
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Insert_InterruptVeener SysTick
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Insert_InterruptVeener IRQ0
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Insert_InterruptVeener IRQ1
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Insert_InterruptVeener IRQ2
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Insert_InterruptVeener IRQ3
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Insert_InterruptVeener IRQ4
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Insert_InterruptVeener IRQ5
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Insert_InterruptVeener IRQ6
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Insert_InterruptVeener IRQ7
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Insert_InterruptVeener IRQ8
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Insert_InterruptVeener IRQ9
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Insert_InterruptVeener IRQ10
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Insert_InterruptVeener IRQ11
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Insert_InterruptVeener IRQ12
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Insert_InterruptVeener IRQ13
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Insert_InterruptVeener IRQ14
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Insert_InterruptVeener IRQ15
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Insert_InterruptVeener IRQ16
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Insert_InterruptVeener IRQ17
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Insert_InterruptVeener IRQ18
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Insert_InterruptVeener IRQ19
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Insert_InterruptVeener IRQ20
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Insert_InterruptVeener IRQ21
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Insert_InterruptVeener IRQ22
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Insert_InterruptVeener IRQ23
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Insert_InterruptVeener IRQ24
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Insert_InterruptVeener IRQ25
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Insert_InterruptVeener IRQ26
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Insert_InterruptVeener IRQ27
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Insert_InterruptVeener IRQ28
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Insert_InterruptVeener IRQ29
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Insert_InterruptVeener IRQ30
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Insert_InterruptVeener IRQ31
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/* ======================================================================== */
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/* ======================================================================== */
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/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
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.end
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