423 lines
18 KiB
C
423 lines
18 KiB
C
/**
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******************************************************************************
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* @file stm32f2xx_hal_rcc_ex.h
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* @author MCD Application Team
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* @brief Header file of RCC HAL Extension module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F2xx_HAL_RCC_EX_H
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#define __STM32F2xx_HAL_RCC_EX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f2xx_hal_def.h"
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/** @addtogroup STM32F2xx_HAL_Driver
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* @{
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*/
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/** @addtogroup RCCEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
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* @{
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*/
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/**
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* @brief PLLI2S Clock structure definition
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*/
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typedef struct
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{
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uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
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This parameter must be a number between Min_Data = 192 and Max_Data = 432.
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This parameter will be used only when PLLI2S is selected as Clock Source I2S */
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uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
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This parameter must be a number between Min_Data = 2 and Max_Data = 7.
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This parameter will be used only when PLLI2S is selected as Clock Source I2S */
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}RCC_PLLI2SInitTypeDef;
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/**
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* @brief RCC extended clocks structure definition
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*/
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typedef struct
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{
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
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This parameter will be used only when PLLI2S is selected as Clock Source I2S */
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uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
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This parameter can be a value of @ref RCC_RTC_Clock_Source */
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uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
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This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
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}RCC_PeriphCLKInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
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* @{
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*/
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/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
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* @{
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*/
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#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
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#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
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#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
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#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
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/**
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* @}
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*/
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/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
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* @{
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*/
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#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
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#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Macros RCC Exported Macros
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* @{
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*/
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/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
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* @brief Enables or disables the AHB1 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
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#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
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#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
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#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
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/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
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* @brief Get the enable or disable status of the AHB1 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
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#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
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#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
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#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET)
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#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
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__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
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__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
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#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
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#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
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#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
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#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
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#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
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__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
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__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
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/**
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* @}
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*/
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/**
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* @brief Enable ETHERNET clock.
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*/
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#define __HAL_RCC_ETH_CLK_ENABLE() do { \
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__HAL_RCC_ETHMAC_CLK_ENABLE(); \
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__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
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__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
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} while(0)
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/**
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* @brief Disable ETHERNET clock.
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*/
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#define __HAL_RCC_ETH_CLK_DISABLE() do { \
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__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
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__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
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__HAL_RCC_ETHMAC_CLK_DISABLE(); \
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} while(0)
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#endif /* STM32F207xx || STM32F217xx */
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/**
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* @}
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*/
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/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
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* @brief Enable or disable the AHB2 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
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#endif /* STM32F207xx || STM32F217xx */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_HASH_CLK_ENABLE() do { \
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__IO uint32_t tmpreg = 0x00; \
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SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
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UNUSED(tmpreg); \
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} while(0)
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#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
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#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
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#endif /* STM32F215xx || STM32F217xx */
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/**
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* @}
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*/
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/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
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* @brief Get the enable or disable status of the AHB2 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
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#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
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#endif /* defined(STM32F207xx) || defined(STM32F217xx) */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
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#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
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#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
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#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
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#endif /* defined(STM32F215xx) || defined(STM32F217xx) */
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/**
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* @}
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*/
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/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
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* @brief Force or release AHB1 peripheral reset.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
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#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
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#endif /* STM32F207xx || STM32F217xx */
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/**
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* @}
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*/
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/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
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* @brief Force or release AHB2 peripheral reset.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
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#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
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#endif /* STM32F207xx || STM32F217xx */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
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#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
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#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
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#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
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#endif /* STM32F215xx || STM32F217xx */
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/**
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* @}
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*/
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/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
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* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce
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* power consumption.
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
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* @note By default, all peripheral clocks are enabled during SLEEP mode.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
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#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
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#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
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#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
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#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
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#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
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#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
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#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
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#endif /* STM32F207xx || STM32F217xx */
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/**
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* @}
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*/
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/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
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* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce
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* power consumption.
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* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
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* @note By default, all peripheral clocks are enabled during SLEEP mode.
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* @{
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
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#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
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#endif /* STM32F207xx || STM32F217xx */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
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#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
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#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
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#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
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#endif /* STM32F215xx || STM32F217xx */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCCEx_Exported_Functions
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* @{
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*/
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/** @addtogroup RCCEx_Exported_Functions_Group1
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* @{
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
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HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
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HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Constants RCC Private Constants
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* @{
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*/
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/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
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* @brief RCC registers bit address in the alias region
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* @{
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*/
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#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Macros RCC Private Macros
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* @{
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*/
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/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
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* @{
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*/
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#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
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#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
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#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F2xx_HAL_RCC_EX_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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