161 lines
5.9 KiB
C
161 lines
5.9 KiB
C
/************************************************************************************//**
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* \file Source\TRICORE_TC1798\GCC\cpu_comp.c
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* \brief Bootloader compiler specific cpu module source file.
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* \ingroup Target_TRICORE_TC1798
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2015 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You have received a copy of the GNU General Public License along with OpenBLT. It
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* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */
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#include <machine/intrinsics.h>
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/****************************************************************************************
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* Macro definitions
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****************************************************************************************/
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#define CPU_INIT_MODE_TIMEOUT_MS (250u)
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/****************************************************************************************
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* Local function prototypes
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****************************************************************************************/
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static void CpuWriteWDTCON0(blt_int32u uwValue);
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/************************************************************************************//**
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** \brief Disable global interrupts.
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** \return none.
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**
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****************************************************************************************/
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void CpuIrqDisable(void)
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{
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_disable();
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} /*** end of CpuIrqDisable ***/
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/************************************************************************************//**
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** \brief Enable global interrupts.
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** \return none.
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**
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****************************************************************************************/
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void CpuIrqEnable(void)
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{
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_enable();
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} /*** end of CpuIrqEnable ***/
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/************************************************************************************//**
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** \brief This macro clears the EndInit bit, which controls access to system critical
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** registers. Clearing the EndInit bit unlocks all EndInit protectedd
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** registers. Modifications of the EndInit bit are monitored by the watchdog
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** timer such that after clearing the EndInit, the watchdog timer enters a
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** defined time-out mode; EndInit must be set again before the time-out
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** expires.
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** \return none.
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**
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****************************************************************************************/
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void CpuEnterInitMode(void)
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{
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blt_int32u timeout;
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/* request clearing of the EndInit bit */
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CpuWriteWDTCON0(WDT_CON0.reg & ~0x00000001);
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/* set timeout to wait for hardware handshake */
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timeout = TimerGet() + CPU_INIT_MODE_TIMEOUT_MS;
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/* wait for hardware handshake */
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while (WDT_CON0.bits.ENDINIT != 0)
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{
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/* keep the watchdog happy */
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CopService();
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/* break loop if timeout occurred */
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if (TimerGet() > timeout)
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{
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break;
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}
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}
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} /*** end of CpuEnterInitMode ***/
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/************************************************************************************//**
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** \brief This macro sets the EndInit bit, which controls access to system critical
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** registers. Setting the EndInit bit locks all EndInit protected registers.
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** \return none.
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**
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****************************************************************************************/
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void CpuLeaveInitMode(void)
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{
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/* set the EndInit bit */
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CpuWriteWDTCON0(WDT_CON0.reg | 0x00000001);
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} /*** end of CpuLeaveInitMode ***/
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/************************************************************************************//**
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** \brief Write a new value to the WDTCON0 register.
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** \param value New value for the WDTCON0 register.
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** \return none.
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**
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****************************************************************************************/
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static void CpuWriteWDTCON0(blt_int32u value)
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{
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blt_int32u dummy;
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/* load current value of the WDTCON0 register */
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dummy = WDT_CON0.reg;
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/* set HWPW1 = 1111b */
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dummy |= 0x000000F0;
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/* set HWPW0 = WDTDR */
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if (WDT_CON1.bits.DR)
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{
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dummy |= 0x00000008;
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}
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else
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{
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dummy &= ~0x00000008;
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}
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/* set HWPW0 = WDTIR */
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if (WDT_CON1.bits.IR)
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{
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dummy |= 0x00000004;
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}
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else
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{
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dummy &= ~0x00000004;
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}
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/* set WDTLCK = 0 */
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dummy &= ~0x00000002;
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/* unlock access */
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WDT_CON0.reg = dummy;
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/* set HWPW1 = 1111b and WDTLCK = 1 */
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value |= 0x000000F2;
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/* set HWPW0 = 00b */
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value &= ~0x0000000C;
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/* write access and lock */
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WDT_CON0.reg = value;
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} /*** end of CpuWriteWDTCON0 ***/
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/*********************************** end of cpu_comp.c *********************************/
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