159 lines
6.3 KiB
C
159 lines
6.3 KiB
C
/****************************************************************************************
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| Description: bootloader application source file
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| File Name: main.c
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|----------------------------------------------------------------------------------------
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| C O P Y R I G H T
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|----------------------------------------------------------------------------------------
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| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
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|----------------------------------------------------------------------------------------
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| L I C E N S E
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|----------------------------------------------------------------------------------------
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| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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| modify it under the terms of the GNU General Public License as published by the Free
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| Software Foundation, either version 3 of the License, or (at your option) any later
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| version.
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| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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| PURPOSE. See the GNU General Public License for more details.
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| You should have received a copy of the GNU General Public License along with OpenBLT.
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| If not, see <http://www.gnu.org/licenses/>.
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| A special exception to the GPL is included to allow you to distribute a combined work
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| that includes OpenBLT without being obliged to provide the source code for any
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| proprietary components. The exception text is included at the bottom of the license
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| file <license.html>.
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */
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#include "lpc2294.h" /* CPU register definitions */
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/****************************************************************************************
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* Function prototypes
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****************************************************************************************/
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static void Init(void);
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/****************************************************************************************
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** NAME: main
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** PARAMETER: none
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** RETURN VALUE: program return code
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** DESCRIPTION: This is the entry point for the bootloader application and is called
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** by the reset interrupt vector after the C-startup routines executed.
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**
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****************************************************************************************/
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int main(void)
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{
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/* initialize the microcontroller */
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Init();
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/* initialize the bootloader */
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BootInit();
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/* start the infinite program loop */
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while (1)
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{
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/* run the bootloader task */
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BootTask();
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}
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/* program should never get here */
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return 0;
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} /*** end of main ***/
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/****************************************************************************************
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** NAME: Init
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** PARAMETER: none
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** RETURN VALUE: none
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** DESCRIPTION: Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
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** configured equal to Fpll. The GPIO pin of the status LED is configured
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** as digital output.
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**
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****************************************************************************************/
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static void Init(void)
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{
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blt_int8u m_sel; /* pll multiplier register value */
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blt_int8u pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
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blt_int8u p_sel_cnt; /* loop counter to find p_sel */
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blt_int32u f_cco; /* current controller oscillator */
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/* check that pll multiplier value will be in the range 1..32 */
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ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
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BOOT_CPU_XTAL_SPEED_KHZ >= 1);
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ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
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BOOT_CPU_XTAL_SPEED_KHZ <= 32);
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/* calculate MSEL: M = round(Fcclk / Fosc) */
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m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
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BOOT_CPU_XTAL_SPEED_KHZ;
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/* value for the PLLCFG register is -1 */
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m_sel--;
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/* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
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for (p_sel_cnt=0; p_sel_cnt<sizeof(pll_dividers)/sizeof(pll_dividers[0]); p_sel_cnt++)
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{
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/* check f_cco with this pll divider */
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f_cco = BOOT_CPU_SYSTEM_SPEED_KHZ * 2 * pll_dividers[p_sel_cnt];
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if ( (f_cco >= 156000) && (f_cco <= 320000) )
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{
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/* found a valid pll divider value */
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break;
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}
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}
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/* check that a valid value was found */
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ASSERT_RT(p_sel_cnt < (sizeof(pll_dividers)/sizeof(pll_dividers[0])));
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/* set multiplier and divider values */
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PLLCFG = (p_sel_cnt << 5) | m_sel;
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PLLFEED = 0xAA;
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PLLFEED = 0x55;
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/* enable the PLL */
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PLLCON = 0x1;
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PLLFEED = 0xAA;
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PLLFEED = 0x55;
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/* wait for the PLL to lock to set frequency */
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while(!(PLLSTAT & 0x400)) { ; }
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/* connect the PLL as the clock source */
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PLLCON = 0x3;
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PLLFEED = 0xAA;
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PLLFEED = 0x55;
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/* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
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* Fcclk >= 60 MHz: 4 clock cycles
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* Fcclk >= 40 MHz: 3 clock cycles
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* Fcclk >= 20 MHz: 2 clock cycles
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* Fcclk < 20 MHz: 1 clock cycle
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*/
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MAMCR = 0x0;
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#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60)
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MAMTIM = 4;
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#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40)
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MAMTIM = 3;
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#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20)
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MAMTIM = 2;
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#else
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MAMTIM = 1;
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#endif
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MAMCR = 0x2;
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/* setting peripheral Clock (pclk) to System Clock (cclk) */
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VPBDIV = 0x1;
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#if (BOOT_COM_UART_ENABLE > 0)
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/* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
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PINSEL0 |= 0x05;
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#endif
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#if (BOOT_COM_CAN_ENABLE > 0)
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/* configure P0.25 for CAN1 Rx functionality */
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PINSEL1 |= 0x00040000L;
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#endif
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} /*** end of Init ***/
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/*********************************** end of main.c *************************************/
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