397 lines
16 KiB
C
397 lines
16 KiB
C
/**
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* @file xmc_pau.h
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* @date 2015-06-20
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.8 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2016, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-02-20:
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* - Initial version
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*
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* 2015-05-20:
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* - Documentation updated
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*
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* 2015-06-20:
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* - Removed version macros and declaration of GetDriverVersion API
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* @endcond
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*
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*/
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#ifndef XMC_PAU_H
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#define XMC_PAU_H
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/*********************************************************************************************************************
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* HEADER FILES
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*********************************************************************************************************************/
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#include "xmc_common.h"
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#if defined(PAU)
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/**
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* @addtogroup XMClib XMC Peripheral Library
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* @{
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*/
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/**
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* @addtogroup PAU
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* @brief Peripheral Access Unit (PAU) driver for the XMC1000 microcontroller family
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*
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* The Peripheral Access Unit (PAU) supports access control of memories and peripherals.
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* It allows user application to enable/disable the access to the registers of a peripheral.
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* It generates a HardFault exception when there is an access to a disabled or unassigned
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* address location. It also provides information on the availability of peripherals and
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* sizes of memories.
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*
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* The PAU low level driver provides functions to check the availability of peripherals
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* and to enable/disable peripheral access.
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* @{
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*/
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/*********************************************************************************************************************
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* MACROS
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*********************************************************************************************************************/
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/**
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* A convenient symbol for the PAU peripheral base address
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*/
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#define XMC_PAU ((XMC_PAU_t *) PAU_BASE)
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/*
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* This macro is used in the LLD for assertion checks (XMC_ASSERT)
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*/
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#define XMC_PAU_CHECK_MODULE_PTR(p) ((p) == XMC_PAU)
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/*********************************************************************************************************************
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* ENUMS
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*********************************************************************************************************************/
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/**
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* Status return values for PAU low level driver
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*/
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typedef enum XMC_PAU_STATUS
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{
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XMC_PAU_STATUS_OK = 0U, /**< Operation successful */
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XMC_PAU_STATUS_BUSY = 1U, /**< Busy with a previous request */
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XMC_PAU_STATUS_ERROR = 2U /**< Operation unsuccessful */
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} XMC_PAU_STATUS_t;
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/**
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* PAU peripheral select
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*/
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typedef enum XMC_PAU_PERIPHERAL
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{
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XMC_PAU_PERIPHERAL_FLASH = PAU_PRIVDIS0_PDIS2_Msk, /**< Flash SFRs Privilege Disable Flag */
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XMC_PAU_PERIPHERAL_RAM_BLOCK1 = PAU_PRIVDIS0_PDIS5_Msk, /**< RAM Block 1 Privilege Disable Flag */
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XMC_PAU_PERIPHERAL_RAM_BLOCK2 = PAU_PRIVDIS0_PDIS6_Msk, /**< RAM Block 2 Privilege Disable Flag */
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XMC_PAU_PERIPHERAL_RAM_BLOCK3 = PAU_PRIVDIS0_PDIS7_Msk, /**< RAM Block 3 Privilege Disable Flag */
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#if defined(WDT)
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XMC_PAU_PERIPHERAL_WDT = PAU_PRIVDIS0_PDIS19_Msk, /**< WDT Privilege Disable Flag */
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#endif
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#if defined(MATH)
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XMC_PAU_PERIPHERAL_MATH_GLOBAL_AND_DIV = PAU_PRIVDIS0_PDIS20_Msk, /**< MATH Global SFRs and Divider Privilege Disable Flag */
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#endif
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#if defined(MATH)
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XMC_PAU_PERIPHERAL_MATH_CORDIC = PAU_PRIVDIS0_PDIS21_Msk, /**< MATH CORDIC Privilege Disable Flag */
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#endif
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#if defined(PORT0)
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XMC_PAU_PERIPHERAL_PORT0 = PAU_PRIVDIS0_PDIS22_Msk, /**< Port 0 Privilege Disable Flag */
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#endif
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#if defined(PORT1)
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XMC_PAU_PERIPHERAL_PORT1 = PAU_PRIVDIS0_PDIS23_Msk, /**< Port 1 Privilege Disable Flag */
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#endif
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#if defined(PORT2)
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XMC_PAU_PERIPHERAL_PORT2 = PAU_PRIVDIS0_PDIS24_Msk, /**< Port 2 Privilege Disable Flag */
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#endif
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#if defined(PORT3)
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XMC_PAU_PERIPHERAL_PORT3 = PAU_PRIVDIS0_PDIS25_Msk, /**< Port 3 Privilege Disable Flag */
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#endif
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#if defined(PORT4)
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XMC_PAU_PERIPHERAL_PORT4 = PAU_PRIVDIS0_PDIS26_Msk, /**< Port 4 Privilege Disable Flag */
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#endif
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#if defined(USIC0)
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XMC_PAU_PERIPHERAL_USIC0_CH0 = PAU_PRIVDIS1_PDIS0_Msk | 0x10000000U, /**< USIC0 Channel 0 Privilege Disable Flag */
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XMC_PAU_PERIPHERAL_USIC0_CH1 = PAU_PRIVDIS1_PDIS1_Msk | 0x10000000U, /**< USIC0 Channel 1 Privilege Disable Flag */
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#endif
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#if defined(USIC1)
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XMC_PAU_PERIPHERAL_USIC1_CH0 = PAU_PRIVDIS1_PDIS16_Msk | 0x10000000U, /**< USIC1 Channel 0 Privilege Disable Flag */
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XMC_PAU_PERIPHERAL_USIC1_CH1 = PAU_PRIVDIS1_PDIS17_Msk | 0x10000000U, /**< USIC1 Channel 1 Privilege Disable Flag */
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#endif
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#if defined(PRNG)
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XMC_PAU_PERIPHERAL_PRNG = PAU_AVAIL1_AVAIL4_Msk | 0x10000000U, /**< PRNG Availability Flag*/
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#endif
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#if defined(VADC)
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XMC_PAU_PERIPHERAL_VADC_GLOBAL = PAU_PRIVDIS1_PDIS5_Msk | 0x10000000U, /**< VADC0 Basic SFRs Privilege Disable Flag */
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#if defined(VADC_G0)
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XMC_PAU_PERIPHERAL_VADC_GROUP0 = PAU_PRIVDIS1_PDIS6_Msk | 0x10000000U, /**< VADC0 Group 0 SFRs Privilege Disable Flag */
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#endif
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#if defined(VADC_G1)
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XMC_PAU_PERIPHERAL_VADC_GROUP1 = PAU_PRIVDIS1_PDIS7_Msk | 0x10000000U, /**< VADC0 Group 1 SFRs Privilege Disable Flag */
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#endif
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#endif
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#if defined(SHS0)
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XMC_PAU_PERIPHERAL_VADC_SHS0 = PAU_PRIVDIS1_PDIS8_Msk | 0x10000000U, /**< SHS0 Privilege Disable Flag */
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#endif
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#if defined(CCU40)
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XMC_PAU_PERIPHERAL_CCU40_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS9_Msk | 0x10000000U, /**< CCU40_CC40 and CCU40 Kernel SFRs Privilege Disable Flag */
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#if defined(CCU40_CC41)
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XMC_PAU_PERIPHERAL_CCU40_CC41 = PAU_PRIVDIS1_PDIS10_Msk | 0x10000000U, /**< CCU40_CC41 Privilege Disable Flag */
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#endif
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#if defined(CCU40_CC42)
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XMC_PAU_PERIPHERAL_CCU40_CC42 = PAU_PRIVDIS1_PDIS11_Msk | 0x10000000U, /**< CCU40_CC42 Privilege Disable Flag */
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#endif
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#if defined(CCU40_CC43)
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XMC_PAU_PERIPHERAL_CCU40_CC43 = PAU_PRIVDIS1_PDIS12_Msk | 0x10000000U, /**< CCU40_CC43 Privilege Disable Flag */
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#endif
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#endif
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#if defined(CCU41)
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XMC_PAU_PERIPHERAL_CCU41_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS25_Msk | 0x10000000U, /**< CCU41_CC40 and CCU41 Kernel SFRs Privilege Disable Flag */
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#if defined(CCU41_CC41)
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XMC_PAU_PERIPHERAL_CCU41_CC41 = PAU_PRIVDIS1_PDIS26_Msk | 0x10000000U, /**< CCU41_CC41 Privilege Disable Flag */
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#endif
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#if defined(CCU41_CC42)
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XMC_PAU_PERIPHERAL_CCU41_CC42 = PAU_PRIVDIS1_PDIS27_Msk | 0x10000000U, /**< CCU41_CC42 Privilege Disable Flag */
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#endif
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#if defined(CCU41_CC43)
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XMC_PAU_PERIPHERAL_CCU41_CC43 = PAU_PRIVDIS1_PDIS28_Msk | 0x10000000U, /**< CCU41_CC43 Privilege Disable Flag */
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#endif
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#endif
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#if defined(CCU80)
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XMC_PAU_PERIPHERAL_CCU80_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS0_Msk | 0x20000000U, /**< CCU80_CC80 and CCU80 Kernel SFRs Privilege Disable Flag */
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#if defined(CCU80_CC81)
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XMC_PAU_PERIPHERAL_CCU80_CC81 = PAU_PRIVDIS2_PDIS1_Msk | 0x20000000U, /**< CCU80_CC81 Privilege Disable Flag */
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#endif
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#if defined(CCU80_CC82)
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XMC_PAU_PERIPHERAL_CCU80_CC82 = PAU_PRIVDIS2_PDIS2_Msk | 0x20000000U, /**< CCU80_CC82 Privilege Disable Flag */
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#endif
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#if defined(CCU80_CC83)
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XMC_PAU_PERIPHERAL_CCU80_CC83 = PAU_PRIVDIS2_PDIS3_Msk | 0x20000000U, /**< CCU80_CC83 Privilege Disable Flag */
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#endif
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#endif
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#if defined(CCU81)
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XMC_PAU_PERIPHERAL_CCU81_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS16_Msk | 0x20000000U, /**< CCU81_CC80 and CCU81 Kernel SFRs Privilege Disable Flag */
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#if defined(CCU81_CC81)
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XMC_PAU_PERIPHERAL_CCU81_CC81 = PAU_PRIVDIS2_PDIS17_Msk | 0x20000000U, /**< CCU81_CC81 Privilege Disable Flag */
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#endif
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#if defined(CCU81_CC82)
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XMC_PAU_PERIPHERAL_CCU81_CC82 = PAU_PRIVDIS2_PDIS18_Msk | 0x20000000U, /**< CCU81_CC82 Privilege Disable Flag */
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#endif
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#if defined(CCU81_CC83)
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XMC_PAU_PERIPHERAL_CCU81_CC83 = PAU_PRIVDIS2_PDIS19_Msk | 0x20000000U, /**< CCU81_CC83 Privilege Disable Flag */
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#endif
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#endif
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#if defined(POSIF0)
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XMC_PAU_PERIPHERAL_POSIF0 = PAU_PRIVDIS2_PDIS12_Msk | 0x20000000U, /**< POSIF0 Privilege Disable Flag */
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#endif
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#if defined(POSIF1)
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XMC_PAU_PERIPHERAL_POSIF1 = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< POSIF1 Privilege Disable Flag */
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#endif
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#if defined(LEDTS0)
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XMC_PAU_PERIPHERAL_LEDTS0 = PAU_PRIVDIS2_PDIS13_Msk | 0x20000000U, /**< LEDTS0 Privilege Disable Flag */
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#endif
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#if defined(LEDTS1)
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XMC_PAU_PERIPHERAL_LEDTS1 = PAU_PRIVDIS2_PDIS14_Msk | 0x20000000U, /**< LEDTS1 Privilege Disable Flag */
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#endif
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#if defined(LEDTS2)
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XMC_PAU_PERIPHERAL_LEDTS2 = PAU_PRIVDIS2_PDIS29_Msk | 0x20000000U, /**< LEDTS2 Privilege Disable Flag */
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#endif
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#if defined(BCCU0)
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XMC_PAU_PERIPHERAL_BCCU0 = PAU_PRIVDIS2_PDIS15_Msk | 0x20000000U, /**< BCCU0 Privilege Disable Flag */
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#endif
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#if defined(CAN)
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#if defined(CAN_NODE0)
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XMC_PAU_PERIPHERAL_MCAN_NODE0_AND_GLOBAL = PAU_PRIVDIS2_PDIS21_Msk | 0x20000000U, /**< MCAN NODE0 and Global SFRs Privilege */
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#endif
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#if defined(CAN_NODE1)
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XMC_PAU_PERIPHERAL_MCAN_NODE1_AND_GLOBAL = PAU_PRIVDIS2_PDIS23_Msk | 0x20000000U, /**< MCAN NODE1 Privilege Disable Flag */
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#endif
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XMC_PAU_PERIPHERAL_MCAN_OBJECTS = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< MCAN Message Objects Privilege Disable Flag */
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#endif
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} XMC_PAU_PERIPHERAL_t;
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/*********************************************************************************************************************
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* DATA STRUCTURES
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*********************************************************************************************************************/
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/**
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* External Peripheral Access Unit (PAU) device structure <br>
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*
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* The structure represents a collection of all hardware registers
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* used to configure the PAU peripheral on the XMC microcontroller.
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* The registers can be accessed with ::XMC_PAU.
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*/
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typedef struct
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{
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__I uint32_t RESERVED0[16];
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__I uint32_t AVAIL[3];
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__I uint32_t RESERVED1[13];
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__IO uint32_t PRIVDIS[3];
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__I uint32_t RESERVED2[221];
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__I uint32_t ROMSIZE;
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__I uint32_t FLSIZE;
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__I uint32_t RESERVED3[2];
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__I uint32_t RAM0SIZE;
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} XMC_PAU_t;
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/*********************************************************************************************************************
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* API PROTOTYPES
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*********************************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be enabled
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enable the peripheral access <br>
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*
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* \par
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* The function resets the PRIVDISx.PDISy bit to enable the access to the registers of a peripheral
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* during run time.
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*
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* \par<b>Related APIs:</b><br>
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* XMC_PAU_DisablePeripheralAccess()
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*/
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void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
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/**
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* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disable the peripheral access <br>
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*
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* \par
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* The function sets the PRIVDISx.PDISy bit to disable the access to the registers of a peripheral
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* during run time. An access to a disabled or unassigned address location generates a hardfault
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* exception.
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*
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* \par<b>Related APIs:</b><br>
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* XMC_PAU_EnablePeripheralAccess()
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*/
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void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
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/**
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* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access enabled status to be checked
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* @return bool "false" if peripheral access is enabled, "true" otherwise
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*
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* \par<b>Description: </b><br>
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* Checks if the peripheral access is enabled or not <br>
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*
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* \par
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* The function checks the PRIVDISx.PDISy bit to know whether the access to the registers of a peripheral
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* during run time is enabled or not.
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*
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* \par<b>Related APIs:</b><br>
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* XMC_PAU_DisablePeripheralAccess(), XMC_PAU_EnablePeripheralAccess()
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*/
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bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral);
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/**
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* @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
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* @return bool Returns "true" if peripheral is available, "false" otherwise
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*
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* \par<b>Description: </b><br>
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* Checks if a peripheral is available or not <br>
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*
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* \par
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* The function checks the AVAILx.AVAILy bit to know whether the peripheral
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* is available or not for the particular device variant.
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*/
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bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral);
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/**
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* @return uint32_t Returns ROM size
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*
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* \par<b>Description: </b><br>
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* Gets the ROM size <br>
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*
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* \par
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* The function checks the ROMSIZE.ADDR bitfield to indicate the available size of ROM in the device in bytes.
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*/
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__STATIC_INLINE uint32_t XMC_PAU_GetROMSize(void)
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{
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return (uint32_t)(((XMC_PAU->ROMSIZE & PAU_ROMSIZE_ADDR_Msk) >> PAU_ROMSIZE_ADDR_Pos) * 256U);
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}
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/**
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* @return uint32_t Returns flash size
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*
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* \par<b>Description: </b><br>
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* Gets the flash size <br>
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*
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* \par
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* The function checks the FLSIZE.ADDR bitfield to indicate the available size of FLASH in the device in Kbytes.
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*/
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__STATIC_INLINE uint32_t XMC_PAU_GetFlashSize(void)
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{
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return (uint32_t)((((XMC_PAU->FLSIZE & PAU_FLSIZE_ADDR_Msk) >> PAU_FLSIZE_ADDR_Pos) - 1U) * 4U);
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}
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/**
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* @return uint32_t Returns RAM size
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*
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* \par<b>Description: </b><br>
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* Gets RAM size <br>
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*
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* \par
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* The function checks the RAM0SIZE.ADDR bitfield to indicate the available size of RAM in the device in bytes.
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*/
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__STATIC_INLINE uint32_t XMC_PAU_GetRAMSize(void)
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{
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return (uint32_t)(((XMC_PAU->RAM0SIZE & PAU_RAM0SIZE_ADDR_Msk) >> PAU_RAM0SIZE_ADDR_Pos) * 256U);
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}
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* defined(PAU) */
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#endif /* XMC_PAU_H */
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