421 lines
19 KiB
C
421 lines
19 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_syscfg.c
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* @author MCD Application Team
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* @version V1.5.0
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* @date 05-December-2014
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* @brief This file provides firmware functions to manage the following
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* functionalities of the SYSCFG peripheral:
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* + Remapping the memory mapped at 0x00000000
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* + Remapping the DMA channels
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* + Enabling I2C fast mode plus driving capability for I2C pins
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* + Configuring the EXTI lines connection to the GPIO port
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* + Configuring the CFGR2 features (Connecting some internal signal
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* to the break input of TIM1)
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*
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* @verbatim
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===============================================================================
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##### How to use this driver #####
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===============================================================================
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[..]
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The SYSCFG registers can be accessed only when the SYSCFG
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interface APB clock is enabled.
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To enable SYSCFG APB clock use:
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RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
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* @endverbatim
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_syscfg.h"
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/** @addtogroup STM32F0xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup SYSCFG
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* @brief SYSCFG driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup SYSCFG_Private_Functions
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* @{
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*/
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/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
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* @brief SYSCFG Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### SYSCFG Initialization and Configuration functions #####
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===============================================================================
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the SYSCFG registers to their default reset values.
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* @param None
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* @retval None
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* @note MEM_MODE bits are not affected by APB reset.
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* @note MEM_MODE bits took the value from the user option bytes.
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* @note CFGR2 register is not affected by APB reset.
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* @note CLABBB configuration bits are locked when set.
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* @note To unlock the configuration, perform a system reset.
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*/
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void SYSCFG_DeInit(void)
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{
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/* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
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SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
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/* Set EXTICRx registers to reset value */
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SYSCFG->EXTICR[0] = 0;
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SYSCFG->EXTICR[1] = 0;
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SYSCFG->EXTICR[2] = 0;
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SYSCFG->EXTICR[3] = 0;
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/* Set CFGR2 register to reset value: clear SRAM parity error flag */
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SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
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}
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/**
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* @brief Configures the memory mapping at address 0x00000000.
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* @param SYSCFG_MemoryRemap: selects the memory remapping.
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* This parameter can be one of the following values:
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* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
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* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
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* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
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* @retval None
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*/
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void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
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{
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uint32_t tmpctrl = 0;
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/* Check the parameter */
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assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
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/* Get CFGR1 register value */
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tmpctrl = SYSCFG->CFGR1;
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/* Clear MEM_MODE bits */
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tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
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/* Set the new MEM_MODE bits value */
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tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
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/* Set CFGR1 register with the new memory remap configuration */
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SYSCFG->CFGR1 = tmpctrl;
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}
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/**
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* @brief Configure the DMA channels remapping.
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* @param SYSCFG_DMARemap: selects the DMA channels remap.
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* This parameter can be one of the following values:
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* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
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* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
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* @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
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* @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
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* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
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* @param NewState: new state of the DMA channel remapping.
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* This parameter can be: ENABLE or DISABLE.
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* @note When enabled, DMA channel of the selected peripheral is remapped
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* @note When disabled, Default DMA channel is mapped to the selected peripheral
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* @note By default TIM17 DMA requests is mapped to channel 1,
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* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
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* TIM17 DMA requests to channel 2 and use
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* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
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* TIM17 DMA requests to channel 1 (default mapping)
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* @note This function is only used for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F051 devices.
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* @retval None
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*/
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void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Remap the DMA channel */
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SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
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}
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else
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{
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/* use the default DMA channel mapping */
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SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
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}
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}
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/**
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* @brief Configure the I2C fast mode plus driving capability.
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* @param SYSCFG_I2CFastModePlus: selects the pin.
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* This parameter can be one of the following values:
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* @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
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* @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
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* @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
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* @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
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* @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F031 and STM32F030 devices)
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* @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F031 and STM32F030 devices)
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* @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F031 and STM32F030 devices)
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* @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins, available only for STM32F072 devices
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*
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* @param NewState: new state of the DMA channel remapping.
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* This parameter can be: ENABLE or DISABLE.
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* @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
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* @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
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* @note For I2C1, fast mode plus driving capability can be enabled on all selected
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* I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
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* on each one of the following pins PB6, PB7, PB8 and PB9.
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* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
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* can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
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* @note For all I2C2 pins fast mode plus driving capability can be enabled
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* only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
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* @retval None
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*/
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void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable fast mode plus driving capability for selected pin */
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SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
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}
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else
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{
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/* Disable fast mode plus driving capability for selected pin */
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SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
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}
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}
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/** @brief select the modulation envelope source
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* @param SYSCFG_IRDAEnv: select the envelope source.
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* This parameter can be a value
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* @arg SYSCFG_IRDA_ENV_SEL_TIM16
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* @arg SYSCFG_IRDA_ENV_SEL_USART1
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* @arg SYSCFG_IRDA_ENV_SEL_USART4
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* @retval None
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*/
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void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv)
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{
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/* Check the parameters */
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assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv));
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SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL);
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SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv);
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}
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/**
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* @brief Selects the GPIO pin used as EXTI Line.
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* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
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* for EXTI lines where x can be (A, B, C, D, E or F).
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* @note GPIOE is available only for STM32F072.
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* @note GPIOD is not available for STM32F031.
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* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
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* @note This parameter can be EXTI_PinSourcex where x can be:
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* For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
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* For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
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* For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
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* @retval None
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*/
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void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
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{
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uint32_t tmp = 0x00;
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/* Check the parameters */
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assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
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assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
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tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
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SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
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SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
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}
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/**
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* @brief check ISR wrapper: Allow to determine interrupt source per line .
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* @param IT_Source: specifies the interrupt source to check.
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* This parameter can be one of the following values:
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* @arg ITLINE_EWDG EWDG has expired
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* @arg ITLINE_PVDOUT Power voltage detection Interrupt
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* @arg ITLINE_VDDIO2 VDDIO2 Interrupt
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* @arg ITLINE_RTC_WAKEUP RTC WAKEUP -> exti[20] Interrupt
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* @arg ITLINE_RTC_TSTAMP RTC Time Stamp -> exti[19] interrupt
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* @arg ITLINE_RTC_ALRA RTC Alarm -> exti[17] interrupt
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* @arg ITLINE_FLASH_ITF Flash ITF Interrupt
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* @arg ITLINE_CRS CRS Interrupt
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* @arg ITLINE_CLK_CTRL CLK Control Interrupt
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* @arg ITLINE_EXTI0 External Interrupt 0
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* @arg ITLINE_EXTI1 External Interrupt 1
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* @arg ITLINE_EXTI2 External Interrupt 2
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* @arg ITLINE_EXTI3 External Interrupt 3
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* @arg ITLINE_EXTI4 External Interrupt 4
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* @arg ITLINE_EXTI5 External Interrupt 5
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* @arg ITLINE_EXTI6 External Interrupt 6
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* @arg ITLINE_EXTI7 External Interrupt 7
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* @arg ITLINE_EXTI8 External Interrupt 8
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* @arg ITLINE_EXTI9 External Interrupt 9
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* @arg ITLINE_EXTI10 External Interrupt 10
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* @arg ITLINE_EXTI11 External Interrupt 11
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* @arg ITLINE_EXTI12 External Interrupt 12
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* @arg ITLINE_EXTI13 External Interrupt 13
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* @arg ITLINE_EXTI14 External Interrupt 14
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* @arg ITLINE_EXTI15 External Interrupt 15
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* @arg ITLINE_TSC_EOA Touch control EOA Interrupt
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* @arg ITLINE_TSC_MCE Touch control MCE Interrupt
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* @arg ITLINE_DMA1_CH1 DMA1 Channel 1 Interrupt
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* @arg ITLINE_DMA1_CH2 DMA1 Channel 2 Interrupt
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* @arg ITLINE_DMA1_CH3 DMA1 Channel 3 Interrupt
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* @arg ITLINE_DMA2_CH1 DMA2 Channel 1 Interrupt
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* @arg ITLINE_DMA2_CH2 DMA2 Channel 2 Interrupt
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* @arg ITLINE_DMA1_CH4 DMA1 Channel 4 Interrupt
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* @arg ITLINE_DMA1_CH5 DMA1 Channel 5 Interrupt
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* @arg ITLINE_DMA1_CH6 DMA1 Channel 6 Interrupt
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* @arg ITLINE_DMA1_CH7 DMA1 Channel 7 Interrupt
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* @arg ITLINE_DMA2_CH3 DMA2 Channel 3 Interrupt
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* @arg ITLINE_DMA2_CH4 DMA2 Channel 4 Interrupt
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* @arg ITLINE_DMA2_CH5 DMA2 Channel 5 Interrupt
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* @arg ITLINE_ADC ADC Interrupt
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* @arg ITLINE_COMP1 COMP1 Interrupt -> exti[21]
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* @arg ITLINE_COMP2 COMP2 Interrupt -> exti[21]
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* @arg ITLINE_TIM1_BRK TIM1 BRK Interrupt
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* @arg ITLINE_TIM1_UPD TIM1 UPD Interrupt
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* @arg ITLINE_TIM1_TRG TIM1 TRG Interrupt
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* @arg ITLINE_TIM1_CCU TIM1 CCU Interrupt
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* @arg ITLINE_TIM1_CC TIM1 CC Interrupt
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* @arg ITLINE_TIM2 TIM2 Interrupt
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* @arg ITLINE_TIM3 TIM3 Interrupt
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* @arg ITLINE_DAC DAC Interrupt
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* @arg ITLINE_TIM6 TIM6 Interrupt
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* @arg ITLINE_TIM7 TIM7 Interrupt
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* @arg ITLINE_TIM14 TIM14 Interrupt
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* @arg ITLINE_TIM15 TIM15 Interrupt
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* @arg ITLINE_TIM16 TIM16 Interrupt
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* @arg ITLINE_TIM17 TIM17 Interrupt
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* @arg ITLINE_I2C1 I2C1 Interrupt -> exti[23]
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* @arg ITLINE_I2C2 I2C2 Interrupt
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* @arg ITLINE_SPI1 I2C1 Interrupt -> exti[23]
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* @arg ITLINE_SPI2 SPI1 Interrupt
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* @arg ITLINE_USART1 USART1 GLB Interrupt -> exti[25]
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* @arg ITLINE_USART2 USART2 GLB Interrupt -> exti[26]
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* @arg ITLINE_USART3 USART3 Interrupt
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* @arg ITLINE_USART4 USART4 Interrupt
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* @arg ITLINE_USART5 USART5 Interrupt
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* @arg ITLINE_USART6 USART6 Interrupt
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* @arg ITLINE_USART7 USART7 Interrupt
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* @arg ITLINE_USART8 USART8 Interrupt
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* @arg ITLINE_CAN CAN Interrupt
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* @arg ITLINE_CEC CEC Interrupt
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* @retval The new state of IT_LINE_SR.
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*/
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uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine)
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{
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assert_param(IS_SYSCFG_ITLINE(ITSourceLine));
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return(SYSCFG->IT_LINE_SR[(ITSourceLine >> 0x18)] & (ITSourceLine & 0x00FFFFFF));
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}
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/**
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* @brief Connect the selected parameter to the break input of TIM1.
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* @note The selected configuration is locked and can be unlocked by system reset
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* @param SYSCFG_Break: selects the configuration to be connected to break
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* input of TIM1
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* This parameter can be any combination of the following values:
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* @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not available for STM32F030 devices.
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* @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
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* @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
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* @retval None
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*/
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void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
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{
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/* Check the parameter */
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assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
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SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
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}
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/**
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* @brief Checks whether the specified SYSCFG flag is set or not.
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* @param SYSCFG_Flag: specifies the SYSCFG flag to check.
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* This parameter can be one of the following values:
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* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
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* @retval The new state of SYSCFG_Flag (SET or RESET).
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*/
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FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
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{
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FlagStatus bitstatus = RESET;
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/* Check the parameter */
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assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
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/* Check the status of the specified SPI flag */
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if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
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{
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/* SYSCFG_Flag is set */
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bitstatus = SET;
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}
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else
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{
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/* SYSCFG_Flag is reset */
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bitstatus = RESET;
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}
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/* Return the SYSCFG_Flag status */
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return bitstatus;
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}
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/**
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* @brief Clear the selected SYSCFG flag.
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* @param SYSCFG_Flag: selects the flag to be cleared.
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* This parameter can be any combination of the following values:
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* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
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* @retval None
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*/
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void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
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{
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/* Check the parameter */
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assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
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SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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