432 lines
22 KiB
Plaintext
432 lines
22 KiB
Plaintext
1 .syntax unified
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2 .cpu cortex-m3
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3 .fpu softvfp
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4 .eabi_attribute 20, 1
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5 .eabi_attribute 21, 1
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6 .eabi_attribute 23, 3
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7 .eabi_attribute 24, 1
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8 .eabi_attribute 25, 1
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9 .eabi_attribute 26, 1
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10 .eabi_attribute 30, 1
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11 .eabi_attribute 34, 1
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12 .eabi_attribute 18, 4
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13 .thumb
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14 .file "main.c"
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15 .text
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16 .Ltext0:
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17 .cfi_sections .debug_frame
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18 .section .text.main,"ax",%progbits
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19 .align 2
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20 .global main
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21 .thumb
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22 .thumb_func
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24 main:
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25 .LFB29:
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26 .file 1 "main.c"
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1:main.c **** /************************************************************************************//**
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2:main.c **** * \file Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\main.c
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3:main.c **** * \brief Bootloader application source file.
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4:main.c **** * \ingroup Boot_ARMCM3_STM32_Olimex_STM32P103_GCC
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5:main.c **** * \internal
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6:main.c **** *----------------------------------------------------------------------------------------
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7:main.c **** * C O P Y R I G H T
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8:main.c **** *----------------------------------------------------------------------------------------
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9:main.c **** * Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
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10:main.c **** *
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11:main.c **** *----------------------------------------------------------------------------------------
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12:main.c **** * L I C E N S E
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13:main.c **** *----------------------------------------------------------------------------------------
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14:main.c **** * This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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15:main.c **** * modify it under the terms of the GNU General Public License as published by the Free
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16:main.c **** * Software Foundation, either version 3 of the License, or (at your option) any later
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17:main.c **** * version.
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18:main.c **** *
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19:main.c **** * OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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20:main.c **** * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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21:main.c **** * PURPOSE. See the GNU General Public License for more details.
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22:main.c **** *
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23:main.c **** * You should have received a copy of the GNU General Public License along with OpenBLT.
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24:main.c **** * If not, see <http://www.gnu.org/licenses/>.
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25:main.c **** *
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26:main.c **** * A special exception to the GPL is included to allow you to distribute a combined work
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27:main.c **** * that includes OpenBLT without being obliged to provide the source code for any
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28:main.c **** * proprietary components. The exception text is included at the bottom of the license
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29:main.c **** * file <license.html>.
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30:main.c **** *
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31:main.c **** * \endinternal
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32:main.c **** ****************************************************************************************/
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33:main.c ****
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34:main.c **** /****************************************************************************************
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35:main.c **** * Include files
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36:main.c **** ****************************************************************************************/
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37:main.c **** #include "boot.h" /* bootloader generic header */
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38:main.c **** #include "stm32f10x.h" /* microcontroller registers */
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39:main.c **** #if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0)
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40:main.c **** #include "stm32f10x_conf.h" /* STM32 peripheral drivers */
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41:main.c **** #endif
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42:main.c ****
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43:main.c ****
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44:main.c **** /****************************************************************************************
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45:main.c **** * Function prototypes
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46:main.c **** ****************************************************************************************/
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47:main.c **** static void Init(void);
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48:main.c ****
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49:main.c ****
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50:main.c **** /************************************************************************************//**
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51:main.c **** ** \brief This is the entry point for the bootloader application and is called
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52:main.c **** ** by the reset interrupt vector after the C-startup routines executed.
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53:main.c **** ** \return Program return code.
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54:main.c **** **
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55:main.c **** ****************************************************************************************/
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56:main.c **** int main(void)
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57:main.c **** {
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27 .loc 1 57 0
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28 .cfi_startproc
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29 @ Volatile: function does not return.
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30 @ args = 0, pretend = 0, frame = 8
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31 @ frame_needed = 0, uses_anonymous_args = 0
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32 0000 00B5 push {lr}
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33 .cfi_def_cfa_offset 4
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34 .cfi_offset 14, -4
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35 0002 83B0 sub sp, sp, #12
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36 .cfi_def_cfa_offset 16
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37 .LBB4:
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38 .LBB5:
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58:main.c **** /* initialize the microcontroller */
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59:main.c **** Init();
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60:main.c **** /* initialize the bootloader */
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61:main.c **** BootInit();
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62:main.c ****
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63:main.c **** /* start the infinite program loop */
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64:main.c **** while (1)
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65:main.c **** {
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66:main.c **** /* run the bootloader task */
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67:main.c **** BootTask();
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68:main.c **** }
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69:main.c ****
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70:main.c **** /* program should never get here */
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71:main.c **** return 0;
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72:main.c **** } /*** end of main ***/
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73:main.c ****
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74:main.c ****
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75:main.c **** /************************************************************************************//**
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76:main.c **** ** \brief Initializes the microcontroller.
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77:main.c **** ** \return none.
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78:main.c **** **
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79:main.c **** ****************************************************************************************/
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80:main.c **** static void Init(void)
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81:main.c **** {
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82:main.c **** volatile blt_int32u StartUpCounter = 0, HSEStatus = 0;
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39 .loc 1 82 0
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40 0004 0023 movs r3, #0
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41 0006 0093 str r3, [sp]
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42 0008 0193 str r3, [sp, #4]
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83:main.c **** blt_int32u pll_multiplier;
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84:main.c **** #if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0)
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85:main.c **** GPIO_InitTypeDef GPIO_InitStruct;
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86:main.c **** USART_InitTypeDef USART_InitStruct;
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87:main.c **** #endif
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88:main.c ****
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89:main.c **** /* reset the RCC clock configuration to the default reset state (for debug purpose) */
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90:main.c **** /* set HSION bit */
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91:main.c **** RCC->CR |= (blt_int32u)0x00000001;
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43 .loc 1 91 0
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44 000a 03F18043 add r3, r3, #1073741824
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45 000e 03F50433 add r3, r3, #135168
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46 0012 1A68 ldr r2, [r3]
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47 0014 42F00102 orr r2, r2, #1
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48 0018 1A60 str r2, [r3]
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92:main.c **** /* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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93:main.c **** RCC->CFGR &= (blt_int32u)0xF8FF0000;
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49 .loc 1 93 0
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50 001a 5968 ldr r1, [r3, #4]
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51 001c 434A ldr r2, .L12
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52 001e 0A40 ands r2, r2, r1
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53 0020 5A60 str r2, [r3, #4]
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94:main.c **** /* reset HSEON, CSSON and PLLON bits */
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95:main.c **** RCC->CR &= (blt_int32u)0xFEF6FFFF;
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54 .loc 1 95 0
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55 0022 1A68 ldr r2, [r3]
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56 0024 22F08472 bic r2, r2, #17301504
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57 0028 22F48032 bic r2, r2, #65536
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58 002c 1A60 str r2, [r3]
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96:main.c **** /* reset HSEBYP bit */
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97:main.c **** RCC->CR &= (blt_int32u)0xFFFBFFFF;
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59 .loc 1 97 0
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60 002e 1A68 ldr r2, [r3]
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61 0030 22F48022 bic r2, r2, #262144
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62 0034 1A60 str r2, [r3]
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98:main.c **** /* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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99:main.c **** RCC->CFGR &= (blt_int32u)0xFF80FFFF;
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63 .loc 1 99 0
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64 0036 5A68 ldr r2, [r3, #4]
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65 0038 22F4FE02 bic r2, r2, #8323072
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66 003c 5A60 str r2, [r3, #4]
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100:main.c **** /* disable all interrupts and clear pending bits */
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101:main.c **** RCC->CIR = 0x009F0000;
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67 .loc 1 101 0
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68 003e 4FF41F02 mov r2, #10420224
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69 0042 9A60 str r2, [r3, #8]
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102:main.c **** /* enable HSE */
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103:main.c **** RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
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70 .loc 1 103 0
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71 0044 1A68 ldr r2, [r3]
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72 0046 42F48032 orr r2, r2, #65536
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73 004a 1A60 str r2, [r3]
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104:main.c **** /* wait till HSE is ready and if Time out is reached exit */
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105:main.c **** do
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106:main.c **** {
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107:main.c **** HSEStatus = RCC->CR & RCC_CR_HSERDY;
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74 .loc 1 107 0
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75 004c 1946 mov r1, r3
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108:main.c **** StartUpCounter++;
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109:main.c **** }
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110:main.c **** while((HSEStatus == 0) && (StartUpCounter != 1500));
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76 .loc 1 110 0
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77 004e 40F2DC52 movw r2, #1500
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78 .L3:
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107:main.c **** StartUpCounter++;
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79 .loc 1 107 0
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80 0052 0B68 ldr r3, [r1]
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81 0054 03F40033 and r3, r3, #131072
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82 0058 0193 str r3, [sp, #4]
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108:main.c **** StartUpCounter++;
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83 .loc 1 108 0
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84 005a 009B ldr r3, [sp]
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85 005c 0133 adds r3, r3, #1
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86 005e 0093 str r3, [sp]
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87 .loc 1 110 0
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88 0060 019B ldr r3, [sp, #4]
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89 0062 13B9 cbnz r3, .L2
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90 0064 009B ldr r3, [sp]
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91 0066 9342 cmp r3, r2
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92 0068 F3D1 bne .L3
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93 .L2:
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111:main.c **** /* check if time out was reached */
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112:main.c **** if ((RCC->CR & RCC_CR_HSERDY) == RESET)
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94 .loc 1 112 0
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95 006a 314B ldr r3, .L12+4
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96 006c 1B68 ldr r3, [r3]
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97 006e 13F4003F tst r3, #131072
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98 0072 03D1 bne .L4
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113:main.c **** {
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114:main.c **** /* cannot continue when HSE is not ready */
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115:main.c **** ASSERT_RT(BLT_FALSE);
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99 .loc 1 115 0
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100 0074 2F48 ldr r0, .L12+8
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101 0076 7321 movs r1, #115
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102 0078 FFF7FEFF bl AssertFailure
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103 .LVL0:
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104 .L4:
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116:main.c **** }
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117:main.c **** /* enable flash prefetch buffer */
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118:main.c **** FLASH->ACR |= FLASH_ACR_PRFTBE;
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105 .loc 1 118 0
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106 007c 2E4B ldr r3, .L12+12
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107 007e 1A68 ldr r2, [r3]
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108 0080 42F01002 orr r2, r2, #16
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109 0084 1A60 str r2, [r3]
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119:main.c **** /* reset flash wait state configuration to default 0 wait states */
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120:main.c **** FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
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110 .loc 1 120 0
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111 0086 1A68 ldr r2, [r3]
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112 0088 22F00302 bic r2, r2, #3
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113 008c 1A60 str r2, [r3]
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121:main.c **** #if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
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122:main.c **** /* configure 2 flash wait states */
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123:main.c **** FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
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114 .loc 1 123 0
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115 008e 1A68 ldr r2, [r3]
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116 0090 42F00202 orr r2, r2, #2
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117 0094 1A60 str r2, [r3]
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124:main.c **** #elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
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125:main.c **** /* configure 1 flash wait states */
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126:main.c **** FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
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127:main.c **** #endif
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128:main.c **** /* HCLK = SYSCLK */
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129:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
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118 .loc 1 129 0
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119 0096 A3F58053 sub r3, r3, #4096
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120 009a 5A68 ldr r2, [r3, #4]
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121 009c 5A60 str r2, [r3, #4]
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130:main.c **** /* PCLK2 = HCLK/2 */
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131:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2;
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122 .loc 1 131 0
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123 009e 5A68 ldr r2, [r3, #4]
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124 00a0 42F40052 orr r2, r2, #8192
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125 00a4 5A60 str r2, [r3, #4]
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132:main.c **** /* PCLK1 = HCLK/2 */
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133:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2;
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126 .loc 1 133 0
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127 00a6 5A68 ldr r2, [r3, #4]
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128 00a8 42F48062 orr r2, r2, #1024
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129 00ac 5A60 str r2, [r3, #4]
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134:main.c **** /* reset PLL configuration */
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135:main.c **** RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
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130 .loc 1 135 0
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131 00ae 5A68 ldr r2, [r3, #4]
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132 00b0 22F47C12 bic r2, r2, #4128768
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133 00b4 5A60 str r2, [r3, #4]
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134 .LVL1:
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136:main.c **** RCC_CFGR_PLLMULL));
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137:main.c **** /* assert that the pll_multiplier is between 2 and 16 */
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138:main.c **** ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2);
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139:main.c **** ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16);
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140:main.c **** /* calculate multiplier value */
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141:main.c **** pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
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142:main.c **** /* convert to register value */
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143:main.c **** pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18);
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144:main.c **** /* set the PLL multiplier and clock source */
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145:main.c **** RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
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135 .loc 1 145 0
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136 00b6 5A68 ldr r2, [r3, #4]
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137 00b8 42F4E812 orr r2, r2, #1900544
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138 00bc 5A60 str r2, [r3, #4]
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146:main.c **** /* enable PLL */
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147:main.c **** RCC->CR |= RCC_CR_PLLON;
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139 .loc 1 147 0
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140 00be 1A68 ldr r2, [r3]
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141 00c0 42F08072 orr r2, r2, #16777216
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142 00c4 1A60 str r2, [r3]
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143 .L5:
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148:main.c **** /* wait till PLL is ready */
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149:main.c **** while((RCC->CR & RCC_CR_PLLRDY) == 0)
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144 .loc 1 149 0
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145 00c6 1A68 ldr r2, [r3]
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146 00c8 12F0007F tst r2, #33554432
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147 00cc FBD0 beq .L5
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150:main.c **** {
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151:main.c **** }
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152:main.c **** /* select PLL as system clock source */
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153:main.c **** RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
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148 .loc 1 153 0
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149 00ce 184B ldr r3, .L12+4
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150 00d0 5A68 ldr r2, [r3, #4]
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151 00d2 22F00302 bic r2, r2, #3
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152 00d6 5A60 str r2, [r3, #4]
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154:main.c **** RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
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153 .loc 1 154 0
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154 00d8 5A68 ldr r2, [r3, #4]
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155 00da 42F00202 orr r2, r2, #2
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156 00de 5A60 str r2, [r3, #4]
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155:main.c **** /* wait till PLL is used as system clock source */
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156:main.c **** while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
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157 .loc 1 156 0
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158 00e0 1A46 mov r2, r3
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159 .L6:
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160 00e2 5368 ldr r3, [r2, #4]
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161 00e4 03F00C03 and r3, r3, #12
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162 00e8 082B cmp r3, #8
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163 00ea FAD1 bne .L6
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157:main.c **** {
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158:main.c **** }
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159:main.c **** #if (BOOT_COM_CAN_ENABLE > 0)
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160:main.c **** /* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */
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161:main.c **** RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001);
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162:main.c **** /* configure CAN Rx (GPIOB8) as alternate function input pull-up */
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163:main.c **** /* first reset the configuration */
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164:main.c **** GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0);
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165:main.c **** /* CNF8[1:0] = %10 and MODE8[1:0] = %00 */
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166:main.c **** GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0);
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167:main.c **** /* configure CAN Tx (GPIOB9) as alternate function push-pull */
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168:main.c **** /* first reset the configuration */
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169:main.c **** GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4);
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170:main.c **** /* CNF9[1:0] = %10 and MODE9[1:0] = %11 */
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171:main.c **** GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4);
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172:main.c **** /* remap CAN1 pins to PortB */
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173:main.c **** AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13);
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174:main.c **** AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13);
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175:main.c **** /* enable clocks for CAN controller peripheral */
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176:main.c **** RCC->APB1ENR |= (blt_int32u)0x02000000;
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177:main.c **** #endif
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178:main.c **** #if (BOOT_COM_UART_ENABLE > 0)
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179:main.c **** /* enable clock for USART2 peripheral */
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180:main.c **** RCC->APB1ENR |= (blt_int32u)0x00020000;
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164 .loc 1 180 0
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165 00ec 104B ldr r3, .L12+4
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166 00ee DA69 ldr r2, [r3, #28]
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167 00f0 42F40032 orr r2, r2, #131072
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168 00f4 DA61 str r2, [r3, #28]
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181:main.c **** /* enable clocks for USART2 transmitter and receiver pins (GPIOA and AFIO) */
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182:main.c **** RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001);
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169 .loc 1 182 0
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170 00f6 9A69 ldr r2, [r3, #24]
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171 00f8 42F00502 orr r2, r2, #5
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172 00fc 9A61 str r2, [r3, #24]
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183:main.c **** /* configure USART2 Tx (GPIOA2) as alternate function push-pull */
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184:main.c **** /* first reset the configuration */
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185:main.c **** GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 8);
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173 .loc 1 185 0
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174 00fe A3F58433 sub r3, r3, #67584
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175 0102 1A68 ldr r2, [r3]
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176 0104 22F47062 bic r2, r2, #3840
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177 0108 1A60 str r2, [r3]
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186:main.c **** /* CNF2[1:0] = %10 and MODE2[1:0] = %11 */
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187:main.c **** GPIOA->CRL |= (blt_int32u)((blt_int32u)0xb << 8);
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178 .loc 1 187 0
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179 010a 1A68 ldr r2, [r3]
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180 010c 42F43062 orr r2, r2, #2816
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181 0110 1A60 str r2, [r3]
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188:main.c **** /* configure USART2 Rx (GPIOA3) as alternate function input floating */
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189:main.c **** /* first reset the configuration */
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190:main.c **** GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 12);
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182 .loc 1 190 0
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183 0112 1A68 ldr r2, [r3]
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184 0114 22F47042 bic r2, r2, #61440
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185 0118 1A60 str r2, [r3]
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191:main.c **** /* CNF2[1:0] = %01 and MODE2[1:0] = %00 */
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192:main.c **** GPIOA->CRL |= (blt_int32u)((blt_int32u)0x4 << 12);
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186 .loc 1 192 0
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187 011a 1A68 ldr r2, [r3]
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188 011c 42F48042 orr r2, r2, #16384
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189 0120 1A60 str r2, [r3]
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190 .LBE5:
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191 .LBE4:
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61:main.c ****
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192 .loc 1 61 0
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193 0122 FFF7FEFF bl BootInit
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194 .LVL2:
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195 .L7:
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67:main.c **** }
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196 .loc 1 67 0 discriminator 1
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197 0126 FFF7FEFF bl BootTask
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198 .LVL3:
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68:main.c ****
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199 .loc 1 68 0 discriminator 1
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200 012a FCE7 b .L7
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201 .L13:
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202 .align 2
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203 .L12:
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204 012c 0000FFF8 .word -117506048
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205 0130 00100240 .word 1073876992
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206 0134 00000000 .word .LC0
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207 0138 00200240 .word 1073881088
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208 .cfi_endproc
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209 .LFE29:
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211 .section .rodata.str1.4,"aMS",%progbits,1
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212 .align 2
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213 .LC0:
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214 0000 6D61696E .ascii "main.c\000"
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214 2E6300
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215 0007 00 .text
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216 .Letext0:
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217 .file 2 "../../../Source/ARMCM3_STM32/types.h"
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218 .file 3 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\mach
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219 .file 4 "c:\\program files (x86)\\gnu tools arm embedded\\4.9 2015q1\\arm-none-eabi\\include\\stdi
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220 .file 5 "./lib/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h"
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221 .file 6 "../../../Source/boot.h"
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222 .file 7 "./lib/CMSIS/CM3/CoreSupport/core_cm3.h"
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223 .file 8 "../../../Source/assert.h"
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DEFINED SYMBOLS
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*ABS*:00000000 main.c
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C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:19 .text.main:00000000 $t
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C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:24 .text.main:00000000 main
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C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:204 .text.main:0000012c $d
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C:\Users\lwngim1\AppData\Local\Temp\cc1yUehE.s:212 .rodata.str1.4:00000000 $d
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.debug_frame:00000010 $d
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|
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UNDEFINED SYMBOLS
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AssertFailure
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BootInit
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BootTask
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