991 lines
35 KiB
C
991 lines
35 KiB
C
/**
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******************************************************************************
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* @file stm32g0xx_hal_rcc_ex.c
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* @author MCD Application Team
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* @brief Extended RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities RCC extended peripheral:
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* + Extended Peripheral Control functions
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* + Extended Clock management functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g0xx_hal.h"
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/** @addtogroup STM32G0xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCCEx RCCEx
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* @brief RCC Extended HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private defines -----------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
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* @{
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*/
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#define PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */
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#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define LSCO_GPIO_PORT GPIOA
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#define LSCO_PIN GPIO_PIN_2
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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* @{
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*/
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/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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* @brief Extended Peripheral Control functions
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*
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@verbatim
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===============================================================================
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##### Extended Peripheral Control functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to control the RCC Clocks
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frequencies.
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[..]
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(@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to
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select the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) and RCC_BDCR register are set to their reset values.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initialize the RCC extended peripherals clocks according to the specified
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* parameters in the @ref RCC_PeriphCLKInitTypeDef.
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* @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that
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* contains a field PeriphClockSelection which can be a combination of the following values:
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* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
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* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock
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* @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
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* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1)
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* @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2)
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* @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2)
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* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (2)
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*
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* @note (1) Peripherals are not available on all devices
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* @note (2) Peripherals clock selection is not available on all devices
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* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
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* the RTC clock source: in this case the access to Backup domain is enabled.
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*
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t tmpregister;
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uint32_t tickstart;
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HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
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HAL_StatusTypeDef status = HAL_OK; /* Final status */
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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/*-------------------------- RTC clock source configuration ----------------------*/
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if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
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{
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FlagStatus pwrclkchanged = RESET;
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/* Check for RTC Parameters used to output RTCCLK */
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assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
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/* Enable Power Clock */
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if (__HAL_RCC_PWR_IS_CLK_DISABLED())
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{
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__HAL_RCC_PWR_CLK_ENABLE();
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pwrclkchanged = SET;
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}
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR1, PWR_CR1_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
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{
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if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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{
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ret = HAL_TIMEOUT;
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break;
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}
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}
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if (ret == HAL_OK)
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{
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/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
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tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
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/* Reset the Backup domain only if the RTC Clock source selection is modified */
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if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
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{
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/* Store the content of BDCR register before the reset of Backup Domain */
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tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
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/* RTC Clock selection can be changed only if the Backup Domain is reset */
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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/* Restore the Content of BDCR register */
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RCC->BDCR = tmpregister;
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}
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/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
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if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
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{
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
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{
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if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
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{
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ret = HAL_TIMEOUT;
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break;
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}
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}
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}
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if (ret == HAL_OK)
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{
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/* Apply new RTC clock source selection */
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__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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}
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else
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{
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/* set overall return value */
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status = ret;
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}
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}
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else
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{
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/* set overall return value */
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status = ret;
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}
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/* Restore clock configuration if changed */
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if (pwrclkchanged == SET)
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{
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__HAL_RCC_PWR_CLK_DISABLE();
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}
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}
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/*-------------------------- USART1 clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
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/* Configure the USART1 clock source */
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__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
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}
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#if defined(RCC_CCIPR_USART2SEL)
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/*-------------------------- USART2 clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
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{
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/* Check the parameters */
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assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
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/* Configure the USART2 clock source */
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__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
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}
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#endif /* RCC_CCIPR_USART2SEL */
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#if defined(RCC_CCIPR_LPUART1SEL)
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/*-------------------------- LPUART1 clock source configuration ------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
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/* Configure the LPUAR1 clock source */
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__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
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}
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#endif /* RCC_CCIPR_LPUART1SEL */
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#if defined(RCC_CCIPR_LPTIM1SEL)
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/*-------------------------- LPTIM1 clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
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{
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assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
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__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
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}
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#endif /* RCC_CCIPR_LPTIM1SEL */
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#if defined(RCC_CCIPR_LPTIM2SEL)
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/*-------------------------- LPTIM2 clock source configuration -------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
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{
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assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
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__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
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}
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#endif /* RCC_CCIPR_LPTIM2SEL */
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/*-------------------------- I2C1 clock source configuration ---------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
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/* Configure the I2C1 clock source */
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__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
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}
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#if defined(RCC_CCIPR_RNGSEL)
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/*-------------------------- RNG clock source configuration ----------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
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{
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assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
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__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
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if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
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{
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/* Enable PLLQCLK output */
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__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
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}
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}
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#endif /* RCC_CCIPR_RNGSEL */
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/*-------------------------- ADC clock source configuration ----------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
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{
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/* Check the parameters */
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assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
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/* Configure the ADC interface clock source */
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__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
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if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC)
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{
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/* Enable PLLPCLK output */
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__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
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}
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}
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#if defined(RCC_CCIPR_CECSEL)
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/*-------------------------- CEC clock source configuration ---------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
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{
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/* Check the parameters */
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assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
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/* Configure the CEC clock source */
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__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
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}
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#endif /* RCC_CCIPR_CECSEL */
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#if defined(RCC_CCIPR_TIM1SEL)
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/*-------------------------- TIM1 clock source configuration ---------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
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/* Configure the TIM1 clock source */
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__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
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if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL)
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{
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/* Enable PLLQCLK output */
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__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
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}
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}
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#endif /* RCC_CCIPR_TIM1SEL */
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#if defined(RCC_CCIPR_TIM15SEL)
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/*-------------------------- TIM15 clock source configuration ---------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
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{
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/* Check the parameters */
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assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
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/* Configure the TIM15 clock source */
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__HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
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if (PeriphClkInit->Tim15ClockSelection == RCC_TIM15CLKSOURCE_PLL)
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{
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/* Enable PLLQCLK output */
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__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
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}
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}
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#endif /* RCC_CCIPR_TIM15SEL */
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/*-------------------------- I2S1 clock source configuration ---------------------*/
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if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
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{
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/* Check the parameters */
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assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
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/* Configure the I2S1 clock source */
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__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
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if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL)
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{
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/* Enable PLLPCLK output */
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__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
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}
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}
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return status;
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}
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/**
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* @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
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* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
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* returns the configuration information for the Extended Peripherals
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* clocks: I2C1, I2S1, USART1, RTC, ADC,
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* LPTIM1 (1), LPTIM2 (1), TIM1 (2), TIM15 (1)(2), USART2 (2), LPUART1 (1), CEC (1) and RNG (1)
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* @note (1) Peripheral is not available on all devices
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* @note (2) Peripheral clock selection is not available on all devices
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* @retval None
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*/
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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/* Set all possible values for the extended clock type parameter------------*/
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PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2S1 | \
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RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC ;
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#if defined(RCC_CCIPR_LPTIM1SEL) && defined(RCC_CCIPR_LPTIM2SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM1;
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#endif /* RCC_CCIPR_LPTIM1SEL && RCC_CCIPR_LPTIM2SEL */
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#if defined(RCC_CCIPR_RNGSEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_RNG;
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#endif /* RCC_CCIPR_RNGSEL */
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#if defined(RCC_CCIPR_LPUART1SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1;
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#endif /* RCC_CCIPR_LPUART1SEL */
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#if defined(RCC_CCIPR_CECSEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
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#endif /* RCC_CCIPR_CECSEL */
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#if defined(RCC_CCIPR_TIM1SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
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#endif /* RCC_CCIPR_TIM1SEL */
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#if defined(RCC_CCIPR_TIM15SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
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#endif /* RCC_CCIPR_TIM15SEL */
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#if defined(RCC_CCIPR_USART2SEL)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
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#endif /* RCC_CCIPR_USART2SEL */
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/* Get the USART1 clock source ---------------------------------------------*/
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PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
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#if defined(RCC_CCIPR_USART2SEL)
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/* Get the USART2 clock source ---------------------------------------------*/
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PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
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#endif /* RCC_CCIPR_USART2SEL */
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#if defined(RCC_CCIPR_LPUART1SEL)
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/* Get the LPUART1 clock source --------------------------------------------*/
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PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
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#endif /* RCC_CCIPR_LPUART1SEL */
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/* Get the I2C1 clock source -----------------------------------------------*/
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PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
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#if defined(RCC_CCIPR_LPTIM1SEL)
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/* Get the LPTIM1 clock source ---------------------------------------------*/
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PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
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#endif /* RCC_CCIPR_LPTIM1SEL */
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#if defined(RCC_CCIPR_LPTIM2SEL)
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/* Get the LPTIM2 clock source ---------------------------------------------*/
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PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
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#endif /* RCC_CCIPR_LPTIM2SEL */
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#if defined(RCC_CCIPR_TIM1SEL)
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/* Get the TIM1 clock source ---------------------------------------------*/
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PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
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#endif /* RCC_CCIPR_TIM1SEL */
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#if defined(RCC_CCIPR_TIM15SEL)
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/* Get the TIM15 clock source ---------------------------------------------*/
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PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
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#endif /* RCC_CCIPR_TIM15SEL */
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/* Get the RTC clock source ------------------------------------------------*/
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PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
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#if defined(RCC_CCIPR_RNGSEL)
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/* Get the RNG clock source ------------------------------------------------*/
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PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
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#endif /* RCC_CCIPR_RNGSEL */
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/* Get the ADC clock source -----------------------------------------------*/
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PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
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#if defined(RCC_CCIPR_CECSEL)
|
|
/* Get the CEC clock source -----------------------------------------------*/
|
|
PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
|
|
#endif /* RCC_CCIPR_CECSEL */
|
|
/* Get the I2S1 clock source -----------------------------------------------*/
|
|
PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE();
|
|
}
|
|
|
|
/**
|
|
* @brief Return the peripheral clock frequency for peripherals with clock source from PLL
|
|
* @note Return 0 if peripheral clock identifier not managed by this API
|
|
* @param PeriphClk Peripheral clock identifier
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
|
|
* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
|
|
* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
|
|
* @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock
|
|
* @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
|
|
* @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1)
|
|
* @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2)
|
|
* @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2)
|
|
* @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1)
|
|
* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1)
|
|
* @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock(1)
|
|
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1)
|
|
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (1)(2)
|
|
* @note (1) Peripheral not available on all devices
|
|
* @note (2) Peripheral Clock configuration not available on all devices
|
|
* @retval Frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
|
|
{
|
|
uint32_t frequency = 0U;
|
|
uint32_t srcclk;
|
|
uint32_t pllvco;
|
|
uint32_t plln;
|
|
#if defined(RCC_CCIPR_RNGSEL)
|
|
uint32_t rngclk;
|
|
uint32_t rngdiv;
|
|
#endif
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
|
|
|
|
if (PeriphClk == RCC_PERIPHCLK_RTC)
|
|
{
|
|
/* Get the current RTC source */
|
|
srcclk = __HAL_RCC_GET_RTC_SOURCE();
|
|
|
|
/* Check if LSE is ready and if RTC clock selection is LSE */
|
|
if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Check if LSI is ready and if RTC clock selection is LSI */
|
|
else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
|
|
{
|
|
frequency = LSI_VALUE;
|
|
}
|
|
/* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) &&(srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
|
|
{
|
|
frequency = HSE_VALUE / 32U;
|
|
}
|
|
/* Clock not enabled for RTC*/
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Other external peripheral clock source than RTC */
|
|
|
|
/* Compute PLL clock input */
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */
|
|
{
|
|
pllvco = HSI_VALUE;
|
|
}
|
|
else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */
|
|
{
|
|
pllvco = HSE_VALUE;
|
|
}
|
|
else /* No source */
|
|
{
|
|
pllvco = 0U;
|
|
}
|
|
|
|
/* f(PLL Source) / PLLM */
|
|
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
|
|
|
|
switch (PeriphClk)
|
|
{
|
|
#if defined(RCC_CCIPR_RNGSEL)
|
|
case RCC_PERIPHCLK_RNG:
|
|
|
|
srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL);
|
|
if (srcclk == RCC_RNGCLKSOURCE_HSI_DIV8) /* HSI_DIV8 ? */
|
|
{
|
|
rngclk = HSI_VALUE / 8U;
|
|
}
|
|
else if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */
|
|
{
|
|
/* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
|
|
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
|
|
rngclk = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
|
|
}
|
|
else if (srcclk == RCC_RNGCLKSOURCE_SYSCLK) /* SYSCLK ? */
|
|
{
|
|
rngclk = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else /* No clock source */
|
|
{
|
|
rngclk = 0U;
|
|
}
|
|
|
|
rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
|
|
frequency = (rngclk / rngdiv);
|
|
|
|
break;
|
|
#endif /* RCC_CCIPR_RNGSEL */
|
|
case RCC_PERIPHCLK_USART1:
|
|
/* Get the current USART1 source */
|
|
srcclk = __HAL_RCC_GET_USART1_SOURCE();
|
|
|
|
if (srcclk == RCC_USART1CLKSOURCE_PCLK1) /* PCLK1 ? */
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) /* SYSCLK ? */
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Clock not enabled for USART1 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#if defined(RCC_CCIPR_USART2SEL)
|
|
case RCC_PERIPHCLK_USART2:
|
|
/* Get the current USART2 source */
|
|
srcclk = __HAL_RCC_GET_USART2_SOURCE();
|
|
|
|
if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Clock not enabled for USART2 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_USART2SEL */
|
|
#if defined(RCC_CCIPR_CECSEL)
|
|
case RCC_PERIPHCLK_CEC:
|
|
/* Get the current CEC source */
|
|
srcclk = __HAL_RCC_GET_CEC_SOURCE();
|
|
|
|
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_CECCLKSOURCE_HSI_DIV488))
|
|
{
|
|
frequency = (HSI_VALUE / 488U);
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Clock not enabled for CEC */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_CECSEL */
|
|
|
|
#if defined(RCC_CCIPR_LPUART1SEL)
|
|
case RCC_PERIPHCLK_LPUART1:
|
|
/* Get the current LPUART1 source */
|
|
srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
|
|
|
|
if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Clock not enabled for LPUART1 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_LPUART1SEL */
|
|
|
|
case RCC_PERIPHCLK_ADC:
|
|
|
|
srcclk = __HAL_RCC_GET_ADC_SOURCE();
|
|
|
|
if (srcclk == RCC_ADCCLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else if (srcclk == RCC_ADCCLKSOURCE_HSI)
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if (srcclk == RCC_ADCCLKSOURCE_PLLADC)
|
|
{
|
|
if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U)
|
|
{
|
|
/* f(PLLP) = f(VCO input) * PLLN / PLLP */
|
|
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
|
|
frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U);
|
|
}
|
|
}
|
|
/* Clock not enabled for ADC */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
|
|
case RCC_PERIPHCLK_I2C1:
|
|
/* Get the current I2C1 source */
|
|
srcclk = __HAL_RCC_GET_I2C1_SOURCE();
|
|
|
|
if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
/* Clock not enabled for I2C1 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
|
|
case RCC_PERIPHCLK_I2S1:
|
|
/* Get the current I2S1 source */
|
|
srcclk = __HAL_RCC_GET_I2S1_SOURCE();
|
|
|
|
if (srcclk == RCC_I2S1CLKSOURCE_PLL)
|
|
{
|
|
if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U)
|
|
{
|
|
/* f(PLLP) = f(VCO input) * PLLN / PLLP */
|
|
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
|
|
frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U);
|
|
}
|
|
}
|
|
else if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK)
|
|
{
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if (srcclk == RCC_I2S1CLKSOURCE_EXT)
|
|
{
|
|
/* External clock used.*/
|
|
frequency = EXTERNAL_I2S1_CLOCK_VALUE;
|
|
}
|
|
/* Clock not enabled for I2S1 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
|
|
#if defined(RCC_CCIPR_LPTIM1SEL)
|
|
case RCC_PERIPHCLK_LPTIM1:
|
|
/* Get the current LPTIM1 source */
|
|
srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
|
|
|
|
if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
|
|
{
|
|
frequency = LSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Clock not enabled for LPTIM1 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_LPTIM1SEL */
|
|
|
|
#if defined(RCC_CCIPR_LPTIM2SEL)
|
|
case RCC_PERIPHCLK_LPTIM2:
|
|
/* Get the current LPTIM2 source */
|
|
srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
|
|
|
|
if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
|
|
{
|
|
frequency = LSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
|
|
{
|
|
frequency = HSI_VALUE;
|
|
}
|
|
else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Clock not enabled for LPTIM2 */
|
|
else
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_LPTIM2SEL */
|
|
|
|
#if defined(RCC_CCIPR_TIM1SEL)
|
|
case RCC_PERIPHCLK_TIM1:
|
|
|
|
srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL);
|
|
|
|
if (srcclk == RCC_TIM1CLKSOURCE_PLL) /* PLL ? */
|
|
{
|
|
if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U)
|
|
{
|
|
/* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
|
|
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
|
|
frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
|
|
}
|
|
}
|
|
else if (srcclk == RCC_TIM1CLKSOURCE_PCLK1) /* PCLK1 ? */
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else /* No clock source */
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_TIM1SEL */
|
|
|
|
#if defined(RCC_CCIPR_TIM15SEL)
|
|
case RCC_PERIPHCLK_TIM15:
|
|
|
|
srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL);
|
|
|
|
if (srcclk == RCC_TIM15CLKSOURCE_PLL) /* PLL ? */
|
|
{
|
|
if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U)
|
|
{
|
|
/* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
|
|
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
|
|
frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U);
|
|
}
|
|
}
|
|
else if (srcclk == RCC_TIM15CLKSOURCE_PCLK1) /* PCLK1 ? */
|
|
{
|
|
frequency = HAL_RCC_GetPCLK1Freq();
|
|
}
|
|
else /* No clock source */
|
|
{
|
|
/* Nothing to do as frequency already initialized to 0U */
|
|
}
|
|
break;
|
|
#endif /* RCC_CCIPR_TIM15SEL */
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
return (frequency);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
|
|
* @brief Extended Clock management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Extended clock management functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control the
|
|
activation or deactivation of LSE CSS, Low speed clock output and
|
|
clock after wake-up from STOP mode.
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Select the Low Speed clock source to output on LSCO pin (PA2).
|
|
* @param LSCOSource specifies the Low Speed clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
|
|
* @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
|
|
{
|
|
GPIO_InitTypeDef GPIO_InitStruct;
|
|
FlagStatus pwrclkchanged = RESET;
|
|
FlagStatus backupchanged = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
|
|
|
|
/* LSCO Pin Clock Enable */
|
|
LSCO_CLK_ENABLE();
|
|
|
|
/* Configue the LSCO pin in analog mode */
|
|
GPIO_InitStruct.Pin = LSCO_PIN;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
|
|
|
|
/* Update LSCOSEL clock source in Backup Domain control register */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
pwrclkchanged = SET;
|
|
}
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
{
|
|
HAL_PWR_EnableBkUpAccess();
|
|
backupchanged = SET;
|
|
}
|
|
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
|
|
|
|
if (backupchanged == SET)
|
|
{
|
|
HAL_PWR_DisableBkUpAccess();
|
|
}
|
|
if (pwrclkchanged == SET)
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the Low Speed clock output.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_DisableLSCO(void)
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
FlagStatus backupchanged = RESET;
|
|
|
|
/* Update LSCOEN bit in Backup Domain control register */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
pwrclkchanged = SET;
|
|
}
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
{
|
|
/* Enable access to the backup domain */
|
|
HAL_PWR_EnableBkUpAccess();
|
|
backupchanged = SET;
|
|
}
|
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
|
|
|
|
/* Restore previous configuration */
|
|
if (backupchanged == SET)
|
|
{
|
|
/* Disable access to the backup domain */
|
|
HAL_PWR_DisableBkUpAccess();
|
|
}
|
|
if (pwrclkchanged == SET)
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|