866 lines
28 KiB
C
866 lines
28 KiB
C
/**************************************************************************//**
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* @file cmsis_armcc.h
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* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
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* @version V5.0.4
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* @date 10. January 2018
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __CMSIS_ARMCC_H
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#define __CMSIS_ARMCC_H
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
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#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
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#endif
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/* CMSIS compiler control architecture macros */
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#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
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(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
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#define __ARM_ARCH_6M__ 1
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#endif
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#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
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#define __ARM_ARCH_7M__ 1
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#endif
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#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
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#define __ARM_ARCH_7EM__ 1
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#endif
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/* __ARM_ARCH_8M_BASE__ not applicable */
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/* __ARM_ARCH_8M_MAIN__ not applicable */
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE __inline
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static __inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE static __forceinline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __declspec(noreturn)
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT __packed struct
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION __packed union
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __RESTRICT
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#define __RESTRICT __restrict
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#endif
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/**
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\brief Enable IRQ Interrupts
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\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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/* intrinsic void __enable_irq(); */
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/**
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\brief Disable IRQ Interrupts
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\details Disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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/* intrinsic void __disable_irq(); */
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/**
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\brief Get Control Register
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\details Returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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/**
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\brief Set Control Register
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\details Writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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/**
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\brief Get IPSR Register
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\details Returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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/**
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\brief Get APSR Register
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\details Returns the content of the APSR Register.
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\return APSR Register value
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*/
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__STATIC_INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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/**
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\brief Get xPSR Register
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\details Returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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/**
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\brief Get Process Stack Pointer
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\details Returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__STATIC_INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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/**
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\brief Set Process Stack Pointer
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\details Assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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/**
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\brief Get Main Stack Pointer
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\details Returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__STATIC_INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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/**
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\brief Set Main Stack Pointer
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\details Assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = topOfMainStack;
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}
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/**
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\brief Get Priority Mask
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\details Returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__STATIC_INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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/**
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\brief Set Priority Mask
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\details Assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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/**
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\brief Enable FIQ
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\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/**
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\brief Disable FIQ
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\details Disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/**
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\brief Get Base Priority
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\details Returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__STATIC_INLINE uint32_t __get_BASEPRI(void)
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{
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
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}
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/**
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\brief Set Base Priority
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\details Assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xFFU);
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}
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/**
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\brief Set Base Priority with condition
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\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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or the new value increases the BASEPRI priority level.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
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{
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register uint32_t __regBasePriMax __ASM("basepri_max");
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__regBasePriMax = (basePri & 0xFFU);
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}
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/**
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\brief Get Fault Mask
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\details Returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__STATIC_INLINE uint32_t __get_FAULTMASK(void)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
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}
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/**
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\brief Set Fault Mask
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\details Assigns the given value to the Fault Mask register.
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\param [in] faultMask Fault Mask value to set
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*/
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__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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__regFaultMask = (faultMask & (uint32_t)1U);
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}
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#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
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/**
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\brief Get FPSCR
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\details Returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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__STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0U);
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#endif
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}
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/**
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\brief Set FPSCR
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\details Assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#else
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(void)fpscr;
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#endif
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}
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/*@} end of CMSIS_Core_RegAccFunctions */
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/* ########################## Core Instruction Access ######################### */
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/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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Access to dedicated instructions
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@{
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*/
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/**
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\brief No Operation
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\details No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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#define __NOP __nop
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/**
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\brief Wait For Interrupt
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\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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*/
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#define __WFI __wfi
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/**
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\brief Wait For Event
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\details Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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#define __WFE __wfe
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/**
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\brief Send Event
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\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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*/
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#define __SEV __sev
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/**
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\brief Instruction Synchronization Barrier
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\details Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or memory,
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after the instruction has been completed.
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*/
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#define __ISB() do {\
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__schedule_barrier();\
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__isb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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#define __DSB() do {\
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__schedule_barrier();\
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__dsb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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#define __DMB() do {\
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__schedule_barrier();\
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__dmb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV __rev
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] op1 Value to rotate
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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#define __ROR __ror
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/**
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\brief Breakpoint
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\details Causes the processor to enter Debug state.
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Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __breakpoint(value)
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/**
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\brief Reverse bit order of value
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\details Reverses the bit order of the given value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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#define __RBIT __rbit
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#else
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
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{
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uint32_t result;
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uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
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result = value; /* r will be reversed bits of v; first get LSB of v */
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for (value >>= 1U; value != 0U; value >>= 1U)
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{
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result <<= 1U;
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result |= value & 1U;
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s--;
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}
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result <<= s; /* shift when v's highest bits are zero */
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return result;
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}
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#endif
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/**
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\brief Count leading zeros
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\details Counts the number of leading zeros of a data value.
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ __clz
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
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/**
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\brief LDR Exclusive (8 bit)
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\details Executes a exclusive LDR instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
|
|
*/
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
|
#else
|
|
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief LDR Exclusive (16 bit)
|
|
\details Executes a exclusive LDR instruction for 16 bit values.
|
|
\param [in] ptr Pointer to data
|
|
\return value of type uint16_t at (*ptr)
|
|
*/
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
|
#else
|
|
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief LDR Exclusive (32 bit)
|
|
\details Executes a exclusive LDR instruction for 32 bit values.
|
|
\param [in] ptr Pointer to data
|
|
\return value of type uint32_t at (*ptr)
|
|
*/
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
|
#else
|
|
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief STR Exclusive (8 bit)
|
|
\details Executes a exclusive STR instruction for 8 bit values.
|
|
\param [in] value Value to store
|
|
\param [in] ptr Pointer to location
|
|
\return 0 Function succeeded
|
|
\return 1 Function failed
|
|
*/
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
|
#else
|
|
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief STR Exclusive (16 bit)
|
|
\details Executes a exclusive STR instruction for 16 bit values.
|
|
\param [in] value Value to store
|
|
\param [in] ptr Pointer to location
|
|
\return 0 Function succeeded
|
|
\return 1 Function failed
|
|
*/
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
|
#else
|
|
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief STR Exclusive (32 bit)
|
|
\details Executes a exclusive STR instruction for 32 bit values.
|
|
\param [in] value Value to store
|
|
\param [in] ptr Pointer to location
|
|
\return 0 Function succeeded
|
|
\return 1 Function failed
|
|
*/
|
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
|
#else
|
|
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief Remove the exclusive lock
|
|
\details Removes the exclusive lock which is created by LDREX.
|
|
*/
|
|
#define __CLREX __clrex
|
|
|
|
|
|
/**
|
|
\brief Signed Saturate
|
|
\details Saturates a signed value.
|
|
\param [in] value Value to be saturated
|
|
\param [in] sat Bit position to saturate to (1..32)
|
|
\return Saturated value
|
|
*/
|
|
#define __SSAT __ssat
|
|
|
|
|
|
/**
|
|
\brief Unsigned Saturate
|
|
\details Saturates an unsigned value.
|
|
\param [in] value Value to be saturated
|
|
\param [in] sat Bit position to saturate to (0..31)
|
|
\return Saturated value
|
|
*/
|
|
#define __USAT __usat
|
|
|
|
|
|
/**
|
|
\brief Rotate Right with Extend (32 bit)
|
|
\details Moves each bit of a bitstring right by one bit.
|
|
The carry input is shifted in at the left end of the bitstring.
|
|
\param [in] value Value to rotate
|
|
\return Rotated value
|
|
*/
|
|
#ifndef __NO_EMBEDDED_ASM
|
|
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
|
{
|
|
rrx r0, r0
|
|
bx lr
|
|
}
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief LDRT Unprivileged (8 bit)
|
|
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
|
\param [in] ptr Pointer to data
|
|
\return value of type uint8_t at (*ptr)
|
|
*/
|
|
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
|
|
|
|
|
/**
|
|
\brief LDRT Unprivileged (16 bit)
|
|
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
|
\param [in] ptr Pointer to data
|
|
\return value of type uint16_t at (*ptr)
|
|
*/
|
|
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
|
|
|
|
|
/**
|
|
\brief LDRT Unprivileged (32 bit)
|
|
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
|
\param [in] ptr Pointer to data
|
|
\return value of type uint32_t at (*ptr)
|
|
*/
|
|
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
|
|
|
|
|
/**
|
|
\brief STRT Unprivileged (8 bit)
|
|
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
|
\param [in] value Value to store
|
|
\param [in] ptr Pointer to location
|
|
*/
|
|
#define __STRBT(value, ptr) __strt(value, ptr)
|
|
|
|
|
|
/**
|
|
\brief STRT Unprivileged (16 bit)
|
|
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
|
\param [in] value Value to store
|
|
\param [in] ptr Pointer to location
|
|
*/
|
|
#define __STRHT(value, ptr) __strt(value, ptr)
|
|
|
|
|
|
/**
|
|
\brief STRT Unprivileged (32 bit)
|
|
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
|
\param [in] value Value to store
|
|
\param [in] ptr Pointer to location
|
|
*/
|
|
#define __STRT(value, ptr) __strt(value, ptr)
|
|
|
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
|
|
|
/**
|
|
\brief Signed Saturate
|
|
\details Saturates a signed value.
|
|
\param [in] value Value to be saturated
|
|
\param [in] sat Bit position to saturate to (1..32)
|
|
\return Saturated value
|
|
*/
|
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
|
{
|
|
if ((sat >= 1U) && (sat <= 32U))
|
|
{
|
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
|
const int32_t min = -1 - max ;
|
|
if (val > max)
|
|
{
|
|
return max;
|
|
}
|
|
else if (val < min)
|
|
{
|
|
return min;
|
|
}
|
|
}
|
|
return val;
|
|
}
|
|
|
|
/**
|
|
\brief Unsigned Saturate
|
|
\details Saturates an unsigned value.
|
|
\param [in] value Value to be saturated
|
|
\param [in] sat Bit position to saturate to (0..31)
|
|
\return Saturated value
|
|
*/
|
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
|
{
|
|
if (sat <= 31U)
|
|
{
|
|
const uint32_t max = ((1U << sat) - 1U);
|
|
if (val > (int32_t)max)
|
|
{
|
|
return max;
|
|
}
|
|
else if (val < 0)
|
|
{
|
|
return 0U;
|
|
}
|
|
}
|
|
return (uint32_t)val;
|
|
}
|
|
|
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
|
|
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
|
|
|
|
|
/* ################### Compiler specific Intrinsics ########################### */
|
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
|
Access to dedicated SIMD instructions
|
|
@{
|
|
*/
|
|
|
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
|
|
|
#define __SADD8 __sadd8
|
|
#define __QADD8 __qadd8
|
|
#define __SHADD8 __shadd8
|
|
#define __UADD8 __uadd8
|
|
#define __UQADD8 __uqadd8
|
|
#define __UHADD8 __uhadd8
|
|
#define __SSUB8 __ssub8
|
|
#define __QSUB8 __qsub8
|
|
#define __SHSUB8 __shsub8
|
|
#define __USUB8 __usub8
|
|
#define __UQSUB8 __uqsub8
|
|
#define __UHSUB8 __uhsub8
|
|
#define __SADD16 __sadd16
|
|
#define __QADD16 __qadd16
|
|
#define __SHADD16 __shadd16
|
|
#define __UADD16 __uadd16
|
|
#define __UQADD16 __uqadd16
|
|
#define __UHADD16 __uhadd16
|
|
#define __SSUB16 __ssub16
|
|
#define __QSUB16 __qsub16
|
|
#define __SHSUB16 __shsub16
|
|
#define __USUB16 __usub16
|
|
#define __UQSUB16 __uqsub16
|
|
#define __UHSUB16 __uhsub16
|
|
#define __SASX __sasx
|
|
#define __QASX __qasx
|
|
#define __SHASX __shasx
|
|
#define __UASX __uasx
|
|
#define __UQASX __uqasx
|
|
#define __UHASX __uhasx
|
|
#define __SSAX __ssax
|
|
#define __QSAX __qsax
|
|
#define __SHSAX __shsax
|
|
#define __USAX __usax
|
|
#define __UQSAX __uqsax
|
|
#define __UHSAX __uhsax
|
|
#define __USAD8 __usad8
|
|
#define __USADA8 __usada8
|
|
#define __SSAT16 __ssat16
|
|
#define __USAT16 __usat16
|
|
#define __UXTB16 __uxtb16
|
|
#define __UXTAB16 __uxtab16
|
|
#define __SXTB16 __sxtb16
|
|
#define __SXTAB16 __sxtab16
|
|
#define __SMUAD __smuad
|
|
#define __SMUADX __smuadx
|
|
#define __SMLAD __smlad
|
|
#define __SMLADX __smladx
|
|
#define __SMLALD __smlald
|
|
#define __SMLALDX __smlaldx
|
|
#define __SMUSD __smusd
|
|
#define __SMUSDX __smusdx
|
|
#define __SMLSD __smlsd
|
|
#define __SMLSDX __smlsdx
|
|
#define __SMLSLD __smlsld
|
|
#define __SMLSLDX __smlsldx
|
|
#define __SEL __sel
|
|
#define __QADD __qadd
|
|
#define __QSUB __qsub
|
|
|
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
|
|
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
|
|
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
|
|
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
|
|
|
|
|
#endif /* __CMSIS_ARMCC_H */
|