229 lines
9.9 KiB
ArmAsm
229 lines
9.9 KiB
ArmAsm
/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_S32K118.s */
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/* @purpose: GNU Compiler Collection Startup File */
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/* S32K118 */
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/* @version: 1.0 */
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/* @date: 2018-1-22 */
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/* @build: b170107 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* Copyright 2018 NXP */
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/* All rights reserved. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
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/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
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/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
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/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
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/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
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/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
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/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
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/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
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/* THE POSSIBILITY OF SUCH DAMAGE. */
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/*****************************************************************************/
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/* Version: GNU Compiler Collection */
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/*****************************************************************************/
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.syntax unified
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.arch armv6-m
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.section .isr_vector, "a"
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* Non Maskable Interrupt */
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.long HardFault_Handler /* Cortex-M0 SV Hard Fault Interrupt */
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long SVC_Handler /* Cortex-M0 SV Call Interrupt */
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.long 0
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.long 0
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.long PendSV_Handler /* Cortex-M0 Pend SV Interrupt */
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.long SysTick_Handler /* Cortex-M0 System Tick Interrupt */
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.long DMA0_IRQHandler /* DMA channel 0 transfer complete */
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.long DMA1_IRQHandler /* DMA channel 1 transfer complete */
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.long DMA2_IRQHandler /* DMA channel 2 transfer complete */
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.long DMA3_IRQHandler /* DMA channel 3 transfer complete */
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.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-3 */
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.long ERM_fault_IRQHandler /* ERM single and double bit error correction */
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.long RTC_IRQHandler /* RTC alarm interrupt */
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.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
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.long LPTMR0_IRQHandler /* LPTIMER interrupt request */
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.long PORT_IRQHandler /* Port A, B, C, D and E pin detect interrupt */
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.long CAN0_ORed_Err_Wakeup_IRQHandler /* OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */
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.long CAN0_ORed_0_31_MB_IRQHandler /* OR’ed Message buffer (0-15, 16-31) */
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.long FTM0_Ch0_7_IRQHandler /* FTM0 Channel 0 to 7 interrupt */
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.long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt */
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.long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt */
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.long FTM1_Ch0_7_IRQHandler /* FTM1 Channel 0 to 7 interrupt */
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.long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt */
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.long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt */
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.long FTFC_IRQHandler /* FTFC Command complete, Read collision and Double bit fault detect */
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.long PDB0_IRQHandler /* PDB0 interrupt */
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.long LPIT0_IRQHandler /* LPIT interrupt */
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.long SCG_CMU_LVD_LVWSCG_IRQHandler /* PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */
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.long WDOG_IRQHandler /* WDOG interrupt request out before wdg reset out */
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.long RCM_IRQHandler /* RCM Asynchronous Interrupt */
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.long LPI2C0_Master_Slave_IRQHandler /* LPI2C0 Master Interrupt and Slave Interrupt */
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.long FLEXIO_IRQHandler /* FlexIO Interrupt */
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.long LPSPI0_IRQHandler /* LPSPI0 Interrupt */
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.long LPSPI1_IRQHandler /* LPSPI1 Interrupt */
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.long ADC0_IRQHandler /* ADC0 interrupt request. */
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.long CMP0_IRQHandler /* CMP0 interrupt request */
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.long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt */
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.long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt */
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.long 0x55AA11EE /* Reserved for OpenBLT checksum */
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.size __isr_vector, . - __isr_vector
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/* Flash Configuration */
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.section .FlashConfig, "a"
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.long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
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.long 0xFFFFFFFF /* */
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.long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
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.long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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/* Init the rest of the registers */
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ldr r1,=0
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ldr r2,=0
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ldr r3,=0
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ldr r4,=0
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ldr r5,=0
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ldr r6,=0
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ldr r7,=0
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mov r8,r7
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mov r9,r7
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mov r10,r7
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mov r11,r7
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mov r12,r7
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#ifdef START_FROM_FLASH
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/* Init ECC RAM */
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ldr r1, =__RAM_START
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ldr r2, =__RAM_END
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subs r2, r1
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subs r2, #1
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ble .LC5
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movs r0, 0
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movs r3, #4
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.LC4:
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str r0, [r1]
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add r1, r1, r3
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subs r2, 4
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bge .LC4
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.LC5:
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#endif
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/* Initialize the stack pointer */
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ldr r0,=__StackTop
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mov r13,r0
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#ifndef __NO_SYSTEM_INIT
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/* Call the system init routine */
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Init .data and .bss sections */
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ldr r0,=init_data_bss
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blx r0
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cpsie i /* Unmask interrupts */
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#ifndef __START
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#ifdef __EWL__
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#define __START __thumb_startup
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#else
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#define __START _start
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#endif
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#endif
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bl __START
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JumpToSelf:
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b JumpToSelf
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak DefaultISR
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.type DefaultISR, %function
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DefaultISR:
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b DefaultISR
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.size DefaultISR, . - DefaultISR
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, DefaultISR
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.endm
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/* Exception Handlers */
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler DMA0_IRQHandler
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def_irq_handler DMA1_IRQHandler
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def_irq_handler DMA2_IRQHandler
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def_irq_handler DMA3_IRQHandler
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def_irq_handler DMA_Error_IRQHandler
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def_irq_handler ERM_fault_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler RTC_Seconds_IRQHandler
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def_irq_handler LPTMR0_IRQHandler
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def_irq_handler PORT_IRQHandler
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def_irq_handler CAN0_ORed_Err_Wakeup_IRQHandler
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def_irq_handler CAN0_ORed_0_31_MB_IRQHandler
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def_irq_handler FTM0_Ch0_7_IRQHandler
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def_irq_handler FTM0_Fault_IRQHandler
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def_irq_handler FTM0_Ovf_Reload_IRQHandler
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def_irq_handler FTM1_Ch0_7_IRQHandler
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def_irq_handler FTM1_Fault_IRQHandler
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def_irq_handler FTM1_Ovf_Reload_IRQHandler
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def_irq_handler FTFC_IRQHandler
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def_irq_handler PDB0_IRQHandler
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def_irq_handler LPIT0_IRQHandler
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def_irq_handler SCG_CMU_LVD_LVWSCG_IRQHandler
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def_irq_handler WDOG_IRQHandler
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def_irq_handler RCM_IRQHandler
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def_irq_handler LPI2C0_Master_Slave_IRQHandler
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def_irq_handler FLEXIO_IRQHandler
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def_irq_handler LPSPI0_IRQHandler
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def_irq_handler LPSPI1_IRQHandler
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def_irq_handler ADC0_IRQHandler
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def_irq_handler CMP0_IRQHandler
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def_irq_handler LPUART1_RxTx_IRQHandler
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def_irq_handler LPUART0_RxTx_IRQHandler
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.end
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