187 lines
8.0 KiB
C
187 lines
8.0 KiB
C
/************************************************************************************//**
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* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c
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* \brief Bootloader application source file.
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* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You have received a copy of the GNU General Public License along with OpenBLT. It
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* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */
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#include "device_registers.h" /* device registers */
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#include "system_S32K118.h" /* device sconfiguration */
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/****************************************************************************************
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* Function prototypes
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****************************************************************************************/
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static void Init(void);
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static void SystemClockConfig(void);
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/************************************************************************************//**
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** \brief This is the entry point for the bootloader application and is called
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** by the reset interrupt vector after the C-startup routines executed.
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** \return none.
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**
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****************************************************************************************/
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void main(void)
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{
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/* Initialize the microcontroller. */
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Init();
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/* Initialize the bootloader. */
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BootInit();
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/* Start the infinite program loop. */
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while (1)
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{
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/* Run the bootloader task. */
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BootTask();
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}
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} /*** end of main ***/
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/************************************************************************************//**
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** \brief Initializes the microcontroller.
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** \return none.
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**
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****************************************************************************************/
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static void Init(void)
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{
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/* Configure the system clock. */
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SystemClockConfig();
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/* Enable the peripheral clock for the ports that are used. */
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PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK;
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PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
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PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
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/* Configure SW2 (PD3) GPIO pin for (optional) backdoor entry input. */
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/* Input GPIO pin configuration. PD3 = GPIO, MUX = ALT1. */
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PORTD->PCR[3] |= PORT_PCR_MUX(1);
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/* Disable pull device, as SW2 already has a pull down resistor on the board. */
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PORTD->PCR[3] &= ~PORT_PCR_PE(1);
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/* Configure and enable Port D pin 3 GPIO as digital input */
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PTD->PDDR &= ~GPIO_PDDR_PDD(1 << 3U);
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PTD->PIDR &= ~GPIO_PIDR_PID(1 << 3U);
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#if (BOOT_COM_RS232_ENABLE > 0)
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/* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */
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PORTB->PCR[0] |= PORT_PCR_MUX(2);
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/* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */
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PORTB->PCR[1] |= PORT_PCR_MUX(2);
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#endif
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#if (BOOT_COM_CAN_ENABLE > 0)
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/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
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PORTE->PCR[4] |= PORT_PCR_MUX(5);
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/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
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PORTE->PCR[5] |= PORT_PCR_MUX(5);
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#endif
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} /*** end of Init ***/
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/************************************************************************************//**
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** \brief System Clock Configuration. This code was derived from a S32 Design Studio
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** example program. It enables the SOCS (40 MHz external crystal), FIRC (48
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** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for
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** the system clock and configures the normal RUN mode for the following clock
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** settings:
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** - CORE_CLK = 48 MHz
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** - SYS_CLK = 48 MHz
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** - BUS_CLK = 48 MHz
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** - FLASH_CLK = 24 MHz
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** - SOSCDIV1_CLK = 40 MHz
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** - SOSCDIV2_CLK = 40 MHz
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** - FIRCDIV1_CLK = 48 MHz
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** - FIRCDIV2_CLK = 48 MHz
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** - SIRCDIV1_CLK = 8 MHz
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** - SIRCDIV2_CLK = 8 MHz
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** \return none.
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**
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****************************************************************************************/
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static void SystemClockConfig(void)
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{
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/* --------- SOSC Initialization (40 MHz) ------------------------------------------ */
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/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
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SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
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/* Range=3: High freq (SOSC betw 8MHz - 40MHz).
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* HGO=0: Config xtal osc for low power.
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* EREFS=1: Input is external XTAL.
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*/
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SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK;
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/* Ensure SOSCCSR unlocked. */
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while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
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{
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;
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}
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/* LK=0: SOSCCSR can be written.
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* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
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* SOSCCM=0: OSC CLK monitor disabled.
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* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
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* SOSCLPEN=0: Sys OSC disabled in VLP modes.
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* SOSCSTEN=0: Sys OSC disabled in Stop modes.
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* SOSCEN=1: Enable oscillator.
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*/
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SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
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/* Wait for system OSC clock to become valid. */
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while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
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{
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;
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}
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/* --------- FIRC Initialization --------------------------------------------------- */
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/* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK
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* and FIRCDIV1_CLK, divide by 1 = 48 MHz.
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*/
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SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1);
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/* --------- SIRC Initialization --------------------------------------------------- */
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/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
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* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
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*/
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SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
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/* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */
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/* Select FIRC as clock source.
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* DIVCORE=0, div. by 1: Core clock = 48 MHz.
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* DIVBUS=0, div. by 1: bus clock = 48 MHz.
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* DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz
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*/
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SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) |
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SCG_RCCR_DIVSLOW(1);
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/* Wait until system clock source is FIRC. */
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while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U)
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{
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;
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}
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/* Evaluate the clock register settings and calculates the current core clock. This
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* function must be called when the clock manager component is not used.
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*/
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SystemCoreClockUpdate();
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} /*** end of SystemClockConfig ***/
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/*********************************** end of main.c *************************************/
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