189 lines
9.6 KiB
C
189 lines
9.6 KiB
C
//*****************************************************************************
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//
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// hw_hibernate.h - Defines and Macros for the Hibernation module.
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//
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// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.1 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_HIBERNATE_H__
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#define __HW_HIBERNATE_H__
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//*****************************************************************************
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//
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// The following are defines for the Hibernation module register addresses.
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//
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//*****************************************************************************
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#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
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#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
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#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
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#define HIB_CTL 0x400FC010 // Hibernation Control
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#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
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#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
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#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
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// Status
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#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
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#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
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#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
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#define HIB_DATA 0x400FC030 // Hibernation Data
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCC register.
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//
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//*****************************************************************************
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#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
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#define HIB_RTCC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCM0 register.
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//
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//*****************************************************************************
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#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
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#define HIB_RTCM0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCLD register.
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//
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//*****************************************************************************
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#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
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#define HIB_RTCLD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CTL register.
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//
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//*****************************************************************************
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#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
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#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
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#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
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#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
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// Comparator
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#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
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#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
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#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
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#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
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#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
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#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
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#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
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#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
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#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
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#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
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#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
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#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
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#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IM register.
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//
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//*****************************************************************************
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#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
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// Interrupt Mask
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#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
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#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
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// Mask
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#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RIS register.
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//
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//*****************************************************************************
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#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
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// Interrupt Status
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#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
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// Status
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#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
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// Interrupt Status
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#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_MIS register.
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//
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//*****************************************************************************
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#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
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// Interrupt Status
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#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
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// Interrupt Status
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#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
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// Interrupt Status
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#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
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// Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IC register.
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//
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//*****************************************************************************
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#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
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// Interrupt Clear
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#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
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// Interrupt Clear
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#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
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// Interrupt Clear
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#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
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// Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCT register.
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//
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//*****************************************************************************
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#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
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#define HIB_RTCT_TRIM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCSS register.
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//
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//*****************************************************************************
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#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
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#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
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#define HIB_RTCSS_RTCSSM_S 16
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#define HIB_RTCSS_RTCSSC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_DATA register.
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//
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//*****************************************************************************
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#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
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#define HIB_DATA_RTD_S 0
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#endif // __HW_HIBERNATE_H__
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