133 lines
7.4 KiB
C
133 lines
7.4 KiB
C
//*****************************************************************************
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//
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// hw_sysexc.h - Macros used when accessing the system exception module.
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//
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// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.1 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_SYSEXC_H__
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#define __HW_SYSEXC_H__
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//*****************************************************************************
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//
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// The following are defines for the System Exception Module register
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// addresses.
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//
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//*****************************************************************************
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#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
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// Status
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#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
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#define SYSEXC_MIS 0x400F9008 // System Exception Masked
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// Interrupt Status
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#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SYSEXC_RIS register.
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//
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//*****************************************************************************
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#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
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// Raw Interrupt Status
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#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
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// Exception Raw Interrupt Status
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#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
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// Exception Raw Interrupt Status
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#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
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// Raw Interrupt Status
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#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
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// Exception Raw Interrupt Status
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#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
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// Exception Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SYSEXC_IM register.
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//
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//*****************************************************************************
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#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
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// Interrupt Mask
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#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
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// Exception Interrupt Mask
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#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
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// Exception Interrupt Mask
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#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
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// Interrupt Mask
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#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
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// Exception Interrupt Mask
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#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
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// Exception Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SYSEXC_MIS register.
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//
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//*****************************************************************************
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#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
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// Masked Interrupt Status
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#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
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// Exception Masked Interrupt
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// Status
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#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
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// Exception Masked Interrupt
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// Status
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#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
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// Masked Interrupt Status
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#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
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// Exception Masked Interrupt
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// Status
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#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
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// Exception Masked Interrupt
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// Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SYSEXC_IC register.
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//
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//*****************************************************************************
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#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
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// Interrupt Clear
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#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
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// Exception Interrupt Clear
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#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
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// Exception Interrupt Clear
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#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
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// Interrupt Clear
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#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
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// Exception Interrupt Clear
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#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
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// Exception Interrupt Clear
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#endif // __HW_SYSEXC_H__
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