445 lines
20 KiB
C
445 lines
20 KiB
C
/************************************************************************************//**
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* \file Source\HCS12\can.c
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* \brief Bootloader CAN communication interface source file.
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* \ingroup Target_HCS12
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You have received a copy of the GNU General Public License along with OpenBLT. It
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* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */
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#if (BOOT_COM_CAN_ENABLE > 0)
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/****************************************************************************************
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* Type definitions
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****************************************************************************************/
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/** \brief Structure type with the layout of a CAN reception message slot. */
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typedef volatile struct
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{
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volatile blt_int8u idr[4]; /**< identifier register 0..3 */
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volatile blt_int8u dsr[8]; /**< data segment register 0..7 */
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volatile blt_int8u dlr; /**< data length register */
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volatile blt_int8u dummy; /**< unused */
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volatile blt_int16u tstamp; /**< timestamp register */
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} tCanRxMsgSlot;
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/** \brief Structure type with the layout of a CAN transmit message slot. */
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typedef volatile struct
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{
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volatile blt_int8u idr[4]; /**< identifier register 0..3 */
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volatile blt_int8u dsr[8]; /**< data segment register 0..7 */
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volatile blt_int8u dlr; /**< data length register */
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volatile blt_int8u tbpr; /**< transmit buffer priority register */
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volatile blt_int16u tstamp; /**< timestamp register */
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} tCanTxMsgSlot;
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/** \brief Structure type with the layout of the CAN related control registers. */
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typedef volatile struct
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{
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volatile blt_int8u cctl0; /**< control register 0 */
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volatile blt_int8u cctl1; /**< control register 1 */
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volatile blt_int8u cbtr0; /**< bus timing register 0 */
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volatile blt_int8u cbtr1; /**< bus timing register 1 */
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volatile blt_int8u crflg; /**< receiver flag register */
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volatile blt_int8u crier; /**< receiver interrupt enable register */
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volatile blt_int8u ctflg; /**< transmitter flag register */
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volatile blt_int8u ctier; /**< transmitter interrupt enable register */
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volatile blt_int8u ctarq; /**< transmitter message abort control */
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volatile blt_int8u ctaak; /**< transmitter message abort control */
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volatile blt_int8u ctbsel; /**< transmit buffer selection */
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volatile blt_int8u cidac; /**< identifier acceptance control register */
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volatile blt_int8u dummy1[2]; /**< reserved (2) */
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volatile blt_int8u crxerr; /**< receive error counter */
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volatile blt_int8u ctxerr; /**< transmit error counter */
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volatile blt_int8u cidar0; /**< identifier acceptance register 0 */
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volatile blt_int8u cidar1; /**< identifier acceptance register 1 */
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volatile blt_int8u cidar2; /**< identifier acceptance register 2 */
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volatile blt_int8u cidar3; /**< identifier acceptance register 3 */
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volatile blt_int8u cidmr0; /**< identifier mask register 0 */
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volatile blt_int8u cidmr1; /**< identifier mask register 1 */
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volatile blt_int8u cidmr2; /**< identifier mask register 2 */
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volatile blt_int8u cidmr3; /**< identifier mask register 3 */
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volatile blt_int8u cidar4; /**< identifier acceptance register 4 */
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volatile blt_int8u cidar5; /**< identifier acceptance register 5 */
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volatile blt_int8u cidar6; /**< identifier acceptance register 6 */
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volatile blt_int8u cidar7; /**< identifier acceptance register 7 */
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volatile blt_int8u cidmr4; /**< identifier mask register 4 */
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volatile blt_int8u cidmr5; /**< identifier mask register 5 */
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volatile blt_int8u cidmr6; /**< identifier mask register 6 */
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volatile blt_int8u cidmr7; /**< identifier mask register 7 */
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volatile tCanRxMsgSlot rxSlot; /**< foreground receive message slot */
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volatile tCanTxMsgSlot txSlot; /**< foreground transmit message slot */
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} tCanRegs;
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/** \brief Structure type with the layout of the CAN bus timing registers. */
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typedef struct
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{
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blt_int8u tseg1; /**< CAN time segment 1 */
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blt_int8u tseg2; /**< CAN time segment 2 */
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} tCanBusTiming;
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/****************************************************************************************
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* Macro definitions
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****************************************************************************************/
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#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
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/** \brief Set CAN base address to CAN0. */
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#define CAN_REGS_BASE_ADDRESS (0x0140)
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#elif (BOOT_COM_CAN_CHANNEL_INDEX == 1)
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/** \brief Set CAN base address to CAN1. */
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#define CAN_REGS_BASE_ADDRESS (0x0180)
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#elif (BOOT_COM_CAN_CHANNEL_INDEX == 2)
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/** \brief Set CAN base address to CAN2. */
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#define CAN_REGS_BASE_ADDRESS (0x01c0)
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#elif (BOOT_COM_CAN_CHANNEL_INDEX == 3)
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/** \brief Set CAN base address to CAN3. */
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#define CAN_REGS_BASE_ADDRESS (0x0200)
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#elif (BOOT_COM_CAN_CHANNEL_INDEX == 4)
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/** \brief Set CAN base address to CAN4. */
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#define CAN_REGS_BASE_ADDRESS (0x0280)
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#endif
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/** \brief Macro for accessing the CAN related control registers. */
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#define CAN ((volatile tCanRegs *)CAN_REGS_BASE_ADDRESS)
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/** \brief Configures a CAN message id for 29-bit (extended). */
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#define EXTIDMASK_BIT (0x80000000)
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/* macros for conveniently converting standard and extended message identifiers to the
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* format specified by the MSCAN message slot.
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*/
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#define CONVERT_STD_ID_TO_REG0(id) ((blt_int8u)(((blt_int16u)id & 0x07f8) >> 3))
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#define CONVERT_STD_ID_TO_REG1(id) ((blt_int8u)(id & 0x07) << 5)
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#define CONVERT_STD_ID_TO_REG2(id) (0)
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#define CONVERT_STD_ID_TO_REG3(id) (0)
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#define CONVERT_EXT_ID_TO_REG0(id) ((blt_int8u)(id >> 21))
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#define CONVERT_EXT_ID_TO_REG1(id) ((((blt_int8u)(id >> 15)) & 0x07) | \
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(((blt_int8u)(id >> 13)) & 0xe0) | (IDE_BIT))
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#define CONVERT_EXT_ID_TO_REG2(id) ((blt_int8u)(((blt_int16u)id & 0x7f80) >> 7))
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#define CONVERT_EXT_ID_TO_REG3(id) ((blt_int8u)(id & 0x7f) << 1)
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/****************************************************************************************
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* Register definitions
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****************************************************************************************/
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/** \brief Initialization mode request bit. */
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#define INITRQ_BIT (0x01)
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/** \brief Initialization mode handshake bit. */
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#define INITAK_BIT (0x01)
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/** \brief CAN controller enable bit. */
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#define CANE_BIT (0x80)
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/** \brief Filter mode bit 0. */
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#define IDAM0_BIT (0x10)
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/** \brief Filter mode bit 1. */
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#define IDAM1_BIT (0x20)
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/** \brief Transmit buffer 0 select bit. */
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#define TX0_BIT (0x01)
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/** \brief Transmit buffer 0 empty bit. */
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#define TXE0_BIT (0x01)
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/** \brief 29-bit extended id bit. */
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#define IDE_BIT (0x08)
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/** \brief Receive buffer full flag bit. */
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#define RXF_BIT (0x01)
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/****************************************************************************************
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* Function prototypes
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****************************************************************************************/
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static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int8u *btr0, blt_int8u *btr1);
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/****************************************************************************************
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* Local constant declarations
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****************************************************************************************/
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/**
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* \brief Array with possible time quanta configurations.
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* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
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* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
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* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2)
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* * 100%. This array contains possible and valid time quanta configurations
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* with a sample point between 68..78%.
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*/
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static const tCanBusTiming canTiming[] =
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{
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/* TQ | TSEG1 | TSEG2 | SP */
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/* ------------------------- */
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{ 5, 2 }, /* 8 | 5 | 2 | 75% */
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{ 6, 2 }, /* 9 | 6 | 2 | 78% */
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{ 6, 3 }, /* 10 | 6 | 3 | 70% */
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{ 7, 3 }, /* 11 | 7 | 3 | 73% */
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{ 8, 3 }, /* 12 | 8 | 3 | 75% */
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{ 9, 3 }, /* 13 | 9 | 3 | 77% */
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{ 9, 4 }, /* 14 | 9 | 4 | 71% */
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{ 10, 4 }, /* 15 | 10 | 4 | 73% */
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{ 11, 4 }, /* 16 | 11 | 4 | 75% */
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{ 12, 4 }, /* 17 | 12 | 4 | 76% */
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{ 12, 5 }, /* 18 | 12 | 5 | 72% */
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{ 13, 5 }, /* 19 | 13 | 5 | 74% */
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{ 14, 5 }, /* 20 | 14 | 5 | 75% */
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{ 15, 5 }, /* 21 | 15 | 5 | 76% */
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{ 15, 6 }, /* 22 | 15 | 6 | 73% */
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{ 16, 6 }, /* 23 | 16 | 6 | 74% */
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{ 16, 7 }, /* 24 | 16 | 7 | 71% */
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{ 16, 8 } /* 25 | 16 | 8 | 68% */
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};
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/************************************************************************************//**
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** \brief Initializes the CAN controller and synchronizes it to the CAN bus.
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** \return none.
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**
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****************************************************************************************/
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void CanInit(void)
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{
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blt_int8u btrRegValues[2];
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blt_bool result;
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blt_int32u accept_code;
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blt_int32u accept_mask;
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/* the current implementation supports CAN0..4. throw an assertion error in case a
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* different CAN channel is configured.
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*/
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ASSERT_CT((BOOT_COM_CAN_CHANNEL_INDEX >= 0) && (BOOT_COM_CAN_CHANNEL_INDEX <= 4));
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/* enter initialization mode. note that this automatically disables CAN interrupts */
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CAN->cctl0 = INITRQ_BIT;
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/* wait for initialization mode entry handshake from the hardware */
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while ((CAN->cctl1 & INITAK_BIT) == 0)
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{
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;
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}
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/* enable the CAN controller, disable wake up and listen modes and set the
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* crystal oscillator as the clock source.
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*/
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CAN->cctl1 = CANE_BIT;
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/* configure baudrate */
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result = CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btrRegValues[0], &btrRegValues[1]);
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ASSERT_RT(result == BLT_TRUE);
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/* configure the baudrate */
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CAN->cbtr0 = btrRegValues[0];
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CAN->cbtr1 = btrRegValues[1];
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/* enable 2 32-bit acceptance filters. both will be configured for the same code and
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* mask. the only difference is that filter 0 will be setup to receive extended 29-bit
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* identifiers and filter 0 to receive standard 11-bit identifiers.
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*/
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CAN->cidac &= ~(IDAM1_BIT | IDAM0_BIT);
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/* set the acceptance filter code and mask to a value that only BOOT_COM_CAN_RX_MSG_ID
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* is received.
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*/
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accept_code = BOOT_COM_CAN_RX_MSG_ID;
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accept_mask = 0;
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/* configure acceptance filter 0 for 29-bit extended identifiers */
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CAN->cidar0 = CONVERT_EXT_ID_TO_REG0(accept_code);
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CAN->cidar1 = CONVERT_EXT_ID_TO_REG1(accept_code);
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CAN->cidar2 = CONVERT_EXT_ID_TO_REG2(accept_code);
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CAN->cidar3 = CONVERT_EXT_ID_TO_REG3(accept_code);
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CAN->cidmr0 = CONVERT_EXT_ID_TO_REG0(accept_mask);
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CAN->cidmr1 = (CONVERT_EXT_ID_TO_REG1(accept_mask) | 0x10) & ~IDE_BIT;
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CAN->cidmr2 = CONVERT_EXT_ID_TO_REG2(accept_mask);
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CAN->cidmr3 = CONVERT_EXT_ID_TO_REG3(accept_mask);
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/* configure acceptance filter 1 for 11-bit standard identifiers */
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CAN->cidar4 = CONVERT_STD_ID_TO_REG0(accept_code);
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CAN->cidar5 = CONVERT_STD_ID_TO_REG1(accept_code);
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CAN->cidar6 = CONVERT_STD_ID_TO_REG2(accept_code);
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CAN->cidar7 = CONVERT_STD_ID_TO_REG3(accept_code);
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CAN->cidmr4 = CONVERT_STD_ID_TO_REG0(accept_mask);
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CAN->cidmr5 = CONVERT_STD_ID_TO_REG1(accept_mask) | (0x04 | 0x02 | 0x01);
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CAN->cidmr6 = CONVERT_STD_ID_TO_REG2(accept_mask);
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CAN->cidmr7 = CONVERT_STD_ID_TO_REG3(accept_mask);
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/* leave initialization mode and synchronize to the CAN bus */
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CAN->cctl0 &= ~INITRQ_BIT;
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/* wait for CAN bus synchronization handshake from the hardware */
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while ((CAN->cctl1 & INITAK_BIT) != 0)
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{
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;
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}
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/* bring transmit buffer 0 in the foreground as this is the only one used by this
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* driver.
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*/
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CAN->ctbsel = TX0_BIT;
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} /*** end of CanInit ***/
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/************************************************************************************//**
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** \brief Transmits a packet formatted for the communication interface.
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** \param data Pointer to byte array with data that it to be transmitted.
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** \param len Number of bytes that are to be transmitted.
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** \return none.
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**
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****************************************************************************************/
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void CanTransmitPacket(blt_int8u *data, blt_int8u len)
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{
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blt_int8u byte_idx;
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blt_int32u txMsgId;
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/* double check that the transmit slot is really available */
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ASSERT_RT((CAN->ctflg & TXE0_BIT) != 0);
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/* is this a message with an 11-bit identifier? */
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if ((BOOT_COM_CAN_TX_MSG_ID & EXTIDMASK_BIT) == 0)
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{
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/* store the identifier */
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txMsgId = BOOT_COM_CAN_TX_MSG_ID;
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txMsgId &= ~EXTIDMASK_BIT;
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CAN->txSlot.idr[0] = CONVERT_STD_ID_TO_REG0(txMsgId);
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CAN->txSlot.idr[1] = CONVERT_STD_ID_TO_REG1(txMsgId);
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CAN->txSlot.idr[2] = CONVERT_STD_ID_TO_REG2(txMsgId);
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CAN->txSlot.idr[3] = CONVERT_STD_ID_TO_REG3(txMsgId);
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}
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else
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{
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/* store the identifier */
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txMsgId = BOOT_COM_CAN_TX_MSG_ID;
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txMsgId &= ~EXTIDMASK_BIT;
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CAN->txSlot.idr[0] = CONVERT_EXT_ID_TO_REG0(txMsgId);
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CAN->txSlot.idr[1] = CONVERT_EXT_ID_TO_REG1(txMsgId);
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CAN->txSlot.idr[2] = CONVERT_EXT_ID_TO_REG2(txMsgId);
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CAN->txSlot.idr[3] = CONVERT_EXT_ID_TO_REG3(txMsgId);
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}
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/* store the data length code */
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CAN->txSlot.dlr = len;
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/* store the message data */
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for (byte_idx=0; byte_idx<len; byte_idx++)
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{
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CAN->txSlot.dsr[byte_idx] = data[byte_idx];
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}
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/* start the transmission by clearing the buffer empty flag. must be done
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* by writing a 1 value.
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*/
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CAN->ctflg = TXE0_BIT;
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/* wait for transmit completion */
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while ((CAN->ctflg & TXE0_BIT) == 0)
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{
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/* keep the watchdog happy */
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CopService();
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}
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} /*** end of CanTransmitPacket ***/
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/************************************************************************************//**
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** \brief Receives a communication interface packet if one is present.
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** \param data Pointer to byte array where the data is to be stored.
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** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise.
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**
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****************************************************************************************/
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blt_bool CanReceivePacket(blt_int8u *data)
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{
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blt_int32u rxMsgId;
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blt_int8u rxMsgLen;
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blt_int8u byte_idx;
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blt_bool result = BLT_FALSE;
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/* check if a new message was received */
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if ((CAN->crflg & RXF_BIT) == RXF_BIT)
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{
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/* check IDE-bit to determine if it is a 11-bit or 29-bit identifier */
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if ((CAN->rxSlot.idr[1] & IDE_BIT) == 0)
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{
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/* 11-bit id */
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rxMsgId = (*(blt_int16u *)(&CAN->rxSlot.idr[0])) >> 5;
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}
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else
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{
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/* 29-bit id */
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rxMsgId = (blt_int32u)(((*(blt_int32u *)(&CAN->rxSlot.idr[0])) & 0x0007ffff) >> 1) |
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(blt_int32u)(((*(blt_int32u *)(&CAN->rxSlot.idr[0])) & 0xffe00000) >> 3);
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rxMsgId |= EXTIDMASK_BIT;
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}
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/* is this the packet identifier? */
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if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID)
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{
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result = BLT_TRUE;
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/* store the dlc */
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rxMsgLen = CAN->rxSlot.dlr & 0xf;
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/* copy message data */
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for (byte_idx=0; byte_idx<rxMsgLen; byte_idx++)
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{
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data[byte_idx] = CAN->rxSlot.dsr[byte_idx];
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}
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}
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/* release the receive object by clearing the rx flag */
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CAN->crflg &= RXF_BIT;
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}
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return result;
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} /*** end of CanReceivePacket ***/
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/************************************************************************************//**
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** \brief Search algorithm to match the desired baudrate to a possible bus timing
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** configuration.
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** \param baud The desired baudrate in kbps. Valid values are 10..1000.
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** \param btr0 Pointer to where the value for register CANxBTR0 will be stored.
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** \param btr1 Pointer to where the value for register CANxBTR1 will be stored.
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** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
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** otherwise.
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**
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****************************************************************************************/
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static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int8u *btr0, blt_int8u *btr1)
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{
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blt_int8u prescaler;
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blt_int8u cnt;
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/* loop through all possible time quanta configurations to find a match */
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for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
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{
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if ((BOOT_CPU_XTAL_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
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{
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/* compute the prescaler that goes with this TQ configuration */
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prescaler = (blt_int8u)(BOOT_CPU_XTAL_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1)));
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/* make sure the prescaler is valid */
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if ((prescaler > 0) && (prescaler <= 64))
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{
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/* store the MSCAN bustiming register values */
|
|
*btr0 = prescaler - 1;
|
|
*btr1 = ((canTiming[cnt].tseg2 - 1) << 4) | (canTiming[cnt].tseg1 - 1);
|
|
/* found a good bus timing configuration */
|
|
return BLT_TRUE;
|
|
}
|
|
}
|
|
/* service the watchdog */
|
|
CopService();
|
|
}
|
|
/* could not find a good bus timing configuration */
|
|
return BLT_FALSE;
|
|
} /*** end of CanGetSpeedConfig ***/
|
|
#endif /* BOOT_COM_CAN_ENABLE > 0 */
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|
|
|
|
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/*********************************** end of can.c **************************************/
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