288 lines
10 KiB
ArmAsm
288 lines
10 KiB
ArmAsm
; ---------------------------------------------------------------------------------------
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; @file: startup_S32K118.s
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; @purpose: IAR Startup File
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; S32K118
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; @version: 1.0
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; @date: 2018-1-22
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; @build: b170107
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; ---------------------------------------------------------------------------------------
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;
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; Copyright 2018 NXP
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; All rights reserved.
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;
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; THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
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; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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; IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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; IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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; THE POSSIBILITY OF SUCH DAMAGE.
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:ROOT(2)
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EXTERN main
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EXTERN SystemInit
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EXTERN init_data_bss
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; Non Maskable Interrupt
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DCD HardFault_Handler ; Cortex-M0 SV Hard Fault Interrupt
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DCD 0
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DCD 0
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DCD 0
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler ; Cortex-M0 SV Call Interrupt
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DCD 0
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DCD 0
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DCD PendSV_Handler ; Cortex-M0 Pend SV Interrupt
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DCD SysTick_Handler ; Cortex-M0 System Tick Interrupt
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DCD DMA0_IRQHandler ; DMA channel 0 transfer complete
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DCD DMA1_IRQHandler ; DMA channel 1 transfer complete
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DCD DMA2_IRQHandler ; DMA channel 2 transfer complete
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DCD DMA3_IRQHandler ; DMA channel 3 transfer complete
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DCD DMA_Error_IRQHandler ; DMA error interrupt channels 0-3
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DCD ERM_fault_IRQHandler ; ERM single and double bit error correction
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DCD RTC_IRQHandler ; RTC alarm interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD LPTMR0_IRQHandler ; LPTIMER interrupt request
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DCD PORT_IRQHandler ; Port A, B, C, D and E pin detect interrupt
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DCD CAN0_ORed_Err_Wakeup_IRQHandler ; OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode
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DCD CAN0_ORed_0_31_MB_IRQHandler ; OR’ed Message buffer (0-15, 16-31)
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DCD FTM0_Ch0_7_IRQHandler ; FTM0 Channel 0 to 7 interrupt
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DCD FTM0_Fault_IRQHandler ; FTM0 Fault interrupt
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DCD FTM0_Ovf_Reload_IRQHandler ; FTM0 Counter overflow and Reload interrupt
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DCD FTM1_Ch0_7_IRQHandler ; FTM1 Channel 0 to 7 interrupt
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DCD FTM1_Fault_IRQHandler ; FTM1 Fault interrupt
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DCD FTM1_Ovf_Reload_IRQHandler ; FTM1 Counter overflow and Reload interrupt
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DCD FTFC_IRQHandler ; FTFC Command complete, Read collision and Double bit fault detect
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DCD PDB0_IRQHandler ; PDB0 interrupt
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DCD LPIT0_IRQHandler ; LPIT interrupt
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DCD SCG_CMU_LVD_LVWSCG_IRQHandler ; PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt
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DCD WDOG_IRQHandler ; WDOG interrupt request out before wdg reset out
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DCD RCM_IRQHandler ; RCM Asynchronous Interrupt
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DCD LPI2C0_Master_Slave_IRQHandler ; LPI2C0 Master Interrupt and Slave Interrupt
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DCD FLEXIO_IRQHandler ; FlexIO Interrupt
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DCD LPSPI0_IRQHandler ; LPSPI0 Interrupt
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DCD LPSPI1_IRQHandler ; LPSPI1 Interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt request.
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DCD CMP0_IRQHandler ; CMP0 interrupt request
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DCD LPUART1_RxTx_IRQHandler ; LPUART1 Transmit / Receive Interrupt
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DCD LPUART0_RxTx_IRQHandler ; LPUART0 Transmit / Receive Interrupt
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__Vectors_End
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SECTION FlashConfig:CODE
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__FlashConfig
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DCD 0xFFFFFFFF ; 8 bytes backdoor comparison key
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DCD 0xFFFFFFFF ;
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DCD 0xFFFFFFFF ; 4 bytes program flash protection bytes
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DCD 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured)
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__FlashConfig_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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CPSID I ; Mask interrupts
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;; Init the rest of the registers
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LDR R1,=0
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LDR R2,=0
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LDR R3,=0
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LDR R4,=0
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LDR R5,=0
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LDR R6,=0
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LDR R7,=0
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MOV R8,R7
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MOV R9,R7
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MOV R10,R7
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MOV R11,R7
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MOV R12,R7
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#ifdef START_FROM_FLASH
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IMPORT __RAM_START, __RAM_END
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;; INIT ECC RAM
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LDR R1, =__RAM_START
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LDR R2, =__RAM_END
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SUBS R2, R2, R1
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SUBS R2, #1
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BLE .LC5
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MOVS R0, #0
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MOVS R3, #4
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.LC4:
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STR R0, [R1]
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ADD R1, R1, R3
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SUBS R2, #4
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BGE .LC4
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.LC5:
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#endif
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;; Initialize the stack pointer
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LDR R0, =sfe(CSTACK)
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MOV R13,R0
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#ifndef __NO_SYSTEM_INIT
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;; Call the CMSIS system init routine
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LDR R0, =SystemInit
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BLX R0
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#endif
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;; Init .data and .bss sections
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LDR R0, =init_data_bss
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BLX R0
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CPSIE I ; Unmask interrupts
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BL main
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JumpToSelf
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B JumpToSelf
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B .
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B .
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B .
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B .
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B .
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PUBWEAK DMA0_IRQHandler
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PUBWEAK DMA1_IRQHandler
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PUBWEAK DMA2_IRQHandler
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PUBWEAK DMA3_IRQHandler
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PUBWEAK DMA_Error_IRQHandler
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PUBWEAK ERM_fault_IRQHandler
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PUBWEAK RTC_IRQHandler
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PUBWEAK RTC_Seconds_IRQHandler
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PUBWEAK LPTMR0_IRQHandler
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PUBWEAK PORT_IRQHandler
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PUBWEAK CAN0_ORed_Err_Wakeup_IRQHandler
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PUBWEAK CAN0_ORed_0_31_MB_IRQHandler
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PUBWEAK FTM0_Ch0_7_IRQHandler
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PUBWEAK FTM0_Fault_IRQHandler
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PUBWEAK FTM0_Ovf_Reload_IRQHandler
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PUBWEAK FTM1_Ch0_7_IRQHandler
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PUBWEAK FTM1_Fault_IRQHandler
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PUBWEAK FTM1_Ovf_Reload_IRQHandler
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PUBWEAK FTFC_IRQHandler
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PUBWEAK PDB0_IRQHandler
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PUBWEAK LPIT0_IRQHandler
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PUBWEAK SCG_CMU_LVD_LVWSCG_IRQHandler
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PUBWEAK WDOG_IRQHandler
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PUBWEAK RCM_IRQHandler
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PUBWEAK LPI2C0_Master_Slave_IRQHandler
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PUBWEAK FLEXIO_IRQHandler
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PUBWEAK LPSPI0_IRQHandler
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PUBWEAK LPSPI1_IRQHandler
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PUBWEAK ADC0_IRQHandler
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PUBWEAK CMP0_IRQHandler
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PUBWEAK LPUART1_RxTx_IRQHandler
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PUBWEAK LPUART0_RxTx_IRQHandler
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PUBWEAK DefaultISR
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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HardFault_Handler
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SVC_Handler
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PendSV_Handler
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SysTick_Handler
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DMA0_IRQHandler
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DMA1_IRQHandler
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DMA2_IRQHandler
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DMA3_IRQHandler
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DMA_Error_IRQHandler
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ERM_fault_IRQHandler
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RTC_IRQHandler
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RTC_Seconds_IRQHandler
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LPTMR0_IRQHandler
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PORT_IRQHandler
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CAN0_ORed_Err_Wakeup_IRQHandler
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CAN0_ORed_0_31_MB_IRQHandler
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FTM0_Ch0_7_IRQHandler
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FTM0_Fault_IRQHandler
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FTM0_Ovf_Reload_IRQHandler
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FTM1_Ch0_7_IRQHandler
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FTM1_Fault_IRQHandler
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FTM1_Ovf_Reload_IRQHandler
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FTFC_IRQHandler
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PDB0_IRQHandler
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LPIT0_IRQHandler
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SCG_CMU_LVD_LVWSCG_IRQHandler
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WDOG_IRQHandler
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RCM_IRQHandler
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LPI2C0_Master_Slave_IRQHandler
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FLEXIO_IRQHandler
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LPSPI0_IRQHandler
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LPSPI1_IRQHandler
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ADC0_IRQHandler
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CMP0_IRQHandler
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LPUART1_RxTx_IRQHandler
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LPUART0_RxTx_IRQHandler
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DefaultISR
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B DefaultISR
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END
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