724 lines
23 KiB
C
724 lines
23 KiB
C
//*****************************************************************************
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//
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// interrupt.c - Driver for the NVIC Interrupt Controller.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup interrupt_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_nvic.h"
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#include "inc/hw_types.h"
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#include "driverlib/cpulib.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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//*****************************************************************************
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//
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// This is a mapping between priority grouping encodings and the number of
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// preemption priority bits.
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//
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//*****************************************************************************
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static const unsigned long g_pulPriority[] =
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{
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NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
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NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
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NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
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};
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//*****************************************************************************
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//
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// This is a mapping between interrupt number and the register that contains
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// the priority encoding for that interrupt.
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//
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//*****************************************************************************
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static const unsigned long g_pulRegs[] =
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{
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0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
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NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
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NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
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};
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//*****************************************************************************
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//
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//! \internal
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//! The default interrupt handler.
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//!
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//! This is the default interrupt handler for all interrupts. It simply loops
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//! forever so that the system state is preserved for observation by a
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//! debugger. Since interrupts should be disabled before unregistering the
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//! corresponding handler, this should never be called.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static void
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IntDefaultHandler(void)
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{
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//
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// Go into an infinite loop.
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//
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while(1)
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{
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}
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}
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//*****************************************************************************
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//
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// The processor vector table.
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//
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// This contains a list of the handlers for the various interrupt sources in
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// the system. The layout of this list is defined by the hardware; assertion
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// of an interrupt causes the processor to start executing directly at the
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// address given in the corresponding location in this list.
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//
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//*****************************************************************************
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#if defined(ewarm)
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static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
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#elif defined(sourcerygxx)
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static __attribute__((section(".cs3.region-head.ram")))
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void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
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#elif defined(ccs)
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#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
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void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
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#else
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static __attribute__((section("vtable")))
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void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
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#endif
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//*****************************************************************************
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//
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//! Enables the processor interrupt.
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//!
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//! Allows the processor to respond to interrupts. This does not affect the
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//! set of interrupts enabled in the interrupt controller; it just gates the
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//! single interrupt from the controller to the processor.
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//!
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//! \note Previously, this function had no return value. As such, it was
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//! possible to include <tt>interrupt.h</tt> and call this function without
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//! having included <tt>hw_types.h</tt>. Now that the return is a
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//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
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//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
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//!
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//! \return Returns \b true if interrupts were disabled when the function was
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//! called or \b false if they were initially enabled.
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//
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//*****************************************************************************
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tBoolean
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IntMasterEnable(void)
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{
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//
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// Enable processor interrupts.
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//
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return(CPUcpsie());
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}
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//*****************************************************************************
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//
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//! Disables the processor interrupt.
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//!
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//! Prevents the processor from receiving interrupts. This does not affect the
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//! set of interrupts enabled in the interrupt controller; it just gates the
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//! single interrupt from the controller to the processor.
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//!
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//! \note Previously, this function had no return value. As such, it was
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//! possible to include <tt>interrupt.h</tt> and call this function without
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//! having included <tt>hw_types.h</tt>. Now that the return is a
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//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
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//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
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//!
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//! \return Returns \b true if interrupts were already disabled when the
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//! function was called or \b false if they were initially enabled.
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//
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//*****************************************************************************
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tBoolean
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IntMasterDisable(void)
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{
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//
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// Disable processor interrupts.
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//
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return(CPUcpsid());
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}
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//*****************************************************************************
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//
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//! Registers a function to be called when an interrupt occurs.
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//!
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//! \param ulInterrupt specifies the interrupt in question.
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//! \param pfnHandler is a pointer to the function to be called.
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//!
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//! This function is used to specify the handler function to be called when the
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//! given interrupt is asserted to the processor. When the interrupt occurs,
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//! if it is enabled (via IntEnable()), the handler function will be called in
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//! interrupt context. Since the handler function can preempt other code, care
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//! must be taken to protect memory or peripherals that are accessed by the
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//! handler and other non-handler code.
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//!
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//! \note The use of this function (directly or indirectly via a peripheral
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//! driver interrupt register function) moves the interrupt vector table from
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//! flash to SRAM. Therefore, care must be taken when linking the application
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//! to ensure that the SRAM vector table is located at the beginning of SRAM;
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//! otherwise NVIC will not look in the correct portion of memory for the
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//! vector table (it requires the vector table be on a 1 kB memory alignment).
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//! Normally, the SRAM vector table is so placed via the use of linker scripts.
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//! See the discussion of compile-time versus run-time interrupt handler
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//! registration in the introduction to this chapter.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
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{
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unsigned long ulIdx, ulValue;
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//
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// Check the arguments.
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//
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ASSERT(ulInterrupt < NUM_INTERRUPTS);
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//
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// Make sure that the RAM vector table is correctly aligned.
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//
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ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
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//
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// See if the RAM vector table has been initialized.
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//
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if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
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{
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//
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// Copy the vector table from the beginning of FLASH to the RAM vector
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// table.
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//
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ulValue = HWREG(NVIC_VTABLE);
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for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
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{
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g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
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ulValue);
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}
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//
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// Point NVIC at the RAM vector table.
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//
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HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
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}
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//
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// Save the interrupt handler.
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//
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g_pfnRAMVectors[ulInterrupt] = pfnHandler;
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}
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//*****************************************************************************
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//
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//! Unregisters the function to be called when an interrupt occurs.
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//!
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//! \param ulInterrupt specifies the interrupt in question.
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//!
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//! This function is used to indicate that no handler should be called when the
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//! given interrupt is asserted to the processor. The interrupt source will be
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//! automatically disabled (via IntDisable()) if necessary.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IntUnregister(unsigned long ulInterrupt)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulInterrupt < NUM_INTERRUPTS);
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//
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// Reset the interrupt handler.
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//
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g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
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}
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//*****************************************************************************
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//
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//! Sets the priority grouping of the interrupt controller.
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//!
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//! \param ulBits specifies the number of bits of preemptable priority.
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//!
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//! This function specifies the split between preemptable priority levels and
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//! subpriority levels in the interrupt priority specification. The range of
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//! the grouping values are dependent upon the hardware implementation; on
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//! the Stellaris family, three bits are available for hardware interrupt
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//! prioritization and therefore priority grouping values of three through
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//! seven have the same effect.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IntPriorityGroupingSet(unsigned long ulBits)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBits < NUM_PRIORITY);
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//
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// Set the priority grouping.
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//
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HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
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}
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//*****************************************************************************
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//
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//! Gets the priority grouping of the interrupt controller.
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//!
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//! This function returns the split between preemptable priority levels and
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//! subpriority levels in the interrupt priority specification.
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//!
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//! \return The number of bits of preemptable priority.
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//
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//*****************************************************************************
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unsigned long
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IntPriorityGroupingGet(void)
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{
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unsigned long ulLoop, ulValue;
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//
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// Read the priority grouping.
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//
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ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
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//
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// Loop through the priority grouping values.
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//
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for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
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{
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//
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// Stop looping if this value matches.
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//
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if(ulValue == g_pulPriority[ulLoop])
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{
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break;
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}
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}
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//
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// Return the number of priority bits.
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//
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return(ulLoop);
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}
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//*****************************************************************************
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//
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//! Sets the priority of an interrupt.
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//!
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//! \param ulInterrupt specifies the interrupt in question.
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//! \param ucPriority specifies the priority of the interrupt.
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//!
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//! This function is used to set the priority of an interrupt. When multiple
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//! interrupts are asserted simultaneously, the ones with the highest priority
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//! are processed before the lower priority interrupts. Smaller numbers
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//! correspond to higher interrupt priorities; priority 0 is the highest
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//! interrupt priority.
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//!
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//! The hardware priority mechanism will only look at the upper N bits of the
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//! priority level (where N is 3 for the Stellaris family), so any
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//! prioritization must be performed in those bits. The remaining bits can be
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//! used to sub-prioritize the interrupt sources, and may be used by the
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//! hardware priority mechanism on a future part. This arrangement allows
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//! priorities to migrate to different NVIC implementations without changing
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//! the gross prioritization of the interrupts.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
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{
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unsigned long ulTemp;
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//
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// Check the arguments.
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//
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ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
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//
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// Set the interrupt priority.
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//
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ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
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ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
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ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
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HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
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}
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//*****************************************************************************
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//
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//! Gets the priority of an interrupt.
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//!
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//! \param ulInterrupt specifies the interrupt in question.
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//!
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//! This function gets the priority of an interrupt. See IntPrioritySet() for
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//! a definition of the priority value.
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//!
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//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
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//! specified.
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//
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//*****************************************************************************
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long
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IntPriorityGet(unsigned long ulInterrupt)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
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//
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// Return the interrupt priority.
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//
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return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
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0xFF);
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}
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//*****************************************************************************
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//
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//! Enables an interrupt.
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//!
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//! \param ulInterrupt specifies the interrupt to be enabled.
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//!
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//! The specified interrupt is enabled in the interrupt controller. Other
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//! enables for the interrupt (such as at the peripheral level) are unaffected
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//! by this function.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IntEnable(unsigned long ulInterrupt)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulInterrupt < NUM_INTERRUPTS);
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//
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// Determine the interrupt to enable.
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//
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if(ulInterrupt == FAULT_MPU)
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{
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//
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// Enable the MemManage interrupt.
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//
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HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
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}
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else if(ulInterrupt == FAULT_BUS)
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{
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//
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// Enable the bus fault interrupt.
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//
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HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
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}
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else if(ulInterrupt == FAULT_USAGE)
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{
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//
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// Enable the usage fault interrupt.
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//
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HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
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}
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else if(ulInterrupt == FAULT_SYSTICK)
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{
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//
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// Enable the System Tick interrupt.
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//
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HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
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}
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else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
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{
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//
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// Enable the general interrupt.
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//
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HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
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}
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else if(ulInterrupt >= 48)
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{
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//
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// Enable the general interrupt.
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//
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HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
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}
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}
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|
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//*****************************************************************************
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//
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//! Disables an interrupt.
|
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//!
|
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//! \param ulInterrupt specifies the interrupt to be disabled.
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//!
|
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//! The specified interrupt is disabled in the interrupt controller. Other
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//! enables for the interrupt (such as at the peripheral level) are unaffected
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//! by this function.
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//!
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//! \return None.
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//
|
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//*****************************************************************************
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void
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IntDisable(unsigned long ulInterrupt)
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{
|
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//
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// Check the arguments.
|
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//
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ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
|
|
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//
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// Determine the interrupt to disable.
|
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//
|
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if(ulInterrupt == FAULT_MPU)
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{
|
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//
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// Disable the MemManage interrupt.
|
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//
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HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
|
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}
|
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else if(ulInterrupt == FAULT_BUS)
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{
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//
|
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// Disable the bus fault interrupt.
|
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//
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HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
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}
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else if(ulInterrupt == FAULT_USAGE)
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{
|
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//
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// Disable the usage fault interrupt.
|
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//
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HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
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}
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else if(ulInterrupt == FAULT_SYSTICK)
|
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{
|
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//
|
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// Disable the System Tick interrupt.
|
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//
|
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HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
|
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}
|
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else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
|
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{
|
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//
|
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// Disable the general interrupt.
|
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//
|
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HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
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}
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else if(ulInterrupt >= 48)
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{
|
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//
|
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// Disable the general interrupt.
|
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//
|
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HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
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}
|
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}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Pends an interrupt.
|
|
//!
|
|
//! \param ulInterrupt specifies the interrupt to be pended.
|
|
//!
|
|
//! The specified interrupt is pended in the interrupt controller. This will
|
|
//! cause the interrupt controller to execute the corresponding interrupt
|
|
//! handler at the next available time, based on the current interrupt state
|
|
//! priorities. For example, if called by a higher priority interrupt handler,
|
|
//! the specified interrupt handler will not be called until after the current
|
|
//! interrupt handler has completed execution. The interrupt must have been
|
|
//! enabled for it to be called.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
IntPendSet(unsigned long ulInterrupt)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
|
|
|
//
|
|
// Determine the interrupt to pend.
|
|
//
|
|
if(ulInterrupt == FAULT_NMI)
|
|
{
|
|
//
|
|
// Pend the NMI interrupt.
|
|
//
|
|
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
|
|
}
|
|
else if(ulInterrupt == FAULT_PENDSV)
|
|
{
|
|
//
|
|
// Pend the PendSV interrupt.
|
|
//
|
|
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
|
|
}
|
|
else if(ulInterrupt == FAULT_SYSTICK)
|
|
{
|
|
//
|
|
// Pend the SysTick interrupt.
|
|
//
|
|
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
|
|
}
|
|
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
|
|
{
|
|
//
|
|
// Pend the general interrupt.
|
|
//
|
|
HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
|
|
}
|
|
else if(ulInterrupt >= 48)
|
|
{
|
|
//
|
|
// Pend the general interrupt.
|
|
//
|
|
HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unpends an interrupt.
|
|
//!
|
|
//! \param ulInterrupt specifies the interrupt to be unpended.
|
|
//!
|
|
//! The specified interrupt is unpended in the interrupt controller. This will
|
|
//! cause any previously generated interrupts that have not been handled yet
|
|
//! (due to higher priority interrupts or the interrupt no having been enabled
|
|
//! yet) to be discarded.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
IntPendClear(unsigned long ulInterrupt)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
|
|
|
//
|
|
// Determine the interrupt to unpend.
|
|
//
|
|
if(ulInterrupt == FAULT_PENDSV)
|
|
{
|
|
//
|
|
// Unpend the PendSV interrupt.
|
|
//
|
|
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
|
|
}
|
|
else if(ulInterrupt == FAULT_SYSTICK)
|
|
{
|
|
//
|
|
// Unpend the SysTick interrupt.
|
|
//
|
|
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
|
|
}
|
|
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
|
|
{
|
|
//
|
|
// Unpend the general interrupt.
|
|
//
|
|
HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
|
|
}
|
|
else if(ulInterrupt >= 48)
|
|
{
|
|
//
|
|
// Unpend the general interrupt.
|
|
//
|
|
HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the priority masking level
|
|
//!
|
|
//! \param ulPriorityMask is the priority level that will be masked.
|
|
//!
|
|
//! This function sets the interrupt priority masking level so that all
|
|
//! interrupts at the specified or lesser priority level is masked. This
|
|
//! can be used to globally disable a set of interrupts with priority below
|
|
//! a predetermined threshold. A value of 0 disables priority
|
|
//! masking.
|
|
//!
|
|
//! Smaller numbers correspond to higher interrupt priorities. So for example
|
|
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
|
|
//! and interrupts with a numerical priority of 4 and greater will be blocked.
|
|
//!
|
|
//! The hardware priority mechanism will only look at the upper N bits of the
|
|
//! priority level (where N is 3 for the Stellaris family), so any
|
|
//! prioritization must be performed in those bits.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
IntPriorityMaskSet(unsigned long ulPriorityMask)
|
|
{
|
|
CPUbasepriSet(ulPriorityMask);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the priority masking level
|
|
//!
|
|
//! This function gets the current setting of the interrupt priority masking
|
|
//! level. The value returned is the priority level such that all interrupts
|
|
//! of that and lesser priority are masked. A value of 0 means that priority
|
|
//! masking is disabled.
|
|
//!
|
|
//! Smaller numbers correspond to higher interrupt priorities. So for example
|
|
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
|
|
//! and interrupts with a numerical priority of 4 and greater will be blocked.
|
|
//!
|
|
//! The hardware priority mechanism will only look at the upper N bits of the
|
|
//! priority level (where N is 3 for the Stellaris family), so any
|
|
//! prioritization must be performed in those bits.
|
|
//!
|
|
//! \return Returns the value of the interrupt priority level mask.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
IntPriorityMaskGet(void)
|
|
{
|
|
return(CPUbasepriGet());
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|