1612 lines
52 KiB
C
1612 lines
52 KiB
C
//*****************************************************************************
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//
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// uart.c - Driver for the UART.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup uart_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "inc/hw_uart.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/uartlib.h"
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//*****************************************************************************
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//
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// The system clock divider defining the maximum baud rate supported by the
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// UART.
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//
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//*****************************************************************************
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#define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \
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(CLASS_IS_FURY && REVISION_IS_A2) || \
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(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
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16 : 8)
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//*****************************************************************************
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//
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//! \internal
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//! Checks a UART base address.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! This function determines if a UART port base address is valid.
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//!
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//! \return Returns \b true if the base address is valid and \b false
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//! otherwise.
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//
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//*****************************************************************************
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#ifdef DEBUG
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static tBoolean
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UARTBaseValid(unsigned long ulBase)
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{
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return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
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(ulBase == UART2_BASE));
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}
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#endif
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//*****************************************************************************
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//
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//! Sets the type of parity.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param ulParity specifies the type of parity to use.
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//!
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//! Sets the type of parity to use for transmitting and expect when receiving.
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//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
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//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
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//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
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//! parity bit; it is always either one or zero based on the mode.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
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{
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
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(ulParity == UART_CONFIG_PAR_EVEN) ||
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(ulParity == UART_CONFIG_PAR_ODD) ||
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(ulParity == UART_CONFIG_PAR_ONE) ||
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(ulParity == UART_CONFIG_PAR_ZERO));
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//
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// Set the parity mode.
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//
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HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
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~(UART_LCRH_SPS | UART_LCRH_EPS |
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UART_LCRH_PEN)) | ulParity);
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}
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//*****************************************************************************
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//
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//! Gets the type of parity currently being used.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! This function gets the type of parity used for transmitting data and
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//! expected when receiving data.
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//!
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//! \return Returns the current parity settings, specified as one of
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//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
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//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
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//
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//*****************************************************************************
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unsigned long
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UARTParityModeGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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//
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// Return the current parity setting.
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//
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return(HWREG(ulBase + UART_O_LCRH) &
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(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
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}
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//*****************************************************************************
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//
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//! Sets the FIFO level at which interrupts are generated.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
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//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
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//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
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//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
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//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
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//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
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//!
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//! This function sets the FIFO level at which transmit and receive interrupts
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//! are generated.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
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unsigned long ulRxLevel)
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{
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
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(ulTxLevel == UART_FIFO_TX2_8) ||
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(ulTxLevel == UART_FIFO_TX4_8) ||
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(ulTxLevel == UART_FIFO_TX6_8) ||
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(ulTxLevel == UART_FIFO_TX7_8));
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ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
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(ulRxLevel == UART_FIFO_RX2_8) ||
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(ulRxLevel == UART_FIFO_RX4_8) ||
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(ulRxLevel == UART_FIFO_RX6_8) ||
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(ulRxLevel == UART_FIFO_RX7_8));
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//
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// Set the FIFO interrupt levels.
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//
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HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
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}
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//*****************************************************************************
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//
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//! Gets the FIFO level at which interrupts are generated.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
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//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
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//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
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//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
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//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
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//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
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//!
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//! This function gets the FIFO level at which transmit and receive interrupts
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//! are generated.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
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unsigned long *pulRxLevel)
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{
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unsigned long ulTemp;
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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//
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// Read the FIFO level register.
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//
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ulTemp = HWREG(ulBase + UART_O_IFLS);
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//
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// Extract the transmit and receive FIFO levels.
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//
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*pulTxLevel = ulTemp & UART_IFLS_TX_M;
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*pulRxLevel = ulTemp & UART_IFLS_RX_M;
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}
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//*****************************************************************************
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//
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//! Sets the configuration of a UART.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param ulUARTClk is the rate of the clock supplied to the UART module.
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//! \param ulBaud is the desired baud rate.
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//! \param ulConfig is the data format for the port (number of data bits,
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//! number of stop bits, and parity).
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//!
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//! This function configures the UART for operation in the specified data
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//! format. The baud rate is provided in the \e ulBaud parameter and the data
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//! format in the \e ulConfig parameter.
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//!
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//! The \e ulConfig parameter is the logical OR of three values: the number of
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//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
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//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
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//! select from eight to five data bits per byte (respectively).
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//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
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//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
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//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
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//! select the parity mode (no parity bit, even parity bit, odd parity bit,
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//! parity bit always one, and parity bit always zero, respectively).
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//!
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//! The peripheral clock will be the same as the processor clock. This will be
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//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
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//! if it is constant and known (to save the code/execution overhead of a call
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//! to SysCtlClockGet()).
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//!
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//! This function replaces the original UARTConfigSet() API and performs the
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//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
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//! API to this API.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
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unsigned long ulBaud, unsigned long ulConfig)
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{
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unsigned long ulDiv;
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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ASSERT(ulBaud != 0);
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ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER));
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//
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// Stop the UART.
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//
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UARTDisable(ulBase);
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//
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// Is the required baud rate greater than the maximum rate supported
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// without the use of high speed mode?
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//
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if((ulBaud * 16) > ulUARTClk)
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{
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//
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// Enable high speed mode.
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//
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HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
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//
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// Half the supplied baud rate to compensate for enabling high speed
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// mode. This allows the following code to be common to both cases.
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//
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ulBaud /= 2;
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}
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else
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{
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//
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// Disable high speed mode.
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//
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HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
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}
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//
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// Compute the fractional baud rate divider.
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//
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ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
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//
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// Set the baud rate.
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//
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HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
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HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
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//
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// Set parity, data length, and number of stop bits.
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//
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HWREG(ulBase + UART_O_LCRH) = ulConfig;
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//
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// Clear the flags register.
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//
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HWREG(ulBase + UART_O_FR) = 0;
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//
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// Start the UART.
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//
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UARTEnable(ulBase);
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}
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//*****************************************************************************
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//
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//! Gets the current configuration of a UART.
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//!
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//! \param ulBase is the base address of the UART port.
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//! \param ulUARTClk is the rate of the clock supplied to the UART module.
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//! \param pulBaud is a pointer to storage for the baud rate.
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//! \param pulConfig is a pointer to storage for the data format.
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//!
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//! The baud rate and data format for the UART is determined, given an
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//! explicitly provided peripheral clock (hence the ExpClk suffix). The
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//! returned baud rate is the actual baud rate; it may not be the exact baud
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//! rate requested or an ``official'' baud rate. The data format returned in
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//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
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//! UARTConfigSetExpClk().
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//!
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//! The peripheral clock will be the same as the processor clock. This will be
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//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
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//! if it is constant and known (to save the code/execution overhead of a call
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//! to SysCtlClockGet()).
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//!
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//! This function replaces the original UARTConfigGet() API and performs the
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//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
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//! API to this API.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
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unsigned long *pulBaud, unsigned long *pulConfig)
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{
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unsigned long ulInt, ulFrac;
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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//
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// Compute the baud rate.
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//
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ulInt = HWREG(ulBase + UART_O_IBRD);
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ulFrac = HWREG(ulBase + UART_O_FBRD);
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*pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
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//
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// See if high speed mode enabled.
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//
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if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
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{
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//
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// High speed mode is enabled so the actual baud rate is actually
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// double what was just calculated.
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//
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*pulBaud *= 2;
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}
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//
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// Get the parity, data length, and number of stop bits.
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//
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*pulConfig = (HWREG(ulBase + UART_O_LCRH) &
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(UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
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UART_LCRH_EPS | UART_LCRH_PEN));
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}
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//*****************************************************************************
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//
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//! Enables transmitting and receiving.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
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//! FIFOs.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT(UARTBaseValid(ulBase));
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//
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// Enable the FIFO.
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//
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HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
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//
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// Enable RX, TX, and the UART.
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//
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HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
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UART_CTL_RXE);
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}
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|
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//*****************************************************************************
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//
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//! Disables transmitting and receiving.
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//!
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//! \param ulBase is the base address of the UART port.
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//!
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//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
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//! transmission of the current character, and flushes the transmit FIFO.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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UARTDisable(unsigned long ulBase)
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{
|
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//
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// Check the arguments.
|
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//
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ASSERT(UARTBaseValid(ulBase));
|
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|
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//
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// Wait for end of TX.
|
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//
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while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
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{
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}
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//
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// Disable the FIFO.
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//
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HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
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|
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//
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// Disable the UART.
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//
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HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
|
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UART_CTL_RXE);
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}
|
|
|
|
//*****************************************************************************
|
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//
|
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//! Enables the transmit and receive FIFOs.
|
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//!
|
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//! \param ulBase is the base address of the UART port.
|
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//!
|
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//! This functions enables the transmit and receive FIFOs in the UART.
|
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//!
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//! \return None.
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//
|
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//*****************************************************************************
|
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void
|
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UARTFIFOEnable(unsigned long ulBase)
|
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{
|
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//
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// Check the arguments.
|
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//
|
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ASSERT(UARTBaseValid(ulBase));
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|
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//
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// Enable the FIFO.
|
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//
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HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
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}
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|
|
//*****************************************************************************
|
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//
|
|
//! Disables the transmit and receive FIFOs.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This functions disables the transmit and receive FIFOs in the UART.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
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UARTFIFODisable(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
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//
|
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// Disable the FIFO.
|
|
//
|
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HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
|
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}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables SIR (IrDA) mode on the specified UART.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param bLowPower indicates if SIR Low Power Mode is to be used.
|
|
//!
|
|
//! Enables the SIREN control bit for IrDA mode on the UART. If the
|
|
//! \e bLowPower flag is set, then SIRLP bit will also be set.
|
|
//!
|
|
//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Enable SIR and SIRLP (if appropriate).
|
|
//
|
|
if(bLowPower)
|
|
{
|
|
HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
|
|
}
|
|
else
|
|
{
|
|
HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables SIR (IrDA) mode on the specified UART.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
|
|
//!
|
|
//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTDisableSIR(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Disable SIR and SIRLP (if appropriate).
|
|
//
|
|
HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables ISO 7816 smart card mode on the specified UART.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
|
|
//! This call also sets 8 bit word length and even parity as required by ISO
|
|
//! 7816.
|
|
//!
|
|
//! \note The availability of ISO 7816 smart card mode varies with the
|
|
//! Stellaris part and UART in use. Please consult the datasheet for the part
|
|
//! you are using to determine whether this support is available.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTSmartCardEnable(unsigned long ulBase)
|
|
{
|
|
unsigned long ulVal;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Set 8 bit word length, even parity, 2 stop bits (even though the STP2
|
|
// bit is ignored when in smartcard mode, this lets the caller read back
|
|
// the actual setting in use).
|
|
//
|
|
ulVal = HWREG(ulBase + UART_O_LCRH);
|
|
ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
|
|
UART_LCRH_WLEN_M);
|
|
ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2;
|
|
HWREG(ulBase + UART_O_LCRH) = ulVal;
|
|
|
|
//
|
|
// Enable SMART mode.
|
|
//
|
|
HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables ISO 7816 smart card mode on the specified UART.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
|
|
//!
|
|
//! \note The availability of ISO 7816 smart card mode varies with the
|
|
//! Stellaris part and UART in use. Please consult the datasheet for the part
|
|
//! you are using to determine whether this support is available.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTSmartCardDisable(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Disable the SMART bit.
|
|
//
|
|
HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the states of the DTR and/or RTS modem control signals.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulControl is a bit-mapped flag indicating which modem control bits
|
|
//! should be set.
|
|
//!
|
|
//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
|
|
//!
|
|
//! The \e ulControl parameter is the logical OR of any of the following:
|
|
//!
|
|
//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
|
|
//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
|
|
//!
|
|
//! \note The availability of hardware modem handshake signals varies with the
|
|
//! Stellaris part and UART in use. Please consult the datasheet for the part
|
|
//! you are using to determine whether this support is available.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
|
|
{
|
|
unsigned long ulTemp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(ulBase == UART1_BASE);
|
|
ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
|
|
|
|
//
|
|
// Set the appropriate modem control output bits.
|
|
//
|
|
ulTemp = HWREG(ulBase + UART_O_CTL);
|
|
ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
|
|
HWREG(ulBase + UART_O_CTL) = ulTemp;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the states of the DTR and/or RTS modem control signals.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulControl is a bit-mapped flag indicating which modem control bits
|
|
//! should be set.
|
|
//!
|
|
//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
|
|
//!
|
|
//! The \e ulControl parameter is the logical OR of any of the following:
|
|
//!
|
|
//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
|
|
//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
|
|
//!
|
|
//! \note The availability of hardware modem handshake signals varies with the
|
|
//! Stellaris part and UART in use. Please consult the datasheet for the part
|
|
//! you are using to determine whether this support is available.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
|
|
{
|
|
unsigned long ulTemp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(ulBase == UART1_BASE);
|
|
ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
|
|
|
|
//
|
|
// Set the appropriate modem control output bits.
|
|
//
|
|
ulTemp = HWREG(ulBase + UART_O_CTL);
|
|
ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
|
|
HWREG(ulBase + UART_O_CTL) = ulTemp;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the states of the DTR and RTS modem control signals.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Returns the current states of each of the two UART modem control signals,
|
|
//! DTR and RTS.
|
|
//!
|
|
//! \note The availability of hardware modem handshake signals varies with the
|
|
//! Stellaris part and UART in use. Please consult the datasheet for the part
|
|
//! you are using to determine whether this support is available.
|
|
//!
|
|
//! \return Returns the states of the handshake output signals. This will be a
|
|
//! logical logical OR combination of values \b UART_OUTPUT_RTS and
|
|
//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
|
|
//! associated signal is asserted.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
UARTModemControlGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(ulBase == UART1_BASE);
|
|
|
|
return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the states of the RI, DCD, DSR and CTS modem status signals.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Returns the current states of each of the four UART modem status signals,
|
|
//! RI, DCD, DSR and CTS.
|
|
//!
|
|
//! \note The availability of hardware modem handshake signals varies with the
|
|
//! Stellaris part and UART in use. Please consult the datasheet for the part
|
|
//! you are using to determine whether this support is available.
|
|
//!
|
|
//! \return Returns the states of the handshake output signals. This will be a
|
|
//! logical logical OR combination of values \b UART_INPUT_RI, \b
|
|
//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
|
|
//! presence of each flag indicates that the associated signal is asserted.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
UARTModemStatusGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(ulBase == UART1_BASE);
|
|
|
|
return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
|
|
UART_INPUT_CTS | UART_INPUT_DSR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the UART hardware flow control mode to be used.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulMode indicates the flow control modes to be used. This is a
|
|
//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
|
|
//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
|
|
//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
|
|
//!
|
|
//! Sets the required hardware flow control modes. If \e ulMode contains
|
|
//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
|
|
//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
|
|
//! the RTS output is controlled by the hardware and is asserted only when
|
|
//! there is space available in the receive FIFO. If no hardware flow control
|
|
//! is required, UART_FLOWCONTROL_NONE should be passed.
|
|
//!
|
|
//! \note The availability of hardware flow control varies with the Stellaris
|
|
//! part and UART in use. Please consult the datasheet for the part you are
|
|
//! using to determine whether this support is available.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
|
|
|
|
//
|
|
// Set the flow control mode as requested.
|
|
//
|
|
HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
|
|
~(UART_FLOWCONTROL_TX |
|
|
UART_FLOWCONTROL_RX)) | ulMode);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Returns the UART hardware flow control mode currently in use.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Returns the current hardware flow control mode.
|
|
//!
|
|
//! \note The availability of hardware flow control varies with the Stellaris
|
|
//! part and UART in use. Please consult the datasheet for the part you are
|
|
//! using to determine whether this support is available.
|
|
//!
|
|
//! \return Returns the current flow control mode in use. This is a
|
|
//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
|
|
//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
|
|
//! flow control is in use. If hardware flow control is disabled, \b
|
|
//! UART_FLOWCONTROL_NONE will be returned.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
UARTFlowControlGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
|
|
UART_FLOWCONTROL_RX));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the operating mode for the UART transmit interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulMode is the operating mode for the transmit interrupt. It may be
|
|
//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
|
|
//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
|
|
//! level.
|
|
//!
|
|
//! This function allows the mode of the UART transmit interrupt to be set. By
|
|
//! default, the transmit interrupt is asserted when the FIFO level falls past
|
|
//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
|
|
//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
|
|
//! transmit interrupt will only be asserted once the transmitter is completely
|
|
//! idle - the transmit FIFO is empty and all bits, including any stop bits,
|
|
//! have cleared the transmitter.
|
|
//!
|
|
//! \note The availability of end-of-transmission mode varies with the
|
|
//! Stellaris part in use. Please consult the datasheet for the part you are
|
|
//! using to determine whether this support is available.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
|
|
(ulMode == UART_TXINT_MODE_FIFO));
|
|
|
|
//
|
|
// Set or clear the EOT bit of the UART control register as appropriate.
|
|
//
|
|
HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
|
|
~(UART_TXINT_MODE_EOT |
|
|
UART_TXINT_MODE_FIFO)) | ulMode);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Returns the current operating mode for the UART transmit interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function returns the current operating mode for the UART transmit
|
|
//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
|
|
//! transmit interrupt is currently set to be asserted once the transmitter is
|
|
//! completely idle - the transmit FIFO is empty and all bits, including any
|
|
//! stop bits, have cleared the transmitter. The return value will be \b
|
|
//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
|
|
//! level of the transmit FIFO.
|
|
//!
|
|
//! \note The availability of end-of-transmission mode varies with the
|
|
//! Stellaris part in use. Please consult the datasheet for the part you are
|
|
//! using to determine whether this support is available.
|
|
//!
|
|
//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
UARTTxIntModeGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Return the current transmit interrupt mode.
|
|
//
|
|
return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
|
|
UART_TXINT_MODE_FIFO));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Determines if there are any characters in the receive FIFO.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function returns a flag indicating whether or not there is data
|
|
//! available in the receive FIFO.
|
|
//!
|
|
//! \return Returns \b true if there is data in the receive FIFO or \b false
|
|
//! if there is no data in the receive FIFO.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
UARTCharsAvail(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Return the availability of characters.
|
|
//
|
|
return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Determines if there is any space in the transmit FIFO.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function returns a flag indicating whether or not there is space
|
|
//! available in the transmit FIFO.
|
|
//!
|
|
//! \return Returns \b true if there is space available in the transmit FIFO
|
|
//! or \b false if there is no space available in the transmit FIFO.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
UARTSpaceAvail(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Return the availability of space.
|
|
//
|
|
return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Receives a character from the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Gets a character from the receive FIFO for the specified port.
|
|
//!
|
|
//! This function replaces the original UARTCharNonBlockingGet() API and
|
|
//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
|
|
//! the original API to this API.
|
|
//!
|
|
//! \return Returns the character read from the specified port, cast as a
|
|
//! \e long. A \b -1 is returned if there are no characters present in the
|
|
//! receive FIFO. The UARTCharsAvail() function should be called before
|
|
//! attempting to call this function.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
UARTCharGetNonBlocking(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// See if there are any characters in the receive FIFO.
|
|
//
|
|
if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
|
|
{
|
|
//
|
|
// Read and return the next character.
|
|
//
|
|
return(HWREG(ulBase + UART_O_DR));
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// There are no characters, so return a failure.
|
|
//
|
|
return(-1);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Waits for a character from the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Gets a character from the receive FIFO for the specified port. If there
|
|
//! are no characters available, this function waits until a character is
|
|
//! received before returning.
|
|
//!
|
|
//! \return Returns the character read from the specified port, cast as a
|
|
//! \e long.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
UARTCharGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Wait until a char is available.
|
|
//
|
|
while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Now get the char.
|
|
//
|
|
return(HWREG(ulBase + UART_O_DR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sends a character to the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ucData is the character to be transmitted.
|
|
//!
|
|
//! Writes the character \e ucData to the transmit FIFO for the specified port.
|
|
//! This function does not block, so if there is no space available, then a
|
|
//! \b false is returned, and the application must retry the function later.
|
|
//!
|
|
//! This function replaces the original UARTCharNonBlockingPut() API and
|
|
//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
|
|
//! the original API to this API.
|
|
//!
|
|
//! \return Returns \b true if the character was successfully placed in the
|
|
//! transmit FIFO or \b false if there was no space available in the transmit
|
|
//! FIFO.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// See if there is space in the transmit FIFO.
|
|
//
|
|
if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
|
|
{
|
|
//
|
|
// Write this character to the transmit FIFO.
|
|
//
|
|
HWREG(ulBase + UART_O_DR) = ucData;
|
|
|
|
//
|
|
// Success.
|
|
//
|
|
return(true);
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// There is no space in the transmit FIFO, so return a failure.
|
|
//
|
|
return(false);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Waits to send a character from the specified port.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ucData is the character to be transmitted.
|
|
//!
|
|
//! Sends the character \e ucData to the transmit FIFO for the specified port.
|
|
//! If there is no space available in the transmit FIFO, this function waits
|
|
//! until there is space available before returning.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTCharPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Wait until space is available.
|
|
//
|
|
while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Send the char.
|
|
//
|
|
HWREG(ulBase + UART_O_DR) = ucData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Causes a BREAK to be sent.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param bBreakState controls the output level.
|
|
//!
|
|
//! Calling this function with \e bBreakState set to \b true asserts a break
|
|
//! condition on the UART. Calling this function with \e bBreakState set to
|
|
//! \b false removes the break condition. For proper transmission of a break
|
|
//! command, the break must be asserted for at least two complete frames.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Set the break condition as requested.
|
|
//
|
|
HWREG(ulBase + UART_O_LCRH) =
|
|
(bBreakState ?
|
|
(HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
|
|
(HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Determines whether the UART transmitter is busy or not.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! Allows the caller to determine whether all transmitted bytes have cleared
|
|
//! the transmitter hardware. If \b false is returned, the transmit FIFO is
|
|
//! empty and all bits of the last transmitted character, including all stop
|
|
//! bits, have left the hardware shift register.
|
|
//!
|
|
//! \return Returns \b true if the UART is transmitting or \b false if all
|
|
//! transmissions are complete.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
UARTBusy(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the argument.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Determine if the UART is busy.
|
|
//
|
|
return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Registers an interrupt handler for a UART interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param pfnHandler is a pointer to the function to be called when the
|
|
//! UART interrupt occurs.
|
|
//!
|
|
//! This function does the actual registering of the interrupt handler. This
|
|
//! will enable the global interrupt in the interrupt controller; specific UART
|
|
//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
|
|
//! handler's responsibility to clear the interrupt source.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
|
|
{
|
|
unsigned long ulInt;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Determine the interrupt number based on the UART port.
|
|
//
|
|
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
|
|
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
|
|
|
|
//
|
|
// Register the interrupt handler.
|
|
//
|
|
IntRegister(ulInt, pfnHandler);
|
|
|
|
//
|
|
// Enable the UART interrupt.
|
|
//
|
|
IntEnable(ulInt);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unregisters an interrupt handler for a UART interrupt.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function does the actual unregistering of the interrupt handler. It
|
|
//! will clear the handler to be called when a UART interrupt occurs. This
|
|
//! will also mask off the interrupt in the interrupt controller so that the
|
|
//! interrupt handler no longer is called.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTIntUnregister(unsigned long ulBase)
|
|
{
|
|
unsigned long ulInt;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Determine the interrupt number based on the UART port.
|
|
//
|
|
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
|
|
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
|
|
|
|
//
|
|
// Disable the interrupt.
|
|
//
|
|
IntDisable(ulInt);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
IntUnregister(ulInt);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual UART interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
|
|
//!
|
|
//! Enables the indicated UART interrupt sources. Only the sources that are
|
|
//! enabled can be reflected to the processor interrupt; disabled sources have
|
|
//! no effect on the processor.
|
|
//!
|
|
//! The \e ulIntFlags parameter is the logical OR of any of the following:
|
|
//!
|
|
//! - \b UART_INT_OE - Overrun Error interrupt
|
|
//! - \b UART_INT_BE - Break Error interrupt
|
|
//! - \b UART_INT_PE - Parity Error interrupt
|
|
//! - \b UART_INT_FE - Framing Error interrupt
|
|
//! - \b UART_INT_RT - Receive Timeout interrupt
|
|
//! - \b UART_INT_TX - Transmit interrupt
|
|
//! - \b UART_INT_RX - Receive interrupt
|
|
//! - \b UART_INT_DSR - DSR interrupt
|
|
//! - \b UART_INT_DCD - DCD interrupt
|
|
//! - \b UART_INT_CTS - CTS interrupt
|
|
//! - \b UART_INT_RI - RI interrupt
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Enable the specified interrupts.
|
|
//
|
|
HWREG(ulBase + UART_O_IM) |= ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual UART interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
|
|
//!
|
|
//! Disables the indicated UART interrupt sources. Only the sources that are
|
|
//! enabled can be reflected to the processor interrupt; disabled sources have
|
|
//! no effect on the processor.
|
|
//!
|
|
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
|
|
//! parameter to UARTIntEnable().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Disable the specified interrupts.
|
|
//
|
|
HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current interrupt status.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param bMasked is \b false if the raw interrupt status is required and
|
|
//! \b true if the masked interrupt status is required.
|
|
//!
|
|
//! This returns the interrupt status for the specified UART. Either the raw
|
|
//! interrupt status or the status of interrupts that are allowed to reflect to
|
|
//! the processor can be returned.
|
|
//!
|
|
//! \return Returns the current interrupt status, enumerated as a bit field of
|
|
//! values described in UARTIntEnable().
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return(HWREG(ulBase + UART_O_MIS));
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(ulBase + UART_O_RIS));
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears UART interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
|
|
//!
|
|
//! The specified UART interrupt sources are cleared, so that they no longer
|
|
//! assert. This function must be called in the interrupt handler to keep the
|
|
//! interrupt from being recognized again immediately upon exit.
|
|
//!
|
|
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
|
|
//! parameter to UARTIntEnable().
|
|
//!
|
|
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
|
|
//! take several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (because the interrupt controller still sees
|
|
//! the interrupt source asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Clear the requested interrupt sources.
|
|
//
|
|
HWREG(ulBase + UART_O_ICR) = ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enable UART DMA operation.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
|
|
//!
|
|
//! The specified UART DMA features are enabled. The UART can be
|
|
//! configured to use DMA for transmit or receive, and to disable
|
|
//! receive if an error occurs. The \e ulDMAFlags parameter is the
|
|
//! logical OR of any of the following values:
|
|
//!
|
|
//! - UART_DMA_RX - enable DMA for receive
|
|
//! - UART_DMA_TX - enable DMA for transmit
|
|
//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
|
|
//!
|
|
//! \note The uDMA controller must also be set up before DMA can be used
|
|
//! with the UART.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Set the requested bits in the UART DMA control register.
|
|
//
|
|
HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disable UART DMA operation.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//! \param ulDMAFlags is a bit mask of the DMA features to disable.
|
|
//!
|
|
//! This function is used to disable UART DMA features that were enabled
|
|
//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
|
|
//! \e ulDMAFlags parameter is the logical OR of any of the following values:
|
|
//!
|
|
//! - UART_DMA_RX - disable DMA for receive
|
|
//! - UART_DMA_TX - disable DMA for transmit
|
|
//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Clear the requested bits in the UART DMA control register.
|
|
//
|
|
HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets current receiver errors.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function returns the current state of each of the 4 receiver error
|
|
//! sources. The returned errors are equivalent to the four error bits
|
|
//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
|
|
//! with the exception that the overrun error is set immediately the overrun
|
|
//! occurs rather than when a character is next read.
|
|
//!
|
|
//! \return Returns a logical OR combination of the receiver error flags,
|
|
//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
|
|
//! and \b UART_RXERROR_OVERRUN.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
UARTRxErrorGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Return the current value of the receive status register.
|
|
//
|
|
return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears all reported receiver errors.
|
|
//!
|
|
//! \param ulBase is the base address of the UART port.
|
|
//!
|
|
//! This function is used to clear all receiver error conditions reported via
|
|
//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
|
|
//! break interrupts, this function must be called after clearing the interrupt
|
|
//! to ensure that later errors of the same type trigger another interrupt.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
UARTRxErrorClear(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(UARTBaseValid(ulBase));
|
|
|
|
//
|
|
// Any write to the Error Clear Register will clear all bits which are
|
|
// currently set.
|
|
//
|
|
HWREG(ulBase + UART_O_ECR) = 0;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
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//! @}
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//
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//*****************************************************************************
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