707 lines
23 KiB
C
707 lines
23 KiB
C
//*****************************************************************************
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//
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// ssi.c - Driver for Synchronous Serial Interface.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup ssi_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_ssi.h"
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#include "inc/hw_types.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/ssi.h"
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//*****************************************************************************
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//
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//! Configures the synchronous serial interface.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
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//! \param ulProtocol specifies the data transfer protocol.
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//! \param ulMode specifies the mode of operation.
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//! \param ulBitRate specifies the clock rate.
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//! \param ulDataWidth specifies number of bits transferred per frame.
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//!
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//! This function configures the synchronous serial interface. It sets
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//! the SSI protocol, mode of operation, bit rate, and data width.
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//!
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//! The \e ulProtocol parameter defines the data frame format. The
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//! \e ulProtocol parameter can be one of the following values:
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//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
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//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
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//! frame formats imply the following polarity and phase configurations:
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//!
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//! <pre>
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//! Polarity Phase Mode
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//! 0 0 SSI_FRF_MOTO_MODE_0
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//! 0 1 SSI_FRF_MOTO_MODE_1
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//! 1 0 SSI_FRF_MOTO_MODE_2
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//! 1 1 SSI_FRF_MOTO_MODE_3
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//! </pre>
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//!
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//! The \e ulMode parameter defines the operating mode of the SSI module. The
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//! SSI module can operate as a master or slave; if a slave, the SSI can be
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//! configured to disable output on its serial output line. The \e ulMode
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//! parameter can be one of the following values: \b SSI_MODE_MASTER,
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//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
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//!
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//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
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//! must satisfy the following clock ratio criteria:
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//!
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//! - FSSI >= 2 * bit rate (master mode)
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//! - FSSI >= 12 * bit rate (slave modes)
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//!
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//! where FSSI is the frequency of the clock supplied to the SSI module.
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//!
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//! The \e ulDataWidth parameter defines the width of the data transfers, and
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//! can be a value between 4 and 16, inclusive.
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//!
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//! The peripheral clock will be the same as the processor clock. This will be
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//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
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//! if it is constant and known (to save the code/execution overhead of a call
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//! to SysCtlClockGet()).
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//!
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//! This function replaces the original SSIConfig() API and performs the same
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//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
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//! this API.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
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unsigned long ulProtocol, unsigned long ulMode,
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unsigned long ulBitRate, unsigned long ulDataWidth)
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{
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unsigned long ulMaxBitRate;
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unsigned long ulRegVal;
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unsigned long ulPreDiv;
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unsigned long ulSCR;
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unsigned long ulSPH_SPO;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
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(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
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(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
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(ulProtocol == SSI_FRF_MOTO_MODE_3) ||
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(ulProtocol == SSI_FRF_TI) ||
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(ulProtocol == SSI_FRF_NMW));
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ASSERT((ulMode == SSI_MODE_MASTER) ||
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(ulMode == SSI_MODE_SLAVE) ||
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(ulMode == SSI_MODE_SLAVE_OD));
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ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
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((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
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ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
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ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
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//
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// Set the mode.
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//
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ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
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ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
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HWREG(ulBase + SSI_O_CR1) = ulRegVal;
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//
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// Set the clock predivider.
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//
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ulMaxBitRate = ulSSIClk / ulBitRate;
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ulPreDiv = 0;
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do
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{
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ulPreDiv += 2;
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ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
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}
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while(ulSCR > 255);
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HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
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//
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// Set protocol and clock rate.
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//
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ulSPH_SPO = (ulProtocol & 3) << 6;
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ulProtocol &= SSI_CR0_FRF_M;
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ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
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HWREG(ulBase + SSI_O_CR0) = ulRegVal;
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}
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//*****************************************************************************
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//
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//! Enables the synchronous serial interface.
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//!
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//! \param ulBase specifies the SSI module base address.
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//!
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//! This function enables operation of the synchronous serial interface. The
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//! synchronous serial interface must be configured before it is enabled.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Read-modify-write the enable bit.
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//
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HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
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}
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//*****************************************************************************
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//
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//! Disables the synchronous serial interface.
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//!
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//! \param ulBase specifies the SSI module base address.
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//!
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//! This function disables operation of the synchronous serial interface.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Read-modify-write the enable bit.
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//
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HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
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}
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//*****************************************************************************
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//
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//! Registers an interrupt handler for the synchronous serial interface.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! synchronous serial interface interrupt occurs.
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//!
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//! This sets the handler to be called when an SSI interrupt
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//! occurs. This will enable the global interrupt in the interrupt controller;
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//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
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//! it is the interrupt handler's responsibility to clear the interrupt source
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//! via SSIIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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unsigned long ulInt;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Determine the interrupt number based on the SSI port.
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//
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ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
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//
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// Register the interrupt handler, returning an error if an error occurs.
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//
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IntRegister(ulInt, pfnHandler);
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//
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// Enable the synchronous serial interface interrupt.
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//
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IntEnable(ulInt);
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}
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//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the synchronous serial interface.
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//!
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//! \param ulBase specifies the SSI module base address.
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//!
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//! This function will clear the handler to be called when a SSI
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//! interrupt occurs. This will also mask off the interrupt in the interrupt
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//! controller so that the interrupt handler no longer is called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIIntUnregister(unsigned long ulBase)
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{
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unsigned long ulInt;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Determine the interrupt number based on the SSI port.
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//
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ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
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//
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// Disable the interrupt.
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//
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IntDisable(ulInt);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(ulInt);
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}
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//*****************************************************************************
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//
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//! Enables individual SSI interrupt sources.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
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//!
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//! Enables the indicated SSI interrupt sources. Only the sources that are
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//! enabled can be reflected to the processor interrupt; disabled sources have
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//! no effect on the processor. The \e ulIntFlags parameter can be any of the
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//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Enable the specified interrupts.
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//
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HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
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}
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//*****************************************************************************
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//
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//! Disables individual SSI interrupt sources.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
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//!
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//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
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//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
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//! values.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Disable the specified interrupts.
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//
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HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
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}
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//*****************************************************************************
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//
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//! Gets the current interrupt status.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param bMasked is \b false if the raw interrupt status is required or
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//! \b true if the masked interrupt status is required.
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//!
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//! This function returns the interrupt status for the SSI module. Either the
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//! raw interrupt status or the status of interrupts that are allowed to
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//! reflect to the processor can be returned.
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//!
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//! \return The current interrupt status, enumerated as a bit field of
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//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
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//
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//*****************************************************************************
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unsigned long
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SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Return either the interrupt status or the raw interrupt status as
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// requested.
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//
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if(bMasked)
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{
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return(HWREG(ulBase + SSI_O_MIS));
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}
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else
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{
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return(HWREG(ulBase + SSI_O_RIS));
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}
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}
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//*****************************************************************************
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//
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//! Clears SSI interrupt sources.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
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//!
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//! The specified SSI interrupt sources are cleared so that they no longer
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//! assert. This function must be called in the interrupt handler to keep the
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//! interrupts from being recognized again immediately upon exit. The
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//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
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//! \b SSI_RXOR values.
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//!
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//! \note Because there is a write buffer in the Cortex-M3 processor, it may
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//! take several clock cycles before the interrupt source is actually cleared.
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//! Therefore, it is recommended that the interrupt source be cleared early in
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//! the interrupt handler (as opposed to the very last action) to avoid
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//! returning from the interrupt handler before the interrupt source is
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//! actually cleared. Failure to do so may result in the interrupt handler
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//! being immediately reentered (because the interrupt controller still sees
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//! the interrupt source asserted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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//
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// Clear the requested interrupt sources.
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//
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HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
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}
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//*****************************************************************************
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//
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//! Puts a data element into the SSI transmit FIFO.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param ulData is the data to be transmitted over the SSI interface.
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//!
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//! This function places the supplied data into the transmit FIFO of the
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//! specified SSI module.
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//!
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//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
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//! where N is the data width as configured by SSIConfigSetExpClk(). For
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//! example, if the interface is configured for 8-bit data width, the upper 24
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//! bits of \e ulData are discarded.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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SSIDataPut(unsigned long ulBase, unsigned long ulData)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
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SSI_CR0_DSS_M))) == 0);
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//
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// Wait until there is space.
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//
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while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
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{
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}
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//
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// Write the data to the SSI.
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//
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HWREG(ulBase + SSI_O_DR) = ulData;
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}
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//*****************************************************************************
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//
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//! Puts a data element into the SSI transmit FIFO.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param ulData is the data to be transmitted over the SSI interface.
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//!
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//! This function places the supplied data into the transmit FIFO of the
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//! specified SSI module. If there is no space in the FIFO, then this function
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//! returns a zero.
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//!
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//! This function replaces the original SSIDataNonBlockingPut() API and
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//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
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//! the original API to this API.
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//!
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//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
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//! where N is the data width as configured by SSIConfigSetExpClk(). For
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//! example, if the interface is configured for 8-bit data width, the upper 24
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//! bits of \e ulData are discarded.
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//!
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//! \return Returns the number of elements written to the SSI transmit FIFO.
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//
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//*****************************************************************************
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long
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SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
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ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
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SSI_CR0_DSS_M))) == 0);
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//
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// Check for space to write.
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//
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if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
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{
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HWREG(ulBase + SSI_O_DR) = ulData;
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return(1);
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}
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else
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{
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return(0);
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}
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}
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//*****************************************************************************
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//
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//! Gets a data element from the SSI receive FIFO.
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//!
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//! \param ulBase specifies the SSI module base address.
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//! \param pulData is a pointer to a storage location for data that was
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//! received over the SSI interface.
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//!
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//! This function gets received data from the receive FIFO of the specified
|
|
//! SSI module and places that data into the location specified by the
|
|
//! \e pulData parameter.
|
|
//!
|
|
//! \note Only the lower N bits of the value written to \e pulData contain
|
|
//! valid data, where N is the data width as configured by
|
|
//! SSIConfigSetExpClk(). For example, if the interface is configured for
|
|
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
|
|
//! contain valid data.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SSIDataGet(unsigned long ulBase, unsigned long *pulData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
|
|
|
|
//
|
|
// Wait until there is data to be read.
|
|
//
|
|
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
|
|
{
|
|
}
|
|
|
|
//
|
|
// Read data from SSI.
|
|
//
|
|
*pulData = HWREG(ulBase + SSI_O_DR);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets a data element from the SSI receive FIFO.
|
|
//!
|
|
//! \param ulBase specifies the SSI module base address.
|
|
//! \param pulData is a pointer to a storage location for data that was
|
|
//! received over the SSI interface.
|
|
//!
|
|
//! This function gets received data from the receive FIFO of the specified SSI
|
|
//! module and places that data into the location specified by the \e ulData
|
|
//! parameter. If there is no data in the FIFO, then this function returns a
|
|
//! zero.
|
|
//!
|
|
//! This function replaces the original SSIDataNonBlockingGet() API and
|
|
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
|
|
//! the original API to this API.
|
|
//!
|
|
//! \note Only the lower N bits of the value written to \e pulData contain
|
|
//! valid data, where N is the data width as configured by
|
|
//! SSIConfigSetExpClk(). For example, if the interface is configured for
|
|
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
|
|
//! contain valid data.
|
|
//!
|
|
//! \return Returns the number of elements read from the SSI receive FIFO.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
|
|
|
|
//
|
|
// Check for data to read.
|
|
//
|
|
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
|
|
{
|
|
*pulData = HWREG(ulBase + SSI_O_DR);
|
|
return(1);
|
|
}
|
|
else
|
|
{
|
|
return(0);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enable SSI DMA operation.
|
|
//!
|
|
//! \param ulBase is the base address of the SSI port.
|
|
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
|
|
//!
|
|
//! The specified SSI DMA features are enabled. The SSI can be
|
|
//! configured to use DMA for transmit and/or receive data transfers.
|
|
//! The \e ulDMAFlags parameter is the logical OR of any of the following
|
|
//! values:
|
|
//!
|
|
//! - SSI_DMA_RX - enable DMA for receive
|
|
//! - SSI_DMA_TX - enable DMA for transmit
|
|
//!
|
|
//! \note The uDMA controller must also be set up before DMA can be used
|
|
//! with the SSI.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
|
|
|
|
//
|
|
// Set the requested bits in the UART DMA control register.
|
|
//
|
|
HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disable SSI DMA operation.
|
|
//!
|
|
//! \param ulBase is the base address of the SSI port.
|
|
//! \param ulDMAFlags is a bit mask of the DMA features to disable.
|
|
//!
|
|
//! This function is used to disable SSI DMA features that were enabled
|
|
//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
|
|
//! \e ulDMAFlags parameter is the logical OR of any of the following values:
|
|
//!
|
|
//! - SSI_DMA_RX - disable DMA for receive
|
|
//! - SSI_DMA_TX - disable DMA for transmit
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
|
|
|
|
//
|
|
// Clear the requested bits in the UART DMA control register.
|
|
//
|
|
HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Determines whether the SSI transmitter is busy or not.
|
|
//!
|
|
//! \param ulBase is the base address of the SSI port.
|
|
//!
|
|
//! Allows the caller to determine whether all transmitted bytes have cleared
|
|
//! the transmitter hardware. If \b false is returned, then the transmit FIFO
|
|
//! is empty and all bits of the last transmitted word have left the hardware
|
|
//! shift register.
|
|
//!
|
|
//! \return Returns \b true if the SSI is transmitting or \b false if all
|
|
//! transmissions are complete.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
SSIBusy(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
|
|
|
|
//
|
|
// Determine if the SSI is busy.
|
|
//
|
|
return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|