358 lines
13 KiB
C
358 lines
13 KiB
C
/**
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******************************************************************************
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* @file system_stm32f30x.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 27-February-2014
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32F30x devices,
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* and is generated by the clock configuration tool
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* stm32f30x_Clock_Configuration_V1.0.0.xls
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f30x.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (8 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
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* function will do nothing and HSI still used as system clock source. User can
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* add some code to deal with this issue inside the SetSysClock() function.
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*
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* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
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* in "stm32f30x.h" file. When HSE is used as system clock source, directly or
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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* Supported STM32F30x device
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*-----------------------------------------------------------------------------
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* System Clock source | PLL(HSI)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 64000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 64000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 2
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 8000000
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*----------------------------------------------------------------------------
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* PLLMUL | 16
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*-----------------------------------------------------------------------------
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* PREDIV | 2
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*-----------------------------------------------------------------------------
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* USB Clock | DISABLE
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 2
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f30x_system
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* @{
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*/
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/** @addtogroup STM32F30x_System_Private_Includes
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* @{
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*/
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#include "stm32f30x.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_Variables
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* @{
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*/
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uint32_t SystemCoreClock = 64000000;
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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/**
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* @}
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*/
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/** @addtogroup STM32F30x_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR &= 0xF87FC00C;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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/* Reset PREDIV1[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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/* Reset USARTSW[1:0], I2CSW and TIMs bits */
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RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings ----------------------------------*/
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SetSysClock();
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
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* 8 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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pllmull = ( pllmull >> 18) + 2;
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if (pllsource == 0x00)
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{
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/* HSI oscillator clock divided by 2 selected as PLL clock entry */
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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}
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else
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{
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prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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/* HSE oscillator clock selected as PREDIV1 clock entry */
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SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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}
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break;
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default: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency ----------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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/* At this stage the HSI is already enabled and used as System clock source */
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/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
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/* Enable Prefetch Buffer and set Flash Latency */
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FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
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/* HCLK = SYSCLK / 1 */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK / 1 */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK / 2 */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
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/* PLL configuration */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16);
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
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{
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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