313 lines
11 KiB
C
313 lines
11 KiB
C
/***************************************************************************//**
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* @file
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* @brief Digital to Analog Converter (DAC) peripheral API for EFM32.
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef __EFM32_DAC_H
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#define __EFM32_DAC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include "efm32.h"
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup DAC
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* @{
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/** Validation of DAC register block pointer reference for assert statements. */
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#define DAC_REF_VALID(ref) ((ref) == DAC0)
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/** @endcond */
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/** Conversion mode. */
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typedef enum
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{
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dacConvModeContinuous = _DAC_CTRL_CONVMODE_CONTINUOUS, /**< Continuous mode. */
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dacConvModeSampleHold = _DAC_CTRL_CONVMODE_SAMPLEHOLD, /**< Sample/hold mode. */
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dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF /**< Sample/shut off mode. */
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} DAC_ConvMode_TypeDef;
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/** Output mode. */
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typedef enum
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{
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dacOutputDisable = _DAC_CTRL_OUTMODE_DISABLE, /**< Output to pin and ADC disabled. */
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dacOutputPin = _DAC_CTRL_OUTMODE_PIN, /**< Output to pin only. */
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dacOutputADC = _DAC_CTRL_OUTMODE_ADC, /**< Output to ADC only */
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dacOutputPinADC = _DAC_CTRL_OUTMODE_PINADC /**< Output to pin and ADC. */
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} DAC_Output_TypeDef;
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/** Peripheral Reflex System signal used to trigger single sample. */
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typedef enum
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{
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dacPRSSELCh0 = _DAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
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dacPRSSELCh1 = _DAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
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dacPRSSELCh2 = _DAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
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dacPRSSELCh3 = _DAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
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dacPRSSELCh4 = _DAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
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dacPRSSELCh5 = _DAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
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dacPRSSELCh6 = _DAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
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dacPRSSELCh7 = _DAC_CH0CTRL_PRSSEL_PRSCH7 /**< PRS channel 7. */
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} DAC_PRSSEL_TypeDef;
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/** Reference voltage for DAC. */
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typedef enum
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{
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dacRef1V25 = _DAC_CTRL_REFSEL_1V25, /**< Internal 1.25V bandgap reference. */
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dacRef2V5 = _DAC_CTRL_REFSEL_2V5, /**< Internal 2.5V bandgap reference. */
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dacRefVDD = _DAC_CTRL_REFSEL_VDD /**< VDD reference. */
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} DAC_Ref_TypeDef;
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/** Refresh interval. */
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typedef enum
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{
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dacRefresh8 = _DAC_CTRL_REFRSEL_8CYCLES, /**< Refresh every 8 prescaled cycles. */
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dacRefresh16 = _DAC_CTRL_REFRSEL_16CYCLES, /**< Refresh every 16 prescaled cycles. */
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dacRefresh32 = _DAC_CTRL_REFRSEL_32CYCLES, /**< Refresh every 32 prescaled cycles. */
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dacRefresh64 = _DAC_CTRL_REFRSEL_64CYCLES /**< Refresh every 64 prescaled cycles. */
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} DAC_Refresh_TypeDef;
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/*******************************************************************************
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******************************* STRUCTS ***********************************
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******************************************************************************/
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/** DAC init structure, common for both channels. */
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typedef struct
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{
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/** Refresh interval. Only used if REFREN bit set for a DAC channel. */
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DAC_Refresh_TypeDef refresh;
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/** Reference voltage to use. */
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DAC_Ref_TypeDef reference;
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/** Output mode */
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DAC_Output_TypeDef outMode;
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/** Conversion mode. */
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DAC_ConvMode_TypeDef convMode;
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/**
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* Prescaler used to get DAC clock. Derived as follows:
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* DACclk=HFPERclk/(2^prescale). The DAC clock should be <= 1MHz.
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*/
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uint8_t prescale;
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/** Enable/disable use of low pass filter on output. */
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bool lpEnable;
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/** Enable/disable reset of prescaler on ch0 start. */
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bool ch0ResetPre;
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/** Enable/disable output enable control by CH1 PRS signal. */
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bool outEnablePRS;
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/** Enable/disable sine mode. */
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bool sineEnable;
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/** Select if single ended or differential mode. */
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bool diff;
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} DAC_Init_TypeDef;
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/** Default config for DAC init structure. */
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#define DAC_INIT_DEFAULT \
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{ dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
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dacRef1V25, /* 1.25V internal reference. */ \
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dacOutputPin, /* Output to pin only. */ \
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dacConvModeContinuous, /* Continuous mode. */ \
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0, /* No prescaling. */ \
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false, /* Do not enable low pass filter. */ \
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false, /* Do not reset prescaler on ch0 start. */ \
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false, /* DAC output enable always on. */ \
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false, /* Disable sine mode. */ \
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false /* Single ended mode. */ \
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}
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/** DAC channel init structure. */
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typedef struct
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{
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/** Enable channel. */
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bool enable;
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/**
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* Peripheral reflex system trigger enable. If false, channel is triggered
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* by writing to CHnDATA.
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*/
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bool prsEnable;
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/**
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* Enable/disable automatic refresh of channel. Refresh interval must be
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* defined in common control init, please see DAC_Init().
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*/
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bool refreshEnable;
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/**
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* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
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* is enabled.
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*/
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DAC_PRSSEL_TypeDef prsSel;
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} DAC_InitChannel_TypeDef;
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/** Default config for DAC channel init structure. */
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#define DAC_INITCHANNEL_DEFAULT \
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{ false, /* Leave channel disabled when init done. */ \
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false, /* Disable PRS triggering. */ \
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false, /* Channel not refreshed automatically. */ \
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dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
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}
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/*******************************************************************************
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***************************** PROTOTYPES **********************************
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******************************************************************************/
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void DAC_Enable(DAC_TypeDef *dac, unsigned int ch, bool enable);
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void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init);
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void DAC_InitChannel(DAC_TypeDef *dac,
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const DAC_InitChannel_TypeDef *init,
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unsigned int ch);
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/***************************************************************************//**
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* @brief
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* Clear one or more pending DAC interrupts.
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*
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* @param[in] dac
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* Pointer to DAC peripheral register block.
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*
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* @param[in] flags
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* Pending DAC interrupt source to clear. Use a bitwise logic OR combination of
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* valid interrupt flags for the DAC module (DAC_IF_nnn).
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******************************************************************************/
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static __INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)
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{
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dac->IFC = flags;
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}
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/***************************************************************************//**
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* @brief
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* Disable one or more DAC interrupts.
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*
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* @param[in] dac
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* Pointer to DAC peripheral register block.
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*
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* @param[in] flags
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* DAC interrupt sources to disable. Use a bitwise logic OR combination of
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* valid interrupt flags for the DAC module (DAC_IF_nnn).
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******************************************************************************/
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static __INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
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{
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dac->IEN &= ~(flags);
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}
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/***************************************************************************//**
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* @brief
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* Enable one or more DAC interrupts.
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*
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* @note
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* Depending on the use, a pending interrupt may already be set prior to
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* enabling the interrupt. Consider using DAC_IntClear() prior to enabling
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* if such a pending interrupt should be ignored.
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*
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* @param[in] dac
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* Pointer to DAC peripheral register block.
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*
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* @param[in] flags
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* DAC interrupt sources to enable. Use a bitwise logic OR combination of
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* valid interrupt flags for the DAC module (DAC_IF_nnn).
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******************************************************************************/
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static __INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)
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{
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dac->IEN |= flags;
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}
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/***************************************************************************//**
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* @brief
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* Get pending DAC interrupt flags.
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*
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* @note
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* The event bits are not cleared by the use of this function.
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*
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* @param[in] dac
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* Pointer to DAC peripheral register block.
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*
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* @return
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* DAC interrupt sources pending. A bitwise logic OR combination of valid
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* interrupt flags for the DAC module (DAC_IF_nnn).
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******************************************************************************/
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static __INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
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{
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return(dac->IF);
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}
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/***************************************************************************//**
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* @brief
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* Set one or more pending DAC interrupts from SW.
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*
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* @param[in] dac
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* Pointer to DAC peripheral register block.
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*
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* @param[in] flags
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* DAC interrupt sources to set to pending. Use a bitwise logic OR combination
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* of valid interrupt flags for the DAC module (DAC_IF_nnn).
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******************************************************************************/
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static __INLINE void DAC_IntSet(DAC_TypeDef *dac, uint32_t flags)
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{
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dac->IFS = flags;
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}
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uint8_t DAC_PrescaleCalc(uint32_t dacFreq, uint32_t hfperFreq);
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void DAC_Reset(DAC_TypeDef *dac);
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/** @} (end addtogroup DAC) */
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/** @} (end addtogroup EFM32_Library) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EFM32_DAC_H */
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