790 lines
26 KiB
C
790 lines
26 KiB
C
/***************************************************************************//**
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* @file
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* @brief Inter-integrated Circuit (I2C) Peripheral API for EFM32.
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#include "efm32.h"
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#include "efm32_i2c.h"
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#include "efm32_cmu.h"
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#include "efm32_bitband.h"
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#include "efm32_assert.h"
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup I2C
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* @brief Inter-integrated Circuit (I2C) Peripheral API for EFM32
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* @{
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******************************************************************************/
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/*******************************************************************************
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******************************* DEFINES ***********************************
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/** Validation of I2C register block pointer reference for assert statements. */
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#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY)
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#define I2C_REF_VALID(ref) ((ref) == I2C0)
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#endif
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#if defined(_EFM32_GIANT_FAMILY)
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#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1))
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#endif
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/** Error flags indicating I2C transfer has failed somehow. */
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/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
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/* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
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/* RXUF is only likely to occur with this SW if using a debugger peeking into */
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/* RXDATA register. Thus, we ignore those types of fault. */
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#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
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/** @endcond */
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/** Master mode transfer states. */
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typedef enum
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{
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i2cStateStartAddrSend, /**< Send start + (first part of) address. */
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i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (first part of) address. */
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i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on second part of 10 bit address. */
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i2cStateRStartAddrSend, /**< Send repeated start + (first part of) address. */
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i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on address sent after repeated start. */
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i2cStateDataSend, /**< Send data. */
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i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */
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i2cStateWFData, /**< Wait for data. */
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i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */
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i2cStateDone /**< Transfer completed successfully. */
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} I2C_TransferState_TypeDef;
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/** @endcond */
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/*******************************************************************************
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******************************* STRUCTS ***********************************
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/** Structure used to store state information on an ongoing master mode transfer. */
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typedef struct
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{
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/** Current state. */
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I2C_TransferState_TypeDef state;
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/** Result return code. */
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I2C_TransferReturn_TypeDef result;
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/** Offset in current sequence buffer. */
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uint16_t offset;
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/* Index to current sequence buffer in use. */
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uint8_t bufIndx;
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/** Reference to I2C transfer sequence definition provided by user. */
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I2C_TransferSeq_TypeDef *seq;
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} I2C_Transfer_TypeDef;
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/** @endcond */
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/*******************************************************************************
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***************************** LOCAL DATA *******^**************************
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/**
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* Lookup table for Nlow + Nhigh setting defined by CLHR. Set undefined
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* index (0x3) to reflect default setting just in case.
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*/
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static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 3, 4 + 4 };
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/** Transfer state info for ongoing master mode transfer */
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static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT];
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/** @endcond */
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/*******************************************************************************
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************************** GLOBAL FUNCTIONS *******************************
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Get current configured I2C bus frequency.
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*
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* @details
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* This frequency is only of relevance when acting as master.
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*
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* @param[in] i2c
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* Pointer to I2C peripheral register block.
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*
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* @return
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* Current I2C frequency in Hz.
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******************************************************************************/
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uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
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{
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uint32_t hfperclk;
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uint32_t n;
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/* Max frequency is given by fSCL = fHFPERCLK/((Nlow + Nhigh)(DIV + 1) + 4) */
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hfperclk = CMU_ClockFreqGet(cmuClock_HFPER);
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n = (uint32_t)(i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]);
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return(hfperclk / ((n * (i2c->CLKDIV + 1)) + 4));
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}
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/***************************************************************************//**
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* @brief
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* Set I2C bus frequency.
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*
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* @details
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* The bus frequency is only of relevance when acting as a master. The bus
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* frequency should not be set higher than the max frequency accepted by the
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* slowest device on the bus.
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*
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* Notice that due to asymmetric requirements on low and high I2C clock
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* cycles by the I2C specification, the actual max frequency allowed in order
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* to comply with the specification may be somewhat lower than expected.
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*
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* Please refer to the reference manual, details on I2C clock generation,
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* for max allowed theoretical frequencies for different modes.
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*
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* @param[in] i2c
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* Pointer to I2C peripheral register block.
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*
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* @param[in] refFreq
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* I2C reference clock frequency in Hz that will be used. If set to 0,
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* the currently configured reference clock is assumed. Setting it to a higher
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* than actual configured value only has the consequence of reducing the real
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* I2C frequency.
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*
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* @param[in] freq
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* Bus frequency to set (actual bus speed may be lower due to integer
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* prescaling). Safe (according to I2C specification) max frequencies for
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* standard, fast and fast+ modes are available using I2C_FREQ_ defines.
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* (Using I2C_FREQ_ defines requires corresponding setting of @p type.)
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* Slowest slave device on bus must always be considered.
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*
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* @param[in] type
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* Clock low to high ratio type to use. If not using i2cClockHLRStandard,
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* make sure all devices on the bus support the specified mode. Using a
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* non-standard ratio is useful to achieve higher bus clock in fast and
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* fast+ modes.
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******************************************************************************/
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void I2C_BusFreqSet(I2C_TypeDef *i2c,
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uint32_t refFreq,
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uint32_t freq,
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I2C_ClockHLR_TypeDef type)
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{
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uint32_t n;
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uint32_t div;
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/* Unused parameter */
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(void)type;
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/* Avoid divide by 0 */
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EFM_ASSERT(freq);
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if (!freq)
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{
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return;
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}
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/* Frequency is given by fSCL = fHFPERCLK/((Nlow + Nhigh)(DIV + 1) + 4), thus */
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/* DIV = ((fHFPERCLK - 4fSCL)/((Nlow + Nhigh)fSCL)) - 1 */
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if (!refFreq)
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{
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refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
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}
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n = (uint32_t)(i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]);
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div = (refFreq - (4 * freq)) / (n * freq);
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EFM_ASSERT(div);
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if (div)
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{
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div--;
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}
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/* Clock divisor must be at least 1 in slave mode according to reference */
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/* manual (in which case there is normally no need to set bus frequency). */
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if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div)
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{
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div = 1;
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}
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EFM_ASSERT(div <= _I2C_CLKDIV_DIV_MASK);
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i2c->CLKDIV = div;
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}
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/***************************************************************************//**
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* @brief
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* Enable/disable I2C.
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*
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* @note
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* After enabling the I2C (from being disabled), the I2C is in BUSY state.
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*
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* @param[in] i2c
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* Pointer to I2C peripheral register block.
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*
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* @param[in] enable
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* true to enable counting, false to disable.
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******************************************************************************/
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void I2C_Enable(I2C_TypeDef *i2c, bool enable)
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{
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EFM_ASSERT(I2C_REF_VALID(i2c));
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BITBAND_Peripheral(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, (unsigned int)enable);
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}
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/***************************************************************************//**
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* @brief
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* Initialize I2C.
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*
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* @param[in] i2c
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* Pointer to I2C peripheral register block.
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*
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* @param[in] init
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* Pointer to I2C initialization structure.
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******************************************************************************/
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void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
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{
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EFM_ASSERT(I2C_REF_VALID(i2c));
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i2c->IEN = 0;
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i2c->IFC = _I2C_IFC_MASK;
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I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr);
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BITBAND_Peripheral(&(i2c->CTRL),
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_I2C_CTRL_SLAVE_SHIFT,
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~((unsigned int)(init->master)));
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BITBAND_Peripheral(&(i2c->CTRL),
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_I2C_CTRL_EN_SHIFT,
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(unsigned int)(init->enable));
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}
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/***************************************************************************//**
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* @brief
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* Reset I2C to same state as after a HW reset.
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*
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* @note
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* The ROUTE register is NOT reset by this function, in order to allow for
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* centralized setup of this feature.
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*
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* @param[in] i2c
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* Pointer to I2C peripheral register block.
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******************************************************************************/
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void I2C_Reset(I2C_TypeDef *i2c)
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{
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i2c->CTRL = _I2C_CTRL_RESETVALUE;
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i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE;
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i2c->SADDR = _I2C_SADDR_RESETVALUE;
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i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE;
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i2c->IEN = _I2C_IEN_RESETVALUE;
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i2c->IFC = _I2C_IFC_MASK;
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/* Do not reset route register, setting should be done independently */
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}
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/***************************************************************************//**
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* @brief
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* Continue an initiated I2C transfer (single master mode only).
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*
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* @details
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* This function is used repeatedly after a I2C_TransferInit() in order to
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* complete a transfer. It may be used in polled mode as the below example
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* shows:
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* @verbatim
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* I2C_TransferReturn_TypeDef ret;
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*
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* // Do a polled transfer
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* ret = I2C_TransferInit(I2C0, seq);
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* while (ret == i2cTransferInProgress)
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* {
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* ret = I2C_Transfer(I2C0);
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* }
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* @endverbatim
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* It may also be used in interrupt driven mode, where this function is invoked
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* from the interrupt handler. Notice that if used in interrupt mode, NVIC
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* interrupts must be configured and enabled for the I2C bus used. I2C
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* peripheral specific interrupts are managed by this SW.
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*
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* @note
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* Only single master mode is supported.
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*
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* @param[in] i2c
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* Pointer to I2C peripheral register block.
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*
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* @return
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* Returns status for ongoing transfer.
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* @li #i2cTransferInProgress - indicates that transfer not finished.
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* @li #i2cTransferDone - transfer completed successfully.
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* @li otherwise some sort of error has occurred.
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*
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******************************************************************************/
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I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
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{
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uint32_t tmp;
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uint32_t pending;
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I2C_Transfer_TypeDef *transfer;
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I2C_TransferSeq_TypeDef *seq;
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EFM_ASSERT(I2C_REF_VALID(i2c));
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/* Support up to 2 I2C buses */
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if (i2c == I2C0)
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{
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transfer = i2cTransfer;
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}
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#if (I2C_COUNT > 1)
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else if (i2c == I2C1)
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{
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transfer = i2cTransfer + 1;
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}
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#endif
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else
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{
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return(i2cTransferUsageFault);
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}
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seq = transfer->seq;
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for (;; )
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{
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pending = i2c->IF;
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/* If some sort of fault, abort transfer. */
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if (pending & I2C_IF_ERRORS)
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{
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if (pending & I2C_IF_ARBLOST)
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{
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/* If arbitration fault, it indicates either a slave device */
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/* not responding as expected, or other master which is not */
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/* supported by this SW. */
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transfer->result = i2cTransferArbLost;
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}
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else if (pending & I2C_IF_BUSERR)
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{
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/* A bus error indicates a misplaced start or stop, which should */
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/* not occur in master mode controlled by this SW. */
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transfer->result = i2cTransferBusErr;
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}
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/* If error situation occurred, it is difficult to know */
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/* exact cause and how to resolve. It will be up to a wrapper */
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/* to determine how to handle a fault/recovery if possible. */
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transfer->state = i2cStateDone;
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goto done;
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}
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switch (transfer->state)
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{
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/***************************************************/
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/* Send first start+address (first byte if 10 bit) */
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/***************************************************/
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case i2cStateStartAddrSend:
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if (seq->flags & I2C_FLAG_10BIT_ADDR)
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{
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tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
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/* In 10 bit address mode, the address following the first */
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/* start always indicate write. */
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}
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else
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{
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tmp = (uint32_t)(seq->addr) & 0xfe;
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if (seq->flags & I2C_FLAG_READ)
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{
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/* Indicate read request */
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tmp |= 1;
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}
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}
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transfer->state = i2cStateAddrWFAckNack;
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i2c->TXDATA = tmp; /* Data not transmitted until START sent */
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i2c->CMD = I2C_CMD_START;
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goto done;
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/*******************************************************/
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/* Wait for ACK/NACK on address (first byte if 10 bit) */
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/*******************************************************/
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case i2cStateAddrWFAckNack:
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if (pending & I2C_IF_NACK)
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{
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i2c->IFC = I2C_IFC_NACK;
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transfer->result = i2cTransferNack;
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transfer->state = i2cStateWFStopSent;
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i2c->CMD = I2C_CMD_STOP;
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}
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else if (pending & I2C_IF_ACK)
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{
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i2c->IFC = I2C_IFC_ACK;
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/* If 10 bit address, send 2nd byte of address. */
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if (seq->flags & I2C_FLAG_10BIT_ADDR)
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{
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transfer->state = i2cStateAddrWF2ndAckNack;
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i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
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}
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else
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{
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/* Determine whether receiving or sending data */
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if (seq->flags & I2C_FLAG_READ)
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{
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transfer->state = i2cStateWFData;
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}
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else
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{
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transfer->state = i2cStateDataSend;
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continue;
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}
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}
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}
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goto done;
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/******************************************************/
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/* Wait for ACK/NACK on second byte of 10 bit address */
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/******************************************************/
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case i2cStateAddrWF2ndAckNack:
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if (pending & I2C_IF_NACK)
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{
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i2c->IFC = I2C_IFC_NACK;
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transfer->result = i2cTransferNack;
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transfer->state = i2cStateWFStopSent;
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i2c->CMD = I2C_CMD_STOP;
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}
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else if (pending & I2C_IF_ACK)
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{
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i2c->IFC = I2C_IFC_ACK;
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/* If using plain read sequence with 10 bit address, switch to send */
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/* repeated start. */
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if (seq->flags & I2C_FLAG_READ)
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{
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transfer->state = i2cStateRStartAddrSend;
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}
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/* Otherwise expected to write 0 or more bytes */
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else
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{
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transfer->state = i2cStateDataSend;
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}
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continue;
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}
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goto done;
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/*******************************/
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/* Send repeated start+address */
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/*******************************/
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case i2cStateRStartAddrSend:
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if (seq->flags & I2C_FLAG_10BIT_ADDR)
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{
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tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
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}
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else
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{
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tmp = seq->addr & 0xfe;
|
|
}
|
|
|
|
/* If this is a write+read combined sequence, then read is about to start */
|
|
if (seq->flags & I2C_FLAG_WRITE_READ)
|
|
{
|
|
/* Indicate read request */
|
|
tmp |= 1;
|
|
}
|
|
|
|
transfer->state = i2cStateRAddrWFAckNack;
|
|
/* We have to write START cmd first since repeated start, otherwise */
|
|
/* data would be sent first. */
|
|
i2c->CMD = I2C_CMD_START;
|
|
i2c->TXDATA = tmp;
|
|
goto done;
|
|
|
|
/**********************************************************************/
|
|
/* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
|
|
/**********************************************************************/
|
|
case i2cStateRAddrWFAckNack:
|
|
if (pending & I2C_IF_NACK)
|
|
{
|
|
i2c->IFC = I2C_IFC_NACK;
|
|
transfer->result = i2cTransferNack;
|
|
transfer->state = i2cStateWFStopSent;
|
|
i2c->CMD = I2C_CMD_STOP;
|
|
}
|
|
else if (pending & I2C_IF_ACK)
|
|
{
|
|
i2c->IFC = I2C_IFC_ACK;
|
|
|
|
/* Determine whether receiving or sending data */
|
|
if (seq->flags & I2C_FLAG_WRITE_READ)
|
|
{
|
|
transfer->state = i2cStateWFData;
|
|
}
|
|
else
|
|
{
|
|
transfer->state = i2cStateDataSend;
|
|
continue;
|
|
}
|
|
}
|
|
goto done;
|
|
|
|
/*****************************/
|
|
/* Send a data byte to slave */
|
|
/*****************************/
|
|
case i2cStateDataSend:
|
|
/* Reached end of data buffer? */
|
|
if (transfer->offset >= seq->buf[transfer->bufIndx].len)
|
|
{
|
|
/* Move to next message part */
|
|
transfer->offset = 0;
|
|
transfer->bufIndx++;
|
|
|
|
/* Send repeated start when switching to read mode on 2nd buffer */
|
|
if (seq->flags & I2C_FLAG_WRITE_READ)
|
|
{
|
|
transfer->state = i2cStateRStartAddrSend;
|
|
continue;
|
|
}
|
|
|
|
/* Only writing from one buffer, or finished both buffers */
|
|
if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1))
|
|
{
|
|
transfer->state = i2cStateWFStopSent;
|
|
i2c->CMD = I2C_CMD_STOP;
|
|
goto done;
|
|
}
|
|
|
|
/* Reprocess in case next buffer is empty */
|
|
continue;
|
|
}
|
|
|
|
/* Send byte */
|
|
i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
|
|
transfer->state = i2cStateDataWFAckNack;
|
|
goto done;
|
|
|
|
/*********************************************************/
|
|
/* Wait for ACK/NACK from slave after sending data to it */
|
|
/*********************************************************/
|
|
case i2cStateDataWFAckNack:
|
|
if (pending & I2C_IF_NACK)
|
|
{
|
|
i2c->IFC = I2C_IFC_NACK;
|
|
transfer->result = i2cTransferNack;
|
|
transfer->state = i2cStateWFStopSent;
|
|
i2c->CMD = I2C_CMD_STOP;
|
|
}
|
|
else if (pending & I2C_IF_ACK)
|
|
{
|
|
i2c->IFC = I2C_IFC_ACK;
|
|
transfer->state = i2cStateDataSend;
|
|
continue;
|
|
}
|
|
goto done;
|
|
|
|
/****************************/
|
|
/* Wait for data from slave */
|
|
/****************************/
|
|
case i2cStateWFData:
|
|
if (pending & I2C_IF_RXDATAV)
|
|
{
|
|
uint8_t data;
|
|
|
|
/* Must read out data in order to not block further progress */
|
|
data = (uint8_t)(i2c->RXDATA);
|
|
|
|
/* Make sure not storing beyond end of buffer just in case */
|
|
if (transfer->offset < seq->buf[transfer->bufIndx].len)
|
|
{
|
|
seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
|
|
}
|
|
|
|
/* If we have read all requested data, then the sequence should end */
|
|
if (transfer->offset >= seq->buf[transfer->bufIndx].len)
|
|
{
|
|
transfer->state = i2cStateWFStopSent;
|
|
i2c->CMD = I2C_CMD_NACK;
|
|
i2c->CMD = I2C_CMD_STOP;
|
|
}
|
|
else
|
|
{
|
|
/* Send ACK and wait for next byte */
|
|
i2c->CMD = I2C_CMD_ACK;
|
|
}
|
|
}
|
|
goto done;
|
|
|
|
/***********************************/
|
|
/* Wait for STOP to have been sent */
|
|
/***********************************/
|
|
case i2cStateWFStopSent:
|
|
if (pending & I2C_IF_MSTOP)
|
|
{
|
|
i2c->IFC = I2C_IFC_MSTOP;
|
|
transfer->state = i2cStateDone;
|
|
}
|
|
goto done;
|
|
|
|
/******************************/
|
|
/* Unexpected state, SW fault */
|
|
/******************************/
|
|
default:
|
|
transfer->result = i2cTransferSwFault;
|
|
transfer->state = i2cStateDone;
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
done:
|
|
|
|
if (transfer->state == i2cStateDone)
|
|
{
|
|
/* Disable interrupt sources when done */
|
|
i2c->IEN = 0;
|
|
|
|
/* Update result unless some fault already occurred */
|
|
if (transfer->result == i2cTransferInProgress)
|
|
{
|
|
transfer->result = i2cTransferDone;
|
|
}
|
|
}
|
|
/* Until transfer is done keep returning i2cTransferInProgress */
|
|
else
|
|
{
|
|
return(i2cTransferInProgress);
|
|
}
|
|
|
|
return transfer->result;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Prepare and start an I2C transfer (single master mode only).
|
|
*
|
|
* @details
|
|
* This function must be invoked in order to start an I2C transfer
|
|
* sequence. In order to actually complete the transfer, I2C_Transfer() must
|
|
* be used either in polled mode or by adding a small driver wrapper utilizing
|
|
* interrupts.
|
|
*
|
|
* @note
|
|
* Only single master mode is supported.
|
|
*
|
|
* @param[in] i2c
|
|
* Pointer to I2C peripheral register block.
|
|
*
|
|
* @param[in] seq
|
|
* Pointer to sequence structure defining the I2C transfer to take place. The
|
|
* referenced structure must exist until the transfer has fully completed.
|
|
*
|
|
* @return
|
|
* Returns status for ongoing transfer:
|
|
* @li #i2cTransferInProgress - indicates that transfer not finished.
|
|
* @li otherwise some sort of error has occurred.
|
|
******************************************************************************/
|
|
I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
|
|
I2C_TransferSeq_TypeDef *seq)
|
|
{
|
|
I2C_Transfer_TypeDef *transfer;
|
|
|
|
EFM_ASSERT(I2C_REF_VALID(i2c));
|
|
EFM_ASSERT(seq);
|
|
|
|
/* Support up to 2 I2C buses */
|
|
if (i2c == I2C0)
|
|
{
|
|
transfer = i2cTransfer;
|
|
}
|
|
#if (I2C_COUNT > 1)
|
|
else if (i2c == I2C1)
|
|
{
|
|
transfer = i2cTransfer + 1;
|
|
}
|
|
#endif
|
|
else
|
|
{
|
|
return(i2cTransferUsageFault);
|
|
}
|
|
|
|
/* Check if in busy state. Since this SW assumes single master, we can */
|
|
/* just issue an abort. The BUSY state is normal after a reset. */
|
|
if (i2c->STATE & I2C_STATE_BUSY)
|
|
{
|
|
i2c->CMD = I2C_CMD_ABORT;
|
|
}
|
|
|
|
/* Make sure user is not trying to read 0 bytes, it is not */
|
|
/* possible according to I2C spec, since slave will always start */
|
|
/* sending first byte ACK on address. The read operation can */
|
|
/* only be stopped by NACKing a received byte, ie minimum 1 byte. */
|
|
if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) ||
|
|
((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
|
|
)
|
|
{
|
|
return(i2cTransferUsageFault);
|
|
}
|
|
|
|
/* Prepare for a transfer */
|
|
transfer->state = i2cStateStartAddrSend;
|
|
transfer->result = i2cTransferInProgress;
|
|
transfer->offset = 0;
|
|
transfer->bufIndx = 0;
|
|
transfer->seq = seq;
|
|
|
|
/* Ensure buffers are empty */
|
|
i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
|
|
if (i2c->IF & I2C_IF_RXDATAV)
|
|
{
|
|
i2c->RXDATA;
|
|
}
|
|
|
|
/* Clear all pending interrupts prior to starting transfer. */
|
|
i2c->IFC = _I2C_IFC_MASK;
|
|
|
|
/* Enable those interrupts we are interested in throughout transfer. */
|
|
/* Notice that the I2C interrupt must also be enabled in the NVIC, but */
|
|
/* that is left for an additional driver wrapper. */
|
|
i2c->IEN = I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP |
|
|
I2C_IF_RXDATAV | I2C_IF_ERRORS;
|
|
|
|
/* Start transfer */
|
|
return(I2C_Transfer(i2c));
|
|
}
|
|
|
|
/** @} (end addtogroup I2C) */
|
|
/** @} (end addtogroup EFM32_Library) */
|