118 lines
4.7 KiB
C
118 lines
4.7 KiB
C
/***************************************************************************//**
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* @file
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* @brief Memory Protection Unit (MPU) Peripheral API for EFM32.
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#include "efm32_mpu.h"
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#include "efm32_assert.h"
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup MPU
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* @brief Memory Protection Unit (MPU) Peripheral API for EFM32
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* @details
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* This module contains functions to enable, disable and setup the MPU.
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* The MPU is used to control access attributes and permissions in the
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* memory map. The settings that can be controlled are:
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*
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* @li Executable attribute.
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* @li Cachable, bufferable and shareable attributes.
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* @li Cache policy.
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* @li Access permissions: Priviliged or User state, read or write access,
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* and combinations of all these.
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*
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* The MPU can be activated and deactivated with functions:
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* @verbatim
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* MPU_Enable(..);
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* MPU_Disable();@endverbatim
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* The MPU can control 8 memory regions with individual access control
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* settings. Section attributes and permissions are set with:
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* @verbatim
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* MPU_ConfigureRegion(..);@endverbatim
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* It is advisable to disable the MPU when altering region settings.
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*
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*
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* @{
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******************************************************************************/
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/*******************************************************************************
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************************** GLOBAL FUNCTIONS *******************************
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Configure an MPU region.
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*
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* @details
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* Writes to MPU RBAR and RASR registers.
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* Refer to Cortex-M3 Reference Manual, MPU chapter for further details.
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* To disable a region it is only required to set init->regionNo to the
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* desired value and init->regionEnable = false.
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*
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* @param[in] init
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* Pointer to a structure containing MPU region init information.
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******************************************************************************/
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void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init)
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{
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EFM_ASSERT(init->regionNo < ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >>
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MPU_TYPE_DREGION_Pos));
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MPU->RNR = init->regionNo;
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if (init->regionEnable)
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{
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EFM_ASSERT(!(init->baseAddress & ~MPU_RBAR_ADDR_Msk));
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EFM_ASSERT(init->tex <= 0x7);
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MPU->RBAR = init->baseAddress;
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MPU->RASR = ((init->disableExec ? 1 : 0) << MPU_RASR_XN_Pos) |
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(init->accessPermission << MPU_RASR_AP_Pos) |
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(init->tex << MPU_RASR_TEX_Pos) |
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((init->shareable ? 1 : 0) << MPU_RASR_S_Pos) |
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((init->cacheable ? 1 : 0) << MPU_RASR_C_Pos) |
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((init->bufferable ? 1 : 0) << MPU_RASR_B_Pos) |
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(init->srd << MPU_RASR_SRD_Pos) |
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(init->size << MPU_RASR_SIZE_Pos) |
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(1 << MPU_RASR_ENA_Pos);
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}
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else
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{
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MPU->RBAR = 0;
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MPU->RASR = 0;
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}
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}
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/** @} (end addtogroup CMU) */
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/** @} (end addtogroup EFM32_Library) */
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