655 lines
22 KiB
C
655 lines
22 KiB
C
/***************************************************************************//**
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* @file
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* @brief Pulse Counter (PCNT) peripheral API for EFM32
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#include "efm32_pcnt.h"
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#include "efm32_cmu.h"
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#include "efm32_assert.h"
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#include "efm32_bitband.h"
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup PCNT
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* @brief Pulse Counter (PCNT) Peripheral API for EFM32
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* @{
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******************************************************************************/
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/*******************************************************************************
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******************************* DEFINES ***********************************
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/** Validation of PCNT register block pointer reference for assert statements. */
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#if (PCNT_COUNT == 1)
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#define PCNT_REF_VALID(ref) ((ref) == PCNT0)
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#elif (PCNT_COUNT == 2)
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#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
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#elif (PCNT_COUNT == 3)
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#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
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((ref) == PCNT2))
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#else
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#error Undefined number of pulse counters (PCNT).
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#endif
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/** @endcond */
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/*******************************************************************************
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************************** LOCAL FUNCTIONS ********************************
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/***************************************************************************//**
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* @brief
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* Map PCNT structure into instance number.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block
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*
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* @return
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* Instance number.
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******************************************************************************/
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static __INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt)
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{
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return(((uint32_t)pcnt - PCNT0_BASE) / 0x400);
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}
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/***************************************************************************//**
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* @brief
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* Wait for ongoing sync of register(s) to low frequency domain to complete.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block
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*
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* @param[in] mask
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* Bitmask corresponding to SYNCBUSY register defined bits, indicating
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* registers that must complete any ongoing synchronization.
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******************************************************************************/
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static __INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask)
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{
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/* Avoid deadlock if modifying the same register twice when freeze mode is
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* activated. */
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if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE)
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{
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return;
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}
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/* Wait for any pending previous write operation to have been completed in low
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* frequency domain. */
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while (pcnt->SYNCBUSY & mask)
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;
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}
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/** @endcond */
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/*******************************************************************************
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************************** GLOBAL FUNCTIONS *******************************
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Reset PCNT counters and TOP register.
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*
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* @note
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* Notice that special SYNCBUSY handling is not applicable for the RSTEN
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* bit of the control register, so we don't need to wait for it when only
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* modifying RSTEN. (It would mean undefined wait time if clocked by external
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* clock.) The SYNCBUSY bit will however be set, leading to a synchronization
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* in the LF domain, with in reality no changes.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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******************************************************************************/
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void PCNT_CounterReset(PCNT_TypeDef *pcnt)
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{
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EFM_ASSERT(PCNT_REF_VALID(pcnt));
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/* Enable reset of CNT and TOP register */
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BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
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/* Disable reset of CNT and TOP register */
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BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
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}
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/***************************************************************************//**
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* @brief
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* Set counter and top values.
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*
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* @details
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* The pulse counter is disabled while changing these values, and reenabled
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* (if originally enabled) when values have been set.
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*
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* @note
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* This function will stall until synchronization to low frequency domain is
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* completed. For that reason, it should normally not be used when using
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* an external clock to clock the PCNT module, since stall time may be
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* undefined in that case. The counter should normally only be set when
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* operating in (or about to enable) #pcntModeOvsSingle mode.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] count
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* Value to set in counter register.
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*
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* @param[in] top
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* Value to set in top register.
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******************************************************************************/
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void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
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{
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uint32_t ctrl;
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EFM_ASSERT(PCNT_REF_VALID(pcnt));
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/* Keep current control setting, must be restored */
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ctrl = pcnt->CTRL;
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/* If enabled, disable pulse counter before changing values */
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if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
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{
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
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pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE;
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}
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/* Load into TOPB */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
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pcnt->TOPB = count;
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/* Load TOPB value into TOP */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
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/* This bit has no effect on rev. C and onwards parts - for compatibility */
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pcnt->CMD = PCNT_CMD_LTOPBIM;
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
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/* Load TOP into CNT */
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pcnt->CMD = PCNT_CMD_LCNTIM;
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/* Restore TOP? ('count' setting has been loaded into pcnt->TOP, better
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* to use 'top' than pcnt->TOP in compare, since latter may in theory not
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* be visible yet.) */
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if (top != count)
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{
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/* Wait for command to sync LCNTIM before setting TOPB */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
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/* Load into TOPB, we don't need to check for TOPB sync complete here,
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* it has been ensured above. */
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pcnt->TOPB = top;
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/* Load TOPB value into TOP */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
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pcnt->CMD = PCNT_CMD_LTOPBIM;
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}
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/* Reenable if it was enabled */
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if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
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{
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD);
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pcnt->CTRL = ctrl;
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}
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}
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/***************************************************************************//**
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* @brief
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* Set PCNT operational mode.
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*
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* @details
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* Notice that this function does not do any configuration. Setting operational
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* mode is normally only required after initialization is done, and if not
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* done as part of initialization. Or if requiring to disable/reenable pulse
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* counter.
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*
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* @note
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* This function may stall until synchronization to low frequency domain is
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* completed. For that reason, it should normally not be used when using
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* an external clock to clock the PCNT module, since stall time may be
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* undefined in that case.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] mode
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* Operational mode to use for PCNT.
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******************************************************************************/
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void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode)
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{
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uint32_t tmp;
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EFM_ASSERT(PCNT_REF_VALID(pcnt));
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/* Set as specified */
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tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK;
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tmp |= (uint32_t)mode << _PCNT_CTRL_MODE_SHIFT;
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/* LF register about to be modified require sync. busy check */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
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pcnt->CTRL = tmp;
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}
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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/***************************************************************************//**
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* @brief
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* Enable/disable the selected PRS input of PCNT.
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*
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* @details
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* Notice that this function does not do any configuration.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] prsInput
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* PRS input (S0 or S1) of the selected PCNT module.
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*
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* @param[in] enable
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* Set to true to enable, false to disable the selected PRS input.
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******************************************************************************/
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void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,
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PCNT_PRSInput_TypeDef prsInput,
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bool enable)
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{
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EFM_ASSERT(PCNT_REF_VALID(pcnt));
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/* Enable/disable the selected PRS input on the selected PCNT module. */
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switch (prsInput)
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{
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/* Enable/disable PRS input S0. */
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case pcntPRSInputS0:
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{
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BITBAND_Peripheral(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, (uint32_t)enable);
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}
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break;
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/* Enable/disable PRS input S1. */
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case pcntPRSInputS1:
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{
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BITBAND_Peripheral(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, (uint32_t)enable);
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}
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break;
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/* Invalid parameter, asserted. */
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default:
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{
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EFM_ASSERT(0);
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}
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break;
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}
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}
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#endif
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/***************************************************************************//**
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* @brief
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* PCNT register synchronization freeze control.
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*
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* @details
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* Some PCNT registers require synchronization into the low frequency (LF)
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* domain. The freeze feature allows for several such registers to be
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* modified before passing them to the LF domain simultaneously (which
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* takes place when the freeze mode is disabled).
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*
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* @note
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* When enabling freeze mode, this function will wait for all current
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* ongoing PCNT synchronization to LF domain to complete (Normally
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* synchronization will not be in progress.) However for this reason, when
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* using freeze mode, modifications of registers requiring LF synchronization
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* should be done within one freeze enable/disable block to avoid unecessary
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* stalling.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] enable
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* @li true - enable freeze, modified registers are not propagated to the
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* LF domain
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* @li false - disables freeze, modified registers are propagated to LF
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* domain
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******************************************************************************/
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void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
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{
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EFM_ASSERT(PCNT_REF_VALID(pcnt));
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if (enable)
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{
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/* Wait for any ongoing LF synchronization to complete. This is just to
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* protect against the rare case when a user:
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* - modifies a register requiring LF sync
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* - then enables freeze before LF sync completed
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* - then modifies the same register again
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* since modifying a register while it is in sync progress should be
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* avoided. */
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while (pcnt->SYNCBUSY)
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;
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pcnt->FREEZE = PCNT_FREEZE_REGFREEZE;
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}
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else
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{
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pcnt->FREEZE = 0;
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}
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}
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/***************************************************************************//**
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* @brief
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* Init pulse counter.
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*
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* @details
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* This function will configure the pulse counter. The clock selection is
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* configured as follows, depending on operational mode:
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*
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* @li #pcntModeOvsSingle - Use LFACLK.
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* @li #pcntModeExtSingle - Use external PCNTn_S0 pin.
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* @li #pcntModeExtQuad - Use external PCNTn_S0 pin.
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*
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* Notice that the LFACLK must be enabled in all modes, since some basic setup
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* is done with this clock even if external pin clock usage mode is chosen.
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* The pulse counter clock for the selected instance must also be enabled
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* prior to init.
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*
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* Notice that pins used by the PCNT module must be properly configured
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* by the user explicitly through setting the ROUTE register, in order for
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* the PCNT to work as intended.
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*
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* Writing to CNT will not occur in external clock modes (EXTCLKQUAD and
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* EXTCLKSINGLE) because the external clock rate is unknown. The user should
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* handle it manually depending on the application
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*
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* TOPB is written for all modes but in external clock mode it will take
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* 3 external clock cycles to sync to TOP
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*
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*
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* @note
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* Initializing requires synchronization into the low frequency domain. This
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* may cause some delay.
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*
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* @param[in] pcnt
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* Pointer to PCNT peripheral register block.
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*
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* @param[in] init
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* Pointer to initialization structure used to initialize.
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******************************************************************************/
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void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
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{
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unsigned int inst;
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uint32_t tmp;
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EFM_ASSERT(PCNT_REF_VALID(pcnt));
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/* Map pointer to instance */
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inst = PCNT_Map(pcnt);
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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/* Selecting the PRS channels for the PRS input sources of the PCNT. These are
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* written with a Read-Modify-Write sequence in order to keep the value of the
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* input enable bits which can be modified using PCNT_PRSInputEnable(). */
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tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK);
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tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) |
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((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
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pcnt->INPUT = tmp;
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#endif
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/* Build CTRL setting, except for mode */
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tmp = 0;
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if (init->negEdge)
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{
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tmp |= PCNT_CTRL_EDGE_NEG;
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}
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if (init->countDown)
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{
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tmp |= PCNT_CTRL_CNTDIR_DOWN;
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}
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if (init->filter)
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{
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tmp |= PCNT_CTRL_FILT;
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}
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#if (defined (_EFM32_TINY_FAMILY) || defined (_EFM32_GIANT_FAMILY))
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if (init->hyst)
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{
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tmp |= PCNT_CTRL_HYST;
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}
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if (init->s1CntDir)
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{
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tmp |= PCNT_CTRL_S1CDIR;
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}
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/* Configure counter events for regular and auxiliary counter. */
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tmp |= init->cntEvent << _PCNT_CTRL_CNTEV_SHIFT;
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tmp |= init->auxCntEvent << _PCNT_CTRL_AUXCNTEV_SHIFT;
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#endif
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/* Reset pulse counter while changing clock source. The reset bit */
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/* is asynchronous, we don't have to check for SYNCBUSY. */
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BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
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/* Select LFACLK to clock in control setting */
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CMU_PCNTClockExternalSet(inst, false);
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/* Handling depends on whether using external clock or not. */
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switch (init->mode)
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{
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case pcntModeExtSingle:
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case pcntModeExtQuad:
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tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
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/* In most cases, the SYNCBUSY bit is set due to reset bit set, and waiting
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* for asynchronous reset bit is strictly not necessary.
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* But in theory, other operations on CTRL register may have been done
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* outside this function, so wait. */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
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/* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing
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* the clock source to an external clock */
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pcnt->CTRL = PCNT_CTRL_RSTEN;
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/* Wait until CTRL write synchronized into LF domain. */
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PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
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/* Change to external clock BEFORE disabling reset */
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CMU_PCNTClockExternalSet(inst, true);
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/* Write to TOPB. If using external clock TOPB will sync to TOP at the same
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* time as the mode. This will insure that if the user chooses to count
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* down, the first "countable" pulse will make CNT go to TOP and not 0xFF
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* (default TOP value). */
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pcnt->TOPB = init->top;
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/* This bit has no effect on rev. C and onwards parts - for compatibility */
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pcnt->CMD = PCNT_CMD_LTOPBIM;
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/* Write the CTRL register with the configurations.
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* This should be written after TOPB in the eventuality of a pulse between
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* these two writes that would cause the CTRL register to be synced one
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* clock cycle earlier than the TOPB. */
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pcnt->CTRL = tmp;
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/* There are no syncs for TOP, CMD or CTRL because the clock rate is unknown
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* and the program could stall
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* These will be synced within 3 clock cycles of the external clock /
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* For the same reason CNT cannot be written here. */
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break;
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/* pcntModeDisable */
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/* pcntModeOvsSingle */
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default:
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/* No need to set disabled mode if already disabled. */
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if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
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{
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/* Set control to disabled mode, leave reset on until ensured disabled.
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* We don't need to wait for CTRL SYNCBUSY completion here, it was
|
|
* triggered by reset bit above, which is asynchronous. */
|
|
pcnt->CTRL = tmp | PCNT_CTRL_MODE_DISABLE | PCNT_CTRL_RSTEN;
|
|
|
|
/* Wait until CTRL write synchronized into LF domain before proceeding
|
|
* to disable reset. */
|
|
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
|
|
}
|
|
|
|
/* Disable reset bit, counter should now be in disabled mode. */
|
|
BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
|
|
|
|
/* Set counter and top values as specified. */
|
|
PCNT_CounterTopSet(pcnt, init->counter, init->top);
|
|
|
|
/* Enter oversampling mode if selected. */
|
|
if (init->mode == pcntModeOvsSingle)
|
|
{
|
|
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
|
|
pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Reset PCNT to same state as after a HW reset.
|
|
*
|
|
* @details
|
|
* Notice the LFACLK must be enabled, since some basic reset is done with
|
|
* this clock. The pulse counter clock for the selected instance must also
|
|
* be enabled prior to init.
|
|
*
|
|
* @note
|
|
* The ROUTE register is NOT reset by this function, in order to allow for
|
|
* centralized setup of this feature.
|
|
*
|
|
* @param[in] pcnt
|
|
* Pointer to PCNT peripheral register block.
|
|
******************************************************************************/
|
|
void PCNT_Reset(PCNT_TypeDef *pcnt)
|
|
{
|
|
unsigned int inst;
|
|
|
|
EFM_ASSERT(PCNT_REF_VALID(pcnt));
|
|
|
|
/* Map pointer to instance and clock info */
|
|
inst = PCNT_Map(pcnt);
|
|
|
|
pcnt->IEN = _PCNT_IEN_RESETVALUE;
|
|
|
|
/* Notice that special SYNCBUSY handling is not applicable for the RSTEN
|
|
* bit of the control register, so we don't need to wait for it when only
|
|
* modifying RSTEN. The SYNCBUSY bit will be set, leading to a
|
|
* synchronization in the LF domain, with in reality no changes to LF domain.
|
|
* Enable reset of CNT and TOP register. */
|
|
BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1);
|
|
|
|
/* Select LFACLK as default */
|
|
CMU_PCNTClockExternalSet(inst, false);
|
|
|
|
PCNT_TopBufferSet(pcnt, _PCNT_TOPB_RESETVALUE);
|
|
|
|
/* Reset CTRL leaving RSTEN set */
|
|
pcnt->CTRL = _PCNT_CTRL_RESETVALUE | PCNT_CTRL_RSTEN;
|
|
|
|
/* Disable reset after CTRL reg has been synchronized */
|
|
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
|
|
BITBAND_Peripheral(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
|
|
|
|
/* Clear pending interrupts */
|
|
pcnt->IFC = _PCNT_IFC_MASK;
|
|
|
|
/* Do not reset route register, setting should be done independently */
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Set top buffer value.
|
|
*
|
|
* @note
|
|
* This function may stall until synchronization to low frequency domain is
|
|
* completed. For that reason, it should normally not be used when using
|
|
* an external clock to clock the PCNT module, since stall time may be
|
|
* undefined in that case.
|
|
*
|
|
* @param[in] pcnt
|
|
* Pointer to PCNT peripheral register block.
|
|
*
|
|
* @param[in] val
|
|
* Value to set in top buffer register.
|
|
******************************************************************************/
|
|
void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
|
|
{
|
|
EFM_ASSERT(PCNT_REF_VALID(pcnt));
|
|
|
|
/* LF register about to be modified require sync. busy check */
|
|
PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
|
|
pcnt->TOPB = val;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Set top value.
|
|
*
|
|
* @note
|
|
* This function will stall until synchronization to low frequency domain is
|
|
* completed. For that reason, it should normally not be used when using
|
|
* an external clock to clock the PCNT module, since stall time may be
|
|
* undefined in that case.
|
|
*
|
|
* @param[in] pcnt
|
|
* Pointer to PCNT peripheral register block.
|
|
*
|
|
* @param[in] val
|
|
* Value to set in top register.
|
|
******************************************************************************/
|
|
void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
|
|
{
|
|
EFM_ASSERT(PCNT_REF_VALID(pcnt));
|
|
|
|
/* LF register about to be modified require sync. busy check */
|
|
|
|
/* Load into TOPB */
|
|
PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
|
|
pcnt->TOPB = val;
|
|
|
|
/* Load TOPB value into TOP */
|
|
PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
|
|
pcnt->CMD = PCNT_CMD_LTOPBIM;
|
|
}
|
|
|
|
|
|
/** @} (end addtogroup PCNT) */
|
|
/** @} (end addtogroup EFM32_Library) */
|