92 lines
3.9 KiB
C
92 lines
3.9 KiB
C
/************************************************************************************//**
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* \file Source/ARM7_LPC2000/GCC/cpu_comp.c
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* \brief Bootloader cpu module source file.
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* \ingroup Target_ARM7_LPC2000
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You have received a copy of the GNU General Public License along with OpenBLT. It
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* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */
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/************************************************************************************//**
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** \brief Obtains current value of CPSR CPU register. Derived from a sample by R O
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** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
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** or commercial purposes.
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** \return CPSR value.
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**
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****************************************************************************************/
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static blt_int32u IrqGetCPSR(void)
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{
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blt_int32u retval;
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asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
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return retval;
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} /*** end of IrqGetCPSR ***/
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/************************************************************************************//**
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** \brief Update value of CPSR CPU register. Derived from a sample by R O
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** Software that is Copyright 2004, R O SoftWare, and can be used for hobby
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** or commercial purposes.
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** \param val CPSR value.
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** \return none.
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**
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****************************************************************************************/
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static void IrqSetCPSR(blt_int32u val)
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{
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asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
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} /*** end of IrqSetCPSR ***/
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/************************************************************************************//**
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** \brief Disable global interrupts.
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** \return none.
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**
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****************************************************************************************/
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void CpuIrqDisable(void)
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{
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blt_int32u _cpsr;
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_cpsr = IrqGetCPSR();
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IrqSetCPSR(_cpsr | 0x00000080);
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} /*** end of CpuIrqDisable ***/
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/************************************************************************************//**
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** \brief Enable global interrupts.
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** \return none.
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**
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****************************************************************************************/
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void CpuIrqEnable(void)
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{
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blt_int32u _cpsr;
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_cpsr = IrqGetCPSR();
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IrqSetCPSR(_cpsr & ~0x00000080);
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} /*** end of CpuIrqEnable ***/
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/*********************************** end of cpu_comp.c *********************************/
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