304 lines
11 KiB
Plaintext
304 lines
11 KiB
Plaintext
/**
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* @file XMC4700x2048.ld
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* @date 2017-04-20
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*
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* @cond
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*********************************************************************************************************************
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* Linker file for the GNU C Compiler v1.3
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* Supported devices: XMC4700-E196x2048
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* XMC4700-F144x2048
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* XMC4700-F100x2048
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-09-03:
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* - Initial version
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*
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* 2016-03-08:
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* - Fix size of BSS and DATA sections to be multiple of 4
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* - Add assertion to check that region SRAM_combined does not overflowed no_init section
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*
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* 2017-04-07:
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* - Added new symbols __text_size and eText
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*
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* 2017-04-20:
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* - Change vtable location to flash area to save ram
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*
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* @endcond
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*
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*/
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OUTPUT_FORMAT("elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(Reset_Handler)
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stack_size = DEFINED(stack_size) ? stack_size : 2048;
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no_init_size = 64;
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MEMORY
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{
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FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x8000
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FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x8000
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PSRAM_1(!RX) : ORIGIN = 0x1FFE8040, LENGTH = 0x17fc0
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DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000
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DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000
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SRAM_combined(!RX) : ORIGIN = 0x1FFE8040, LENGTH = 0x57fc0
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SHARED(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x40
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}
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SECTIONS
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{
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/* Shared data section that also shouldn't get zeroed */
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.shared (NOLOAD) :
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{
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. = ALIGN(4);
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_sshared = .; /* define a global symbol at shared start */
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__shared_start__ = _sshared;
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*(.shared)
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*(.shared.*)
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KEEP(*(.shared))
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. = ALIGN(4);
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_eshared = .; /* define a global symbol at shared end */
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__shared_end__ = _eshared;
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} >SHARED
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/* TEXT section */
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.text :
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{
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sText = .;
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KEEP(*(.reset));
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*(.text .text.* .gnu.linkonce.t.*);
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/* C++ Support */
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r*)
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*(vtable)
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. = ALIGN(4);
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} > FLASH_1_cached AT > FLASH_1_uncached
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.eh_frame_hdr : ALIGN (4)
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{
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KEEP (*(.eh_frame_hdr))
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} > FLASH_1_cached AT > FLASH_1_uncached
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.eh_frame : ALIGN (4)
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{
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KEEP (*(.eh_frame))
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} > FLASH_1_cached AT > FLASH_1_uncached
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/* Exception handling, exidx needs a dedicated section */
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH_1_cached AT > FLASH_1_uncached
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. = ALIGN(4);
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__exidx_start = .;
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.ARM.exidx : ALIGN(4)
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH_1_cached AT > FLASH_1_uncached
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__exidx_end = .;
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. = ALIGN(4);
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/* DSRAM layout (Lowest to highest)*/
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Stack (NOLOAD) :
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{
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__stack_start = .;
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. = . + stack_size;
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__stack_end = .;
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__initial_sp = .;
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} > SRAM_combined
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/* functions with __attribute__((section(".ram_code"))) */
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.ram_code :
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{
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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__ram_code_start = .;
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*(.ram_code)
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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__ram_code_end = .;
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} > SRAM_combined AT > FLASH_1_uncached
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__ram_code_load = LOADADDR (.ram_code);
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__ram_code_size = __ram_code_end - __ram_code_start;
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/* Standard DATA and user defined DATA/BSS/CONST sections */
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.data :
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{
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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__data_start = .;
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* (.data);
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* (.data*);
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*(*.data);
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*(.gnu.linkonce.d*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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__data_end = .;
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} > SRAM_combined AT > FLASH_1_uncached
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__data_load = LOADADDR (.data);
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__data_size = __data_end - __data_start;
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__text_size = (__exidx_end - sText) + __data_size + __ram_code_size;
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eText = sText + __text_size;
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/* BSS section */
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.bss (NOLOAD) :
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{
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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__bss_start = .;
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* (.bss);
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* (.bss*);
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* (COMMON);
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*(.gnu.linkonce.b*)
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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__bss_end = .;
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} > SRAM_combined
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__bss_size = __bss_end - __bss_start;
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/* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */
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__shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end);
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USB_RAM (__bss_end + __shift_loc) (NOLOAD) :
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{
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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USB_RAM_start = .;
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*(USB_RAM)
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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USB_RAM_end = .;
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} > SRAM_combined
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USB_RAM_size = USB_RAM_end - USB_RAM_start;
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ETH_RAM (USB_RAM_end) (NOLOAD) :
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{
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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ETH_RAM_start = .;
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*(ETH_RAM)
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. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
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ETH_RAM_end = .;
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. = ALIGN(8);
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Heap_Bank1_Start = .;
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} > SRAM_combined
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ETH_RAM_size = ETH_RAM_end - ETH_RAM_start;
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/* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/
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.no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) :
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{
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Heap_Bank1_End = .;
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* (.no_init);
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} > SRAM_combined
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/* Heap - Bank1*/
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Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start;
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ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")
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/DISCARD/ :
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{
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*(.comment)
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}
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.stab 0 (NOLOAD) : { *(.stab) }
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.stabstr 0 (NOLOAD) : { *(.stabstr) }
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_pubtypes 0 : { *(.debug_pubtypes) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* DWARF 2.1 */
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.debug_ranges 0 : { *(.debug_ranges) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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/* Build attributes */
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.build_attributes 0 : { *(.ARM.attributes) }
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}
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