205 lines
8.1 KiB
C
205 lines
8.1 KiB
C
/************************************************************************************//**
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* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c
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* \brief Demo program application source file.
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* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You have received a copy of the GNU General Public License along with OpenBLT. It
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* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "header.h" /* generic header */
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/****************************************************************************************
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* Function prototypes
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****************************************************************************************/
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static void Init(void);
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static void SystemClockConfig(void);
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/************************************************************************************//**
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** \brief This is the entry point for the bootloader application and is called
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** by the reset interrupt vector after the C-startup routines executed.
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** \return none.
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**
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****************************************************************************************/
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void main(void)
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{
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/* Initialize the microcontroller. */
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Init();
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/* Initialize the bootloader interface */
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BootComInit();
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/* Start the infinite program loop. */
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while (1)
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{
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/* Toggle LED with a fixed frequency. */
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LedToggle();
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/* Check for bootloader activation request */
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BootComCheckActivationRequest();
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}
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} /*** end of main ***/
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/************************************************************************************//**
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** \brief Initializes the microcontroller.
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** \return none.
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**
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****************************************************************************************/
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static void Init(void)
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{
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/* Configure the system clock. */
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SystemClockConfig();
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/* Enable the peripheral clock for the ports that are used. */
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PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK;
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PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
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PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
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#if (BOOT_COM_RS232_ENABLE > 0)
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/* UART RX GPIO pin configuration. PC6 = UART1 RX, MUX = ALT2. */
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PORTC->PCR[6] |= PORT_PCR_MUX(2);
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/* UART TX GPIO pin configuration. PC7 = UART1 TX, MUX = ALT2. */
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PORTC->PCR[7] |= PORT_PCR_MUX(2);
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#endif
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#if (BOOT_COM_CAN_ENABLE > 0)
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/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
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PORTE->PCR[4] |= PORT_PCR_MUX(5);
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/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
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PORTE->PCR[5] |= PORT_PCR_MUX(5);
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#endif
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/* Initialize the timer driver. */
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TimerInit();
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/* Initialize the led driver. */
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LedInit();
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/* Enable the global interrupts. */
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ENABLE_INTERRUPTS();
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} /*** end of Init ***/
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/************************************************************************************//**
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** \brief System Clock Configuration. This code was derived from a S32 Design Studio
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** example program. It uses the 8 MHz external crystal as a source for the
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** PLL and configures the normal RUN mode for the following clock settings:
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** - SPLL_CLK = 160 MHz
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** - CORE_CLK = 80 MHz
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** - SYS_CLK = 80 MHz
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** - BUS_CLK = 40 MHz
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** - FLASH_CLK = 26.67 MHz
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** - SIRCDIV1_CLK = 8 MHz
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** - SIRCDIV2_CLK = 8 MHz
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** \return none.
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**
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****************************************************************************************/
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static void SystemClockConfig(void)
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{
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/* --------- SOSC Initialization (8 MHz) ------------------------------------------- */
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/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
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SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
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/* Range=2: Medium freq (SOSC betw 1MHz-8MHz).
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* HGO=0: Config xtal osc for low power.
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* EREFS=1: Input is external XTAL.
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*/
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SCG->SOSCCFG = SCG_SOSCCFG_RANGE(2) | SCG_SOSCCFG_EREFS_MASK;
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/* Ensure SOSCCSR unlocked. */
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while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
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{
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;
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}
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/* LK=0: SOSCCSR can be written.
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* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
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* SOSCCM=0: OSC CLK monitor disabled.
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* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
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* SOSCLPEN=0: Sys OSC disabled in VLP modes.
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* SOSCSTEN=0: Sys OSC disabled in Stop modes.
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* SOSCEN=1: Enable oscillator.
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*/
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SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
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/* Wait for system OSC clock to become valid. */
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while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
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{
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;
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}
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/* --------- SPLL Initialization (160 MHz) ----------------------------------------- */
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/* Ensure SPLLCSR is unlocked. */
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while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK)
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{
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;
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}
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/* SPLLEN=0: SPLL is disabled (default). */
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SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK;
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/* SPLLDIV1 divide by 2 and SPLLDIV2 divide by 4. */
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SCG->SPLLDIV |= SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(3);
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/* PREDIV=0: Divide SOSC_CLK by 0+1=1.
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* MULT=24: Multiply sys pll by 4+24=40.
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* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz.
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*/
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SCG->SPLLCFG = SCG_SPLLCFG_MULT(24);
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/* Ensure SPLLCSR is unlocked. */
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while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK)
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{
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;
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}
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/* LK=0: SPLLCSR can be written.
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* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled.
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* SPLLCM=0: SPLL CLK monitor disabled.
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* SPLLSTEN=0: SPLL disabled in Stop modes.
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* SPLLEN=1: Enable SPLL.
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*/
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SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK;
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/* Wait for SPLL to become valid. */
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while (!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK))
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{
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;
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}
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/* --------- SIRC Initialization --------------------------------------------------- */
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/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
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* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
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*/
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SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
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/* --------- Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL ------------------ */
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/* Select PLL as clock source.
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* DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz.
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* DIVBUS=1, div. by 2: bus clock = 40 MHz.
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* DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz.
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*/
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SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_DIVBUS(1) |
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SCG_RCCR_DIVSLOW(2);
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/* Wait until system clock source is SPLL. */
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while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U)
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{
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;
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}
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/* Evaluate the clock register settings and calculates the current core clock. This
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* function must be called when the clock manager component is not used.
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*/
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SystemCoreClockUpdate();
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} /*** end of SystemClockConfig ***/
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/*********************************** end of main.c *************************************/
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