git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@409 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2803 lines
99 KiB
C
2803 lines
99 KiB
C
/**
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******************************************************************************
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* @file stm32f3xx_hal_tim_ex.c
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* @author MCD Application Team
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* @brief TIM HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Timer Extended peripheral:
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* + Time Hall Sensor Interface Initialization
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* + Time Hall Sensor Interface Start
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* + Time Complementary signal bread and dead time configuration
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* + Time Master and Slave synchronization configuration
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* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
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* + Time OCRef clear configuration
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* + Timer remapping capabilities configuration
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@verbatim
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==============================================================================
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##### TIMER Extended features #####
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==============================================================================
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[..]
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The Timer Extended features include:
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(#) Complementary outputs with programmable dead-time for :
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(++) Output Compare
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(++) PWM generation (Edge and Center-aligned Mode)
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(++) One-pulse mode output
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(#) Synchronization circuit to control the timer with external signals and to
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interconnect several timers together.
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(#) Break input to put the timer output signals in reset state or in a known state.
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(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
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positioning purposes
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Initialize the TIM low level resources by implementing the following functions
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depending from feature used :
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(++) Complementary Output Compare : HAL_TIM_OC_MspInit()
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(++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
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(++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
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(++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
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(#) Initialize the TIM low level resources :
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(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
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(##) TIM pins configuration
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(+++) Enable the clock for the TIM GPIOs using the following function:
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__HAL_RCC_GPIOx_CLK_ENABLE();
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(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
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(#) The external Clock can be configured, if needed (the default clock is the
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internal clock from the APBx), using the following function:
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HAL_TIM_ConfigClockSource, the clock configuration should be done before
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any start function.
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(#) Configure the TIM in the desired functioning mode using one of the
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initialization function of this driver:
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(++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
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Timer Hall Sensor Interface and the commutation event with the corresponding
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Interrupt and DMA request if needed (Note that One Timer is used to interface
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with the Hall sensor Interface and another Timer should be used to use
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the commutation event).
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(#) Activate the TIM peripheral using one of the start functions:
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(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
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(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
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(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
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(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f3xx_hal.h"
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/** @addtogroup STM32F3xx_HAL_Driver
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* @{
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*/
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/** @defgroup TIMEx TIMEx
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* @brief TIM Extended HAL module driver
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* @{
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*/
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#ifdef HAL_TIM_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
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defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
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defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
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defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
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#define BDTR_BKF_SHIFT (16U)
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#define BDTR_BK2F_SHIFT (20U)
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#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
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/* STM32F302xC || STM32F303xC || STM32F358xx || */
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/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
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/* STM32F301x8 || STM32F302x8 || STM32F318xx */
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
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* @{
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*/
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static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
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#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
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defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
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defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
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defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
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static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
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TIM_OC_InitTypeDef *OC_Config);
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static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
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TIM_OC_InitTypeDef *OC_Config);
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#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
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/* STM32F302xC || STM32F303xC || STM32F358xx || */
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/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
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/* STM32F301x8 || STM32F302x8 || STM32F318xx */
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/**
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* @}
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*/
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/* Exported functions ---------------------------------------------------------*/
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/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
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* @{
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*/
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/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
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* @brief Timer Hall Sensor functions
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*
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@verbatim
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==============================================================================
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##### Timer Hall Sensor functions #####
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==============================================================================
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[..]
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This section provides functions allowing to:
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(+) Initialize and configure TIM HAL Sensor.
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(+) De-initialize TIM HAL Sensor.
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(+) Start the Hall Sensor Interface.
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(+) Stop the Hall Sensor Interface.
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(+) Start the Hall Sensor Interface and enable interrupts.
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(+) Stop the Hall Sensor Interface and disable interrupts.
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(+) Start the Hall Sensor Interface and enable DMA transfers.
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(+) Stop the Hall Sensor Interface and disable DMA transfers.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
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* @param htim TIM Encoder Interface handle
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* @param sConfig TIM Hall Sensor configuration structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
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{
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TIM_OC_InitTypeDef OC_Config;
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/* Check the TIM handle allocation */
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if(htim == NULL)
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{
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return HAL_ERROR;
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}
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
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assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
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assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
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assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
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assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
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assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
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if(htim->State == HAL_TIM_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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htim->Lock = HAL_UNLOCKED;
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/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
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HAL_TIMEx_HallSensor_MspInit(htim);
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}
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/* Set the TIM state */
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htim->State = HAL_TIM_STATE_BUSY;
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/* Configure the Time base in the Encoder Mode */
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TIM_Base_SetConfig(htim->Instance, &htim->Init);
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/* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
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TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
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/* Reset the IC1PSC Bits */
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htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
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/* Set the IC1PSC value */
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htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
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/* Enable the Hall sensor interface (XOR function of the three inputs) */
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htim->Instance->CR2 |= TIM_CR2_TI1S;
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/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
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htim->Instance->SMCR &= ~TIM_SMCR_TS;
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htim->Instance->SMCR |= TIM_TS_TI1F_ED;
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/* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
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htim->Instance->SMCR &= ~TIM_SMCR_SMS;
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htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
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/* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
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OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
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OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
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OC_Config.OCMode = TIM_OCMODE_PWM2;
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OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
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OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
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OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
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OC_Config.Pulse = sConfig->Commutation_Delay;
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TIM_OC2_SetConfig(htim->Instance, &OC_Config);
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/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
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register to 101U */
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htim->Instance->CR2 &= ~TIM_CR2_MMS;
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htim->Instance->CR2 |= TIM_TRGO_OC2REF;
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/* Initialize the TIM state*/
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htim->State= HAL_TIM_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief DeInitializes the TIM Hall Sensor interface
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* @param htim TIM Hall Sensor handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
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{
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/* Check the parameters */
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assert_param(IS_TIM_INSTANCE(htim->Instance));
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htim->State = HAL_TIM_STATE_BUSY;
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/* Disable the TIM Peripheral Clock */
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__HAL_TIM_DISABLE(htim);
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/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
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HAL_TIMEx_HallSensor_MspDeInit(htim);
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/* Change TIM state */
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htim->State = HAL_TIM_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(htim);
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return HAL_OK;
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}
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/**
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* @brief Initializes the TIM Hall Sensor MSP.
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* @param htim TIM handle
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* @retval None
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*/
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__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(htim);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief DeInitializes TIM Hall Sensor MSP.
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* @param htim TIM handle
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* @retval None
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*/
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__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(htim);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief Starts the TIM Hall Sensor Interface.
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* @param htim TIM Hall Sensor handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
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{
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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/* Enable the Input Capture channel 1
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(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
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/* Enable the Peripheral */
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__HAL_TIM_ENABLE(htim);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Stops the TIM Hall sensor Interface.
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* @param htim TIM Hall Sensor handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
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{
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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/* Disable the Input Capture channels 1U, 2 and 3
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(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
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/* Disable the Peripheral */
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__HAL_TIM_DISABLE(htim);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
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* @param htim TIM Hall Sensor handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
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{
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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/* Enable the capture compare Interrupts 1 event */
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__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
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/* Enable the Input Capture channel 1
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(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
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/* Enable the Peripheral */
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__HAL_TIM_ENABLE(htim);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
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* @param htim TIM handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
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{
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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/* Disable the Input Capture channel 1
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(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
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/* Disable the capture compare Interrupts event */
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__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
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/* Disable the Peripheral */
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__HAL_TIM_DISABLE(htim);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Starts the TIM Hall Sensor Interface in DMA mode.
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* @param htim TIM Hall Sensor handle
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* @param pData The destination Buffer address.
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* @param Length The length of data to be transferred from TIM peripheral to memory.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
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{
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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if((htim->State == HAL_TIM_STATE_BUSY))
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{
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return HAL_BUSY;
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}
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else if((htim->State == HAL_TIM_STATE_READY))
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{
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if(((uint32_t)pData == 0U ) && (Length > 0U))
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{
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return HAL_ERROR;
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}
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else
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{
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htim->State = HAL_TIM_STATE_BUSY;
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}
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}
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/* Enable the Input Capture channel 1
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(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
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TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
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/* Set the DMA Input Capture 1 Callback */
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htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
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/* Set the DMA error callback */
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htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
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/* Enable the DMA channel for Capture 1U*/
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HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
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/* Enable the capture compare 1 Interrupt */
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__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
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/* Enable the Peripheral */
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__HAL_TIM_ENABLE(htim);
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Stops the TIM Hall Sensor Interface in DMA mode.
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* @param htim TIM handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
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{
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/* Check the parameters */
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assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
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|
|
|
/* Disable the Input Capture channel 1
|
|
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
|
|
|
/* Disable the capture compare Interrupts 1 event */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
|
|
* @brief Timer Complementary Output Compare functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### Timer Complementary Output Compare functions #####
|
|
==============================================================================
|
|
[..]
|
|
This section provides functions allowing to:
|
|
(+) Start the Complementary Output Compare.
|
|
(+) Stop the Complementary Output Compare.
|
|
(+) Start the Complementary Output Compare and enable interrupts.
|
|
(+) Stop the Complementary Output Compare and disable interrupts.
|
|
(+) Start the Complementary Output Compare and enable DMA transfers.
|
|
(+) Stop the Complementary Output Compare and disable DMA transfers.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Starts the TIM Output Compare signal generation on the complementary
|
|
* output.
|
|
* @param htim TIM Output Compare handle
|
|
* @param Channel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Enable the Capture compare channel N */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the TIM Output Compare signal generation on the complementary
|
|
* output.
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Disable the Capture compare channel N */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Starts the TIM Output Compare signal generation in interrupt mode
|
|
* on the complementary output.
|
|
* @param htim TIM OC handle
|
|
* @param Channel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Enable the TIM Output Compare interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Enable the TIM Output Compare interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Enable the TIM Output Compare interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Enable the TIM Output Compare interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Enable the TIM Break interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
|
|
|
|
/* Enable the Capture compare channel N */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the TIM Output Compare signal generation in interrupt mode
|
|
* on the complementary output.
|
|
* @param htim TIM Output Compare handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
uint32_t tmpccer = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Disable the TIM Output Compare interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Disable the TIM Output Compare interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Disable the TIM Output Compare interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Disable the TIM Output Compare interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Disable the Capture compare channel N */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
|
tmpccer = htim->Instance->CCER;
|
|
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
|
|
{
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
|
}
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Starts the TIM Output Compare signal generation in DMA mode
|
|
* on the complementary output.
|
|
* @param htim TIM Output Compare handle
|
|
* @param Channel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @param pData The source Buffer address.
|
|
* @param Length The length of data to be transferred from memory to TIM peripheral
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
if((htim->State == HAL_TIM_STATE_BUSY))
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if((htim->State == HAL_TIM_STATE_READY))
|
|
{
|
|
if(((uint32_t)pData == 0U ) && (Length > 0U))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
}
|
|
}
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
|
|
|
/* Enable the TIM Output Compare DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
|
|
|
/* Enable the TIM Output Compare DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
|
|
|
/* Enable the TIM Output Compare DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
|
|
|
/* Enable the TIM Output Compare DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Enable the Capture compare channel N */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the TIM Output Compare signal generation in DMA mode
|
|
* on the complementary output.
|
|
* @param htim TIM Output Compare handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Disable the TIM Output Compare DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Disable the TIM Output Compare DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Disable the TIM Output Compare DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Disable the TIM Output Compare interrupt */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Disable the Capture compare channel N */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
|
|
* @brief Timer Complementary PWM functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### Timer Complementary PWM functions #####
|
|
==============================================================================
|
|
[..]
|
|
This section provides functions allowing to:
|
|
(+) Start the Complementary PWM.
|
|
(+) Stop the Complementary PWM.
|
|
(+) Start the Complementary PWM and enable interrupts.
|
|
(+) Stop the Complementary PWM and disable interrupts.
|
|
(+) Start the Complementary PWM and enable DMA transfers.
|
|
(+) Stop the Complementary PWM and disable DMA transfers.
|
|
(+) Start the Complementary Input Capture measurement.
|
|
(+) Stop the Complementary Input Capture.
|
|
(+) Start the Complementary Input Capture and enable interrupts.
|
|
(+) Stop the Complementary Input Capture and disable interrupts.
|
|
(+) Start the Complementary Input Capture and enable DMA transfers.
|
|
(+) Stop the Complementary Input Capture and disable DMA transfers.
|
|
(+) Start the Complementary One Pulse generation.
|
|
(+) Stop the Complementary One Pulse.
|
|
(+) Start the Complementary One Pulse and enable interrupts.
|
|
(+) Stop the Complementary One Pulse and disable interrupts.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Starts the PWM signal generation on the complementary output.
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Enable the complementary PWM output */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the PWM signal generation on the complementary output.
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Disable the complementary PWM output */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Starts the PWM signal generation in interrupt mode on the
|
|
* complementary output.
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Enable the TIM Capture/Compare 1 interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Enable the TIM Capture/Compare 2 interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Enable the TIM Capture/Compare 3 interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Enable the TIM Capture/Compare 4 interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Enable the TIM Break interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
|
|
|
|
/* Enable the complementary PWM output */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the PWM signal generation in interrupt mode on the
|
|
* complementary output.
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
uint32_t tmpccer = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Disable the TIM Capture/Compare 1 interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Disable the TIM Capture/Compare 2 interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Disable the TIM Capture/Compare 3 interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Disable the TIM Capture/Compare 3 interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Disable the complementary PWM output */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
|
tmpccer = htim->Instance->CCER;
|
|
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
|
|
{
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
|
}
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Starts the TIM PWM signal generation in DMA mode on the
|
|
* complementary output
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @param pData The source Buffer address.
|
|
* @param Length The length of data to be transferred from memory to TIM peripheral
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
if((htim->State == HAL_TIM_STATE_BUSY))
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if((htim->State == HAL_TIM_STATE_READY))
|
|
{
|
|
if(((uint32_t)pData == 0U ) && (Length > 0U))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
}
|
|
}
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
|
|
|
/* Enable the TIM Capture/Compare 1 DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
|
|
|
/* Enable the TIM Capture/Compare 2 DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
|
|
|
/* Enable the TIM Capture/Compare 3 DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Set the DMA Period elapsed callback */
|
|
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
|
/* Enable the DMA channel */
|
|
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
|
|
|
/* Enable the TIM Capture/Compare 4 DMA request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Enable the complementary PWM output */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
|
|
* output
|
|
* @param htim TIM handle
|
|
* @param Channel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Disable the TIM Capture/Compare 1 DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Disable the TIM Capture/Compare 2 DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Disable the TIM Capture/Compare 3 DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Disable the TIM Capture/Compare 4 DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Disable the complementary PWM output */
|
|
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
|
|
* @brief Timer Complementary One Pulse functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### Timer Complementary One Pulse functions #####
|
|
==============================================================================
|
|
[..]
|
|
This section provides functions allowing to:
|
|
(+) Start the Complementary One Pulse generation.
|
|
(+) Stop the Complementary One Pulse.
|
|
(+) Start the Complementary One Pulse and enable interrupts.
|
|
(+) Stop the Complementary One Pulse and disable interrupts.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Starts the TIM One Pulse signal generation on the complemetary
|
|
* output.
|
|
* @param htim TIM One Pulse handle
|
|
* @param OutputChannel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
|
/* Enable the complementary One Pulse output */
|
|
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the TIM One Pulse signal generation on the complementary
|
|
* output.
|
|
* @param htim TIM One Pulse handle
|
|
* @param OutputChannel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
{
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
|
/* Disable the complementary One Pulse output */
|
|
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
|
|
* complementary channel.
|
|
* @param htim TIM One Pulse handle
|
|
* @param OutputChannel TIM Channel to be enabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
|
/* Enable the TIM Capture/Compare 1 interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
|
/* Enable the TIM Capture/Compare 2 interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
|
/* Enable the complementary One Pulse output */
|
|
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
|
|
|
/* Enable the Main Ouput */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
|
|
* complementary channel.
|
|
* @param htim TIM One Pulse handle
|
|
* @param OutputChannel TIM Channel to be disabled
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
|
/* Disable the TIM Capture/Compare 1 interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
|
/* Disable the TIM Capture/Compare 2 interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
|
/* Disable the complementary One Pulse output */
|
|
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
|
|
|
|
/* Disable the Main Ouput */
|
|
__HAL_TIM_MOE_DISABLE(htim);
|
|
|
|
/* Disable the Peripheral */
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
|
|
* @brief Peripheral Control functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### Peripheral Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This section provides functions allowing to:
|
|
(+) Configure the commutation event in case of use of the Hall sensor interface.
|
|
(+) Configure Output channels for OC and PWM mode.
|
|
|
|
(+) Configure Complementary channels, break features and dead time.
|
|
(+) Configure Master synchronization.
|
|
(+) Configure timer remapping capabilities.
|
|
(+) Enable or disable channel grouping
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
|
|
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
|
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/**
|
|
* @brief Configure the TIM commutation event sequence.
|
|
* @note this function is mandatory to use the commutation event in order to
|
|
* update the configuration at each commutation detection on the TRGI input of the Timer,
|
|
* the typical use of this feature is with the use of another Timer(interface Timer)
|
|
* configured in Hall sensor interface, this interface Timer will generate the
|
|
* commutation at its TRGO output (connected to Timer used in this function) each time
|
|
* the TI1 of the Interface Timer detect a commutation at its input TI1.
|
|
* @param htim TIM handle
|
|
* @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TS_ITR0: Internal trigger 0 selected
|
|
* @arg TIM_TS_ITR1: Internal trigger 1 selected
|
|
* @arg TIM_TS_ITR2: Internal trigger 2 selected
|
|
* @arg TIM_TS_ITR3: Internal trigger 3 selected
|
|
* @arg TIM_TS_NONE: No trigger is needed
|
|
* @param CommutationSource the Commutation Event source
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
|
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
|
|
|
|
__HAL_LOCK(htim);
|
|
|
|
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
|
|
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
|
|
{
|
|
/* Select the Input trigger */
|
|
htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
htim->Instance->SMCR |= InputTrigger;
|
|
}
|
|
|
|
/* Select the Capture Compare preload feature */
|
|
htim->Instance->CR2 |= TIM_CR2_CCPC;
|
|
/* Select the Commutation event source */
|
|
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
|
htim->Instance->CR2 |= CommutationSource;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIM commutation event sequence with interrupt.
|
|
* @note this function is mandatory to use the commutation event in order to
|
|
* update the configuration at each commutation detection on the TRGI input of the Timer,
|
|
* the typical use of this feature is with the use of another Timer(interface Timer)
|
|
* configured in Hall sensor interface, this interface Timer will generate the
|
|
* commutation at its TRGO output (connected to Timer used in this function) each time
|
|
* the TI1 of the Interface Timer detect a commutation at its input TI1.
|
|
* @param htim TIM handle
|
|
* @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TS_ITR0: Internal trigger 0 selected
|
|
* @arg TIM_TS_ITR1: Internal trigger 1 selected
|
|
* @arg TIM_TS_ITR2: Internal trigger 2 selected
|
|
* @arg TIM_TS_ITR3: Internal trigger 3 selected
|
|
* @arg TIM_TS_NONE: No trigger is needed
|
|
* @param CommutationSource the Commutation Event source
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
|
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
|
|
|
|
__HAL_LOCK(htim);
|
|
|
|
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
|
|
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
|
|
{
|
|
/* Select the Input trigger */
|
|
htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
htim->Instance->SMCR |= InputTrigger;
|
|
}
|
|
|
|
/* Select the Capture Compare preload feature */
|
|
htim->Instance->CR2 |= TIM_CR2_CCPC;
|
|
/* Select the Commutation event source */
|
|
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
|
htim->Instance->CR2 |= CommutationSource;
|
|
|
|
/* Enable the Commutation Interrupt Request */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIM commutation event sequence with DMA.
|
|
* @note this function is mandatory to use the commutation event in order to
|
|
* update the configuration at each commutation detection on the TRGI input of the Timer,
|
|
* the typical use of this feature is with the use of another Timer(interface Timer)
|
|
* configured in Hall sensor interface, this interface Timer will generate the
|
|
* commutation at its TRGO output (connected to Timer used in this function) each time
|
|
* the TI1 of the Interface Timer detect a commutation at its input TI1.
|
|
* @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
|
|
* @param htim TIM handle
|
|
* @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TS_ITR0: Internal trigger 0 selected
|
|
* @arg TIM_TS_ITR1: Internal trigger 1 selected
|
|
* @arg TIM_TS_ITR2: Internal trigger 2 selected
|
|
* @arg TIM_TS_ITR3: Internal trigger 3 selected
|
|
* @arg TIM_TS_NONE: No trigger is needed
|
|
* @param CommutationSource the Commutation Event source
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
|
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
|
|
|
|
__HAL_LOCK(htim);
|
|
|
|
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
|
|
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
|
|
{
|
|
/* Select the Input trigger */
|
|
htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
htim->Instance->SMCR |= InputTrigger;
|
|
}
|
|
|
|
/* Select the Capture Compare preload feature */
|
|
htim->Instance->CR2 |= TIM_CR2_CCPC;
|
|
/* Select the Commutation event source */
|
|
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
|
htim->Instance->CR2 |= CommutationSource;
|
|
|
|
/* Enable the Commutation DMA Request */
|
|
/* Set the DMA Commutation Callback */
|
|
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
|
|
/* Set the DMA error callback */
|
|
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
|
|
|
|
/* Enable the Commutation DMA Request */
|
|
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Initializes the TIM Output Compare Channels according to the specified
|
|
* parameters in the TIM_OC_InitTypeDef.
|
|
* @param htim TIM Output Compare handle
|
|
* @param sConfig TIM Output Compare configuration structure
|
|
* @param Channel TIM Channels to configure
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
|
|
* STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
TIM_OC_InitTypeDef* sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 1 in Output Compare */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 2 in Output Compare */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 3 in Output Compare */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 4 in Output Compare */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_5:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 5 in Output Compare */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_6:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the TIM Channel 6 in Output Compare */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Initializes the TIM PWM channels according to the specified
|
|
* parameters in the TIM_OC_InitTypeDef.
|
|
* @param htim TIM PWM handle
|
|
* @param sConfig TIM PWM configuration structure
|
|
* @param Channel TIM Channels to be configured
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
|
|
* STM32F398xx and STM32F303x8 up to 6 PWM channels can be configured
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
TIM_OC_InitTypeDef* sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_5:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
}
|
|
break;
|
|
|
|
case TIM_CHANNEL_6:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Configures the TIM in master mode.
|
|
* @param htim TIM handle.
|
|
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
|
|
* contains the selected trigger output (TRGO) and the Master/Slave
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
TIM_MasterConfigTypeDef * sMasterConfig)
|
|
{
|
|
uint32_t tmpcr2;
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2U */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
|
|
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
|
|
|
#if defined(STM32F373xC) || defined(STM32F378xx)
|
|
/**
|
|
* @brief Configures the TIM in master mode.
|
|
* @param htim TIM handle.
|
|
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
|
|
* contains the selected trigger output (TRGO) and the Master/Slave
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
__HAL_LOCK(htim);
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
|
/* Reset the MMS Bits */
|
|
htim->Instance->CR2 &= ~TIM_CR2_MMS;
|
|
/* Select the TRGO source */
|
|
htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
|
|
|
|
/* Reset the MSM Bit */
|
|
htim->Instance->SMCR &= ~TIM_SMCR_MSM;
|
|
/* Set or Reset the MSM Bit */
|
|
htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F373xC || STM32F378xx */
|
|
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
|
|
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
|
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/**
|
|
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
|
|
* and the AOE(automatic output enable).
|
|
* @param htim TIM handle
|
|
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
|
|
structure that contains the BDTR Register configuration information
|
|
for the TIM peripheral.
|
|
* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
|
|
STM32F398xx and STM32F303x8 two break inputs can be configured.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
|
|
{
|
|
uint32_t tmpbdtr = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
|
|
assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
|
|
assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
|
|
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
|
|
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
|
|
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
/* Set the BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
|
|
|
|
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
|
{
|
|
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
|
|
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
|
|
|
/* Set the BREAK2 input related BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
|
}
|
|
|
|
/* Set TIMx_BDTR */
|
|
htim->Instance->BDTR = tmpbdtr;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
|
|
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
|
|
|
#if defined(STM32F373xC) || defined(STM32F378xx)
|
|
/**
|
|
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
|
|
* and the AOE(automatic output enable).
|
|
* @param htim TIM handle
|
|
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
|
|
* contains the BDTR Register configuration information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
|
|
{
|
|
uint32_t tmpbdtr = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
|
|
assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
|
|
assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
|
|
assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
|
|
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
|
|
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
/* Set the BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
|
|
/* Set TIMx_BDTR */
|
|
htim->Instance->BDTR = tmpbdtr;
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F373xC || STM32F378xx */
|
|
|
|
#if defined(STM32F303xE) || defined(STM32F398xx) || \
|
|
defined(STM32F303xC) || defined(STM32F358xx) || \
|
|
defined(STM32F334x8)
|
|
#if defined(STM32F303xE) || defined(STM32F398xx)
|
|
/**
|
|
* @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
|
|
* @param htim TIM handle.
|
|
* @param Remap1: specifies the first TIM remapping source.
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
|
|
* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
|
|
* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
|
|
* @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
|
|
* @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
|
|
* @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
|
|
* @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
|
|
* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
|
|
* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
|
|
* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
|
|
* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
|
|
* @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
|
|
* @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
|
|
* @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
|
|
* @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
|
|
* @param Remap2: specifies the second TIMremapping source (if any).
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
|
|
* @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
|
|
* @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
|
|
* @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
|
|
* @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
|
|
* @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
|
|
* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
|
|
* @arg TIM_TIM16_NONE: Non significant value for TIM16
|
|
* @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
|
|
* @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
|
|
* @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
|
|
* @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
|
|
* @retval HAL status
|
|
*/
|
|
#elif defined(STM32F303xC) || defined(STM32F358xx)
|
|
/**
|
|
* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
|
|
* @param htim TIM handle.
|
|
* @param Remap1: specifies the first TIM remapping source.
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
|
|
* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
|
|
* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
|
|
* @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
|
|
* @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
|
|
* @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
|
|
* @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
|
|
* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
|
|
* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
|
|
* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
|
|
* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
|
|
* @param Remap2: specifies the second TIMremapping source (if any).
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
|
|
* @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
|
|
* @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
|
|
* @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
|
|
* @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
|
|
* @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
|
|
* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
|
|
* @retval HAL status
|
|
*/
|
|
#else /* STM32F334x8 */
|
|
/**
|
|
* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
|
|
* @param htim TIM handle.
|
|
* @param Remap1: specifies the first TIM remapping source.
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
|
|
* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
|
|
* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
|
|
* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
|
|
* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
|
|
* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
|
|
* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
|
|
* @param Remap2: specifies the second TIMremapping source (if any).
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
|
|
* @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
|
|
* @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
|
|
* @retval HAL status
|
|
*/
|
|
#endif /* STM32F303xE || STM32F398xx || */
|
|
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
|
|
{
|
|
__HAL_LOCK(htim);
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_REMAP(Remap1));
|
|
assert_param(IS_TIM_REMAP2(Remap2));
|
|
|
|
/* Set the Timer remapping configuration */
|
|
htim->Instance->OR = Remap1 | Remap2;
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F303xE || STM32F398xx || */
|
|
/* STM32F303xC || STM32F358xx || STM32F334x8 */
|
|
|
|
|
|
#if defined(STM32F302xE) || \
|
|
defined(STM32F302xC) || \
|
|
defined(STM32F303x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
|
|
defined(STM32F373xC) || defined(STM32F378xx)
|
|
#if defined(STM32F302xE) || \
|
|
defined(STM32F302xC) || \
|
|
defined(STM32F303x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/**
|
|
* @brief Configures the TIM1 and TIM16 Remapping input capabilities.
|
|
* @param htim TIM handle.
|
|
* @param Remap specifies the TIM remapping source.
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
|
|
* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
|
|
* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
|
|
* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
|
|
* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
|
|
* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
|
|
* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
|
|
* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
|
|
* @retval HAL status
|
|
*/
|
|
#else /* STM32F373xC || STM32F378xx */
|
|
/**
|
|
* @brief Configures the TIM2 and TIM14 Remapping input capabilities.
|
|
* @param htim TIM handle.
|
|
* @param Remap specifies the TIM remapping source.
|
|
* This parameter can be one of the following values:
|
|
* STM32F373xC, STM32F378xx:
|
|
* @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
|
|
* @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
|
|
* @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
|
|
* @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
|
|
* @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
|
|
* @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
|
|
* @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
|
|
* @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
|
|
* @retval HAL status
|
|
*/
|
|
#endif /* STM32F302xE || */
|
|
/* STM32F302xC || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
|
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
|
{
|
|
__HAL_LOCK(htim);
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_REMAP(Remap));
|
|
|
|
/* Set the Timer remapping configuration */
|
|
htim->Instance->OR = Remap;
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F302xE || */
|
|
/* STM32F302xC || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
|
|
/* STM32F373xC || STM32F378xx */
|
|
|
|
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
|
|
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
|
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/**
|
|
* @brief Group channel 5 and channel 1, 2 or 3
|
|
* @param htim TIM handle.
|
|
* @param Channels specifies the reference signal(s) the OC5REF is combined with.
|
|
* This parameter can be any combination of the following values:
|
|
* TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
|
|
* TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
|
|
* TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
|
|
* TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_GROUPCH5(Channels));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
|
/* Clear GC5Cx bit fields */
|
|
htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
|
|
|
|
/* Set GC5Cx bit fields */
|
|
htim->Instance->CCR5 |= Channels;
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
|
|
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup TIM_Exported_Functions_Group8
|
|
* @{
|
|
*/
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
|
|
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
|
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/**
|
|
* @brief Configures the OCRef clear feature
|
|
* @param htim TIM handle
|
|
* @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
|
|
* contains the OCREF clear feature and parameters for the TIM peripheral.
|
|
* @param Channel specifies the TIM Channel
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4
|
|
* @arg TIM_Channel_5: TIM Channel 5
|
|
* @arg TIM_Channel_6: TIM Channel 6
|
|
* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
|
|
* STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
|
|
TIM_ClearInputConfigTypeDef *sClearInputConfig,
|
|
uint32_t Channel)
|
|
{
|
|
uint32_t tmpsmcr = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
|
switch (sClearInputConfig->ClearInputSource)
|
|
{
|
|
case TIM_CLEARINPUTSOURCE_NONE:
|
|
{
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
|
/* Clear the OCREF clear selection bit */
|
|
tmpsmcr &= ~TIM_SMCR_OCCS;
|
|
|
|
/* Clear the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
|
/* Set TIMx_SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
}
|
|
break;
|
|
|
|
case TIM_CLEARINPUTSOURCE_OCREFCLR:
|
|
{
|
|
/* Clear the OCREF clear selection bit */
|
|
htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
|
|
}
|
|
break;
|
|
|
|
case TIM_CLEARINPUTSOURCE_ETR:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
|
|
assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
|
|
assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
|
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
sClearInputConfig->ClearInputPrescaler,
|
|
sClearInputConfig->ClearInputPolarity,
|
|
sClearInputConfig->ClearInputFilter);
|
|
|
|
/* Set the OCREF clear selection bit */
|
|
htim->Instance->SMCR |= TIM_SMCR_OCCS;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
switch (Channel)
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
if(sClearInputConfig->ClearInputState != RESET)
|
|
{
|
|
/* Enable the Ocref clear feature for Channel 1U */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Ocref clear feature for Channel 1U */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
|
|
}
|
|
}
|
|
break;
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
if(sClearInputConfig->ClearInputState != RESET)
|
|
{
|
|
/* Enable the Ocref clear feature for Channel 2U */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Ocref clear feature for Channel 2U */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
|
|
}
|
|
}
|
|
break;
|
|
case TIM_CHANNEL_3:
|
|
{
|
|
if(sClearInputConfig->ClearInputState != RESET)
|
|
{
|
|
/* Enable the Ocref clear feature for Channel 3U */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Ocref clear feature for Channel 3U */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
|
|
}
|
|
}
|
|
break;
|
|
case TIM_CHANNEL_4:
|
|
{
|
|
if(sClearInputConfig->ClearInputState != RESET)
|
|
{
|
|
/* Enable the Ocref clear feature for Channel 4U */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Ocref clear feature for Channel 4U */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
|
|
}
|
|
}
|
|
break;
|
|
case TIM_CHANNEL_5:
|
|
{
|
|
if(sClearInputConfig->ClearInputState != RESET)
|
|
{
|
|
/* Enable the Ocref clear feature for Channel 1U */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Ocref clear feature for Channel 1U */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
|
|
}
|
|
}
|
|
break;
|
|
case TIM_CHANNEL_6:
|
|
{
|
|
if(sClearInputConfig->ClearInputState != RESET)
|
|
{
|
|
/* Enable the Ocref clear feature for Channel 1U */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Ocref clear feature for Channel 1U */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
|
return HAL_OK;
|
|
}
|
|
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
|
|
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
|
|
* @brief Extension Callbacks functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### Extended Callbacks functions #####
|
|
==============================================================================
|
|
[..]
|
|
This section provides Extended TIM callback functions:
|
|
(+) Timer Commutation callback
|
|
(+) Timer Break callback
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Hall commutation changed callback in non blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutationCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Hall Break detection callback in non blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Hall Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
|
* @brief Extended Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### Extended Peripheral State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permit to get in run-time the status of the peripheral
|
|
and the data flow.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Return the TIM Hall Sensor interface state
|
|
* @param htim TIM Hall Sensor handle
|
|
* @retval HAL state
|
|
*/
|
|
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
|
|
{
|
|
return htim->State;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup TIMEx_Private_Functions
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief TIM DMA Commutation callback.
|
|
* @param hdma pointer to DMA handle.
|
|
* @retval None
|
|
*/
|
|
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
|
htim->State= HAL_TIM_STATE_READY;
|
|
|
|
HAL_TIMEx_CommutationCallback(htim);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the TIM Capture Compare Channel xN.
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param Channel specifies the TIM Channel
|
|
* This parameter can be one of the following values:
|
|
* @arg TIM_CHANNEL_1: TIM Channel 1
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3
|
|
* @param ChannelNState specifies the TIM Channel CCxNE bit new state.
|
|
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
|
|
* @retval None
|
|
*/
|
|
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
|
|
{
|
|
uint32_t tmp = 0U;
|
|
|
|
tmp = TIM_CCER_CC1NE << Channel;
|
|
|
|
/* Reset the CCxNE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
|
|
/* Set or reset the CCxNE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
|
|
}
|
|
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
|
|
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
|
|
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
|
|
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/**
|
|
* @brief Timer Ouput Compare 5 configuration
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
uint32_t tmpccmrx = 0U;
|
|
uint32_t tmpccer = 0U;
|
|
uint32_t tmpcr2 = 0U;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
|
|
if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
}
|
|
|
|
/**
|
|
* @brief Timer Ouput Compare 6 configuration
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
uint32_t tmpccmrx = 0U;
|
|
uint32_t tmpccer = 0U;
|
|
uint32_t tmpcr2 = 0U;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
|
|
if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
}
|
|
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
|
|
/* STM32F302xC || STM32F303xC || STM32F358xx || */
|
|
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
|
|
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_TIM_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|