2135 lines
136 KiB
C
2135 lines
136 KiB
C
/**
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* @file xmc4_eru_map.h
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* @date 2016-10-27
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.12 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-02-20:
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* - Initial version
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*
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* 2015-12-07:
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* - Add XMC4300 support
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*
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* 2016-10-27:
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* - Fixed: Remove incorrect ERU0_ETL1_INPUTB_P0_1 and replace it by ERU0_ETL1_INPUTB_SCU_HIB_SR1
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*
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* @endcond
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*/
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#ifndef XMC4_ERU_MAP_H
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#define XMC4_ERU_MAP_H
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/*********************************************************************************************************************
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* MACROS
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*********************************************************************************************************************/
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#define ERU0_ETL0 XMC_ERU0, 0
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#define ERU0_ETL1 XMC_ERU0, 1
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#define ERU0_ETL2 XMC_ERU0, 2
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#define ERU0_ETL3 XMC_ERU0, 3
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#define ERU0_OGU0 XMC_ERU0, 0
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#define ERU0_OGU1 XMC_ERU0, 1
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#define ERU0_OGU2 XMC_ERU0, 2
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#define ERU0_OGU3 XMC_ERU0, 3
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#define ERU1_ETL0 XMC_ERU1, 0
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#define ERU1_ETL1 XMC_ERU1, 1
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#define ERU1_ETL2 XMC_ERU1, 2
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#define ERU1_ETL3 XMC_ERU1, 3
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#define ERU1_OGU0 XMC_ERU1, 0
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#define ERU1_OGU1 XMC_ERU1, 1
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#define ERU1_OGU2 XMC_ERU1, 2
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#define ERU1_OGU3 XMC_ERU1, 3
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#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == LQFP64)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4104) && (UC_PACKAGE == VQFN48)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_HRPWM0_CNO XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_HRPWM0_CNO XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4504) && (UC_PACKAGE == LQFP144)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == BGA196)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4700) && (UC_PACKAGE == LQFP144)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == BGA196)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144)
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#define ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL0_INPUTA_SCU_G0ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL1_INPUTA_SCU_G0ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL1_INPUTA_SCU_HIB_SR0 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL1_INPUTB_SCU_HIB_SR1 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL2_INPUTA_SCU_G1ORCOUT6 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1
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#define ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2
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#define ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0
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#define ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1
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#define ERU0_ETL3_INPUTA_SCU_G1ORCOUT7 XMC_ERU_ETL_INPUT_A3
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#define ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3
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#define ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2
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#define ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0
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#define ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTA_CCU40_ST0 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL0_INPUTA_DAC_SGN_0 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL0_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL0_INPUTB_ERU1_IOUT3 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL0_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL1_INPUTA_CCU40_ST1 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL1_INPUTA_ERU1_IOUT2 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL1_INPUTA_POSIF0_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL1_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL1_INPUTB_ERU1_IOUT2 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL1_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL2_INPUTA_CCU40_ST2 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL2_INPUTA_DAC_SGN_1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL2_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL2_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL2_INPUTB_ECAT0_SYNC0 XMC_ERU_ETL_INPUT_B3
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#define ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL2_INPUTB_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU1_ETL3_INPUTA_CCU40_ST3 XMC_ERU_ETL_INPUT_A2
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#define ERU1_ETL3_INPUTA_ECAT0_SYNC1 XMC_ERU_ETL_INPUT_A3
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#define ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0
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#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
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#define ERU1_ETL3_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B1
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#define ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0
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#define ERU1_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B2
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXH XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU0_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU40_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_ST0 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_STA3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_STB3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_FIXL XMC_ERU_OGU_PERIPHERAL_TRIGGER3
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#define ERU1_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
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#endif
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#endif /* XMC4_ERU_MAP_H */
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