463 lines
16 KiB
C
463 lines
16 KiB
C
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/**
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* @file xmc_ecat.h
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* @date 2015-12-27
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.12 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-12-27:
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* - Initial Version<br>
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*
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* @endcond
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*/
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/**
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* @addtogroup XMClib XMC Peripheral Library
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* @{
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*/
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/**
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* @addtogroup ECAT
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* @brief EtherCAT Low level driver for XMC4800/XMC4300 series.
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*
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* EtherCAT is an Ethernet-based fieldbus system.
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* The EtherCAT Slave Controller (ECAT) read the data addressed to them while the telegram passes through the device.
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* An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface between the EtherCAT
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* fieldbus and the slave application. EtherCAT uses standard IEEE 802.3 Ethernet frames, thus a standard network
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* controller can be used and no special hardware is required on master side. EtherCAT has a reserved EtherType of
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* 0x88A4 that distinguishes it from other Ethernet frames. Thus, EtherCAT can run in parallel to other Ethernet
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* protocols. EtherCAT does not require the IP protocol, however it can be encapsulated in IP/UDP. The EtherCAT
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* Slave Controller processes the frame in hardware. Thus, communication performance is independent from processor
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* power.
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*
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* The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral.
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* For EHTERCAT stack integration, the necessary hardware accees layer APIs shall be explicitly implemented depending
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* upon the stack provider. The XMC_ECAT lld layer provides only the hardware initialization functions for start up and
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* basic functionalities.
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* @{
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*/
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#ifndef XMC_ECAT_H
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#define XMC_ECAT_H
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/**********************************************************************************************************************
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* HEADER FILES
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*********************************************************************************************************************/
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#include "xmc_common.h"
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#if defined (ECAT0)
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#include "xmc_ecat_map.h"
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/**********************************************************************************************************************
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* MACROS
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* ENUMS
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*********************************************************************************************************************/
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/**
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* ECAT status return values
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*/
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typedef enum XMC_ECAT_STATUS
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{
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XMC_ECAT_STATUS_OK = 0U, /**< Driver accepted application request */
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XMC_ECAT_STATUS_BUSY = 1U, /**< Driver is busy and cannot handle request */
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XMC_ECAT_STATUS_ERROR = 2U /**< Driver could not fulfil application request */
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} XMC_ECAT_STATUS_t;
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/**
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* EtherCAT event enumeration types
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*/
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typedef enum XMC_ECAT_EVENT
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{
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XMC_ECAT_EVENT_AL_CONTROL = ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk, /**< Application control event mask */
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XMC_ECAT_EVENT_DC_LATCH = ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk, /**< Distributed Clock latch event mask */
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XMC_ECAT_EVENT_DC_SYNC0 = ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk, /**< State of distributed clock sync-0 event mask */
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XMC_ECAT_EVENT_DC_SYNC1 = ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk, /**< State of distributed clock sync-1 event mask */
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XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER = ECAT_AL_EVENT_MASK_SM_A_MASK_Msk, /**< SyncManager activation register mask*/
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XMC_ECAT_EVENT_EEPROM = ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk, /**< EEPROM Emulation event mask*/
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XMC_ECAT_EVENT_WATCHDOG = ECAT_AL_EVENT_MASK_WP_D_MASK_Msk, /**< WATCHDOG process data event mask*/
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XMC_ECAT_EVENT_SM0 = ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk, /**< Sync Manager 0 event mask*/
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XMC_ECAT_EVENT_SM1 = ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk, /**< Sync Manager 1 event mask*/
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XMC_ECAT_EVENT_SM2 = ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk, /**< Sync Manager 2 event mask*/
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XMC_ECAT_EVENT_SM3 = ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk, /**< Sync Manager 3 event mask*/
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XMC_ECAT_EVENT_SM4 = ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk, /**< Sync Manager 4 event mask*/
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XMC_ECAT_EVENT_SM5 = ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk, /**< Sync Manager 5 event mask*/
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XMC_ECAT_EVENT_SM6 = ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk, /**< Sync Manager 6 event mask*/
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XMC_ECAT_EVENT_SM7 = ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk /**< Sync Manager 7 event mask*/
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} XMC_ECAT_EVENT_t;
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/**********************************************************************************************************************
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* DATA STRUCTURES
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*********************************************************************************************************************/
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/* Anonymous structure/union guard start */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__TASKING__)
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#pragma warning 586
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#endif
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/**
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* ECAT port control data structure
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*/
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typedef struct XMC_ECAT_PORT_CTRL
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{
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union
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{
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struct
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{
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uint32_t enable_rstreq: 1; /**< Master can trigger a reset of the XMC4700 / XMC4800 (::bool) */
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uint32_t: 7; /**< Reserved bits */
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uint32_t latch_input0: 2; /**< Latch input 0 selection (::XMC_ECAT_PORT_LATCHIN0_t) */
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uint32_t: 2; /**< Reserved bits */
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uint32_t latch_input1: 2; /**< Latch input 1 selection (::XMC_ECAT_PORT_LATCHIN1_t) */
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uint32_t: 2; /**< Reserved bits */
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uint32_t phyaddr_offset: 5; /**< Ethernet PHY address offset, address of port 0 */
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uint32_t: 1; /**< Reserved bits */
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uint32_t mdio: 2; /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */
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uint32_t: 8; /**< Reserved bits */
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};
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uint32_t raw;
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} common;
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union
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{
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struct
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{
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uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT0_CTRL_RXD0_t) */
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uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT0_CTRL_RXD1_t) */
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uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT0_CTRL_RXD2_t) */
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uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT0_CTRL_RXD3_t) */
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uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT0_CTRL_RX_ERR_t) */
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uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT0_CTRL_RX_DV_t) */
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uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT0_CTRL_RX_CLK_t) */
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uint32_t: 2; /**< Reserved bits */
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uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT0_CTRL_LINK_t) */
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uint32_t: 10; /**< Reserved bits */
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uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT0_CTRL_TX_CLK_t) */
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uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT0_CTRL_TX_SHIFT_t) */
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};
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uint32_t raw;
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} port0;
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union
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{
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struct
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{
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uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT_CTRL_RXD0_t) */
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uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT_CTRL_RXD1_t) */
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uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT_CTRL_RXD2_t) */
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uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT_CTRL_RXD3_t) */
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uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT_CTRL_RX_ERR_t) */
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uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT_CTRL_RX_DV_t) */
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uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT_CTRL_RX_CLK_t) */
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uint32_t: 2; /**< Reserved bits */
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uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT_CTRL_LINK_t) */
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uint32_t: 10; /**< Reserved bits */
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uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT_CTRL_TX_CLK_t) */
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uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT1_CTRL_TX_SHIFT_t) */
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};
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uint32_t raw;
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} port1;
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} XMC_ECAT_PORT_CTRL_t;
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/**
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* ECAT EEPROM configuration area data structure
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*/
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typedef union XMC_ECAT_CONFIG
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{
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struct
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{
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uint32_t : 8;
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uint32_t : 2;
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uint32_t enable_dc_sync_out : 1;
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uint32_t enable_dc_latch_in : 1;
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uint32_t enable_enhanced_link_p0 : 1;
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uint32_t enable_enhanced_link_p1 : 1;
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uint32_t : 2;
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uint32_t : 16;
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uint16_t sync_pulse_length; /**< Initialization value for Pulse Length of SYNC Signals register*/
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uint32_t : 16;
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uint16_t station_alias; /**< Initialization value for Configured Station Alias Address register */
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uint16_t : 16;
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uint16_t : 16;
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uint16_t checksum;
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};
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uint32_t dword[4]; /**< Four 32 bit double word equivalent to 8 16 bit configuration area word. */
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} XMC_ECAT_CONFIG_t;
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/* Anonymous structure/union guard end */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__TASKING__)
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#pragma warning restore
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#endif
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/**********************************************************************************************************************
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* API PROTOTYPES
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*********************************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @param config XMC_ECAT_CONFIG_t
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* @return XMC_ECAT_STATUS_t ECAT Initialization status
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*
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* \par<b>Description: </b><br>
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* Initialize the Ethernet MAC peripheral <br>
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*
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* \par
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* The function sets the link speed, applies the duplex mode, sets auto-negotiation
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* and loop-back settings.
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*/
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void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config);
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/**
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* @param None
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enable the EtherCAT peripheral <br>
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*
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* \par
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* The function de-asserts the peripheral reset.
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*/
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void XMC_ECAT_Enable(void);
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/**
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* @param None
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disable the EtherCAT peripheral <br>
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*
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* \par
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* The function asserts the peripheral reset.
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*/
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void XMC_ECAT_Disable(void);
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/**
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* @param phy_addr PHY address
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* @param reg_addr Register address
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* @param data The destination to which the read data needs to be copied to.
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*
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* @return XMC_ECAT_STATUS_t EtherCAT Read PHY API return status
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*
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* \par<b>Description: </b><br>
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* Read a PHY register <br>
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*
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* \par
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* The function reads a PHY register. It essentially polls busy bit during max
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* PHY_TIMEOUT time and reads the information into 'data' when not busy.
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*/
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XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
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/**
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* @param phy_addr PHY address
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* @param reg_addr Register address
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* @param data The data to write
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* @return XMC_ECAT_STATUS_t EtherCAT Write PHY API return status
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*
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* \par<b>Description: </b><br>
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* Write a PHY register <br>
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*
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* \par
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* The function reads a PHY register. It essentially writes the data and polls
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* the busy bit until it is no longer busy.
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*/
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XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
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/**
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* @param port_ctrl Port control configuration
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* @return None
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*
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* \par<b>Description: </b><br>
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* Set port control configuration <br>
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*
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* \par
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* The function sets the port control by writing the configuration into the ECAT CON register.
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*
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*/
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__STATIC_INLINE void XMC_ECAT_SetPortControl(const XMC_ECAT_PORT_CTRL_t port_ctrl)
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{
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ECAT0_CON->CON = (uint32_t)port_ctrl.common.raw;
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ECAT0_CON->CONP0 = (uint32_t)port_ctrl.port0.raw;
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ECAT0_CON->CONP1 = (uint32_t)port_ctrl.port1.raw;
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}
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/**
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* @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enable ECAT event(s) <br>
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*
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* \par
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* The function can be used to enable ECAT event(s).
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*/
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void XMC_ECAT_EnableEvent(uint32_t event);
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/**
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* @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disable an ECAT event(s) <br>
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*
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* \par
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* The function can be used to disable ECAT event(s).
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*/
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void XMC_ECAT_DisableEvent(uint32_t event);
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/**
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* @param None
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* @return uint32_t Event status
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*
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* \par<b>Description: </b><br>
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* Get event status <br>
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*
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* \par
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* The function returns the ECAT status and interrupt status as a single word. The user
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* can then check the status of the events by using an appropriate mask.
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*/
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uint32_t XMC_ECAT_GetEventStatus(void);
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/**
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* @param channel SyncManager channel number.
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disables selected SyncManager channel <br>
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*
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* \par
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* Sets bit 0 of the corresponding 0x807 register.
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*/
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void XMC_ECAT_DisableSyncManChannel(const uint8_t channel);
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/**
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* @param channel SyncManager channel number.
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enables selected SyncManager channel <br>
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*
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* \par
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* Resets bit 0 of the corresponding 0x807 register.
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*/
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void XMC_ECAT_EnableSyncManChannel(const uint8_t channel);
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/**
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* @param None
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* @return uint16_t Content of register 0x220-0x221
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*
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* \par<b>Description: </b><br>
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* Get content of AL event register <br>
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*
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* \par
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* Get the first two bytes of the AL Event register (0x220-0x221).
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*/
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__STATIC_INLINE uint16_t XMC_ECAT_GetALEventRegister(void)
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{
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return ((uint16_t)ECAT0->AL_EVENT_REQ);
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}
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/**
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* @param None
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* @return uint16_t Content of register 0x220-0x221
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*
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* \par<b>Description: </b><br>
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* Get content of AL event register <br>
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*
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* \par
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* Get the first two bytes of the AL Event register (0x220-0x221).
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*/
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__STATIC_INLINE uint16_t XMC_ECAT_GetALEventMask(void)
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{
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return ((uint16_t)ECAT0->AL_EVENT_MASK);
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}
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/**
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* @param intMask Interrupt mask (disabled interrupt shall be zero)
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* @return None
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*
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* \par<b>Description: </b><br>
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* Sets application event mask register <br>
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*
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* \par
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* Performs a logical OR with the AL Event Mask register (0x0204 : 0x0205).
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*/
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__STATIC_INLINE void XMC_ECAT_SetALEventMask(uint16_t intMask)
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{
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ECAT0->AL_EVENT_MASK |= (uint32_t)(intMask);
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}
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* defined (ECAT) */
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#endif /* XMC_ECAT_H */
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