199 lines
7.2 KiB
C
199 lines
7.2 KiB
C
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/**
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* @file xmc_ecat.c
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* @date 2015-10-21
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.12 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-12-27:
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* - Add clock gating control in enable/disable APIs
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*
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* 2015-10-21:
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* - Initial Version
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*
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* @endcond
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*/
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/*******************************************************************************
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* HEADER FILES
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*******************************************************************************/
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#include <xmc_ecat.h>
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#if defined (ECAT0)
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#include <xmc_scu.h>
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/*******************************************************************************
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* MACROS
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*******************************************************************************/
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/*******************************************************************************
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* API IMPLEMENTATION
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*******************************************************************************/
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/* The function defines the access state to the MII management for the PDI interface*/
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__STATIC_INLINE void XMC_ECAT_lRequestPhyAccessToMII(void)
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{
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ECAT0->MII_PDI_ACS_STATE |= 0x01;
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}
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/* EtherCAT module clock ungating and deassert reset API (Enables ECAT) */
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void XMC_ECAT_Enable(void)
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{
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XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0);
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XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0);
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while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true){}
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}
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/* EtherCAT module clock gating and assert reset API (Disables ECAT)*/
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void XMC_ECAT_Disable(void)
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{
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XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0);
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while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false){}
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XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0);
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}
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/* EtherCAT initialization function */
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void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config)
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{
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XMC_ECAT_Enable();
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/* The process memory is not accessible until the ESC Configuration Area is loaded successfully. */
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/* words 0x0-0x3 */
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ECAT0->EEP_DATA[0U] = config->dword[0U];
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ECAT0->EEP_DATA[1U] = config->dword[1U];
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ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos);
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/* words 0x4-0x7 */
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ECAT0->EEP_DATA[0U] = config->dword[2U];
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ECAT0->EEP_DATA[1U] = config->dword[3U];
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ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos);
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while (ECAT0->EEP_CONT_STAT & ECAT_EEP_CONT_STAT_L_STAT_Msk)
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{
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/* Wait until the EEPROM_Loaded signal is active */
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}
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}
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/* EtherCAT application event enable API */
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void XMC_ECAT_EnableEvent(uint32_t event)
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{
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ECAT0->AL_EVENT_MASK |= event;
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}
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/* EtherCAT application event disable API */
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void XMC_ECAT_DisableEvent(uint32_t event)
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{
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ECAT0->AL_EVENT_MASK &= ~event;
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}
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/* EtherCAT application event status reading API */
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uint32_t XMC_ECAT_GetEventStatus(void)
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{
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return (ECAT0->AL_EVENT_REQ);
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}
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/* EtherCAT SyncManager channel disable function*/
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void XMC_ECAT_DisableSyncManChannel(const uint8_t channel)
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{
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((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U;
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}
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/* EtherCAT SyncManager channel enable function*/
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void XMC_ECAT_EnableSyncManChannel(const uint8_t channel)
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{
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((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U);
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}
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/* EtherCAT PHY register read function*/
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XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
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{
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XMC_ECAT_STATUS_t status;
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XMC_ECAT_lRequestPhyAccessToMII();
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ECAT0->MII_PHY_ADR = phy_addr;
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ECAT0->MII_PHY_REG_ADR = reg_addr;
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ECAT0->MII_CONT_STAT |= 0x0100U; /* read instruction */
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while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){}
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if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U)
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{
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ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */
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status = XMC_ECAT_STATUS_ERROR;
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}
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else
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{
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*data = (uint16_t)ECAT0->MII_PHY_DATA;
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status = XMC_ECAT_STATUS_OK;
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}
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return status;
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}
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/* EtherCAT PHY register write function*/
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XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
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{
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XMC_ECAT_STATUS_t status;
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XMC_ECAT_lRequestPhyAccessToMII();
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ECAT0->MII_PHY_ADR = phy_addr;
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ECAT0->MII_PHY_REG_ADR = reg_addr;
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ECAT0->MII_PHY_DATA = data;
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ECAT0->MII_CONT_STAT |= 0x0200U; /* write instruction */
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while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){}
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if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U)
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{
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ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */
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status = XMC_ECAT_STATUS_ERROR;
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}
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else
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{
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status = XMC_ECAT_STATUS_OK;
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}
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return status;
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}
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#endif
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