300 lines
12 KiB
C
300 lines
12 KiB
C
/**
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* @file xmc_eth_phy_dp83848.c
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* @date 2015-12-15
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.12 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-06-20:
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* - Initial <br>
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*
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* 2015-12-15:
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* - Added Reset and exit power down
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* - Reset function called in Init function
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*
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* @endcond
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*/
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/*******************************************************************************
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* HEADER FILES
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*******************************************************************************/
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#if defined(XMC_ETH_PHY_DP83848C)
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#include <xmc_eth_phy.h>
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/*******************************************************************************
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* MACROS
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*******************************************************************************/
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/* Basic Registers */
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#define REG_BMCR (0x00U) /* Basic Mode Control Register */
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#define REG_BMSR (0x01U) /* Basic Mode Status Register */
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#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */
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#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */
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#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */
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#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */
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#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */
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#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */
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#define REG_RBR (0x17U) /* RMII and Bypass Register */
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/* Extended Registers */
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#define REG_PHYSTS (0x10U) /* Status Register */
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/* Basic Mode Control Register */
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#define BMCR_RESET (0x8000U) /* Software Reset */
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#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */
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#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */
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#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */
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#define BMCR_POWER_DOWN (0x0800U) /* Power Down */
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#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */
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#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */
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#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */
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#define BMCR_COL_TEST (0x0080U) /* Collision Test */
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/* Basic Mode Status Register */
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#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */
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#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */
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#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */
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#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */
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#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */
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#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */
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#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */
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#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */
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#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */
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#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */
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#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */
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#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */
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/* RMII and Bypass Register */
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#define RBR_RMII_MODE (0x0020U) /* Reduced MII Mode */
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/* PHY Identifier Registers */
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#define PHY_ID1 0x2000 /* DP83848C Device Identifier MSB */
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#define PHY_ID2 0x5C90 /* DP83848C Device Identifier LSB */
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/* PHY Status Register */
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#define PHYSTS_MDI_X 0x4000 /* MDI-X mode enabled by Auto-Negot. */
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#define PHYSTS_REC_ERR 0x2000 /* Receive Error Latch */
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#define PHYSTS_POL_STAT 0x1000 /* Polarity Status */
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#define PHYSTS_FC_SENSE 0x0800 /* False Carrier Sense Latch */
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#define PHYSTS_SIG_DET 0x0400 /* 100Base-TX Signal Detect */
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#define PHYSTS_DES_LOCK 0x0200 /* 100Base-TX Descrambler Lock */
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#define PHYSTS_PAGE_REC 0x0100 /* Link Code Word Page Received */
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#define PHYSTS_MII_INT 0x0080 /* MII Interrupt Pending */
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#define PHYSTS_REM_FAULT 0x0040 /* Remote Fault */
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#define PHYSTS_JABBER_DET 0x0020 /* Jabber Detect */
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#define PHYSTS_ANEG_COMPL 0x0010 /* Auto Negotiation Complete */
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#define PHYSTS_LOOPBACK 0x0008 /* Loopback Status */
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#define PHYSTS_DUPLEX 0x0004 /* Duplex Status (1=Full duplex) */
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#define PHYSTS_SPEED 0x0002 /* Speed10 Status (1=10MBit/s) */
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#define PHYSTS_LINK_STAT 0x0001 /* Link Status (1=established) */
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/*******************************************************************************
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* API IMPLEMENTATION
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*******************************************************************************/
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/* Check if the device identifier is valid */
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static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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uint16_t phy_id1;
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uint16_t phy_id2;
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XMC_ETH_PHY_STATUS_t status;
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/* Check Device Identification. */
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if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) &&
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(XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK))
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{
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if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2))
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{
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status = XMC_ETH_PHY_STATUS_OK;
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}
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else
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{
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status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID;
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}
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}
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else
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{
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status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT;
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}
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return (int32_t)status;
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}
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/* PHY initialize */
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int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config)
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{
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int32_t status;
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uint16_t reg_val;
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status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr);
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if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
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{
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status = XMC_ETH_PHY_Reset(eth_mac, phy_addr);
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if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
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{
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reg_val = 0U;
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if (config->speed == XMC_ETH_LINK_SPEED_100M)
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{
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reg_val |= BMCR_SPEED_SEL;
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}
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if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL)
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{
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reg_val |= BMCR_DUPLEX;
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}
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if (config->enable_auto_negotiate == true)
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{
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reg_val |= BMCR_ANEG_EN;
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}
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if (config->enable_loop_back == true)
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{
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reg_val |= BMCR_LOOPBACK;
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}
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status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_val);
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if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
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{
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/* Configure interface mode */
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switch (config->interface)
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{
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case XMC_ETH_LINK_INTERFACE_MII:
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reg_val = 0x0001;
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break;
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case XMC_ETH_LINK_INTERFACE_RMII:
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reg_val = RBR_RMII_MODE | 0x0001;
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break;
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}
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status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_RBR, reg_val);
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}
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}
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}
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return status;
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}
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/* Reset */
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int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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int32_t status;
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uint16_t reg_bmcr;
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/* Reset PHY*/
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status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET);
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if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
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{
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/* Wait for the reset to complete */
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do
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{
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status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr);
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} while ((reg_bmcr & BMCR_RESET) != 0);
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}
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return status;
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}
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/* Initiate power down */
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int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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int32_t status;
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uint16_t reg_bmcr;
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status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr);
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if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
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{
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reg_bmcr |= BMCR_POWER_DOWN;
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status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
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}
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return status;
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}
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/* Exit power down */
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int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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int32_t status;
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uint16_t reg_bmcr;
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status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr);
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if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
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{
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reg_bmcr &= ~BMCR_POWER_DOWN;
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status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
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}
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return status;
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}
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/* Get link status */
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XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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uint16_t val;
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XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
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return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN);
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}
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/* Get link speed */
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XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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uint16_t val;
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XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val);
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return (XMC_ETH_LINK_SPEED_t)((val & PHYSTS_SPEED) ? XMC_ETH_LINK_SPEED_10M : XMC_ETH_LINK_SPEED_100M);
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}
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/* Get link duplex settings */
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XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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uint16_t val;
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XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val);
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return (XMC_ETH_LINK_DUPLEX_t)((val & PHYSTS_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF);
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}
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bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
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{
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uint16_t val;
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XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
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return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL);
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}
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#endif // defined(XMC_ETH_PHY_DP83848C)
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