403 lines
15 KiB
C
403 lines
15 KiB
C
/**
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* @file xmc_i2c.c
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* @date 2015-10-02
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.12 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-02-20:
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* - Initial <br>
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*
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* 2015-05-20:
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- Modified XMC_I2C_CH_Stop() API for not setting to IDLE the channel if it is busy <br>
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*
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* 2015-06-20:
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* - Removed GetDriverVersion API <br>
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*
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* 2015-08-14:
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* - updated the XMC_I2C_CH_SetBaudrate API to support dynamic change from 400K to low frequencies <br>
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*
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* 2015-09-01:
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* - Modified XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() for supporting multiple events configuration <br>
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*
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* 2015-10-02:
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* - Fixed 10bit addressing
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*
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* @endcond
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*
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*/
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/*********************************************************************************************************************
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* HEADER FILES
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*********************************************************************************************************************/
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#include <xmc_i2c.h>
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/*********************************************************************************************************************
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* MACROS
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*********************************************************************************************************************/
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#define XMC_I2C_7BIT_ADDR_Pos (8U) /**< 7-bit address position */
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#define TRANSMISSION_MODE (3U) /**< The shift control signal is considered active
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without referring to the actual signal level. Data
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frame transfer is possible after each edge of the signal.*/
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#define WORDLENGTH (7U) /**< Word length */
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#define SET_TDV (1U) /**< Transmission data valid */
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#define XMC_I2C_10BIT_ADDR_MASK (0x7C00U) /**< Address mask for 10-bit mode */
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/*********************************************************************************************************************
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* ENUMS
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*********************************************************************************************************************/
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typedef enum XMC_I2C_CH_TDF
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{
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XMC_I2C_CH_TDF_MASTER_SEND = 0U,
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XMC_I2C_CH_TDF_SLAVE_SEND = (uint32_t)1U << 8U,
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XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK = (uint32_t)2U << 8U,
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XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK = (uint32_t)3U << 8U,
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XMC_I2C_CH_TDF_MASTER_START = (uint32_t)4U << 8U,
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XMC_I2C_CH_TDF_MASTER_RESTART = (uint32_t)5U << 8U,
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XMC_I2C_CH_TDF_MASTER_STOP = (uint32_t)6U << 8U
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} XMC_I2C_CH_TDF_t;
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typedef enum XMC_I2C_CH_MAX_SPEED
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{
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XMC_I2C_CH_MAX_SPEED_STANDARD = 100000U,
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XMC_I2C_CH_MAX_SPEED_FAST = 400000U
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} XMC_I2C_CH_MAX_SPEED_t;
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typedef enum XMC_I2C_CH_CLOCK_OVERSAMPLING
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{
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XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD = 10U,
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XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST = 25U
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} XMC_I2C_CH_CLOCK_OVERSAMPLINGS_t;
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/*********************************************************************************************************************
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* API IMPLEMENTATION
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*********************************************************************************************************************/
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/* Initializes the USIC channel by setting the data format, slave address, baudrate, transfer buffer */
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void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config)
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{
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XMC_USIC_CH_Enable(channel);
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/* Data format configuration */
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channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision mode */
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((uint32_t)WORDLENGTH << (uint32_t)USIC_CH_SCTR_WLE_Pos) | /* 8 data bits */
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USIC_CH_SCTR_FLE_Msk | /* unlimited data flow */
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USIC_CH_SCTR_SDIR_Msk | /* MSB shifted first */
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USIC_CH_SCTR_PDL_Msk; /* Passive Data Level */
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XMC_I2C_CH_SetSlaveAddress(channel, config->address);
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(void)XMC_I2C_CH_SetBaudrate(channel, config->baudrate);
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/* Enable transfer buffer */
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channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk;
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/* Clear status flags */
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channel->PSCR = 0xFFFFFFFFU;
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/* Disable parity generation */
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channel->CCR = 0x0U;
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}
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/* Sets the slave address */
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void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address)
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{
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if ((address & XMC_I2C_10BIT_ADDR_MASK) == XMC_I2C_10BIT_ADDR_GROUP)
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{
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channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U);
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}
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else
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{
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channel->PCR_IICMode = ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos;
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}
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}
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/* Read the slave address */
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uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel)
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{
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uint32_t address = channel->PCR_IICMode & (uint32_t)USIC_CH_PCR_IICMode_SLAD_Msk;
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if ((address & 0xffU) == 0U)
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{
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address = address >> XMC_I2C_7BIT_ADDR_Pos;
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}
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else
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{
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address = (address & 0xffU) | ((address >> 1) & 0x0300U);
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}
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return (uint16_t)address;
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}
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/* Sets the baudrate and oversampling based on standard speed or fast speed */
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XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate)
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{
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XMC_I2C_CH_STATUS_t status;
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status = XMC_I2C_CH_STATUS_ERROR;
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if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD)
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{
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channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk;
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if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD) == XMC_USIC_CH_STATUS_OK)
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{
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status = XMC_I2C_CH_STATUS_OK;
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}
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}
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else if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_FAST)
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{
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channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_STIM_Msk;
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if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST) == XMC_USIC_CH_STATUS_OK)
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{
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status = XMC_I2C_CH_STATUS_OK;
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}
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}
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else
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{
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status = XMC_I2C_CH_STATUS_ERROR;
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}
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return status;
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}
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/* Sends master start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command)
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{
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uint32_t temp;
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temp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_START;
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if (command == XMC_I2C_CH_CMD_READ)
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{
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temp |= 0x1U;
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}
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = temp;
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}
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else
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{
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channel->IN[0U] = temp;
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}
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}
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/* Sends master repeated start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command)
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{
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uint32_t tmp;
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tmp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_RESTART;
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if (command == XMC_I2C_CH_CMD_READ)
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{
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tmp |= 0x1U;
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}
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = tmp;
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}
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else
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{
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channel->IN[0U] = tmp;
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}
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}
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/* Sends master stop command to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel)
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{
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP;
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}
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else
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{
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channel->IN[0U] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP;
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}
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}
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/* Sends master send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data)
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{
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data;
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}
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else
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{
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channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data;
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}
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}
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/* Sends slave send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data)
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{
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data;
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}
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else
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{
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channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data;
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}
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}
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/* Sends master receive ack command to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel)
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{
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK;
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}
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else
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{
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channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK;
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}
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}
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/* Sends master receive nack command to IN/TBUF register based on FIFO/non-FIFO modes. */
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void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel)
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{
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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/* check TDV, wait until TBUF is ready */
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}
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/* clear PSR_TBIF */
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XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK;
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}
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else
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{
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channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK;
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}
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}
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/* Reads the data from RBUF if FIFO size is 0 otherwise from OUTR. */
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uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel)
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{
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uint8_t retval;
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/* Check FIFO size */
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if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
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{
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retval = (uint8_t)channel->RBUF;
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}
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else
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{
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retval = (uint8_t)channel->OUTR;
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}
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return retval;
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}
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/* Sets the operating mode of USIC to IDLE */
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XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel)
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{
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XMC_I2C_CH_STATUS_t status = XMC_I2C_CH_STATUS_OK;
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if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
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{
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status = XMC_I2C_CH_STATUS_BUSY;
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}
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else
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{
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/* USIC channel in IDLE mode */
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XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
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}
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return status;
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}
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void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
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{
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channel->CCR |= (event&0x1fc00U);
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channel->PCR_IICMode |= ((event) & 0x41fc0000U);
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}
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void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
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{
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channel->CCR &= (uint32_t)~(event&0x1fc00U);
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channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U);
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}
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