280 lines
11 KiB
C
280 lines
11 KiB
C
/**
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* @file xmc_spi.c
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* @date 2015-11-04
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.8 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2016, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-02-20:
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* - Initial <br>
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*
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* 2015-05-20:
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* - Modified XMC_SPI_CH_Stop() API for not setting to IDLE the channel if it is busy
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* - Modified XMC_SPI_CH_SetInterwordDelay() implementation in order to gain accuracy <br>
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*
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* 2015-06-20:
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* - Removed GetDriverVersion API <br>
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*
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* 2015-09-01:
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* - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration <br>
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*
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* 2015-11-04:
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* - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag <br>
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* @endcond
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*
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*/
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/**
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*
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* @brief SPI driver for XMC microcontroller family
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*
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*/
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/*********************************************************************************************************************
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* HEADER FILES
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********************************************************************************************************************/
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#include <xmc_scu.h>
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#include <xmc_spi.h>
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/*********************************************************************************************************************
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* MACROS
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********************************************************************************************************************/
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#define XMC_SPI_CH_OVERSAMPLING (2UL)
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/*********************************************************************************************************************
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* API IMPLEMENTATION
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********************************************************************************************************************/
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/* Initializes the selected SPI channel with the config structure. */
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void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config)
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{
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XMC_USIC_CH_Enable(channel);
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if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER)
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{
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/* Configure baud rate */
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(void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING);
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}
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/* Configuration of USIC Shift Control */
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/* Transmission Mode (TRM) = 1 */
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/* Passive Data Level (PDL) = 1 */
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channel->SCTR = USIC_CH_SCTR_PDL_Msk |
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(0x1UL << USIC_CH_SCTR_TRM_Pos) |
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(0x3fUL << USIC_CH_SCTR_FLE_Pos)|
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(0x7UL << USIC_CH_SCTR_WLE_Pos);
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/* Configuration of USIC Transmit Control/Status Register */
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/* TBUF Data Enable (TDEN) = 1 */
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/* TBUF Data Single Shot Mode (TDSSM) = 1 */
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channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk |
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(0x01UL << USIC_CH_TCSR_TDEN_Pos) |
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USIC_CH_TCSR_TDSSM_Msk);
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if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER)
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{
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/* Configuration of Protocol Control Register */
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channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk |
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USIC_CH_PCR_SSCMode_SELCTR_Msk |
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(uint32_t)config->selo_inversion |
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USIC_CH_PCR_SSCMode_FEM_Msk);
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}
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/* Clear protocol status */
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channel->PSCR = 0xFFFFFFFFUL;
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/* Set parity settings */
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channel->CCR = (uint32_t)config->parity_mode;
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}
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XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate)
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{
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XMC_SPI_CH_STATUS_t status;
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status = XMC_SPI_CH_STATUS_ERROR;
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if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
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{
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if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
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{
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status = XMC_SPI_CH_STATUS_OK;
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}
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}
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return status;
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}
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/* Enable the selected slave signal by setting (SELO) bits in PCR register. */
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void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave)
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{
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/* Configuration of Protocol Control Register */
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channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk;
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channel->PCR_SSCMode |= (uint32_t)slave;
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}
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/* Disable the slave signals by clearing (SELO) bits in PCR register. */
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void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel)
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{
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XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_MSLS);
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/* Configuration of Protocol Control Register */
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channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk;
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}
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/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */
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void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode)
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{
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channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) |
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(((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk);
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/* Check FIFO size */
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if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
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{
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while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
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{
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}
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XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
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channel->TBUF[mode] = data;
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}
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else
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{
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channel->IN[mode] = data;
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}
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}
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/* Reads the data from the buffers based on the FIFO mode selection. */
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uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
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{
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uint16_t retval;
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/* Check FIFO size */
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if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
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{
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retval = (uint16_t)channel->RBUF;
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}
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else
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{
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retval = (uint16_t)channel->OUTR;
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}
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return retval;
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}
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/* Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields. */
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void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_us)
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{
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uint32_t peripheral_clock;
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uint32_t pdiv;
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uint32_t step;
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uint32_t fFD;
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uint32_t fpdiv;
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uint32_t divider_factor1 = 0U;
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uint32_t divider_factor2 = 32U;
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uint32_t divider_factor1_int = 0U;
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uint32_t divider_factor1_int_min = 4U;
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uint32_t divider_factor1_frac_min =100U;
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uint32_t divider_factor1_frac = 0U;
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uint32_t divider_factor2_temp = 0U;
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peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
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pdiv = (uint32_t)(channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos;
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step = (uint32_t)(channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos;
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fFD = (uint32_t)((peripheral_clock >> 10U) * step);
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fpdiv= fFD/(1U+pdiv);
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if(tinterword_delay_us < (128000000/fpdiv))
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{
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for(divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp)
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{
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divider_factor1 = (tinterword_delay_us*fpdiv)/(divider_factor2_temp*10000);
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divider_factor1_frac = divider_factor1%100U;
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if(divider_factor1_frac > 50)
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{
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divider_factor1_int = (divider_factor1/100U)+1;
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divider_factor1_frac = (divider_factor1_int*100)-divider_factor1;
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}
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else
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{
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divider_factor1_int = (divider_factor1/100U);
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}
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if ((divider_factor1_int < 5U) && (divider_factor1_int > 0) && (divider_factor1_frac < divider_factor1_frac_min))
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{
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divider_factor1_frac_min = divider_factor1_frac;
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divider_factor1_int_min = divider_factor1_int;
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divider_factor2= divider_factor2_temp;
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}
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}
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}
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channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk |
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USIC_CH_PCR_SSCMode_PCTQ1_Msk |
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USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) |
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(((divider_factor1_int_min - 1) << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_PCTQ1_Msk) |
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(((divider_factor2 - 1 ) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_DCTQ1_Msk);
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}
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XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel)
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{
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XMC_SPI_CH_STATUS_t status = XMC_SPI_CH_STATUS_OK;
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if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
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{
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status = XMC_SPI_CH_STATUS_BUSY;
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}
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else
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{
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/* USIC channel in IDLE mode */
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XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
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}
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return status;
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}
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void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
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{
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channel->CCR |= (event&0x1fc00U);
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channel->PCR_SSCMode |= ((event << 13U) & 0xe000U);
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}
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void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
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{
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channel->CCR &= (uint32_t)~(event&0x1fc00U);
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channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U);
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}
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