608 lines
24 KiB
C
608 lines
24 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_cec.c
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* @author MCD Application Team
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* @version V1.3.0
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* @date 16-January-2014
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Consumer Electronics Control (CEC) peripheral
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* applicable only on STM32F051, STM32F042 and STM32F072 devices:
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* + Initialization and Configuration
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* + Data transfers functions
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* + Interrupts and flags management
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*
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* @verbatim
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==============================================================================
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##### CEC features #####
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==============================================================================
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[..] This device provides some features:
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(#) Supports HDMI-CEC specification 1.4.
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(#) Supports two source clocks(HSI/244 or LSE).
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(#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
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It can genarate an interrupt in the CEC clock domain that the CPU
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wakes up from the low power mode.
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(#) Configurable Signal Free Time before of transmission start. The
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number of nominal data bit periods waited before transmission can be
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ruled by Hardware or Software.
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(#) Configurable Peripheral Address (multi-addressing configuration).
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(#) Supports listen mode.The CEC Messages addressed to different destination
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can be received without interfering with CEC bus when Listen mode option is enabled.
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(#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
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(#) Error detection with configurable error bit generation.
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(#) Arbitration lost error in the case of two CEC devices starting at the same time.
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##### How to use this driver #####
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==============================================================================
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[..] This driver provides functions to configure and program the CEC device,
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follow steps below:
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(#) The source clock can be configured using:
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(++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default)
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(++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
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(#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
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(#) Peripherals alternate function.
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(++) Connect the pin to the desired peripherals' Alternate Function (AF) using
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GPIO_PinAFConfig() function.
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(++) Configure the desired pin in alternate function by:
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GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
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(++) Select the type open-drain and output speed via GPIO_OType
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and GPIO_Speed members.
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(++) Call GPIO_Init() function.
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(#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation
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and Bit error generation using the CEC_Init() function.
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The function CEC_Init() must be called when the CEC peripheral is disabled.
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(#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
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(#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
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(#) Enable the NVIC and the corresponding interrupt using the function
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CEC_ITConfig() if you need to use interrupt mode.
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CEC_ITConfig() must be called before enabling the CEC peripheral.
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(#) Enable the CEC using the CEC_Cmd() function.
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(#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
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(#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage()
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(#) Transmit single data through the CEC peripheral using CEC_SendDataByte()
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and Receive the last transmitted byte using CEC_ReceiveDataByte().
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(#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
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[..]
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(@) If the listen mode is enabled, Stop reception generation and Bit error generation
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must be in reset state.
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(@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
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must be called before CEC_StartOfMessage().
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@endverbatim
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_cec.h"
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#include "stm32f0xx_rcc.h"
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/** @addtogroup STM32F0xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup CEC
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* @brief CEC driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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#define BROADCAST_ADDRESS ((uint32_t)0x0000F)
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#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup CEC_Private_Functions
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* @{
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*/
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/** @defgroup CEC_Group1 Initialization and Configuration functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and Configuration functions #####
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===============================================================================
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[..] This section provides functions allowing to initialize:
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(+) CEC own addresses
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(+) CEC Signal Free Time
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(+) CEC Rx Tolerance
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(+) CEC Stop Reception
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(+) CEC Bit Rising Error
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(+) CEC Long Bit Period Error
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[..] This section provides also a function to configure the CEC peripheral in Listen Mode.
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Messages addressed to different destination can be received when Listen mode is
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enabled without interfering with CEC bus.
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the CEC peripheral registers to their default reset values.
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* @param None
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* @retval None
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*/
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void CEC_DeInit(void)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
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}
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/**
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* @brief Initializes the CEC peripheral according to the specified parameters
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* in the CEC_InitStruct.
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* @note The CEC parameters must be configured before enabling the CEC peripheral.
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* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
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* the configuration information for the specified CEC peripheral.
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* @retval None
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*/
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void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
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assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
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assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
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assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
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assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
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assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
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assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
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/* Get the CEC CFGR value */
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tmpreg = CEC->CFGR;
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/* Clear CFGR bits */
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tmpreg &= CFGR_CLEAR_MASK;
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/* Configure the CEC peripheral */
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tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
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CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError |
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CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
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CEC_InitStruct->CEC_SFTOption);
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/* Write to CEC CFGR register */
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CEC->CFGR = tmpreg;
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}
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/**
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* @brief Fills each CEC_InitStruct member with its default value.
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* @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will
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* be initialized.
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* @retval None
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*/
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void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
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{
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CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
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CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
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CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
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CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
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CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
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CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
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CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
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}
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/**
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* @brief Enables or disables the CEC peripheral.
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* @param NewState: new state of the CEC peripheral.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void CEC_Cmd(FunctionalState NewState)
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{
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the CEC peripheral */
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CEC->CR |= CEC_CR_CECEN;
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}
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else
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{
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/* Disable the CEC peripheral */
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CEC->CR &= ~CEC_CR_CECEN;
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}
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}
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/**
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* @brief Enables or disables the CEC Listen Mode.
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* @param NewState: new state of the Listen Mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void CEC_ListenModeCmd(FunctionalState NewState)
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{
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the Listen Mode */
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CEC->CFGR |= CEC_CFGR_LSTN;
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}
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else
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{
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/* Disable the Listen Mode */
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CEC->CFGR &= ~CEC_CFGR_LSTN;
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}
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}
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/**
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* @brief Defines the Own Address of the CEC device.
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* @param CEC_OwnAddress: The CEC own address.
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* @retval None
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*/
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void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
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{
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uint32_t tmp =0x00;
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/* Check the parameters */
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assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
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tmp = 1 <<(CEC_OwnAddress + 16);
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/* Set the CEC own address */
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CEC->CFGR |= tmp;
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}
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/**
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* @brief Clears the Own Address of the CEC device.
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* @param CEC_OwnAddress: The CEC own address.
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* @retval None
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*/
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void CEC_OwnAddressClear(void)
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{
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/* Set the CEC own address */
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CEC->CFGR = 0x0;
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}
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/**
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* @}
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*/
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/** @defgroup CEC_Group2 Data transfers functions
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* @brief Data transfers functions
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*
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@verbatim
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===============================================================================
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##### Data transfers functions #####
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===============================================================================
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[..] This section provides functions allowing the CEC data transfers.The read
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access of the CEC_RXDR register can be done using the CEC_ReceiveData()function
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and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be
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done using CEC_SendData() function.
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@endverbatim
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* @{
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*/
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/**
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* @brief Transmits single data through the CEC peripheral.
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* @param Data: the data to transmit.
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* @retval None
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*/
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void CEC_SendData(uint8_t Data)
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{
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/* Transmit Data */
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CEC->TXDR = Data;
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}
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/**
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* @brief Returns the most recent received data by the CEC peripheral.
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* @param None
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* @retval The received data.
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*/
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uint8_t CEC_ReceiveData(void)
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{
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/* Receive Data */
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return (uint8_t)(CEC->RXDR);
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}
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/**
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* @brief Starts a new message.
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* @param None
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* @retval None
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*/
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void CEC_StartOfMessage(void)
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{
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/* Starts of new message */
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CEC->CR |= CEC_CR_TXSOM;
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}
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/**
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* @brief Transmits message with an EOM bit.
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* @param None
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* @retval None
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*/
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void CEC_EndOfMessage(void)
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{
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/* The data byte will be transmitted with an EOM bit */
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CEC->CR |= CEC_CR_TXEOM;
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}
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/**
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* @}
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*/
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/** @defgroup CEC_Group3 Interrupts and flags management functions
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* @brief Interrupts and flags management functions
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*
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@verbatim
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===============================================================================
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##### Interrupts and flags management functions #####
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===============================================================================
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[..] This section provides functions allowing to configure the CEC Interrupts
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sources and check or clear the flags or pending bits status.
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[..] The user should identify which mode will be used in his application to manage
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the communication: Polling mode or Interrupt mode.
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[..] In polling mode, the CEC can be managed by the following flags:
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(+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
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(+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode.
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The initiator detects low impedance in the CEC line.
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(+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode.
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The transmission is enabled while the software has not yet
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loaded any value into the TXDR register.
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(+) CEC_FLAG_TXEND : to indicate the end of successful transmission.
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(+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR.
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(+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
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starting at the same time.
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(+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
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(+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode.
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(+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode.
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(+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode.
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(+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
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A byte is not yet received while a new byte is stored in the RXDR register.
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(+) CEC_FLAG_RXEND : to indicate the end Of reception
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(+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and
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stored into the RXDR buffer.
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[..]
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(@)In this Mode, it is advised to use the following functions:
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FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
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void CEC_ClearFlag(uint16_t CEC_FLAG);
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[..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
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(+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge
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(+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
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(+) CEC_IT_TXERR : to indicate an error occurs during transmission mode.
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The initiator detects low impedance in the CEC line.
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(+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode.
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The transmission is enabled while the software has not yet
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loaded any value into the TXDR register.
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(+) CEC_IT_TXEND : to indicate the end of successful transmission.
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(+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register.
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(+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
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starting at the same time.
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(+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
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(+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode.
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(+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode.
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(+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode.
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(+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
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A byte is not yet received while a new byte is stored in the RXDR register.
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(+) CEC_IT_RXEND : to indicate the end Of reception
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(+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and
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stored into the RXDR buffer.
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[..]
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(@)In this Mode it is advised to use the following functions:
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void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
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ITStatus CEC_GetITStatus(uint16_t CEC_IT);
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void CEC_ClearITPendingBit(uint16_t CEC_IT);
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@endverbatim
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* @{
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*/
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/**
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* @brief Enables or disables the selected CEC interrupts.
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* @param CEC_IT: specifies the CEC interrupt source to be enabled.
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* This parameter can be any combination of the following values:
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* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
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* @arg CEC_IT_TXERR: Tx Error.
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* @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
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* @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
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* @arg CEC_IT_TXBR: Tx-Byte Request.
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* @arg CEC_IT_ARBLST: Arbitration Lost
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* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
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* @arg CEC_IT_LBPE: Rx Long period Error
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* @arg CEC_IT_SBPE: Rx Short period Error
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* @arg CEC_IT_BRE: Rx Bit Rising Error
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* @arg CEC_IT_RXOVR: Rx Overrun.
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* @arg CEC_IT_RXEND: End Of Reception
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* @arg CEC_IT_RXBR: Rx-Byte Received
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* @param NewState: new state of the selected CEC interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
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{
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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assert_param(IS_CEC_IT(CEC_IT));
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if (NewState != DISABLE)
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{
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/* Enable the selected CEC interrupt */
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CEC->IER |= CEC_IT;
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}
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else
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{
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CEC_IT =~CEC_IT;
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/* Disable the selected CEC interrupt */
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CEC->IER &= CEC_IT;
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}
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}
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/**
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* @brief Gets the CEC flag status.
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* @param CEC_FLAG: specifies the CEC flag to check.
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* This parameter can be one of the following values:
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* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
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* @arg CEC_FLAG_TXERR: Tx Error.
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* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
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* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
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* @arg CEC_FLAG_TXBR: Tx-Byte Request.
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* @arg CEC_FLAG_ARBLST: Arbitration Lost
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* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
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* @arg CEC_FLAG_LBPE: Rx Long period Error
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* @arg CEC_FLAG_SBPE: Rx Short period Error
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* @arg CEC_FLAG_BRE: Rx Bit Rissing Error
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* @arg CEC_FLAG_RXOVR: Rx Overrun.
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* @arg CEC_FLAG_RXEND: End Of Reception.
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* @arg CEC_FLAG_RXBR: Rx-Byte Received.
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* @retval The new state of CEC_FLAG (SET or RESET)
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|
*/
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|
FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG)
|
|
{
|
|
FlagStatus bitstatus = RESET;
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|
|
|
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
|
|
|
|
/* Check the status of the specified CEC flag */
|
|
if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
|
|
{
|
|
/* CEC flag is set */
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
/* CEC flag is reset */
|
|
bitstatus = RESET;
|
|
}
|
|
|
|
/* Return the CEC flag status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the CEC's pending flags.
|
|
* @param CEC_FLAG: specifies the flag to clear.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
|
* @arg CEC_FLAG_TXERR: Tx Error
|
|
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
|
|
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
|
* @arg CEC_FLAG_TXBR: Tx-Byte Request
|
|
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
|
* @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge
|
|
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
|
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
|
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
|
* @arg CEC_FLAG_RXOVR: Rx Overrun
|
|
* @arg CEC_FLAG_RXEND: End Of Reception
|
|
* @arg CEC_FLAG_RXBR: Rx-Byte Received
|
|
* @retval None
|
|
*/
|
|
void CEC_ClearFlag(uint32_t CEC_FLAG)
|
|
{
|
|
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
|
|
|
|
/* Clear the selected CEC flag */
|
|
CEC->ISR = CEC_FLAG;
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified CEC interrupt has occurred or not.
|
|
* @param CEC_IT: specifies the CEC interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
|
|
* @arg CEC_IT_TXERR: Tx Error.
|
|
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
|
|
* @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
|
|
* @arg CEC_IT_TXBR: Tx-Byte Request.
|
|
* @arg CEC_IT_ARBLST: Arbitration Lost.
|
|
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
|
|
* @arg CEC_IT_LBPE: Rx Long period Error.
|
|
* @arg CEC_IT_SBPE: Rx Short period Error.
|
|
* @arg CEC_IT_BRE: Rx Bit Rising Error.
|
|
* @arg CEC_IT_RXOVR: Rx Overrun.
|
|
* @arg CEC_IT_RXEND: End Of Reception.
|
|
* @arg CEC_IT_RXBR: Rx-Byte Received
|
|
* @retval The new state of CEC_IT (SET or RESET).
|
|
*/
|
|
ITStatus CEC_GetITStatus(uint16_t CEC_IT)
|
|
{
|
|
ITStatus bitstatus = RESET;
|
|
uint32_t enablestatus = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CEC_GET_IT(CEC_IT));
|
|
|
|
/* Get the CEC IT enable bit status */
|
|
enablestatus = (CEC->IER & CEC_IT);
|
|
|
|
/* Check the status of the specified CEC interrupt */
|
|
if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
|
|
{
|
|
/* CEC interrupt is set */
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
/* CEC interrupt is reset */
|
|
bitstatus = RESET;
|
|
}
|
|
|
|
/* Return the CEC interrupt status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the CEC's interrupt pending bits.
|
|
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
|
|
* @arg CEC_IT_TXERR: Tx Error
|
|
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun
|
|
* @arg CEC_IT_TXEND: End of Transmission
|
|
* @arg CEC_IT_TXBR: Tx-Byte Request
|
|
* @arg CEC_IT_ARBLST: Arbitration Lost
|
|
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
|
|
* @arg CEC_IT_LBPE: Rx Long period Error
|
|
* @arg CEC_IT_SBPE: Rx Short period Error
|
|
* @arg CEC_IT_BRE: Rx Bit Rising Error
|
|
* @arg CEC_IT_RXOVR: Rx Overrun
|
|
* @arg CEC_IT_RXEND: End Of Reception
|
|
* @arg CEC_IT_RXBR: Rx-Byte Received
|
|
* @retval None
|
|
*/
|
|
void CEC_ClearITPendingBit(uint16_t CEC_IT)
|
|
{
|
|
assert_param(IS_CEC_IT(CEC_IT));
|
|
|
|
/* Clear the selected CEC interrupt pending bits */
|
|
CEC->ISR = CEC_IT;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|