532 lines
31 KiB
ArmAsm
532 lines
31 KiB
ArmAsm
/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_S32K144.s */
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/* @purpose: GNU Compiler Collection Startup File */
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/* S32K144 */
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/* @version: 2.0 */
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/* @date: 2017-1-10 */
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/* @build: b170107 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
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/* Copyright 2016-2017 NXP */
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/* All rights reserved. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
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/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
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/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
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/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
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/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
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/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
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/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
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/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
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/* THE POSSIBILITY OF SUCH DAMAGE. */
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/*****************************************************************************/
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/* Version: GNU Compiler Collection */
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/*****************************************************************************/
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.syntax unified
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.arch armv7-m
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.section .isr_vector, "a"
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler*/
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.long HardFault_Handler /* Hard Fault Handler*/
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.long MemManage_Handler /* MPU Fault Handler*/
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.long BusFault_Handler /* Bus Fault Handler*/
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.long UsageFault_Handler /* Usage Fault Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long SVC_Handler /* SVCall Handler*/
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.long DebugMon_Handler /* Debug Monitor Handler*/
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.long 0 /* Reserved*/
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.long PendSV_Handler /* PendSV Handler*/
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.long SysTick_Handler /* SysTick Handler*/
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/* External Interrupts*/
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.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
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.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
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.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
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.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
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.long DMA4_IRQHandler /* DMA channel 4 transfer complete*/
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.long DMA5_IRQHandler /* DMA channel 5 transfer complete*/
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.long DMA6_IRQHandler /* DMA channel 6 transfer complete*/
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.long DMA7_IRQHandler /* DMA channel 7 transfer complete*/
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.long DMA8_IRQHandler /* DMA channel 8 transfer complete*/
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.long DMA9_IRQHandler /* DMA channel 9 transfer complete*/
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.long DMA10_IRQHandler /* DMA channel 10 transfer complete*/
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.long DMA11_IRQHandler /* DMA channel 11 transfer complete*/
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.long DMA12_IRQHandler /* DMA channel 12 transfer complete*/
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.long DMA13_IRQHandler /* DMA channel 13 transfer complete*/
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.long DMA14_IRQHandler /* DMA channel 14 transfer complete*/
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.long DMA15_IRQHandler /* DMA channel 15 transfer complete*/
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.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-15*/
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.long MCM_IRQHandler /* FPU sources*/
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.long FTFC_IRQHandler /* FTFC Command complete*/
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.long Read_Collision_IRQHandler /* FTFC Read collision*/
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.long LVD_LVW_IRQHandler /* PMC Low voltage detect interrupt*/
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.long FTFC_Fault_IRQHandler /* FTFC Double bit fault detect*/
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.long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/
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.long RCM_IRQHandler /* RCM Asynchronous Interrupt*/
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.long LPI2C0_Master_IRQHandler /* LPI2C0 Master Interrupt*/
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.long LPI2C0_Slave_IRQHandler /* LPI2C0 Slave Interrupt*/
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.long LPSPI0_IRQHandler /* LPSPI0 Interrupt*/
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.long LPSPI1_IRQHandler /* LPSPI1 Interrupt*/
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.long LPSPI2_IRQHandler /* LPSPI2 Interrupt*/
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.long Reserved45_IRQHandler /* Reserved Interrupt 45*/
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.long Reserved46_IRQHandler /* Reserved Interrupt 46*/
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.long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt*/
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.long Reserved48_IRQHandler /* Reserved Interrupt 48*/
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.long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt*/
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.long Reserved50_IRQHandler /* Reserved Interrupt 50*/
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.long LPUART2_RxTx_IRQHandler /* LPUART2 Transmit / Receive Interrupt*/
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.long Reserved52_IRQHandler /* Reserved Interrupt 52*/
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.long Reserved53_IRQHandler /* Reserved Interrupt 53*/
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.long Reserved54_IRQHandler /* Reserved Interrupt 54*/
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.long ADC0_IRQHandler /* ADC0 interrupt request.*/
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.long ADC1_IRQHandler /* ADC1 interrupt request.*/
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.long CMP0_IRQHandler /* CMP0 interrupt request*/
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.long Reserved58_IRQHandler /* Reserved Interrupt 58*/
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.long Reserved59_IRQHandler /* Reserved Interrupt 59*/
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.long ERM_single_fault_IRQHandler /* ERM single bit error correction*/
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.long ERM_double_fault_IRQHandler /* ERM double bit error non-correctable*/
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.long RTC_IRQHandler /* RTC alarm interrupt*/
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.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
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.long LPIT0_Ch0_IRQHandler /* LPIT0 channel 0 overflow interrupt*/
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.long LPIT0_Ch1_IRQHandler /* LPIT0 channel 1 overflow interrupt*/
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.long LPIT0_Ch2_IRQHandler /* LPIT0 channel 2 overflow interrupt*/
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.long LPIT0_Ch3_IRQHandler /* LPIT0 channel 3 overflow interrupt*/
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.long PDB0_IRQHandler /* PDB0 interrupt*/
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.long Reserved69_IRQHandler /* Reserved Interrupt 69*/
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.long Reserved70_IRQHandler /* Reserved Interrupt 70*/
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.long Reserved71_IRQHandler /* Reserved Interrupt 71*/
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.long Reserved72_IRQHandler /* Reserved Interrupt 72*/
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.long SCG_IRQHandler /* SCG bus interrupt request*/
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.long LPTMR0_IRQHandler /* LPTIMER interrupt request*/
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.long PORTA_IRQHandler /* Port A pin detect interrupt*/
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.long PORTB_IRQHandler /* Port B pin detect interrupt*/
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.long PORTC_IRQHandler /* Port C pin detect interrupt*/
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.long PORTD_IRQHandler /* Port D pin detect interrupt*/
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.long PORTE_IRQHandler /* Port E pin detect interrupt*/
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.long SWI_IRQHandler /* Software interrupt*/
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.long Reserved81_IRQHandler /* Reserved Interrupt 81*/
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.long Reserved82_IRQHandler /* Reserved Interrupt 82*/
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.long Reserved83_IRQHandler /* Reserved Interrupt 83*/
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.long PDB1_IRQHandler /* PDB1 interrupt*/
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.long FLEXIO_IRQHandler /* FlexIO Interrupt*/
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.long Reserved86_IRQHandler /* Reserved Interrupt 86*/
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.long Reserved87_IRQHandler /* Reserved Interrupt 87*/
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.long Reserved88_IRQHandler /* Reserved Interrupt 88*/
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.long Reserved89_IRQHandler /* Reserved Interrupt 89*/
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.long Reserved90_IRQHandler /* Reserved Interrupt 90*/
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.long Reserved91_IRQHandler /* Reserved Interrupt 91*/
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.long Reserved92_IRQHandler /* Reserved Interrupt 92*/
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.long Reserved93_IRQHandler /* Reserved Interrupt 93*/
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.long CAN0_ORed_IRQHandler /* CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
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.long CAN0_Error_IRQHandler /* CAN0 Interrupt indicating that errors were detected on the CAN bus*/
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.long CAN0_Wake_Up_IRQHandler /* CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode*/
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.long CAN0_ORed_0_15_MB_IRQHandler /* CAN0 OR'ed Message buffer (0-15)*/
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.long CAN0_ORed_16_31_MB_IRQHandler /* CAN0 OR'ed Message buffer (16-31)*/
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.long Reserved99_IRQHandler /* Reserved Interrupt 99*/
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.long Reserved100_IRQHandler /* Reserved Interrupt 100*/
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.long CAN1_ORed_IRQHandler /* CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
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.long CAN1_Error_IRQHandler /* CAN1 Interrupt indicating that errors were detected on the CAN bus*/
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.long Reserved103_IRQHandler /* Reserved Interrupt 103*/
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.long CAN1_ORed_0_15_MB_IRQHandler /* CAN1 OR'ed Interrupt for Message buffer (0-15)*/
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.long Reserved105_IRQHandler /* Reserved Interrupt 105*/
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.long Reserved106_IRQHandler /* Reserved Interrupt 106*/
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.long Reserved107_IRQHandler /* Reserved Interrupt 107*/
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.long CAN2_ORed_IRQHandler /* CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]*/
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.long CAN2_Error_IRQHandler /* CAN2 Interrupt indicating that errors were detected on the CAN bus*/
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.long Reserved110_IRQHandler /* Reserved Interrupt 110*/
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.long CAN2_ORed_0_15_MB_IRQHandler /* CAN2 OR'ed Message buffer (0-15)*/
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.long Reserved112_IRQHandler /* Reserved Interrupt 112*/
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.long Reserved113_IRQHandler /* Reserved Interrupt 113*/
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.long Reserved114_IRQHandler /* Reserved Interrupt 114*/
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.long FTM0_Ch0_Ch1_IRQHandler /* FTM0 Channel 0 and 1 interrupt*/
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.long FTM0_Ch2_Ch3_IRQHandler /* FTM0 Channel 2 and 3 interrupt*/
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.long FTM0_Ch4_Ch5_IRQHandler /* FTM0 Channel 4 and 5 interrupt*/
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.long FTM0_Ch6_Ch7_IRQHandler /* FTM0 Channel 6 and 7 interrupt*/
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.long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt*/
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.long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt*/
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.long FTM1_Ch0_Ch1_IRQHandler /* FTM1 Channel 0 and 1 interrupt*/
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.long FTM1_Ch2_Ch3_IRQHandler /* FTM1 Channel 2 and 3 interrupt*/
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.long FTM1_Ch4_Ch5_IRQHandler /* FTM1 Channel 4 and 5 interrupt*/
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.long FTM1_Ch6_Ch7_IRQHandler /* FTM1 Channel 6 and 7 interrupt*/
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.long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt*/
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.long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt*/
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.long FTM2_Ch0_Ch1_IRQHandler /* FTM2 Channel 0 and 1 interrupt*/
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.long FTM2_Ch2_Ch3_IRQHandler /* FTM2 Channel 2 and 3 interrupt*/
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.long FTM2_Ch4_Ch5_IRQHandler /* FTM2 Channel 4 and 5 interrupt*/
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.long FTM2_Ch6_Ch7_IRQHandler /* FTM2 Channel 6 and 7 interrupt*/
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.long FTM2_Fault_IRQHandler /* FTM2 Fault interrupt*/
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.long FTM2_Ovf_Reload_IRQHandler /* FTM2 Counter overflow and Reload interrupt*/
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.long FTM3_Ch0_Ch1_IRQHandler /* FTM3 Channel 0 and 1 interrupt*/
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.long FTM3_Ch2_Ch3_IRQHandler /* FTM3 Channel 2 and 3 interrupt*/
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.long FTM3_Ch4_Ch5_IRQHandler /* FTM3 Channel 4 and 5 interrupt*/
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.long FTM3_Ch6_Ch7_IRQHandler /* FTM3 Channel 6 and 7 interrupt*/
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.long FTM3_Fault_IRQHandler /* FTM3 Fault interrupt*/
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.long FTM3_Ovf_Reload_IRQHandler /* FTM3 Counter overflow and Reload interrupt*/
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.long DefaultISR /* 139*/
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.long DefaultISR /* 140*/
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.long DefaultISR /* 141*/
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.long DefaultISR /* 142*/
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.long DefaultISR /* 143*/
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.long DefaultISR /* 144*/
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.long DefaultISR /* 145*/
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.long DefaultISR /* 146*/
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.long DefaultISR /* 147*/
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.long DefaultISR /* 148*/
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.long DefaultISR /* 149*/
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.long DefaultISR /* 150*/
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.long DefaultISR /* 151*/
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.long DefaultISR /* 152*/
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.long DefaultISR /* 153*/
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.long DefaultISR /* 154*/
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.long DefaultISR /* 155*/
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.long DefaultISR /* 156*/
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.long DefaultISR /* 157*/
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.long DefaultISR /* 158*/
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.long DefaultISR /* 159*/
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.long DefaultISR /* 160*/
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.long DefaultISR /* 161*/
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.long DefaultISR /* 162*/
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.long DefaultISR /* 163*/
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.long DefaultISR /* 164*/
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.long DefaultISR /* 165*/
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.long DefaultISR /* 166*/
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.long DefaultISR /* 167*/
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.long DefaultISR /* 168*/
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.long DefaultISR /* 169*/
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.long DefaultISR /* 170*/
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.long DefaultISR /* 171*/
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.long DefaultISR /* 172*/
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.long DefaultISR /* 173*/
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.long DefaultISR /* 174*/
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.long DefaultISR /* 175*/
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.long DefaultISR /* 176*/
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.long DefaultISR /* 177*/
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.long DefaultISR /* 178*/
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.long DefaultISR /* 179*/
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.long DefaultISR /* 180*/
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.long DefaultISR /* 181*/
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.long DefaultISR /* 182*/
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.long DefaultISR /* 183*/
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.long DefaultISR /* 184*/
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.long DefaultISR /* 185*/
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.long DefaultISR /* 186*/
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.long DefaultISR /* 187*/
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.long DefaultISR /* 188*/
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.long DefaultISR /* 189*/
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.long DefaultISR /* 190*/
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.long DefaultISR /* 191*/
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.long DefaultISR /* 192*/
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.long DefaultISR /* 193*/
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.long DefaultISR /* 194*/
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.long DefaultISR /* 195*/
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.long DefaultISR /* 196*/
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.long DefaultISR /* 197*/
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.long DefaultISR /* 198*/
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.long DefaultISR /* 199*/
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.long DefaultISR /* 200*/
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.long DefaultISR /* 201*/
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.long DefaultISR /* 202*/
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.long DefaultISR /* 203*/
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.long DefaultISR /* 204*/
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.long DefaultISR /* 205*/
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.long DefaultISR /* 206*/
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.long DefaultISR /* 207*/
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.long DefaultISR /* 208*/
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.long DefaultISR /* 209*/
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.long DefaultISR /* 210*/
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.long DefaultISR /* 211*/
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.long DefaultISR /* 212*/
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.long DefaultISR /* 213*/
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.long DefaultISR /* 214*/
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.long DefaultISR /* 215*/
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.long DefaultISR /* 216*/
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.long DefaultISR /* 217*/
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.long DefaultISR /* 218*/
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.long DefaultISR /* 219*/
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.long DefaultISR /* 220*/
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.long DefaultISR /* 221*/
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.long DefaultISR /* 222*/
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.long DefaultISR /* 223*/
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.long DefaultISR /* 224*/
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.long DefaultISR /* 225*/
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.long DefaultISR /* 226*/
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.long DefaultISR /* 227*/
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.long DefaultISR /* 228*/
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.long DefaultISR /* 229*/
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.long DefaultISR /* 230*/
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.long DefaultISR /* 231*/
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.long DefaultISR /* 232*/
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.long DefaultISR /* 233*/
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.long DefaultISR /* 234*/
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.long DefaultISR /* 235*/
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.long DefaultISR /* 236*/
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.long DefaultISR /* 237*/
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.long DefaultISR /* 238*/
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.long DefaultISR /* 239*/
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.long DefaultISR /* 240*/
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.long DefaultISR /* 241*/
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.long DefaultISR /* 242*/
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.long DefaultISR /* 243*/
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.long DefaultISR /* 244*/
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.long DefaultISR /* 245*/
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.long DefaultISR /* 246*/
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.long DefaultISR /* 247*/
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.long DefaultISR /* 248*/
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.long DefaultISR /* 249*/
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.long DefaultISR /* 250*/
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.long DefaultISR /* 251*/
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.long DefaultISR /* 252*/
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.long DefaultISR /* 253*/
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.long 0x55AA11EE /* 254 - Reserved for OpenBLT checksum*/
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.long 0xFFFFFFFF /* Reserved for user TRIM value*/
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.size __isr_vector, . - __isr_vector
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/* Flash Configuration */
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.section .FlashConfig, "a"
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.long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
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.long 0xFFFFFFFF /* */
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.long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
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.long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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/* Init the rest of the registers */
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ldr r1,=0
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ldr r2,=0
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ldr r3,=0
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ldr r4,=0
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ldr r5,=0
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ldr r6,=0
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ldr r7,=0
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mov r8,r7
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mov r9,r7
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mov r10,r7
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mov r11,r7
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mov r12,r7
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#ifdef START_FROM_FLASH
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/* Init ECC RAM */
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ldr r1, =__RAM_START
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ldr r2, =__RAM_END
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subs r2, r1
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subs r2, #1
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ble .LC5
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movs r0, 0
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movs r3, #4
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.LC4:
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str r0, [r1]
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add r1, r1, r3
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subs r2, 4
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bge .LC4
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.LC5:
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#endif
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/* Initialize the stack pointer */
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ldr r0,=__StackTop
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mov r13,r0
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#ifndef __NO_SYSTEM_INIT
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/* Call the system init routine */
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Init .data and .bss sections */
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ldr r0,=init_data_bss
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blx r0
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cpsie i /* Unmask interrupts */
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#ifndef __START
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#ifdef __EWL__
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#define __START __thumb_startup
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#else
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#define __START _start
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#endif
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#endif
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bl __START
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JumpToSelf:
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b JumpToSelf
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak DefaultISR
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.type DefaultISR, %function
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DefaultISR:
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b DefaultISR
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.size DefaultISR, . - DefaultISR
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, DefaultISR
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.endm
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/* Exception Handlers */
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler DMA0_IRQHandler
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def_irq_handler DMA1_IRQHandler
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def_irq_handler DMA2_IRQHandler
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def_irq_handler DMA3_IRQHandler
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def_irq_handler DMA4_IRQHandler
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def_irq_handler DMA5_IRQHandler
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def_irq_handler DMA6_IRQHandler
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def_irq_handler DMA7_IRQHandler
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def_irq_handler DMA8_IRQHandler
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def_irq_handler DMA9_IRQHandler
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def_irq_handler DMA10_IRQHandler
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def_irq_handler DMA11_IRQHandler
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def_irq_handler DMA12_IRQHandler
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def_irq_handler DMA13_IRQHandler
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def_irq_handler DMA14_IRQHandler
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def_irq_handler DMA15_IRQHandler
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def_irq_handler DMA_Error_IRQHandler
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def_irq_handler MCM_IRQHandler
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def_irq_handler FTFC_IRQHandler
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def_irq_handler Read_Collision_IRQHandler
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def_irq_handler LVD_LVW_IRQHandler
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def_irq_handler FTFC_Fault_IRQHandler
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def_irq_handler WDOG_EWM_IRQHandler
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def_irq_handler RCM_IRQHandler
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def_irq_handler LPI2C0_Master_IRQHandler
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def_irq_handler LPI2C0_Slave_IRQHandler
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def_irq_handler LPSPI0_IRQHandler
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def_irq_handler LPSPI1_IRQHandler
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def_irq_handler LPSPI2_IRQHandler
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def_irq_handler Reserved45_IRQHandler
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def_irq_handler Reserved46_IRQHandler
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def_irq_handler LPUART0_RxTx_IRQHandler
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def_irq_handler Reserved48_IRQHandler
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def_irq_handler LPUART1_RxTx_IRQHandler
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def_irq_handler Reserved50_IRQHandler
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def_irq_handler LPUART2_RxTx_IRQHandler
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def_irq_handler Reserved52_IRQHandler
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def_irq_handler Reserved53_IRQHandler
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def_irq_handler Reserved54_IRQHandler
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def_irq_handler ADC0_IRQHandler
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def_irq_handler ADC1_IRQHandler
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def_irq_handler CMP0_IRQHandler
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def_irq_handler Reserved58_IRQHandler
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def_irq_handler Reserved59_IRQHandler
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def_irq_handler ERM_single_fault_IRQHandler
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def_irq_handler ERM_double_fault_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler RTC_Seconds_IRQHandler
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def_irq_handler LPIT0_Ch0_IRQHandler
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def_irq_handler LPIT0_Ch1_IRQHandler
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def_irq_handler LPIT0_Ch2_IRQHandler
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def_irq_handler LPIT0_Ch3_IRQHandler
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def_irq_handler PDB0_IRQHandler
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def_irq_handler Reserved69_IRQHandler
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def_irq_handler Reserved70_IRQHandler
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def_irq_handler Reserved71_IRQHandler
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def_irq_handler Reserved72_IRQHandler
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def_irq_handler SCG_IRQHandler
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def_irq_handler LPTMR0_IRQHandler
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def_irq_handler PORTA_IRQHandler
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def_irq_handler PORTB_IRQHandler
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def_irq_handler PORTC_IRQHandler
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def_irq_handler PORTD_IRQHandler
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def_irq_handler PORTE_IRQHandler
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def_irq_handler SWI_IRQHandler
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def_irq_handler Reserved81_IRQHandler
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def_irq_handler Reserved82_IRQHandler
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def_irq_handler Reserved83_IRQHandler
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def_irq_handler PDB1_IRQHandler
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def_irq_handler FLEXIO_IRQHandler
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def_irq_handler Reserved86_IRQHandler
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def_irq_handler Reserved87_IRQHandler
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def_irq_handler Reserved88_IRQHandler
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def_irq_handler Reserved89_IRQHandler
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def_irq_handler Reserved90_IRQHandler
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def_irq_handler Reserved91_IRQHandler
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def_irq_handler Reserved92_IRQHandler
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def_irq_handler Reserved93_IRQHandler
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def_irq_handler CAN0_ORed_IRQHandler
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def_irq_handler CAN0_Error_IRQHandler
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def_irq_handler CAN0_Wake_Up_IRQHandler
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def_irq_handler CAN0_ORed_0_15_MB_IRQHandler
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def_irq_handler CAN0_ORed_16_31_MB_IRQHandler
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def_irq_handler Reserved99_IRQHandler
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def_irq_handler Reserved100_IRQHandler
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def_irq_handler CAN1_ORed_IRQHandler
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def_irq_handler CAN1_Error_IRQHandler
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def_irq_handler Reserved103_IRQHandler
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def_irq_handler CAN1_ORed_0_15_MB_IRQHandler
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def_irq_handler Reserved105_IRQHandler
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def_irq_handler Reserved106_IRQHandler
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def_irq_handler Reserved107_IRQHandler
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def_irq_handler CAN2_ORed_IRQHandler
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def_irq_handler CAN2_Error_IRQHandler
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def_irq_handler Reserved110_IRQHandler
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def_irq_handler CAN2_ORed_0_15_MB_IRQHandler
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def_irq_handler Reserved112_IRQHandler
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def_irq_handler Reserved113_IRQHandler
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def_irq_handler Reserved114_IRQHandler
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def_irq_handler FTM0_Ch0_Ch1_IRQHandler
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def_irq_handler FTM0_Ch2_Ch3_IRQHandler
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def_irq_handler FTM0_Ch4_Ch5_IRQHandler
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def_irq_handler FTM0_Ch6_Ch7_IRQHandler
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def_irq_handler FTM0_Fault_IRQHandler
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def_irq_handler FTM0_Ovf_Reload_IRQHandler
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def_irq_handler FTM1_Ch0_Ch1_IRQHandler
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def_irq_handler FTM1_Ch2_Ch3_IRQHandler
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def_irq_handler FTM1_Ch4_Ch5_IRQHandler
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def_irq_handler FTM1_Ch6_Ch7_IRQHandler
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def_irq_handler FTM1_Fault_IRQHandler
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def_irq_handler FTM1_Ovf_Reload_IRQHandler
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def_irq_handler FTM2_Ch0_Ch1_IRQHandler
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def_irq_handler FTM2_Ch2_Ch3_IRQHandler
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def_irq_handler FTM2_Ch4_Ch5_IRQHandler
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def_irq_handler FTM2_Ch6_Ch7_IRQHandler
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def_irq_handler FTM2_Fault_IRQHandler
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def_irq_handler FTM2_Ovf_Reload_IRQHandler
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def_irq_handler FTM3_Ch0_Ch1_IRQHandler
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def_irq_handler FTM3_Ch2_Ch3_IRQHandler
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def_irq_handler FTM3_Ch4_Ch5_IRQHandler
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def_irq_handler FTM3_Ch6_Ch7_IRQHandler
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def_irq_handler FTM3_Fault_IRQHandler
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def_irq_handler FTM3_Ovf_Reload_IRQHandler
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.end
|