413 lines
19 KiB
ArmAsm
413 lines
19 KiB
ArmAsm
/* File: cstart.S
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* Purpose: startup file for Cortex-M4 devices. Should use with
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* GCC for ARM Embedded Processors
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* Version: V1.3
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* Date: 08 Feb 2012
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*
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* Copyright (c) 2012, ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the ARM Limited nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.syntax unified
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.arch armv7-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x400
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0xC00
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .isr_vector
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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// External Interrupts
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.long SCU_0_IRQHandler // Handler name for SR SCU_0
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.long ERU0_0_IRQHandler // Handler name for SR ERU0_0
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.long ERU0_1_IRQHandler // Handler name for SR ERU0_1
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.long ERU0_2_IRQHandler // Handler name for SR ERU0_2
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.long ERU0_3_IRQHandler // Handler name for SR ERU0_3
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.long ERU1_0_IRQHandler // Handler name for SR ERU1_0
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.long ERU1_1_IRQHandler // Handler name for SR ERU1_1
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.long ERU1_2_IRQHandler // Handler name for SR ERU1_2
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.long ERU1_3_IRQHandler // Handler name for SR ERU1_3
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.long 0 // Not Available
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.long 0 // Not Available
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.long 0 // Not Available
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.long PMU0_0_IRQHandler // Handler name for SR PMU0_0
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.long 0 // Not Available
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.long VADC0_C0_0_IRQHandler // Handler name for SR VADC0_C0_0
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.long VADC0_C0_1_IRQHandler // Handler name for SR VADC0_C0_1
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.long VADC0_C0_2_IRQHandler // Handler name for SR VADC0_C0_1
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.long VADC0_C0_3_IRQHandler // Handler name for SR VADC0_C0_3
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.long VADC0_G0_0_IRQHandler // Handler name for SR VADC0_G0_0
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.long VADC0_G0_1_IRQHandler // Handler name for SR VADC0_G0_1
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.long VADC0_G0_2_IRQHandler // Handler name for SR VADC0_G0_2
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.long VADC0_G0_3_IRQHandler // Handler name for SR VADC0_G0_3
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.long VADC0_G1_0_IRQHandler // Handler name for SR VADC0_G1_0
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.long VADC0_G1_1_IRQHandler // Handler name for SR VADC0_G1_1
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.long VADC0_G1_2_IRQHandler // Handler name for SR VADC0_G1_2
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.long VADC0_G1_3_IRQHandler // Handler name for SR VADC0_G1_3
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.long VADC0_G2_0_IRQHandler // Handler name for SR VADC0_G2_0
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.long VADC0_G2_1_IRQHandler // Handler name for SR VADC0_G2_1
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.long VADC0_G2_2_IRQHandler // Handler name for SR VADC0_G2_2
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.long VADC0_G2_3_IRQHandler // Handler name for SR VADC0_G2_3
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.long VADC0_G3_0_IRQHandler // Handler name for SR VADC0_G3_0
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.long VADC0_G3_1_IRQHandler // Handler name for SR VADC0_G3_1
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.long VADC0_G3_2_IRQHandler // Handler name for SR VADC0_G3_2
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.long VADC0_G3_3_IRQHandler // Handler name for SR VADC0_G3_3
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.long DSD0_0_IRQHandler // Handler name for SR DSD0_0
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.long DSD0_1_IRQHandler // Handler name for SR DSD0_1
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.long DSD0_2_IRQHandler // Handler name for SR DSD0_2
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.long DSD0_3_IRQHandler // Handler name for SR DSD0_3
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.long DSD0_4_IRQHandler // Handler name for SR DSD0_4
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.long DSD0_5_IRQHandler // Handler name for SR DSD0_5
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.long DSD0_6_IRQHandler // Handler name for SR DSD0_6
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.long DSD0_7_IRQHandler // Handler name for SR DSD0_7
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.long DAC0_0_IRQHandler // Handler name for SR DAC0_0
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.long DAC0_1_IRQHandler // Handler name for SR DAC0_0
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.long CCU40_0_IRQHandler // Handler name for SR CCU40_0
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.long CCU40_1_IRQHandler // Handler name for SR CCU40_1
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.long CCU40_2_IRQHandler // Handler name for SR CCU40_2
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.long CCU40_3_IRQHandler // Handler name for SR CCU40_3
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.long CCU41_0_IRQHandler // Handler name for SR CCU41_0
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.long CCU41_1_IRQHandler // Handler name for SR CCU41_1
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.long CCU41_2_IRQHandler // Handler name for SR CCU41_2
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.long CCU41_3_IRQHandler // Handler name for SR CCU41_3
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.long CCU42_0_IRQHandler // Handler name for SR CCU42_0
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.long CCU42_1_IRQHandler // Handler name for SR CCU42_1
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.long CCU42_2_IRQHandler // Handler name for SR CCU42_2
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.long CCU42_3_IRQHandler // Handler name for SR CCU42_3
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.long CCU43_0_IRQHandler // Handler name for SR CCU43_0
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.long CCU43_1_IRQHandler // Handler name for SR CCU43_1
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.long CCU43_2_IRQHandler // Handler name for SR CCU43_2
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.long CCU43_3_IRQHandler // Handler name for SR CCU43_3
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.long CCU80_0_IRQHandler // Handler name for SR CCU80_0
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.long CCU80_1_IRQHandler // Handler name for SR CCU80_1
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.long CCU80_2_IRQHandler // Handler name for SR CCU80_2
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.long CCU80_3_IRQHandler // Handler name for SR CCU80_3
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.long CCU81_0_IRQHandler // Handler name for SR CCU81_0
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.long CCU81_1_IRQHandler // Handler name for SR CCU81_1
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.long CCU81_2_IRQHandler // Handler name for SR CCU81_2
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.long CCU81_3_IRQHandler // Handler name for SR CCU81_3
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.long POSIF0_0_IRQHandler // Handler name for SR POSIF0_0
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.long POSIF0_1_IRQHandler // Handler name for SR POSIF0_1
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.long POSIF1_0_IRQHandler // Handler name for SR POSIF1_0
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.long POSIF1_1_IRQHandler // Handler name for SR POSIF1_1
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.long 0 // Not Available
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.long 0 // Not Available
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.long 0 // Not Available
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.long 0 // Not Available
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.long CAN0_0_IRQHandler // Handler name for SR CAN0_0
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.long CAN0_1_IRQHandler // Handler name for SR CAN0_1
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.long CAN0_2_IRQHandler // Handler name for SR CAN0_2
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.long CAN0_3_IRQHandler // Handler name for SR CAN0_3
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.long CAN0_4_IRQHandler // Handler name for SR CAN0_4
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.long CAN0_5_IRQHandler // Handler name for SR CAN0_5
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.long CAN0_6_IRQHandler // Handler name for SR CAN0_6
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.long CAN0_7_IRQHandler // Handler name for SR CAN0_7
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.long USIC0_0_IRQHandler // Handler name for SR USIC0_0
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.long USIC0_1_IRQHandler // Handler name for SR USIC0_1
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.long USIC0_2_IRQHandler // Handler name for SR USIC0_2
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.long USIC0_3_IRQHandler // Handler name for SR USIC0_3
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.long USIC0_4_IRQHandler // Handler name for SR USIC0_4
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.long USIC0_5_IRQHandler // Handler name for SR USIC0_5
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.long USIC1_0_IRQHandler // Handler name for SR USIC1_0
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.long USIC1_1_IRQHandler // Handler name for SR USIC1_1
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.long USIC1_2_IRQHandler // Handler name for SR USIC1_2
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.long USIC1_3_IRQHandler // Handler name for SR USIC1_3
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.long USIC1_4_IRQHandler // Handler name for SR USIC1_4
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.long USIC1_5_IRQHandler // Handler name for SR USIC1_5
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.long USIC2_0_IRQHandler // Handler name for SR USIC2_0
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.long USIC2_1_IRQHandler // Handler name for SR USIC2_1
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.long USIC2_2_IRQHandler // Handler name for SR USIC2_2
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.long USIC2_3_IRQHandler // Handler name for SR USIC2_3
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.long USIC2_4_IRQHandler // Handler name for SR USIC2_4
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.long USIC2_5_IRQHandler // Handler name for SR USIC2_5
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.long LEDTS0_0_IRQHandler // Handler name for SR LEDTS0_0
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.long 0 // Not Available
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.long FCE0_0_IRQHandler // Handler name for SR FCE0_0
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.long GPDMA0_0_IRQHandler // Handler name for SR GPDMA0_0
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.long SDMMC0_0_IRQHandler // Handler name for SR SDMMC0_0
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.long USB0_0_IRQHandler // Handler name for SR USB0_0
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.long ETH0_0_IRQHandler // Handler name for SR ETH0_0
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.long 0 // Not Available
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.long GPDMA1_0_IRQHandler // Handler name for SR GPDMA1_0
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.long 0 // Not Available
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.size __isr_vector, . - __isr_vector
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.text
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Initialize the stackpointer. this is done automatically after a reset event.
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* the bootloader performs a software reset by calling this reset handler, in
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* which case the stackpointer is not yet initialized. */
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ldr r1, =__StackTop
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mov sp, r1
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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#if 1
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/* Here are two copies of loop implemenations. First one favors code size
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* and the second one favors performance. Default uses the first one.
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* Change to "#if 0" to use the second one */
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.flash_to_ram_loop:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .flash_to_ram_loop
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#else
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subs r3, r2
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ble .flash_to_ram_loop_end
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.flash_to_ram_loop:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .flash_to_ram_loop
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.flash_to_ram_loop_end:
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#endif
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#ifndef __NO_SYSTEM_INIT
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ldr r0, =SystemInit
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blx r0
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#endif
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ldr r0, =_start
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bx r0
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.pool
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.size Reset_Handler, . - Reset_Handler
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/* Our weak _start alternative if we don't use the library _start
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* The zero init section must be cleared, otherwise the librtary is
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* doing that */
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.align 1
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.thumb_func
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.weak _start
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.type _start, %function
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_start:
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/* Zero fill the bss segment. */
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ldr r1, = __bss_start__
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ldr r2, = __bss_end__
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movs r3, #0
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b .fill_zero_bss
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.loop_zero_bss:
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str r3, [r1], #4
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.fill_zero_bss:
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cmp r1, r2
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bcc .loop_zero_bss
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/* Jump to our main */
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bl main
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b .
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.size _start, . - _start
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.align 1
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.thumb_func
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.weak \handler_name
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.type \handler_name, %function
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\handler_name :
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b .
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.size \handler_name, . - \handler_name
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler Default_Handler
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// External Interrupts
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def_irq_handler SCU_0_IRQHandler
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def_irq_handler ERU0_0_IRQHandler
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def_irq_handler ERU0_1_IRQHandler
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def_irq_handler ERU0_2_IRQHandler
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def_irq_handler ERU0_3_IRQHandler
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def_irq_handler ERU1_0_IRQHandler
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def_irq_handler ERU1_1_IRQHandler
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def_irq_handler ERU1_2_IRQHandler
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def_irq_handler ERU1_3_IRQHandler
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def_irq_handler PMU0_0_IRQHandler
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def_irq_handler VADC0_C0_0_IRQHandler
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def_irq_handler VADC0_C0_1_IRQHandler
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def_irq_handler VADC0_C0_2_IRQHandler
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def_irq_handler VADC0_C0_3_IRQHandler
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def_irq_handler VADC0_G0_0_IRQHandler
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def_irq_handler VADC0_G0_1_IRQHandler
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def_irq_handler VADC0_G0_2_IRQHandler
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def_irq_handler VADC0_G0_3_IRQHandler
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def_irq_handler VADC0_G1_0_IRQHandler
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def_irq_handler VADC0_G1_1_IRQHandler
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def_irq_handler VADC0_G1_2_IRQHandler
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def_irq_handler VADC0_G1_3_IRQHandler
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def_irq_handler VADC0_G2_0_IRQHandler
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def_irq_handler VADC0_G2_1_IRQHandler
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def_irq_handler VADC0_G2_2_IRQHandler
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def_irq_handler VADC0_G2_3_IRQHandler
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def_irq_handler VADC0_G3_0_IRQHandler
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def_irq_handler VADC0_G3_1_IRQHandler
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def_irq_handler VADC0_G3_2_IRQHandler
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def_irq_handler VADC0_G3_3_IRQHandler
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def_irq_handler DSD0_0_IRQHandler
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def_irq_handler DSD0_1_IRQHandler
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def_irq_handler DSD0_2_IRQHandler
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def_irq_handler DSD0_3_IRQHandler
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def_irq_handler DSD0_4_IRQHandler
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def_irq_handler DSD0_5_IRQHandler
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def_irq_handler DSD0_6_IRQHandler
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def_irq_handler DSD0_7_IRQHandler
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def_irq_handler DAC0_0_IRQHandler
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def_irq_handler DAC0_1_IRQHandler
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def_irq_handler CCU40_0_IRQHandler
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def_irq_handler CCU40_1_IRQHandler
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def_irq_handler CCU40_2_IRQHandler
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def_irq_handler CCU40_3_IRQHandler
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def_irq_handler CCU41_0_IRQHandler
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def_irq_handler CCU41_1_IRQHandler
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def_irq_handler CCU41_2_IRQHandler
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def_irq_handler CCU41_3_IRQHandler
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def_irq_handler CCU42_0_IRQHandler
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def_irq_handler CCU42_1_IRQHandler
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def_irq_handler CCU42_2_IRQHandler
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def_irq_handler CCU42_3_IRQHandler
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def_irq_handler CCU43_0_IRQHandler
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def_irq_handler CCU43_1_IRQHandler
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def_irq_handler CCU43_2_IRQHandler
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def_irq_handler CCU43_3_IRQHandler
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def_irq_handler CCU80_0_IRQHandler
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def_irq_handler CCU80_1_IRQHandler
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def_irq_handler CCU80_2_IRQHandler
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def_irq_handler CCU80_3_IRQHandler
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def_irq_handler CCU81_0_IRQHandler
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def_irq_handler CCU81_1_IRQHandler
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def_irq_handler CCU81_2_IRQHandler
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def_irq_handler CCU81_3_IRQHandler
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def_irq_handler POSIF0_0_IRQHandler
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def_irq_handler POSIF0_1_IRQHandler
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def_irq_handler POSIF1_0_IRQHandler
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def_irq_handler POSIF1_1_IRQHandler
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def_irq_handler CAN0_0_IRQHandler
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def_irq_handler CAN0_1_IRQHandler
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def_irq_handler CAN0_2_IRQHandler
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def_irq_handler CAN0_3_IRQHandler
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def_irq_handler CAN0_4_IRQHandler
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def_irq_handler CAN0_5_IRQHandler
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def_irq_handler CAN0_6_IRQHandler
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def_irq_handler CAN0_7_IRQHandler
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def_irq_handler USIC0_0_IRQHandler
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def_irq_handler USIC0_1_IRQHandler
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def_irq_handler USIC0_2_IRQHandler
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def_irq_handler USIC0_3_IRQHandler
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def_irq_handler USIC0_4_IRQHandler
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def_irq_handler USIC0_5_IRQHandler
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def_irq_handler USIC1_0_IRQHandler
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def_irq_handler USIC1_1_IRQHandler
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def_irq_handler USIC1_2_IRQHandler
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def_irq_handler USIC1_3_IRQHandler
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def_irq_handler USIC1_4_IRQHandler
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def_irq_handler USIC1_5_IRQHandler
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def_irq_handler USIC2_0_IRQHandler
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def_irq_handler USIC2_1_IRQHandler
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def_irq_handler USIC2_2_IRQHandler
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def_irq_handler USIC2_3_IRQHandler
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def_irq_handler USIC2_4_IRQHandler
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def_irq_handler USIC2_5_IRQHandler
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def_irq_handler LEDTS0_0_IRQHandler
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def_irq_handler FCE0_0_IRQHandler
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def_irq_handler GPDMA0_0_IRQHandler
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def_irq_handler SDMMC0_0_IRQHandler
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def_irq_handler USB0_0_IRQHandler
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def_irq_handler ETH0_0_IRQHandler
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def_irq_handler GPDMA1_0_IRQHandler
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.end
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