277 lines
8.8 KiB
C
277 lines
8.8 KiB
C
/*********************************************************************************************************************
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* @file system_XMC1400.c
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* @brief Device specific initialization for the XMC1400-Series according to CMSIS
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* @version V1.1
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* @date 09 Dec 2015
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*
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* @cond
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*********************************************************************************************************************
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* Copyright (c) 2015-2016, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* *************************** Change history ********************************
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* V1.0, 03 Sep 2015, JFT : Initial version
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* MCLK = 48MHz, PCLK = 96MHz
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* V1.1, 09 Dec 2015, JFT : Enable prefetch unit
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*
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* @endcond
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*/
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/*******************************************************************************
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* HEADER FILES
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*******************************************************************************/
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#include <XMC1400.h>
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#include "system_XMC1400.h"
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/*******************************************************************************
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* MACROS
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*******************************************************************************/
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/* Define WEAK attribute */
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#if !defined(__WEAK)
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#if defined ( __CC_ARM )
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#define __WEAK __attribute__ ((weak))
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#elif defined ( __ICCARM__ )
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#define __WEAK __weak
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#elif defined ( __GNUC__ )
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#define __WEAK __attribute__ ((weak))
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#elif defined ( __TASKING__ )
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#define __WEAK __attribute__ ((weak))
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#endif
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#endif
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#define DCO1_FREQUENCY (48000000U)
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*
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// <h> Clock configuration
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*/
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/*
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// <o> External crystal frequency [Hz]
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// <8000000=> 8MHz
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// <12000000=> 12MHz
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// <16000000=> 16MHz
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// <20000000=> 20MHz
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// <i> Defines external crystal frequency
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// <i> Default: 20MHz
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*/
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#define OSCHP_FREQUENCY (20000000U)
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/*
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// <o> DCLK clock source selection
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// <0=> Internal oscillator DCO1 (48MHz)
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// <1=> External crystal oscillator
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// <i> Default: Internal oscillator DCO1 (48MHz)
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*/
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#define DCLK_CLOCK_SRC 0
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#define DCLK_CLOCK_SRC_DCO1 0
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#define DCLK_CLOCK_SRC_EXT_XTAL 1
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/*
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// <o> OSCHP external oscillator mode
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// <0=> Crystal mode
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// <1=> External clock direct input mode
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// <i> Default: Crystal mode
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*/
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#define OSCHP_MODE 0
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#define OSCHP_MODE_XTAL 0
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#define OSCHP_MODE_DIRECT 1
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/*
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// <o> RTC clock source selection
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// <0=> Internal oscillator DCO2 (32768Hz)
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// <5=> External crystal oscillator
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// <i> Default: Internal oscillator DCO2 (32768Hz)
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*/
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#define RTC_CLOCK_SRC 0
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#define RTC_CLOCK_SRC_DCO2 0
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#define RTC_CLOCK_SRC_EXT_XTAL 5
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/*
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// <o> PCLK clock source selection
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// <0=> MCLK
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// <1=> 2xMCLK
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// <i> Default: 2xMCLK
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*/
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#define PCLK_CLOCK_SRC 1
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#define PCLK_CLOCK_SRC_MCLK 0
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#define PCLK_CLOCK_SRC_2XMCLK 1
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/*
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//-------- <<< end of configuration section >>> ------------------
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*/
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/*******************************************************************************
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* GLOBAL VARIABLES
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*******************************************************************************/
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#if defined ( __CC_ARM )
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uint32_t SystemCoreClock __attribute__((at(0x20003FFC)));
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#elif defined ( __ICCARM__ )
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__no_init uint32_t SystemCoreClock;
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#elif defined ( __GNUC__ )
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uint32_t SystemCoreClock __attribute__((section(".no_init")));
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#elif defined ( __TASKING__ )
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uint32_t SystemCoreClock __at( 0x20003FFC );
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#endif
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/*******************************************************************************
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* LOCAL FUNCTIONS
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*******************************************************************************/
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#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1
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static inline void delay(uint32_t cycles)
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{
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while(cycles > 0)
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{
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__NOP();
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cycles--;
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}
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}
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#endif
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/*******************************************************************************
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* API IMPLEMENTATION
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*******************************************************************************/
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__WEAK void SystemInit(void)
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{
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SystemCoreSetup();
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SystemCoreClockSetup();
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}
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__WEAK void SystemCoreSetup(void)
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{
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/* Enable Prefetch unit */
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SCU_GENERAL->PFUCR &= ~SCU_GENERAL_PFUCR_PFUBYP_Msk;
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}
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__WEAK void SystemCoreClockSetup(void)
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{
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/* Clock setup done during SSW using the CLOCK_VAL1 and CLOCK_VAL2 defined in vector table */
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/* disable bit protection */
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SCU_GENERAL->PASSWD = 0x000000C0UL;
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#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1
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if (OSCHP_GetFrequency() > 20000000U)
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{
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SCU_ANALOG->ANAOSCHPCTRL |= SCU_ANALOG_ANAOSCHPCTRL_HYSCTRL_Msk;
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}
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/* OSCHP source selection - OSC mode */
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SCU_ANALOG->ANAOSCHPCTRL = (SCU_ANALOG->ANAOSCHPCTRL & ~SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk) |
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(OSCHP_MODE << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos);
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/* Enable OSC_HP oscillator watchdog*/
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SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk;
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do
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{
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/* Restart OSC_HP oscillator watchdog */
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SCU_INTERRUPT->SRCLR1 = SCU_INTERRUPT_SRCLR1_LOECI_Msk;
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SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDRES_Msk;
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/* Wait a few DCO2 cycles for the update of the clock detection result */
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delay(2500);
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/* check clock is ok */
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}
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while(SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk);
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/* DCLK source using OSC_HP */
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SCU_CLK->CLKCR1 |= SCU_CLK_CLKCR1_DCLKSEL_Msk;
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#else
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/* DCLK source using DCO1 */
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SCU_CLK->CLKCR1 &= ~SCU_CLK_CLKCR1_DCLKSEL_Msk;
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#endif
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#if RTC_CLOCK_SRC == RTC_CLOCK_SRC_EXT_XTAL
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/* Enable OSC_LP */
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SCU_ANALOG->ANAOSCLPCTRL &= ~SCU_ANALOG_ANAOSCLPCTRL_MODE_Msk;
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#endif
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/* Update PCLK selection mux. */
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/* Fractional divider enabled, MCLK frequency equal DCO1 frequency or external crystal frequency */
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SCU_CLK->CLKCR = (1023UL <<SCU_CLK_CLKCR_CNTADJ_Pos) |
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(RTC_CLOCK_SRC << SCU_CLK_CLKCR_RTCCLKSEL_Pos) |
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(PCLK_CLOCK_SRC << SCU_CLK_CLKCR_PCLKSEL_Pos) |
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0x100U; /* IDIV = 1 */
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/* enable bit protection */
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SCU_GENERAL->PASSWD = 0x000000C3UL;
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SystemCoreClockUpdate();
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}
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__WEAK void SystemCoreClockUpdate(void)
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{
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static uint32_t IDIV, FDIV;
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IDIV = ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
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if (IDIV != 0)
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{
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FDIV = ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
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FDIV |= ((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_FDIV_Msk) << 8;
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/* Fractional divider is enabled and used */
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if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U)
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{
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SystemCoreClock = ((uint32_t)((DCO1_FREQUENCY << 6U) / ((IDIV << 10) + FDIV))) << 4U;
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}
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else
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{
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SystemCoreClock = ((uint32_t)((OSCHP_GetFrequency() << 6U) / ((IDIV << 10) + FDIV))) << 4U;
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}
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}
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else
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{
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/* Fractional divider bypassed. */
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if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U)
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{
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SystemCoreClock = DCO1_FREQUENCY;
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}
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else
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{
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SystemCoreClock = OSCHP_GetFrequency();
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}
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}
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}
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__WEAK uint32_t OSCHP_GetFrequency(void)
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{
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return OSCHP_FREQUENCY;
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}
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