1895 lines
119 KiB
C
1895 lines
119 KiB
C
/**
|
|
* @file xmc1_eru_map.h
|
|
* @date 2015-08-25
|
|
*
|
|
* @cond
|
|
*********************************************************************************************************************
|
|
* XMClib v2.1.8 - XMC Peripheral Driver Library
|
|
*
|
|
* Copyright (c) 2015-2016, Infineon Technologies AG
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
|
|
* following conditions are met:
|
|
*
|
|
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
|
|
* disclaimer.
|
|
*
|
|
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
|
|
* disclaimer in the documentation and/or other materials provided with the distribution.
|
|
*
|
|
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
|
|
* products derived from this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
|
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
|
|
* Infineon Technologies AG dave@infineon.com).
|
|
*********************************************************************************************************************
|
|
*
|
|
* Change History
|
|
* --------------
|
|
*
|
|
* 2015-02-20:
|
|
* - Initial version
|
|
*
|
|
* 2015-08-25:
|
|
* - Added support for XMC1400 devices
|
|
*
|
|
* @endcond
|
|
*/
|
|
#ifndef XMC1_ERU_MAP_H
|
|
#define XMC1_ERU_MAP_H
|
|
|
|
/*********************************************************************************************************************
|
|
* MACROS
|
|
*********************************************************************************************************************/
|
|
#define ERU0_ETL0 XMC_ERU0, 0
|
|
#define ERU0_ETL1 XMC_ERU0, 1
|
|
#define ERU0_ETL2 XMC_ERU0, 2
|
|
#define ERU0_ETL3 XMC_ERU0, 3
|
|
|
|
#define ERU0_OGU0 XMC_ERU0, 0
|
|
#define ERU0_OGU1 XMC_ERU0, 1
|
|
#define ERU0_OGU2 XMC_ERU0, 2
|
|
#define ERU0_OGU3 XMC_ERU0, 3
|
|
|
|
#if defined(ERU1)
|
|
#define ERU1_ETL0 XMC_ERU1, 0
|
|
#define ERU1_ETL1 XMC_ERU1, 1
|
|
#define ERU1_ETL2 XMC_ERU1, 2
|
|
#define ERU1_ETL3 XMC_ERU1, 3
|
|
|
|
#define ERU1_OGU0 XMC_ERU1, 0
|
|
#define ERU1_OGU1 XMC_ERU1, 1
|
|
#define ERU1_OGU2 XMC_ERU1, 2
|
|
#define ERU1_OGU3 XMC_ERU1, 3
|
|
#endif
|
|
|
|
#if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN24)
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP16)
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP38)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1200) && (UC_PACKAGE == TSSOP38)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1201) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP28)
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP38)
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN24)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP16)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP28)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN24)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP16)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP38)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN24)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP16)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP28)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP38)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1401) && (UC_PACKAGE == LQFP64)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1401) && (UC_PACKAGE == VQFN48)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1402) && (UC_PACKAGE == LQFP64)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN48)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1402) && (UC_PACKAGE == VQFN64)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1402) && (UC_PACKAGE == TSSOP38)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN40)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64)
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
|
|
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64)
|
|
#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
|
|
#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
|
|
#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL0_INPUTA_P3_0 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL0_INPUTA_P4_4 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL0_INPUTA_P4_7 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL1_INPUTA_P3_1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL1_INPUTA_P3_3 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL1_INPUTA_P4_5 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL2_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL2_INPUTA_P3_4 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL2_INPUTA_P4_6 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3
|
|
#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
|
|
#define ERU1_ETL3_INPUTA_P2_12 XMC_ERU_ETL_INPUT_A2
|
|
#define ERU1_ETL3_INPUTA_P2_13 XMC_ERU_ETL_INPUT_A3
|
|
#define ERU1_ETL3_INPUTA_POSIF1_SR1 XMC_ERU_ETL_INPUT_A1
|
|
#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0
|
|
#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1
|
|
#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2
|
|
#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3
|
|
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CAN0_SR4 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CAN0_SR5 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CAN0_SR6 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CAN0_SR7 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
|
|
#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
|
|
#endif
|
|
|
|
#endif /* XMC1_ERU_MAP_H */
|