452 lines
15 KiB
ArmAsm
452 lines
15 KiB
ArmAsm
;************************************************
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;*
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;* Part one of the system initialization code, contains low-level
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;* initialization, plain thumb variant.
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;*
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;*********************************************************************************************************************
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;* Copyright (c) 2015-2016, Infineon Technologies AG
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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;* following conditions are met:
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;*
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;* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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;* disclaimer.
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;*
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;* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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;* disclaimer in the documentation and/or other materials provided with the distribution.
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;*
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;* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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;* products derived from this software without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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;* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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;* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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;* Infineon Technologies AG dave@infineon.com).
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;*********************************************************************************************************************
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;*
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;******************* Version History **********************************************
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;
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; V1, May, 7,2015 JFT:a) Initial version, MCLK=8MHz, PCLK=16MHz
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;
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;**********************************************************************************
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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/*****************************************************************************
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* <h> Clock system handling by SSW
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* <h> CLK_VAL1 Configuration
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* <o0.0..9> FDIV Fractional Divider Selection <0-1023>
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* <i> Deafult: 0. Fractional part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024))
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* <o0.10..17> IDIV Divider Selection <1-16>
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* <i> Deafult: 6. Interger part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024) = 8MHz)
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* <o0.18> PCLKSEL PCLK Clock Select
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* <0=> PCLK = MCLK
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* <1=> PCLK = 2 x MCLK
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* <i> Deafult: 2 x MCLK
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* <o0.19..21> RTCCLKSEL RTC Clock Select
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* <0=> 32.768kHz standby clock
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* <1=> 32.768kHz external clock from ERU0.IOUT0
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* <2=> 32.768kHz external clock from ACMP0.OUT
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* <3=> 32.768kHz external clock from ACMP1.OUT
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* <4=> 32.768kHz external clock from ACMP2.OUT
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* <5=> 32.768kHz XTAL clock via OSC_LP
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* <6=> Reserved
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* <7=> Reserved
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* <i> Deafult: 32.768kHz standby clock
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* <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]
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* </h>
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*****************************************************************************/
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#define CLKVAL1_SSW 0x00041800
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/*****************************************************************************
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* <h> CLK_VAL2 Configuration
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* <o0.0> disable VADC and SHS Gating
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* <o0.1> disable CCU80 Gating
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* <o0.2> disable CCU40 Gating
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* <o0.3> disable USIC0 Gating
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* <o0.4> disable BCCU0 Gating
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* <o0.5> disable LEDTS0 Gating
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* <o0.6> disable LEDTS1 Gating
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* <o0.7> disable POSIF0 Gating
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* <o0.8> disable MATH Gating
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* <o0.9> disable WDT Gating
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* <o0.10> disable RTC Gating
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* <o0.16> disable CCU81 Gating
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* <o0.17> disable CCU41 Gating
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* <o0.18> disable USIC1 Gating
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* <o0.19> disable LEDTS2 Gating
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* <o0.20> disable POSIF1 Gating
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* <o0.21> disable MCAN0 Gating
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* <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
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* </h>
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*****************************************************************************/
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#define CLKVAL2_SSW 0x00000100
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD 0 ; 0x8
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DCD 0 ; 0xC
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DCD CLKVAL1_SSW ; 0x10 CLK_VAL1 - (CLKCR default)
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DCD CLKVAL2_SSW ; 0x14 CLK_VAL2 - (CGATCLR0 default)
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SECTION .vect_table:CODE:ROOT(2)
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THUMB
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LDR R0,=HardFault_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=SVC_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=Undef_Handler
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BX R0
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LDR R0,=PendSV_Handler
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BX R0
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LDR R0,=SysTick_Handler
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BX R0
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; External Interrupts
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LDR R0,=IRQ0_Handler ; SCU.SR0, CAN0.SR0, CCU40.SR0, SCU.SR0 | CAN0.SR0
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BX R0
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LDR R0,=IRQ1_Handler ; SCU.SR1, CAN0.SR1, CCU80.SR0, SCU.SR1 | CAN0.SR1
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BX R0
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LDR R0,=IRQ2_Handler ; SCU.SR2, CAN0.SR2, CCU80.SR1, SCU.SR2 | CAN0.SR2
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BX R0
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LDR R0,=IRQ3_Handler ; ERU0.SR0, ERU1.SR0, CAN0.SR0, ERU0.SR0 | ERU1.SR0
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BX R0
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LDR R0,=IRQ4_Handler ; ERU0.SR1, ERU1.SR1, CAN0.SR1, ERU0.SR1 | ERU1.SR1
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BX R0
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LDR R0,=IRQ5_Handler ; ERU0.SR2, ERU1.SR2, CAN0.SR2, ERU0.SR2 | ERU1.SR2
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BX R0
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LDR R0,=IRQ6_Handler ; ERU0.SR3, ERU1.SR3, CAN0.SR3, ERU0.SR3 | ERU1.SR3
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BX R0
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LDR R0,=IRQ7_Handler ; MATH.SR0, CAN0.SR3, CCU40.SR1, MATH.SR0 | CAN0.SR3
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BX R0
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LDR R0,=IRQ8_Handler ; LEDTS2.SR0, CCU40.SR0, CCU80.SR0, LEDTS2.SR0 | CCU40.SR0
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BX R0
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LDR R0,=IRQ9_Handler ; USIC0.SR0, USIC1.SR0, ERU0.SR0, USIC0.SR0 | USIC1.SR0
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BX R0
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LDR R0,=IRQ10_Handler ; USIC0.SR1, USIC1.SR1, ERU0.SR1, USIC0.SR1 | USIC1.SR1
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BX R0
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LDR R0,=IRQ11_Handler ; USIC0.SR2, USIC1.SR2, ERU0.SR2, USIC0.SR2 | USIC1.SR2
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BX R0
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LDR R0,=IRQ12_Handler ; USIC0.SR3, USIC1.SR3, ERU0.SR3, USIC0.SR3 | USIC1.SR3
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BX R0
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LDR R0,=IRQ13_Handler ; USIC0.SR4, USIC1.SR4, CCU80.SR1, USIC0.SR4 | USIC1.SR4
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BX R0
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LDR R0,=IRQ14_Handler ; USIC0.SR5, USIC1.SR5, POSIF0.SR0, USIC0.SR5 | USIC1.SR5
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BX R0
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LDR R0,=IRQ15_Handler ; VADC0.C0SR0, USIC0.SR0, POSIF0.SR1, VADC0.C0SR0 | USIC0.SR0
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BX R0
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LDR R0,=IRQ16_Handler ; VADC0.C0SR1, USIC0.SR1, CCU40.SR2, VADC0.C0SR1 | USIC0.SR1
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BX R0
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LDR R0,=IRQ17_Handler ; VADC0.G0SR0, USIC0.SR2, CAN0.SR0, VADC0.G0SR0 | USIC0.SR2
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BX R0
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LDR R0,=IRQ18_Handler ; VADC0.G0SR1, USIC0.SR3, CAN0.SR1, VADC0.G0SR1 | USIC0.SR3
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BX R0
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LDR R0,=IRQ19_Handler ; VADC0.G1SR0, USIC0.SR4, CAN0.SR2, VADC0.G1SR0 | USIC0.SR4
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BX R0
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LDR R0,=IRQ20_Handler ; VADC0.G1SR1, USIC0.SR5, CAN0.SR3, VADC0.G1SR1 | USIC0.SR5
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BX R0
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LDR R0,=IRQ21_Handler ; CCU40.SR0, CCU41.SR0, USIC0.SR0, CCU40.SR0 | CCU41.SR0
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BX R0
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LDR R0,=IRQ22_Handler ; CCU40.SR1, CCU41.SR1, USIC0.SR1, CCU40.SR1 | CCU41.SR1
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BX R0
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LDR R0,=IRQ23_Handler ; CCU40.SR2, CCU41.SR2, USIC0.SR2, CCU40.SR2 | CCU41.SR2
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BX R0
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LDR R0,=IRQ24_Handler ; CCU40.SR3, CCU41.SR3, USIC0.SR3, CCU40.SR3 | CCU41.SR3
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BX R0
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LDR R0,=IRQ25_Handler ; CCU80.SR0, CCU81.SR0, USIC0.SR4, CCU80.SR0 | CCU81.SR0
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BX R0
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LDR R0,=IRQ26_Handler ; CCU80.SR1, CCU81.SR1, USIC0.SR5, CCU80.SR1 | CCU81.SR1
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BX R0
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LDR R0,=IRQ27_Handler ; POSIF0.SR0, POSIF1.SR0, CCU40.SR3, POSIF0.SR0 | POSIF1.SR0
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BX R0
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LDR R0,=IRQ28_Handler ; POSIF0.SR1, POSIF1.SR1, ERU0.SR0, POSIF0.SR1 | POSIF1.SR1
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BX R0
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LDR R0,=IRQ29_Handler ; LEDTS0.SR0, CCU40.SR1, ERU0.SR1, LEDTS0.SR0 | CCU40.SR1
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BX R0
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LDR R0,=IRQ30_Handler ; LEDTS1.SR0, CCU40.SR2, ERU0.SR2, LEDTS1.SR0 | CCU40.SR2
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BX R0
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LDR R0,=IRQ31_Handler ; BCCU0.SR0, CCU40.SR3, ERU0.SR3, BCCU0.SR0 | CCU40.SR3
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BX R0
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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EXTERN SystemInit
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SECTION .text:CODE:NOROOT(2)
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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; Initialize the stack pointer
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LDR R0, =sfe(CSTACK)
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MOV SP, R0
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK Undef_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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Undef_Handler
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B Undef_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK IRQ0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ0_Handler
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B IRQ0_Handler
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PUBWEAK IRQ1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ1_Handler
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B IRQ1_Handler
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PUBWEAK IRQ2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ2_Handler
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B IRQ2_Handler
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PUBWEAK IRQ3_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ3_Handler
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B IRQ3_Handler
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PUBWEAK IRQ4_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ4_Handler
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B IRQ4_Handler
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PUBWEAK IRQ5_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ5_Handler
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B IRQ5_Handler
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PUBWEAK IRQ6_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ6_Handler
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B IRQ6_Handler
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PUBWEAK IRQ7_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ7_Handler
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B IRQ7_Handler
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PUBWEAK IRQ8_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ8_Handler
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B IRQ8_Handler
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PUBWEAK IRQ9_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ9_Handler
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B IRQ9_Handler
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PUBWEAK IRQ10_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ10_Handler
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B IRQ10_Handler
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PUBWEAK IRQ11_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ11_Handler
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B IRQ11_Handler
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PUBWEAK IRQ12_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ12_Handler
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B IRQ12_Handler
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PUBWEAK IRQ13_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ13_Handler
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B IRQ13_Handler
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PUBWEAK IRQ14_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ14_Handler
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B IRQ14_Handler
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PUBWEAK IRQ15_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ15_Handler
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B IRQ15_Handler
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PUBWEAK IRQ16_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ16_Handler
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B IRQ16_Handler
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PUBWEAK IRQ17_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ17_Handler
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B IRQ17_Handler
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PUBWEAK IRQ18_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ18_Handler
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B IRQ18_Handler
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PUBWEAK IRQ19_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ19_Handler
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B IRQ19_Handler
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PUBWEAK IRQ20_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ20_Handler
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B IRQ20_Handler
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PUBWEAK IRQ21_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ21_Handler
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B IRQ21_Handler
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PUBWEAK IRQ22_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ22_Handler
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B IRQ22_Handler
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PUBWEAK IRQ23_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ23_Handler
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B IRQ23_Handler
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PUBWEAK IRQ24_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ24_Handler
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B IRQ24_Handler
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PUBWEAK IRQ25_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ25_Handler
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B IRQ25_Handler
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PUBWEAK IRQ26_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ26_Handler
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B IRQ26_Handler
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PUBWEAK IRQ27_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ27_Handler
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B IRQ27_Handler
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PUBWEAK IRQ28_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ28_Handler
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B IRQ28_Handler
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PUBWEAK IRQ29_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ29_Handler
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B IRQ29_Handler
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PUBWEAK IRQ30_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ30_Handler
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B IRQ30_Handler
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PUBWEAK IRQ31_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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IRQ31_Handler
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B IRQ31_Handler
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END
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