From 50dfc04853a2c91143716b3c8517e85d7ff54f88 Mon Sep 17 00:00:00 2001 From: blogic Date: Mon, 1 Sep 2014 13:22:00 +0000 Subject: [PATCH] ralink: fix mt7620 ohci 3.10 the ohci phy was not reset properly Signed-off-by: John Crispin Backport of r42290 git-svn-id: svn://svn.openwrt.org/openwrt/branches/barrier_breaker@42384 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch b/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch index fbec32c..d71666e 100644 --- a/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch +++ b/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch @@ -35,7 +35,7 @@ Signed-off-by: John Crispin +obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o --- /dev/null +++ b/drivers/usb/phy/ralink-phy.c -@@ -0,0 +1,191 @@ +@@ -0,0 +1,192 @@ +/* + * Copyright (C) 2013 John Crispin + * @@ -66,6 +66,7 @@ Signed-off-by: John Crispin +#define RT_SYSCFG1_USB0_HOST_MODE BIT(10) + +#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25) ++#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22) +#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18) + @@ -145,7 +146,7 @@ Signed-off-by: John Crispin + +static const struct of_device_id ralink_usbphy_dt_match[] = { + { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) }, -+ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) MT7620_CLKCFG1_UPHY0_CLK_EN }, ++ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | MT7620_CLKCFG1_UPHY0_CLK_EN) }, + {}, +}; +MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);