ralink: backport the ethernet driver from trunk
Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/branches/barrier_breaker@43312 3c298f89-4303-0410-b956-a3cf2f4a3e73
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blogic
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/*
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* Ralink RT305x SoC platform device registration
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*
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT305X_ESW_PLATFORM_H
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#define _RT305X_ESW_PLATFORM_H
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enum {
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RT305X_ESW_VLAN_CONFIG_NONE = 0,
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RT305X_ESW_VLAN_CONFIG_LLLLW,
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RT305X_ESW_VLAN_CONFIG_WLLLL,
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};
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struct rt305x_esw_platform_data
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{
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u8 vlan_config;
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u32 reg_initval_fct2;
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u32 reg_initval_fpa2;
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};
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#endif /* _RT305X_ESW_PLATFORM_H */
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config NET_RALINK
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tristate "Ralink ethernet driver"
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depends on RALINK
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help
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This driver supports the ethernet mac inside the ralink wisocs
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if NET_RALINK
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choice
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prompt "MAC type"
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config NET_RALINK_RT288X
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bool "RT288X"
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depends on SOC_RT288X
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config NET_RALINK_RT305X
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bool "RT305X"
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depends on (SOC_RT305X || SOC_MT7620)
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config NET_RALINK_RT3883
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bool "RT3883"
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depends on SOC_RT3883
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config NET_RALINK_MT7620
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bool "MT7620"
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depends on (SOC_MT7620 || SOC_MT7621)
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endchoice
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config NET_RALINK_MDIO
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def_bool NET_RALINK
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depends on (NET_RALINK_RT288X || NET_RALINK_RT3883 || NET_RALINK_MT7620 || NET_RALINK_MT7621)
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select PHYLIB
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config NET_RALINK_MDIO_RT2880
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def_bool NET_RALINK
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depends on (NET_RALINK_RT288X || NET_RALINK_RT3883)
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select NET_RALINK_MDIO
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config NET_RALINK_ESW_RT3052
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def_bool NET_RALINK
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depends on NET_RALINK_RT305X
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select PHYLIB
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select SWCONFIG
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config NET_RALINK_GSW_MT7620
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def_bool NET_RALINK
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depends on NET_RALINK_MT7620 || NET_RALINK_MT7621
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select NET_RALINK_MDIO
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select PHYLIB
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select SWCONFIG
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endif
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#
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# Makefile for the Ralink SoCs built-in ethernet macs
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#
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ralink-eth-y += ralink_soc_eth.o ralink_ethtool.o
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ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
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ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
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ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
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ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
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ralink-eth-$(CONFIG_NET_RALINK_RT288X) += soc_rt2880.o
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ralink-eth-$(CONFIG_NET_RALINK_RT305X) += soc_rt305x.o
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ralink-eth-$(CONFIG_NET_RALINK_RT3883) += soc_rt3883.o
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ralink-eth-$(CONFIG_NET_RALINK_MT7620) += soc_mt7620.o
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ralink-eth-$(CONFIG_NET_RALINK_MT7621) += soc_mt7621.o
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obj-$(CONFIG_NET_RALINK) += ralink-eth.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,32 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _RALINK_ESW_RT3052_H__
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#define _RALINK_ESW_RT3052_H__
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#ifdef CONFIG_NET_RALINK_ESW_RT3052
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int __init rtesw_init(void);
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void rtesw_exit(void);
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#else
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static inline int __init rtesw_init(void) { return 0; }
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static inline void rtesw_exit(void) { }
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#endif
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#endif
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@ -0,0 +1,805 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/skbuff.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/switch.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include "ralink_soc_eth.h"
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#include <linux/ioport.h>
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#include <linux/switch.h>
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#include <linux/mii.h>
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#include <ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
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#include "ralink_soc_eth.h"
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#include "gsw_mt7620a.h"
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#include "mt7530.h"
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#include "mdio.h"
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#define GSW_REG_PHY_TIMEOUT (5 * HZ)
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#ifdef CONFIG_SOC_MT7621
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#define MT7620A_GSW_REG_PIAC 0x0004
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#else
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#define MT7620A_GSW_REG_PIAC 0x7004
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#endif
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#define GSW_NUM_VLANS 16
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#define GSW_NUM_VIDS 4096
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#define GSW_NUM_PORTS 7
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#define GSW_PORT6 6
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#define GSW_MDIO_ACCESS BIT(31)
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#define GSW_MDIO_READ BIT(19)
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#define GSW_MDIO_WRITE BIT(18)
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#define GSW_MDIO_START BIT(16)
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#define GSW_MDIO_ADDR_SHIFT 20
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#define GSW_MDIO_REG_SHIFT 25
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#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
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#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
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#define GSW_REG_SMACCR0 0x3fE4
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#define GSW_REG_SMACCR1 0x3fE8
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#define GSW_REG_CKGCR 0x3ff0
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#define GSW_REG_IMR 0x7008
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#define GSW_REG_ISR 0x700c
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#define GSW_REG_GPC1 0x7014
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#define SYSC_REG_CHIP_REV_ID 0x0c
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#define SYSC_REG_CFG1 0x14
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#define SYSC_REG_RESET_CTRL 0x34
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#define RST_CTRL_MCM BIT(2)
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#define SYSC_PAD_RGMII2_MDIO 0x58
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#define SYSC_GPIO_MODE 0x60
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#define PORT_IRQ_ST_CHG 0x7f
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#ifdef CONFIG_SOC_MT7621
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#define ESW_PHY_POLLING 0x0000
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#else
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#define ESW_PHY_POLLING 0x7000
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#endif
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#define PMCR_IPG BIT(18)
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#define PMCR_MAC_MODE BIT(16)
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#define PMCR_FORCE BIT(15)
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#define PMCR_TX_EN BIT(14)
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#define PMCR_RX_EN BIT(13)
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#define PMCR_BACKOFF BIT(9)
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#define PMCR_BACKPRES BIT(8)
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#define PMCR_RX_FC BIT(5)
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#define PMCR_TX_FC BIT(4)
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#define PMCR_SPEED(_x) (_x << 2)
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#define PMCR_DUPLEX BIT(1)
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#define PMCR_LINK BIT(0)
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#define PHY_AN_EN BIT(31)
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#define PHY_PRE_EN BIT(30)
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#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
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enum {
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/* Global attributes. */
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GSW_ATTR_ENABLE_VLAN,
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/* Port attributes. */
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GSW_ATTR_PORT_UNTAG,
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};
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enum {
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PORT4_EPHY = 0,
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PORT4_EXT,
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};
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struct mt7620_gsw {
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struct device *dev;
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void __iomem *base;
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int irq;
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int port4;
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long unsigned int autopoll;
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};
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static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
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{
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iowrite32(val, gsw->base + reg);
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}
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static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
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{
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return ioread32(gsw->base + reg);
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}
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static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
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{
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unsigned long t_start = jiffies;
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while (1) {
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if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
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return 0;
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if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
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break;
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}
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}
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printk(KERN_ERR "mdio: MDIO timeout\n");
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return -1;
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}
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static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
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u32 write_data)
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{
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if (mt7620_mii_busy_wait(gsw))
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return -1;
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write_data &= 0xffff;
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gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
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(phy_register << GSW_MDIO_REG_SHIFT) |
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(phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
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MT7620A_GSW_REG_PIAC);
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if (mt7620_mii_busy_wait(gsw))
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return -1;
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return 0;
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}
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static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
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{
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u32 d;
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if (mt7620_mii_busy_wait(gsw))
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return 0xffff;
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gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
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(phy_reg << GSW_MDIO_REG_SHIFT) |
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(phy_addr << GSW_MDIO_ADDR_SHIFT),
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MT7620A_GSW_REG_PIAC);
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if (mt7620_mii_busy_wait(gsw))
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return 0xffff;
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d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
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return d;
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}
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int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
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{
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struct fe_priv *priv = bus->priv;
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struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
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return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
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}
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int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
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{
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struct fe_priv *priv = bus->priv;
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struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
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return _mt7620_mii_read(gsw, phy_addr, phy_reg);
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}
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static void
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mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
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{
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_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
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_mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
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_mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
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}
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static u32
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mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
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{
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u16 high, low;
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_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
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low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
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high = _mt7620_mii_read(gsw, 0x1f, 0x10);
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return (high << 16) | (low & 0xffff);
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}
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static unsigned char *fe_speed_str(int speed)
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{
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switch (speed) {
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case 2:
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case SPEED_1000:
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return "1000";
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case 1:
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case SPEED_100:
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return "100";
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case 0:
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case SPEED_10:
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return "10";
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}
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return "? ";
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}
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int mt7620a_has_carrier(struct fe_priv *priv)
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{
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struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
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int i;
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for (i = 0; i < GSW_PORT6; i++)
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if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
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return 1;
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return 0;
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}
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static void mt7620a_handle_carrier(struct fe_priv *priv)
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{
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if (!priv->phy)
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return;
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if (mt7620a_has_carrier(priv))
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netif_carrier_on(priv->netdev);
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else
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netif_carrier_off(priv->netdev);
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}
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void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
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{
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if (priv->link[port])
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netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
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port, fe_speed_str(priv->phy->speed[port]),
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(DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
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else
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netdev_info(priv->netdev, "port %d link down\n", port);
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mt7620a_handle_carrier(priv);
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}
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static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
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{
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struct fe_priv *priv = (struct fe_priv *) _priv;
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struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
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u32 status;
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int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
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status = gsw_r32(gsw, GSW_REG_ISR);
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if (status & PORT_IRQ_ST_CHG)
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for (i = 0; i <= max; i++) {
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u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
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int link = status & 0x1;
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if (link != priv->link[i]) {
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if (link)
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netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
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i, fe_speed_str((status >> 2) & 3),
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(status & 0x2) ? "Full" : "Half");
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else
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netdev_info(priv->netdev, "port %d link down\n", i);
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}
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priv->link[i] = link;
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}
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mt7620a_handle_carrier(priv);
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gsw_w32(gsw, status, GSW_REG_ISR);
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return IRQ_HANDLED;
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}
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static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
|
||||
{
|
||||
struct fe_priv *priv = (struct fe_priv *) _priv;
|
||||
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
|
||||
u32 reg, i;
|
||||
|
||||
reg = mt7530_mdio_r32(gsw, 0x700c);
|
||||
|
||||
for (i = 0; i < 5; i++)
|
||||
if (reg & BIT(i)) {
|
||||
unsigned int link = mt7530_mdio_r32(gsw, 0x3008 + (i * 0x100)) & 0x1;
|
||||
|
||||
if (link != priv->link[i]) {
|
||||
priv->link[i] = link;
|
||||
if (link)
|
||||
netdev_info(priv->netdev, "port %d link up\n", i);
|
||||
else
|
||||
netdev_info(priv->netdev, "port %d link down\n", i);
|
||||
}
|
||||
}
|
||||
|
||||
mt7620a_handle_carrier(priv);
|
||||
mt7530_mdio_w32(gsw, 0x700c, 0x1f);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mt7620_is_bga(void)
|
||||
{
|
||||
u32 bga = rt_sysc_r32(0x0c);
|
||||
|
||||
return (bga >> 16) & 1;
|
||||
}
|
||||
|
||||
static void gsw_auto_poll(struct mt7620_gsw *gsw)
|
||||
{
|
||||
int phy;
|
||||
int lsb = -1, msb = 0;
|
||||
|
||||
for_each_set_bit(phy, &gsw->autopoll, 32) {
|
||||
if (lsb < 0)
|
||||
lsb = phy;
|
||||
msb = phy;
|
||||
}
|
||||
|
||||
if (lsb == msb)
|
||||
lsb--;
|
||||
|
||||
gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
|
||||
}
|
||||
|
||||
void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
|
||||
{
|
||||
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
|
||||
const __be32 *_id = of_get_property(np, "reg", NULL);
|
||||
int phy_mode, size, id;
|
||||
int shift = 12;
|
||||
u32 val, mask = 0;
|
||||
int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
|
||||
|
||||
if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
|
||||
if (_id)
|
||||
pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
|
||||
else
|
||||
pr_err("%s: invalid port id\n", np->name);
|
||||
return;
|
||||
}
|
||||
|
||||
id = be32_to_cpu(*_id);
|
||||
|
||||
if (id == 4)
|
||||
shift = 14;
|
||||
|
||||
priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
|
||||
if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
|
||||
pr_err("%s: invalid fixed link property\n", np->name);
|
||||
priv->phy->phy_fixed[id] = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
phy_mode = of_get_phy_mode(np);
|
||||
switch (phy_mode) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
mask = 0;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
mask = 1;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
mask = 2;
|
||||
break;
|
||||
default:
|
||||
dev_err(priv->device, "port %d - invalid phy mode\n", id);
|
||||
return;
|
||||
}
|
||||
|
||||
priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
|
||||
if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
|
||||
return;
|
||||
|
||||
val = rt_sysc_r32(SYSC_REG_CFG1);
|
||||
val &= ~(3 << shift);
|
||||
val |= mask << shift;
|
||||
rt_sysc_w32(val, SYSC_REG_CFG1);
|
||||
|
||||
if (priv->phy->phy_fixed[id]) {
|
||||
const __be32 *link = priv->phy->phy_fixed[id];
|
||||
int tx_fc, rx_fc;
|
||||
u32 val = 0;
|
||||
|
||||
priv->phy->speed[id] = be32_to_cpup(link++);
|
||||
tx_fc = be32_to_cpup(link++);
|
||||
rx_fc = be32_to_cpup(link++);
|
||||
priv->phy->duplex[id] = be32_to_cpup(link++);
|
||||
priv->link[id] = 1;
|
||||
|
||||
switch (priv->phy->speed[id]) {
|
||||
case SPEED_10:
|
||||
val = 0;
|
||||
break;
|
||||
case SPEED_100:
|
||||
val = 1;
|
||||
break;
|
||||
case SPEED_1000:
|
||||
val = 2;
|
||||
break;
|
||||
default:
|
||||
dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
|
||||
priv->phy->phy_fixed[id] = 0;
|
||||
return;
|
||||
}
|
||||
val = PMCR_SPEED(val);
|
||||
val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
|
||||
PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
|
||||
if (tx_fc)
|
||||
val |= PMCR_TX_FC;
|
||||
if (rx_fc)
|
||||
val |= PMCR_RX_FC;
|
||||
if (priv->phy->duplex[id])
|
||||
val |= PMCR_DUPLEX;
|
||||
gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
|
||||
dev_info(priv->device, "using fixed link parameters\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
|
||||
u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
|
||||
PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
|
||||
|
||||
gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
|
||||
fe_connect_phy_node(priv, priv->phy->phy_node[id]);
|
||||
gsw->autopoll |= BIT(id);
|
||||
gsw_auto_poll(gsw);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void gsw_hw_init_mt7620(struct mt7620_gsw *gsw, struct device_node *np)
|
||||
{
|
||||
u32 is_BGA = mt7620_is_bga();
|
||||
|
||||
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
|
||||
gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
|
||||
|
||||
if (of_property_read_bool(np, "mediatek,mt7530")) {
|
||||
u32 val;
|
||||
|
||||
/* turn off ephy and set phy base addr to 12 */
|
||||
gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24) | (0xc << 16), GSW_REG_GPC1);
|
||||
|
||||
/* set MT7530 central align */
|
||||
val = mt7530_mdio_r32(gsw, 0x7830);
|
||||
val &= ~1;
|
||||
val |= 1<<1;
|
||||
mt7530_mdio_w32(gsw, 0x7830, val);
|
||||
|
||||
val = mt7530_mdio_r32(gsw, 0x7a40);
|
||||
val &= ~(1<<30);
|
||||
mt7530_mdio_w32(gsw, 0x7a40, val);
|
||||
|
||||
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
|
||||
} else {
|
||||
/* EPHY1 fixup - only run if the ephy is enabled */
|
||||
|
||||
/*correct PHY setting L3.0 BGA*/
|
||||
_mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
|
||||
|
||||
_mt7620_mii_write(gsw, 1, 17, 0x7444);
|
||||
if (is_BGA)
|
||||
_mt7620_mii_write(gsw, 1, 19, 0x0114);
|
||||
else
|
||||
_mt7620_mii_write(gsw, 1, 19, 0x0117);
|
||||
|
||||
_mt7620_mii_write(gsw, 1, 22, 0x10cf);
|
||||
_mt7620_mii_write(gsw, 1, 25, 0x6212);
|
||||
_mt7620_mii_write(gsw, 1, 26, 0x0777);
|
||||
_mt7620_mii_write(gsw, 1, 29, 0x4000);
|
||||
_mt7620_mii_write(gsw, 1, 28, 0xc077);
|
||||
_mt7620_mii_write(gsw, 1, 24, 0x0000);
|
||||
|
||||
_mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
|
||||
_mt7620_mii_write(gsw, 1, 17, 0x4838);
|
||||
|
||||
_mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
|
||||
if (is_BGA) {
|
||||
_mt7620_mii_write(gsw, 1, 21, 0x0515);
|
||||
_mt7620_mii_write(gsw, 1, 22, 0x0053);
|
||||
_mt7620_mii_write(gsw, 1, 23, 0x00bf);
|
||||
_mt7620_mii_write(gsw, 1, 24, 0x0aaf);
|
||||
_mt7620_mii_write(gsw, 1, 25, 0x0fad);
|
||||
_mt7620_mii_write(gsw, 1, 26, 0x0fc1);
|
||||
} else {
|
||||
_mt7620_mii_write(gsw, 1, 21, 0x0517);
|
||||
_mt7620_mii_write(gsw, 1, 22, 0x0fd2);
|
||||
_mt7620_mii_write(gsw, 1, 23, 0x00bf);
|
||||
_mt7620_mii_write(gsw, 1, 24, 0x0aab);
|
||||
_mt7620_mii_write(gsw, 1, 25, 0x00ae);
|
||||
_mt7620_mii_write(gsw, 1, 26, 0x0fff);
|
||||
}
|
||||
_mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
|
||||
_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
|
||||
}
|
||||
|
||||
_mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
|
||||
_mt7620_mii_write(gsw, 0, 30, 0xa000);
|
||||
_mt7620_mii_write(gsw, 1, 30, 0xa000);
|
||||
_mt7620_mii_write(gsw, 2, 30, 0xa000);
|
||||
_mt7620_mii_write(gsw, 3, 30, 0xa000);
|
||||
|
||||
_mt7620_mii_write(gsw, 0, 4, 0x05e1);
|
||||
_mt7620_mii_write(gsw, 1, 4, 0x05e1);
|
||||
_mt7620_mii_write(gsw, 2, 4, 0x05e1);
|
||||
_mt7620_mii_write(gsw, 3, 4, 0x05e1);
|
||||
|
||||
_mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
|
||||
_mt7620_mii_write(gsw, 0, 16, 0x1111);
|
||||
_mt7620_mii_write(gsw, 1, 16, 0x1010);
|
||||
_mt7620_mii_write(gsw, 2, 16, 0x1515);
|
||||
_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
|
||||
|
||||
/* CPU Port6 Force Link 1G, FC ON */
|
||||
gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
|
||||
/* Set Port6 CPU Port */
|
||||
gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
|
||||
|
||||
/* setup port 4 */
|
||||
if (gsw->port4 == PORT4_EPHY) {
|
||||
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
|
||||
val |= 3 << 14;
|
||||
rt_sysc_w32(val, SYSC_REG_CFG1);
|
||||
_mt7620_mii_write(gsw, 4, 30, 0xa000);
|
||||
_mt7620_mii_write(gsw, 4, 4, 0x05e1);
|
||||
_mt7620_mii_write(gsw, 4, 16, 0x1313);
|
||||
pr_info("gsw: setting port4 to ephy mode\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
|
||||
{
|
||||
u32 i;
|
||||
u32 val;
|
||||
|
||||
/* Hardware reset Switch */
|
||||
val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
rt_sysc_w32(val | RST_CTRL_MCM, SYSC_REG_RESET_CTRL);
|
||||
udelay(1000);
|
||||
rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
udelay(10000);
|
||||
|
||||
/* reduce RGMII2 PAD driving strength */
|
||||
rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
|
||||
|
||||
/* gpio mux - RGMII1=Normal mode */
|
||||
rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
|
||||
|
||||
//GMAC1= RGMII mode
|
||||
rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
|
||||
|
||||
/* enable MDIO to control MT7530 */
|
||||
rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
|
||||
|
||||
/* turn off all PHYs */
|
||||
for (i = 0; i <= 4; i++) {
|
||||
val = _mt7620_mii_read(gsw, i, 0x0);
|
||||
val |= (0x1 << 11);
|
||||
_mt7620_mii_write(gsw, i, 0x0, val);
|
||||
}
|
||||
|
||||
/* reset the switch */
|
||||
mt7530_mdio_w32(gsw, 0x7000, 0x3);
|
||||
udelay(10);
|
||||
|
||||
if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
|
||||
/* (GE1, Force 1000M/FD, FC ON) */
|
||||
gsw_w32(gsw, 0x2005e30b, 0x100);
|
||||
mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
|
||||
} else {
|
||||
/* (GE1, Force 1000M/FD, FC ON) */
|
||||
gsw_w32(gsw, 0x2005e33b, 0x100);
|
||||
mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
|
||||
}
|
||||
|
||||
/* (GE2, Link down) */
|
||||
gsw_w32(gsw, 0x8000, 0x200);
|
||||
|
||||
//val = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable
|
||||
val = mt7530_mdio_r32(gsw, 0x7804);
|
||||
val &= ~(1<<8); //Enable Port 6
|
||||
val |= (1<<6); //Disable Port 5
|
||||
val |= (1<<13); //Port 5 as GMAC, no Internal PHY
|
||||
|
||||
val |= (1<<16);//change HW-TRAP
|
||||
printk("change HW-TRAP to 0x%x\n", val);
|
||||
mt7530_mdio_w32(gsw, 0x7804, val);
|
||||
|
||||
val = rt_sysc_r32(0x10);
|
||||
val = (val >> 6) & 0x7;
|
||||
if (val >= 6) {
|
||||
/* 25Mhz Xtal - do nothing */
|
||||
} else if(val >=3) {
|
||||
/* 40Mhz */
|
||||
|
||||
/* disable MT7530 core clock */
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x1f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x410);
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x401f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x0);
|
||||
|
||||
/* disable MT7530 PLL */
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x1f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x40d);
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x401f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x2020);
|
||||
|
||||
/* for MT7530 core clock = 500Mhz */
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x1f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x40e);
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x401f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x119);
|
||||
|
||||
/* enable MT7530 PLL */
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x1f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x40d);
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x401f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x2820);
|
||||
|
||||
udelay(20);
|
||||
|
||||
/* enable MT7530 core clock */
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x1f);
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x410);
|
||||
_mt7620_mii_write(gsw, 0, 13, 0x401f);
|
||||
} else {
|
||||
/* 20Mhz Xtal - TODO */
|
||||
}
|
||||
|
||||
/* RGMII */
|
||||
_mt7620_mii_write(gsw, 0, 14, 0x1);
|
||||
|
||||
/* set MT7530 central align */
|
||||
val = mt7530_mdio_r32(gsw, 0x7830);
|
||||
val &= ~1;
|
||||
val |= 1<<1;
|
||||
mt7530_mdio_w32(gsw, 0x7830, val);
|
||||
|
||||
val = mt7530_mdio_r32(gsw, 0x7a40);
|
||||
val &= ~(1<<30);
|
||||
mt7530_mdio_w32(gsw, 0x7a40, val);
|
||||
|
||||
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
|
||||
mt7530_mdio_w32(gsw, 0x7b00, 0x102); //delay setting for 10/1000M
|
||||
mt7530_mdio_w32(gsw, 0x7b04, 0x14); //delay setting for 10/1000M
|
||||
|
||||
/*Tx Driving*/
|
||||
mt7530_mdio_w32(gsw, 0x7a54, 0x44); //lower driving
|
||||
mt7530_mdio_w32(gsw, 0x7a5c, 0x44); //lower driving
|
||||
mt7530_mdio_w32(gsw, 0x7a64, 0x44); //lower driving
|
||||
mt7530_mdio_w32(gsw, 0x7a6c, 0x44); //lower driving
|
||||
mt7530_mdio_w32(gsw, 0x7a74, 0x44); //lower driving
|
||||
mt7530_mdio_w32(gsw, 0x7a7c, 0x44); //lower driving
|
||||
|
||||
//LANWANPartition();
|
||||
|
||||
/* turn on all PHYs */
|
||||
for (i = 0; i <= 4; i++) {
|
||||
val = _mt7620_mii_read(gsw, i, 0);
|
||||
val &= ~BIT(11);
|
||||
_mt7620_mii_write(gsw, i, 0, val);
|
||||
}
|
||||
|
||||
/* enable irq */
|
||||
val = mt7530_mdio_r32(gsw, 0x7808);
|
||||
val |= 3 << 16;
|
||||
mt7530_mdio_w32(gsw, 0x7808, val);
|
||||
}
|
||||
|
||||
void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
|
||||
{
|
||||
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&priv->page_lock, flags);
|
||||
gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
|
||||
gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
|
||||
GSW_REG_SMACCR0);
|
||||
spin_unlock_irqrestore(&priv->page_lock, flags);
|
||||
}
|
||||
|
||||
static struct of_device_id gsw_match[] = {
|
||||
{ .compatible = "ralink,mt7620a-gsw" },
|
||||
{}
|
||||
};
|
||||
|
||||
int mt7620_gsw_config(struct fe_priv *priv)
|
||||
{
|
||||
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
|
||||
|
||||
/* is the mt7530 internal or external */
|
||||
if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
|
||||
mt7530_probe(priv->device, gsw->base, NULL, 0);
|
||||
mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
|
||||
} else {
|
||||
mt7530_probe(priv->device, gsw->base, NULL, 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt7621_gsw_config(struct fe_priv *priv)
|
||||
{
|
||||
if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
|
||||
mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt7620_gsw_probe(struct fe_priv *priv)
|
||||
{
|
||||
struct mt7620_gsw *gsw;
|
||||
struct device_node *np;
|
||||
const char *port4 = NULL;
|
||||
|
||||
np = of_find_matching_node(NULL, gsw_match);
|
||||
if (!np) {
|
||||
dev_err(priv->device, "no gsw node found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
np = of_node_get(np);
|
||||
|
||||
gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
|
||||
if (!gsw) {
|
||||
dev_err(priv->device, "no gsw memory for private data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
gsw->base = of_iomap(np, 0);
|
||||
if (!gsw->base) {
|
||||
dev_err(priv->device, "gsw ioremap failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
gsw->dev = priv->device;
|
||||
priv->soc->swpriv = gsw;
|
||||
|
||||
of_property_read_string(np, "ralink,port4", &port4);
|
||||
if (port4 && !strcmp(port4, "ephy"))
|
||||
gsw->port4 = PORT4_EPHY;
|
||||
else if (port4 && !strcmp(port4, "gmac"))
|
||||
gsw->port4 = PORT4_EXT;
|
||||
else
|
||||
gsw->port4 = PORT4_EPHY;
|
||||
|
||||
if (IS_ENABLED(CONFIG_SOC_MT7620))
|
||||
gsw_hw_init_mt7620(gsw, np);
|
||||
else
|
||||
gsw_hw_init_mt7621(gsw, np);
|
||||
|
||||
gsw->irq = irq_of_parse_and_map(np, 0);
|
||||
if (gsw->irq) {
|
||||
if (IS_ENABLED(CONFIG_SOC_MT7620)) {
|
||||
request_irq(gsw->irq, gsw_interrupt_mt7620, 0, "gsw", priv);
|
||||
gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
|
||||
} else {
|
||||
request_irq(gsw->irq, gsw_interrupt_mt7621, 0, "gsw", priv);
|
||||
mt7530_mdio_w32(gsw, 0x7008, 0x1f);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RALINK_GSW_MT7620_H__
|
||||
#define _RALINK_GSW_MT7620_H__
|
||||
|
||||
extern int mt7620_gsw_config(struct fe_priv *priv);
|
||||
extern int mt7621_gsw_config(struct fe_priv *priv);
|
||||
extern int mt7620_gsw_probe(struct fe_priv *priv);
|
||||
extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
|
||||
extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
|
||||
extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
|
||||
extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
|
||||
extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
|
||||
extern int mt7620a_has_carrier(struct fe_priv *priv);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/of_mdio.h>
|
||||
|
||||
#include "ralink_soc_eth.h"
|
||||
#include "mdio.h"
|
||||
|
||||
static int fe_mdio_reset(struct mii_bus *bus)
|
||||
{
|
||||
/* TODO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fe_phy_link_adjust(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
spin_lock_irqsave(&priv->phy->lock, flags);
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (priv->phy->phy_node[i]) {
|
||||
struct phy_device *phydev = priv->phy->phy[i];
|
||||
int status_change = 0;
|
||||
|
||||
if (phydev->link)
|
||||
if (priv->phy->duplex[i] != phydev->duplex ||
|
||||
priv->phy->speed[i] != phydev->speed)
|
||||
status_change = 1;
|
||||
|
||||
if (phydev->link != priv->link[i])
|
||||
status_change = 1;
|
||||
|
||||
switch (phydev->speed) {
|
||||
case SPEED_1000:
|
||||
case SPEED_100:
|
||||
case SPEED_10:
|
||||
priv->link[i] = phydev->link;
|
||||
priv->phy->duplex[i] = phydev->duplex;
|
||||
priv->phy->speed[i] = phydev->speed;
|
||||
|
||||
if (status_change && priv->soc->mdio_adjust_link)
|
||||
priv->soc->mdio_adjust_link(priv, i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
|
||||
{
|
||||
const __be32 *_port = NULL;
|
||||
struct phy_device *phydev;
|
||||
int phy_mode, port;
|
||||
|
||||
_port = of_get_property(phy_node, "reg", NULL);
|
||||
|
||||
if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
|
||||
pr_err("%s: invalid port id\n", phy_node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
port = be32_to_cpu(*_port);
|
||||
phy_mode = of_get_phy_mode(phy_node);
|
||||
if (phy_mode < 0) {
|
||||
dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
|
||||
priv->phy->phy_node[port] = NULL;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
|
||||
0, phy_mode);
|
||||
if (IS_ERR(phydev)) {
|
||||
dev_err(priv->device, "could not connect to PHY\n");
|
||||
priv->phy->phy_node[port] = NULL;
|
||||
return PTR_ERR(phydev);
|
||||
}
|
||||
|
||||
phydev->supported &= PHY_GBIT_FEATURES;
|
||||
phydev->advertising = phydev->supported;
|
||||
phydev->no_auto_carrier_off = 1;
|
||||
|
||||
dev_info(priv->device,
|
||||
"connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
|
||||
port, dev_name(&phydev->dev), phydev->phy_id,
|
||||
phydev->drv->name);
|
||||
|
||||
priv->phy->phy[port] = phydev;
|
||||
priv->link[port] = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void phy_init(struct fe_priv *priv, struct phy_device *phy)
|
||||
{
|
||||
phy_attach(priv->netdev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
|
||||
|
||||
phy->autoneg = AUTONEG_ENABLE;
|
||||
phy->speed = 0;
|
||||
phy->duplex = 0;
|
||||
phy->supported &= PHY_BASIC_FEATURES;
|
||||
phy->advertising = phy->supported | ADVERTISED_Autoneg;
|
||||
|
||||
phy_start_aneg(phy);
|
||||
}
|
||||
|
||||
static int fe_phy_connect(struct fe_priv *priv)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (priv->phy->phy_node[i]) {
|
||||
if (!priv->phy_dev) {
|
||||
priv->phy_dev = priv->phy->phy[i];
|
||||
priv->phy_flags = FE_PHY_FLAG_PORT;
|
||||
}
|
||||
} else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
|
||||
phy_init(priv, priv->mii_bus->phy_map[i]);
|
||||
if (!priv->phy_dev) {
|
||||
priv->phy_dev = priv->mii_bus->phy_map[i];
|
||||
priv->phy_flags = FE_PHY_FLAG_ATTACH;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fe_phy_disconnect(struct fe_priv *priv)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
if (priv->phy->phy_fixed[i]) {
|
||||
spin_lock_irqsave(&priv->phy->lock, flags);
|
||||
priv->link[i] = 0;
|
||||
if (priv->soc->mdio_adjust_link)
|
||||
priv->soc->mdio_adjust_link(priv, i);
|
||||
spin_unlock_irqrestore(&priv->phy->lock, flags);
|
||||
} else if (priv->phy->phy[i]) {
|
||||
phy_disconnect(priv->phy->phy[i]);
|
||||
} else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
|
||||
phy_detach(priv->mii_bus->phy_map[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static void fe_phy_start(struct fe_priv *priv)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (priv->phy->phy_fixed[i]) {
|
||||
spin_lock_irqsave(&priv->phy->lock, flags);
|
||||
priv->link[i] = 1;
|
||||
if (priv->soc->mdio_adjust_link)
|
||||
priv->soc->mdio_adjust_link(priv, i);
|
||||
spin_unlock_irqrestore(&priv->phy->lock, flags);
|
||||
} else if (priv->phy->phy[i]) {
|
||||
phy_start(priv->phy->phy[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void fe_phy_stop(struct fe_priv *priv)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
if (priv->phy->phy_fixed[i]) {
|
||||
spin_lock_irqsave(&priv->phy->lock, flags);
|
||||
priv->link[i] = 0;
|
||||
if (priv->soc->mdio_adjust_link)
|
||||
priv->soc->mdio_adjust_link(priv, i);
|
||||
spin_unlock_irqrestore(&priv->phy->lock, flags);
|
||||
} else if (priv->phy->phy[i]) {
|
||||
phy_stop(priv->phy->phy[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static struct fe_phy phy_ralink = {
|
||||
.connect = fe_phy_connect,
|
||||
.disconnect = fe_phy_disconnect,
|
||||
.start = fe_phy_start,
|
||||
.stop = fe_phy_stop,
|
||||
};
|
||||
|
||||
int fe_mdio_init(struct fe_priv *priv)
|
||||
{
|
||||
struct device_node *mii_np;
|
||||
int err;
|
||||
|
||||
if (!priv->soc->mdio_read || !priv->soc->mdio_write)
|
||||
return 0;
|
||||
|
||||
spin_lock_init(&phy_ralink.lock);
|
||||
priv->phy = &phy_ralink;
|
||||
|
||||
mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
|
||||
if (!mii_np) {
|
||||
dev_err(priv->device, "no %s child node found", "mdio-bus");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!of_device_is_available(mii_np)) {
|
||||
err = 0;
|
||||
goto err_put_node;
|
||||
}
|
||||
|
||||
priv->mii_bus = mdiobus_alloc();
|
||||
if (priv->mii_bus == NULL) {
|
||||
err = -ENOMEM;
|
||||
goto err_put_node;
|
||||
}
|
||||
|
||||
priv->mii_bus->name = "mdio";
|
||||
priv->mii_bus->read = priv->soc->mdio_read;
|
||||
priv->mii_bus->write = priv->soc->mdio_write;
|
||||
priv->mii_bus->reset = fe_mdio_reset;
|
||||
priv->mii_bus->priv = priv;
|
||||
priv->mii_bus->parent = priv->device;
|
||||
|
||||
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
|
||||
err = of_mdiobus_register(priv->mii_bus, mii_np);
|
||||
if (err)
|
||||
goto err_free_bus;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_bus:
|
||||
kfree(priv->mii_bus);
|
||||
err_put_node:
|
||||
of_node_put(mii_np);
|
||||
priv->mii_bus = NULL;
|
||||
return err;
|
||||
}
|
||||
|
||||
void fe_mdio_cleanup(struct fe_priv *priv)
|
||||
{
|
||||
if (!priv->mii_bus)
|
||||
return;
|
||||
|
||||
mdiobus_unregister(priv->mii_bus);
|
||||
of_node_put(priv->mii_bus->dev.of_node);
|
||||
kfree(priv->mii_bus);
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RALINK_MDIO_H__
|
||||
#define _RALINK_MDIO_H__
|
||||
|
||||
#ifdef CONFIG_NET_RALINK_MDIO
|
||||
extern int fe_mdio_init(struct fe_priv *priv);
|
||||
extern void fe_mdio_cleanup(struct fe_priv *priv);
|
||||
extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
|
||||
#else
|
||||
static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
|
||||
static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/of_mdio.h>
|
||||
|
||||
#include "ralink_soc_eth.h"
|
||||
#include "mdio_rt2880.h"
|
||||
#include "mdio.h"
|
||||
|
||||
#define FE_MDIO_RETRY 1000
|
||||
|
||||
static unsigned char *rt2880_speed_str(struct fe_priv *priv)
|
||||
{
|
||||
switch (priv->phy->speed[0]) {
|
||||
case SPEED_1000:
|
||||
return "1000";
|
||||
case SPEED_100:
|
||||
return "100";
|
||||
case SPEED_10:
|
||||
return "10";
|
||||
}
|
||||
|
||||
return "?";
|
||||
}
|
||||
|
||||
void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
|
||||
{
|
||||
u32 mdio_cfg;
|
||||
|
||||
if (!priv->link[0]) {
|
||||
netif_carrier_off(priv->netdev);
|
||||
netdev_info(priv->netdev, "link down\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
|
||||
FE_MDIO_CFG_RX_CLK_SKEW_200 |
|
||||
FE_MDIO_CFG_GP1_FRC_EN;
|
||||
|
||||
if (priv->phy->duplex[0] == DUPLEX_FULL)
|
||||
mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
|
||||
|
||||
if (priv->phy->tx_fc[0])
|
||||
mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
|
||||
|
||||
if (priv->phy->rx_fc[0])
|
||||
mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
|
||||
|
||||
switch (priv->phy->speed[0]) {
|
||||
case SPEED_10:
|
||||
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
|
||||
break;
|
||||
case SPEED_100:
|
||||
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
|
||||
break;
|
||||
case SPEED_1000:
|
||||
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
fe_w32(mdio_cfg, FE_MDIO_CFG);
|
||||
|
||||
netif_carrier_on(priv->netdev);
|
||||
netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
|
||||
rt2880_speed_str(priv),
|
||||
(DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
|
||||
}
|
||||
|
||||
static int rt2880_mdio_wait_ready(struct fe_priv *priv)
|
||||
{
|
||||
int retries;
|
||||
|
||||
retries = FE_MDIO_RETRY;
|
||||
while (1) {
|
||||
u32 t;
|
||||
|
||||
t = fe_r32(FE_MDIO_ACCESS);
|
||||
if ((t & (0x1 << 31)) == 0)
|
||||
return 0;
|
||||
|
||||
if (retries-- == 0)
|
||||
break;
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
dev_err(priv->device, "MDIO operation timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
|
||||
{
|
||||
struct fe_priv *priv = bus->priv;
|
||||
int err;
|
||||
u32 t;
|
||||
|
||||
err = rt2880_mdio_wait_ready(priv);
|
||||
if (err)
|
||||
return 0xffff;
|
||||
|
||||
t = (phy_addr << 24) | (phy_reg << 16);
|
||||
fe_w32(t, FE_MDIO_ACCESS);
|
||||
t |= (1 << 31);
|
||||
fe_w32(t, FE_MDIO_ACCESS);
|
||||
|
||||
err = rt2880_mdio_wait_ready(priv);
|
||||
if (err)
|
||||
return 0xffff;
|
||||
|
||||
pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
|
||||
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
|
||||
|
||||
return fe_r32(FE_MDIO_ACCESS) & 0xffff;
|
||||
}
|
||||
|
||||
int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
|
||||
{
|
||||
struct fe_priv *priv = bus->priv;
|
||||
int err;
|
||||
u32 t;
|
||||
|
||||
pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
|
||||
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
|
||||
|
||||
err = rt2880_mdio_wait_ready(priv);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
|
||||
fe_w32(t, FE_MDIO_ACCESS);
|
||||
t |= (1 << 31);
|
||||
fe_w32(t, FE_MDIO_ACCESS);
|
||||
|
||||
return rt2880_mdio_wait_ready(priv);
|
||||
}
|
||||
|
||||
void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
|
||||
{
|
||||
const __be32 *id = of_get_property(np, "reg", NULL);
|
||||
const __be32 *link;
|
||||
int size;
|
||||
int phy_mode;
|
||||
|
||||
if (!id || (be32_to_cpu(*id) != 0)) {
|
||||
pr_err("%s: invalid port id\n", np->name);
|
||||
return;
|
||||
}
|
||||
|
||||
priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
|
||||
if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
|
||||
pr_err("%s: invalid fixed link property\n", np->name);
|
||||
priv->phy->phy_fixed[0] = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
phy_mode = of_get_phy_mode(np);
|
||||
switch (phy_mode) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
break;
|
||||
default:
|
||||
if (!priv->phy->phy_fixed[0])
|
||||
dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
|
||||
break;
|
||||
}
|
||||
|
||||
priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
|
||||
if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
|
||||
return;
|
||||
|
||||
if (priv->phy->phy_fixed[0]) {
|
||||
link = priv->phy->phy_fixed[0];
|
||||
priv->phy->speed[0] = be32_to_cpup(link++);
|
||||
priv->phy->duplex[0] = be32_to_cpup(link++);
|
||||
priv->phy->tx_fc[0] = be32_to_cpup(link++);
|
||||
priv->phy->rx_fc[0] = be32_to_cpup(link++);
|
||||
|
||||
priv->link[0] = 1;
|
||||
switch (priv->phy->speed[0]) {
|
||||
case SPEED_10:
|
||||
break;
|
||||
case SPEED_100:
|
||||
break;
|
||||
case SPEED_1000:
|
||||
break;
|
||||
default:
|
||||
dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
|
||||
priv->phy->phy_fixed[0] = 0;
|
||||
return;
|
||||
}
|
||||
dev_info(priv->device, "using fixed link parameters\n");
|
||||
rt2880_mdio_link_adjust(priv, 0);
|
||||
return;
|
||||
}
|
||||
if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
|
||||
fe_connect_phy_node(priv, priv->phy->phy_node[0]);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RALINK_MDIO_RT2880_H__
|
||||
#define _RALINK_MDIO_RT2880_H__
|
||||
|
||||
void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
|
||||
int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
|
||||
int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
|
||||
void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,588 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/if.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/if_ether.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/netlink.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <net/genetlink.h>
|
||||
#include <linux/switch.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/lockdep.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#include "mt7530.h"
|
||||
|
||||
#define MT7530_CPU_PORT 6
|
||||
#define MT7530_NUM_PORTS 8
|
||||
#define MT7530_NUM_VLANS 16
|
||||
#define MT7530_MAX_VID 4095
|
||||
#define MT7530_MIN_VID 0
|
||||
|
||||
/* registers */
|
||||
#define REG_ESW_VLAN_VTCR 0x90
|
||||
#define REG_ESW_VLAN_VAWD1 0x94
|
||||
#define REG_ESW_VLAN_VAWD2 0x98
|
||||
#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
|
||||
|
||||
#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
|
||||
#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
|
||||
#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
|
||||
|
||||
/* vlan egress mode */
|
||||
enum {
|
||||
ETAG_CTRL_UNTAG = 0,
|
||||
ETAG_CTRL_TAG = 2,
|
||||
ETAG_CTRL_SWAP = 1,
|
||||
ETAG_CTRL_STACK = 3,
|
||||
};
|
||||
|
||||
#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
|
||||
#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
|
||||
#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
|
||||
|
||||
#define REG_HWTRAP 0x7804
|
||||
|
||||
enum {
|
||||
/* Global attributes. */
|
||||
MT7530_ATTR_ENABLE_VLAN,
|
||||
};
|
||||
|
||||
struct mt7530_port_entry {
|
||||
u16 pvid;
|
||||
};
|
||||
|
||||
struct mt7530_vlan_entry {
|
||||
u16 vid;
|
||||
u8 member;
|
||||
u8 etags;
|
||||
};
|
||||
|
||||
struct mt7530_priv {
|
||||
void __iomem *base;
|
||||
struct mii_bus *bus;
|
||||
struct switch_dev swdev;
|
||||
|
||||
bool global_vlan_enable;
|
||||
struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
|
||||
struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
|
||||
};
|
||||
|
||||
struct mt7530_mapping {
|
||||
char *name;
|
||||
u16 pvids[MT7530_NUM_PORTS];
|
||||
u8 members[MT7530_NUM_VLANS];
|
||||
u8 etags[MT7530_NUM_VLANS];
|
||||
u16 vids[MT7530_NUM_VLANS];
|
||||
} mt7530_defaults[] = {
|
||||
{
|
||||
.name = "llllw",
|
||||
.pvids = { 1, 1, 1, 1, 2, 1, 1 },
|
||||
.members = { 0, 0x6f, 0x50 },
|
||||
.etags = { 0, 0x40, 0x40 },
|
||||
.vids = { 0, 1, 2 },
|
||||
}, {
|
||||
.name = "wllll",
|
||||
.pvids = { 2, 1, 1, 1, 1, 1, 1 },
|
||||
.members = { 0, 0x7e, 0x41 },
|
||||
.etags = { 0, 0x40, 0x40 },
|
||||
.vids = { 0, 1, 2 },
|
||||
},
|
||||
};
|
||||
|
||||
struct mt7530_mapping*
|
||||
mt7530_find_mapping(struct device_node *np)
|
||||
{
|
||||
const char *map;
|
||||
int i;
|
||||
|
||||
if (of_property_read_string(np, "ralink,port-map", &map))
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
|
||||
if (!strcmp(map, mt7530_defaults[i].name))
|
||||
return &mt7530_defaults[i];
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void
|
||||
mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++)
|
||||
mt7530->port_entries[i].pvid = map->pvids[i];
|
||||
|
||||
for (i = 0; i < MT7530_NUM_VLANS; i++) {
|
||||
mt7530->vlan_entries[i].member = map->members[i];
|
||||
mt7530->vlan_entries[i].etags = map->etags[i];
|
||||
mt7530->vlan_entries[i].vid = map->vids[i];
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_reset_switch(struct switch_dev *dev)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
int i;
|
||||
|
||||
memset(priv->port_entries, 0, sizeof(priv->port_entries));
|
||||
memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
|
||||
|
||||
/* set default vid of each vlan to the same number of vlan, so the vid
|
||||
* won't need be set explicitly.
|
||||
*/
|
||||
for (i = 0; i < MT7530_NUM_VLANS; i++) {
|
||||
priv->vlan_entries[i].vid = i;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_get_vlan_enable(struct switch_dev *dev,
|
||||
const struct switch_attr *attr,
|
||||
struct switch_val *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
|
||||
val->value.i = priv->global_vlan_enable;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_set_vlan_enable(struct switch_dev *dev,
|
||||
const struct switch_attr *attr,
|
||||
struct switch_val *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
|
||||
priv->global_vlan_enable = val->value.i != 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32
|
||||
mt7530_r32(struct mt7530_priv *priv, u32 reg)
|
||||
{
|
||||
u32 val;
|
||||
if (priv->bus) {
|
||||
u16 high, low;
|
||||
|
||||
mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
|
||||
low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
|
||||
high = mdiobus_read(priv->bus, 0x1f, 0x10);
|
||||
|
||||
return (high << 16) | (low & 0xffff);
|
||||
}
|
||||
|
||||
val = ioread32(priv->base + reg);
|
||||
pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void
|
||||
mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
|
||||
{
|
||||
if (priv->bus) {
|
||||
mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
|
||||
mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
|
||||
mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
|
||||
iowrite32(val, priv->base + reg);
|
||||
}
|
||||
|
||||
static void
|
||||
mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
|
||||
{
|
||||
int i;
|
||||
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
|
||||
|
||||
for (i = 0; i < 20; i++) {
|
||||
u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
|
||||
|
||||
if ((val & BIT(31)) == 0)
|
||||
break;
|
||||
|
||||
udelay(1000);
|
||||
}
|
||||
if (i == 20)
|
||||
printk("mt7530: vtcr timeout\n");
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
|
||||
if (port >= MT7530_NUM_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
*val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
|
||||
*val &= 0xfff;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
|
||||
if (port >= MT7530_NUM_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
|
||||
return -EINVAL;
|
||||
|
||||
priv->port_entries[port].pvid = pvid;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
u32 member;
|
||||
u32 etags;
|
||||
int i;
|
||||
|
||||
val->len = 0;
|
||||
|
||||
if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
|
||||
return -EINVAL;
|
||||
|
||||
mt7530_vtcr(priv, 0, val->port_vlan);
|
||||
|
||||
member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
|
||||
member >>= 16;
|
||||
member &= 0xff;
|
||||
|
||||
etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
|
||||
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++) {
|
||||
struct switch_port *p;
|
||||
int etag;
|
||||
|
||||
if (!(member & BIT(i)))
|
||||
continue;
|
||||
|
||||
p = &val->value.ports[val->len++];
|
||||
p->id = i;
|
||||
|
||||
etag = (etags >> (i * 2)) & 0x3;
|
||||
|
||||
if (etag == ETAG_CTRL_TAG)
|
||||
p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
|
||||
else if (etag != ETAG_CTRL_UNTAG)
|
||||
printk("vlan egress tag control neither untag nor tag.\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
u8 member = 0;
|
||||
u8 etags = 0;
|
||||
int i;
|
||||
|
||||
if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
|
||||
val->len > MT7530_NUM_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < val->len; i++) {
|
||||
struct switch_port *p = &val->value.ports[i];
|
||||
|
||||
if (p->id >= MT7530_NUM_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
member |= BIT(p->id);
|
||||
|
||||
if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
|
||||
etags |= BIT(p->id);
|
||||
}
|
||||
priv->vlan_entries[val->port_vlan].member = member;
|
||||
priv->vlan_entries[val->port_vlan].etags = etags;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
|
||||
struct switch_val *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
int vlan;
|
||||
u16 vid;
|
||||
|
||||
vlan = val->port_vlan;
|
||||
vid = (u16)val->value.i;
|
||||
|
||||
if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
|
||||
return -EINVAL;
|
||||
|
||||
if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
|
||||
return -EINVAL;
|
||||
|
||||
priv->vlan_entries[vlan].vid = vid;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
|
||||
struct switch_val *val)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
u32 vid;
|
||||
int vlan;
|
||||
|
||||
vlan = val->port_vlan;
|
||||
|
||||
vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
|
||||
if (vlan & 1)
|
||||
vid = vid >> 12;
|
||||
vid &= 0xfff;
|
||||
|
||||
val->value.i = vid;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_apply_config(struct switch_dev *dev)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
int i, j;
|
||||
|
||||
if (!priv->global_vlan_enable) {
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++)
|
||||
mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
|
||||
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++)
|
||||
mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* set all ports as security mode */
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++)
|
||||
mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
|
||||
|
||||
/* set all ports as user port */
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++)
|
||||
mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
|
||||
|
||||
for (i = 0; i < MT7530_NUM_VLANS; i++) {
|
||||
u16 vid = priv->vlan_entries[i].vid;
|
||||
u8 member = priv->vlan_entries[i].member;
|
||||
u8 etags = priv->vlan_entries[i].etags;
|
||||
u32 val;
|
||||
|
||||
/* vid of vlan */
|
||||
val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
|
||||
if (i % 2 == 0) {
|
||||
val &= 0xfff000;
|
||||
val |= vid;
|
||||
} else {
|
||||
val &= 0xfff;
|
||||
val |= (vid << 12);
|
||||
}
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
|
||||
|
||||
/* vlan port membership */
|
||||
if (member)
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
|
||||
REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
|
||||
REG_ESW_VLAN_VAWD1_VALID);
|
||||
else
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
|
||||
|
||||
/* egress mode */
|
||||
val = 0;
|
||||
for (j = 0; j < MT7530_NUM_PORTS; j++) {
|
||||
if (etags & BIT(j))
|
||||
val |= ETAG_CTRL_TAG << (j * 2);
|
||||
else
|
||||
val |= ETAG_CTRL_UNTAG << (j * 2);
|
||||
}
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
|
||||
|
||||
/* write to vlan table */
|
||||
mt7530_vtcr(priv, 1, i);
|
||||
}
|
||||
|
||||
/* Port Default PVID */
|
||||
for (i = 0; i < MT7530_NUM_PORTS; i++) {
|
||||
u32 val;
|
||||
val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
|
||||
val &= ~0xfff;
|
||||
val |= priv->port_entries[i].pvid;
|
||||
mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mt7530_get_port_link(struct switch_dev *dev, int port,
|
||||
struct switch_port_link *link)
|
||||
{
|
||||
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
|
||||
u32 speed, pmsr;
|
||||
|
||||
if (port < 0 || port >= MT7530_NUM_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
|
||||
|
||||
link->link = pmsr & 1;
|
||||
link->duplex = (pmsr >> 1) & 1;
|
||||
speed = (pmsr >> 2) & 3;
|
||||
|
||||
switch (speed) {
|
||||
case 0:
|
||||
link->speed = SWITCH_PORT_SPEED_10;
|
||||
break;
|
||||
case 1:
|
||||
link->speed = SWITCH_PORT_SPEED_100;
|
||||
break;
|
||||
case 2:
|
||||
case 3: /* forced gige speed can be 2 or 3 */
|
||||
link->speed = SWITCH_PORT_SPEED_1000;
|
||||
break;
|
||||
default:
|
||||
link->speed = SWITCH_PORT_SPEED_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct switch_attr mt7530_global[] = {
|
||||
{
|
||||
.type = SWITCH_TYPE_INT,
|
||||
.name = "enable_vlan",
|
||||
.description = "VLAN mode (1:enabled)",
|
||||
.max = 1,
|
||||
.id = MT7530_ATTR_ENABLE_VLAN,
|
||||
.get = mt7530_get_vlan_enable,
|
||||
.set = mt7530_set_vlan_enable,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct switch_attr mt7530_port[] = {
|
||||
};
|
||||
|
||||
static const struct switch_attr mt7530_vlan[] = {
|
||||
{
|
||||
.type = SWITCH_TYPE_INT,
|
||||
.name = "vid",
|
||||
.description = "VLAN ID (0-4094)",
|
||||
.set = mt7530_set_vid,
|
||||
.get = mt7530_get_vid,
|
||||
.max = 4094,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct switch_dev_ops mt7530_ops = {
|
||||
.attr_global = {
|
||||
.attr = mt7530_global,
|
||||
.n_attr = ARRAY_SIZE(mt7530_global),
|
||||
},
|
||||
.attr_port = {
|
||||
.attr = mt7530_port,
|
||||
.n_attr = ARRAY_SIZE(mt7530_port),
|
||||
},
|
||||
.attr_vlan = {
|
||||
.attr = mt7530_vlan,
|
||||
.n_attr = ARRAY_SIZE(mt7530_vlan),
|
||||
},
|
||||
.get_vlan_ports = mt7530_get_vlan_ports,
|
||||
.set_vlan_ports = mt7530_set_vlan_ports,
|
||||
.get_port_pvid = mt7530_get_port_pvid,
|
||||
.set_port_pvid = mt7530_set_port_pvid,
|
||||
.get_port_link = mt7530_get_port_link,
|
||||
.apply_config = mt7530_apply_config,
|
||||
.reset_switch = mt7530_reset_switch,
|
||||
};
|
||||
|
||||
int
|
||||
mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
|
||||
{
|
||||
struct switch_dev *swdev;
|
||||
struct mt7530_priv *mt7530;
|
||||
struct mt7530_mapping *map;
|
||||
int ret;
|
||||
|
||||
mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
|
||||
if (!mt7530)
|
||||
return -ENOMEM;
|
||||
|
||||
mt7530->base = base;
|
||||
mt7530->bus = bus;
|
||||
mt7530->global_vlan_enable = vlan;
|
||||
|
||||
swdev = &mt7530->swdev;
|
||||
if (bus) {
|
||||
swdev->alias = "mt7530";
|
||||
swdev->name = "mt7530";
|
||||
} else {
|
||||
swdev->alias = "mt7620";
|
||||
swdev->name = "mt7620";
|
||||
}
|
||||
swdev->cpu_port = MT7530_CPU_PORT;
|
||||
swdev->ports = MT7530_NUM_PORTS;
|
||||
swdev->vlans = MT7530_NUM_VLANS;
|
||||
swdev->ops = &mt7530_ops;
|
||||
|
||||
ret = register_switch(swdev, NULL);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register mt7530\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
map = mt7530_find_mapping(dev->of_node);
|
||||
if (map)
|
||||
mt7530_apply_mapping(mt7530, map);
|
||||
mt7530_apply_config(swdev);
|
||||
|
||||
/* magic vodoo */
|
||||
if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
|
||||
dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
|
||||
mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
|
||||
}
|
||||
dev_info(dev, "loaded %s driver\n", swdev->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _MT7530_H__
|
||||
#define _MT7530_H__
|
||||
|
||||
int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 Michael Lee <igvtee@gmail.com>
|
||||
*/
|
||||
|
||||
#include "ralink_soc_eth.h"
|
||||
|
||||
static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
|
||||
#define _FE(x...) # x,
|
||||
FE_STAT_REG_DECLARE
|
||||
#undef _FE
|
||||
};
|
||||
|
||||
static int fe_get_settings(struct net_device *dev,
|
||||
struct ethtool_cmd *cmd)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
int err;
|
||||
|
||||
if (!priv->phy_dev)
|
||||
goto out_gset;
|
||||
|
||||
if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
|
||||
err = phy_read_status(priv->phy_dev);
|
||||
if (err)
|
||||
goto out_gset;
|
||||
}
|
||||
|
||||
return phy_ethtool_gset(priv->phy_dev, cmd);
|
||||
|
||||
out_gset:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int fe_set_settings(struct net_device *dev,
|
||||
struct ethtool_cmd *cmd)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
|
||||
if (!priv->phy_dev)
|
||||
goto out_sset;
|
||||
|
||||
if (cmd->phy_address != priv->phy_dev->addr) {
|
||||
if (priv->phy->phy_node[cmd->phy_address]) {
|
||||
priv->phy_dev = priv->phy->phy[cmd->phy_address];
|
||||
priv->phy_flags = FE_PHY_FLAG_PORT;
|
||||
} else if (priv->mii_bus &&
|
||||
priv->mii_bus->phy_map[cmd->phy_address]) {
|
||||
priv->phy_dev = priv->mii_bus->phy_map[cmd->phy_address];
|
||||
priv->phy_flags = FE_PHY_FLAG_ATTACH;
|
||||
} else
|
||||
goto out_sset;
|
||||
}
|
||||
|
||||
return phy_ethtool_sset(priv->phy_dev, cmd);
|
||||
|
||||
out_sset:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void fe_get_drvinfo (struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
struct fe_soc_data *soc = priv->soc;
|
||||
|
||||
strlcpy(info->driver, priv->device->driver->name, sizeof(info->driver));
|
||||
strlcpy(info->version, FE_DRV_VERSION, sizeof(info->version));
|
||||
strlcpy(info->bus_info, dev_name(priv->device), sizeof(info->bus_info));
|
||||
|
||||
if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
|
||||
info->n_stats = ARRAY_SIZE(fe_gdma_str);
|
||||
}
|
||||
|
||||
static u32 fe_get_msglevel(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
|
||||
return priv->msg_enable;
|
||||
}
|
||||
|
||||
static void fe_set_msglevel(struct net_device *dev, u32 value)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
|
||||
priv->msg_enable = value;
|
||||
}
|
||||
|
||||
static int fe_nway_reset(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
|
||||
if (!priv->phy_dev)
|
||||
goto out_nway_reset;
|
||||
|
||||
return genphy_restart_aneg(priv->phy_dev);
|
||||
|
||||
out_nway_reset:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static u32 fe_get_link(struct net_device *dev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
int err;
|
||||
|
||||
if (!priv->phy_dev)
|
||||
goto out_get_link;
|
||||
|
||||
if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
|
||||
err = genphy_update_link(priv->phy_dev);
|
||||
if (err)
|
||||
goto out_get_link;
|
||||
}
|
||||
|
||||
return priv->phy_dev->link;
|
||||
|
||||
out_get_link:
|
||||
return ethtool_op_get_link(dev);
|
||||
}
|
||||
|
||||
static void fe_get_ringparam(struct net_device *dev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
ring->rx_max_pending = MAX_DMA_DESC;
|
||||
ring->tx_max_pending = MAX_DMA_DESC;
|
||||
ring->rx_pending = NUM_DMA_DESC;
|
||||
ring->tx_pending = NUM_DMA_DESC;
|
||||
}
|
||||
|
||||
static int fe_get_coalesce(struct net_device *dev,
|
||||
struct ethtool_coalesce *coal)
|
||||
{
|
||||
u32 delay_cfg = fe_reg_r32(FE_REG_DLY_INT_CFG);
|
||||
|
||||
coal->rx_coalesce_usecs = (delay_cfg & 0xff) * FE_DELAY_TIME;
|
||||
coal->rx_max_coalesced_frames = ((delay_cfg >> 8) & 0x7f);
|
||||
coal->use_adaptive_rx_coalesce = (delay_cfg >> 15) & 0x1;
|
||||
|
||||
coal->tx_coalesce_usecs = ((delay_cfg >> 16 )& 0xff) * FE_DELAY_TIME;
|
||||
coal->tx_max_coalesced_frames = ((delay_cfg >> 24) & 0x7f);
|
||||
coal->use_adaptive_tx_coalesce = (delay_cfg >> 31) & 0x1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fe_set_coalesce(struct net_device *dev,
|
||||
struct ethtool_coalesce *coal)
|
||||
{
|
||||
u32 delay_cfg;
|
||||
u32 rx_usecs, tx_usecs;
|
||||
u32 rx_frames, tx_frames;
|
||||
|
||||
if (!coal->use_adaptive_rx_coalesce || !coal->use_adaptive_tx_coalesce)
|
||||
return -EINVAL;
|
||||
|
||||
rx_usecs = DIV_ROUND_UP(coal->rx_coalesce_usecs, FE_DELAY_TIME);
|
||||
rx_frames = coal->rx_max_coalesced_frames;
|
||||
tx_usecs = DIV_ROUND_UP(coal->tx_coalesce_usecs, FE_DELAY_TIME);
|
||||
tx_frames = coal->tx_max_coalesced_frames;
|
||||
|
||||
if (((tx_usecs == 0) && (tx_frames ==0)) ||
|
||||
((rx_usecs == 0) && (rx_frames ==0)))
|
||||
return -EINVAL;
|
||||
|
||||
if (rx_usecs > 0xff) rx_usecs = 0xff;
|
||||
if (rx_frames > 0x7f) rx_frames = 0x7f;
|
||||
if (tx_usecs > 0xff) tx_usecs = 0xff;
|
||||
if (tx_frames > 0x7f) tx_frames = 0x7f;
|
||||
|
||||
delay_cfg = ((((FE_DELAY_EN_INT | tx_frames) << 8) | tx_usecs) << 16) |
|
||||
(((FE_DELAY_EN_INT | rx_frames) << 8) | rx_usecs);
|
||||
|
||||
fe_reg_w32(delay_cfg, FE_REG_DLY_INT_CFG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
|
||||
{
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int fe_get_sset_count(struct net_device *dev, int sset)
|
||||
{
|
||||
switch (sset) {
|
||||
case ETH_SS_STATS:
|
||||
return ARRAY_SIZE(fe_gdma_str);
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
static void fe_get_ethtool_stats(struct net_device *dev,
|
||||
struct ethtool_stats *stats, u64 *data)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(dev);
|
||||
struct fe_hw_stats *hwstats = priv->hw_stats;
|
||||
u64 *data_src, *data_dst;
|
||||
unsigned int start;
|
||||
int i;
|
||||
|
||||
if (netif_running(dev) && netif_device_present(dev)) {
|
||||
if (spin_trylock(&hwstats->stats_lock)) {
|
||||
fe_stats_update(priv);
|
||||
spin_unlock(&hwstats->stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
do {
|
||||
data_src = &hwstats->tx_bytes;
|
||||
data_dst = data;
|
||||
start = u64_stats_fetch_begin_bh(&hwstats->syncp);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
|
||||
*data_dst++ = *data_src++;
|
||||
|
||||
} while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
|
||||
}
|
||||
|
||||
static struct ethtool_ops fe_ethtool_ops = {
|
||||
.get_settings = fe_get_settings,
|
||||
.set_settings = fe_set_settings,
|
||||
.get_drvinfo = fe_get_drvinfo,
|
||||
.get_msglevel = fe_get_msglevel,
|
||||
.set_msglevel = fe_set_msglevel,
|
||||
.nway_reset = fe_nway_reset,
|
||||
.get_link = fe_get_link,
|
||||
.get_ringparam = fe_get_ringparam,
|
||||
.get_coalesce = fe_get_coalesce,
|
||||
.set_coalesce = fe_set_coalesce,
|
||||
};
|
||||
|
||||
void fe_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(netdev);
|
||||
struct fe_soc_data *soc = priv->soc;
|
||||
|
||||
if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
|
||||
fe_ethtool_ops.get_strings = fe_get_strings;
|
||||
fe_ethtool_ops.get_sset_count = fe_get_sset_count;
|
||||
fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
|
||||
}
|
||||
|
||||
SET_ETHTOOL_OPS(netdev, &fe_ethtool_ops);
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 Michael Lee <igvtee@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef FE_ETHTOOL_H
|
||||
#define FE_ETHTOOL_H
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
|
||||
void fe_set_ethtool_ops(struct net_device *netdev);
|
||||
|
||||
#endif /* FE_ETHTOOL_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,455 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* based on Ralink SDK3.3
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef FE_ETH_H
|
||||
#define FE_ETH_H
|
||||
|
||||
#include <linux/mii.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/ethtool.h>
|
||||
|
||||
enum fe_reg {
|
||||
FE_REG_PDMA_GLO_CFG = 0,
|
||||
FE_REG_PDMA_RST_CFG,
|
||||
FE_REG_DLY_INT_CFG,
|
||||
FE_REG_TX_BASE_PTR0,
|
||||
FE_REG_TX_MAX_CNT0,
|
||||
FE_REG_TX_CTX_IDX0,
|
||||
FE_REG_RX_BASE_PTR0,
|
||||
FE_REG_RX_MAX_CNT0,
|
||||
FE_REG_RX_CALC_IDX0,
|
||||
FE_REG_FE_INT_ENABLE,
|
||||
FE_REG_FE_INT_STATUS,
|
||||
FE_REG_FE_DMA_VID_BASE,
|
||||
FE_REG_FE_COUNTER_BASE,
|
||||
FE_REG_FE_RST_GL,
|
||||
FE_REG_COUNT
|
||||
};
|
||||
|
||||
#define FE_DRV_VERSION "0.1.0"
|
||||
|
||||
/* power of 2 to let NEXT_TX_DESP_IDX work */
|
||||
#define NUM_DMA_DESC (1 << 7)
|
||||
#define MAX_DMA_DESC 0xfff
|
||||
|
||||
#define FE_DELAY_EN_INT 0x80
|
||||
#define FE_DELAY_MAX_INT 0x04
|
||||
#define FE_DELAY_MAX_TOUT 0x04
|
||||
#define FE_DELAY_TIME 20
|
||||
#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
|
||||
#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
|
||||
#define FE_PSE_FQFC_CFG_INIT 0x80504000
|
||||
#define FE_PSE_FQFC_CFG_256Q 0xff908000
|
||||
|
||||
/* interrupt bits */
|
||||
#define FE_CNT_PPE_AF BIT(31)
|
||||
#define FE_CNT_GDM_AF BIT(29)
|
||||
#define FE_PSE_P2_FC BIT(26)
|
||||
#define FE_PSE_BUF_DROP BIT(24)
|
||||
#define FE_GDM_OTHER_DROP BIT(23)
|
||||
#define FE_PSE_P1_FC BIT(22)
|
||||
#define FE_PSE_P0_FC BIT(21)
|
||||
#define FE_PSE_FQ_EMPTY BIT(20)
|
||||
#define FE_GE1_STA_CHG BIT(18)
|
||||
#define FE_TX_COHERENT BIT(17)
|
||||
#define FE_RX_COHERENT BIT(16)
|
||||
#define FE_TX_DONE_INT3 BIT(11)
|
||||
#define FE_TX_DONE_INT2 BIT(10)
|
||||
#define FE_TX_DONE_INT1 BIT(9)
|
||||
#define FE_TX_DONE_INT0 BIT(8)
|
||||
#define FE_RX_DONE_INT0 BIT(2)
|
||||
#define FE_TX_DLY_INT BIT(1)
|
||||
#define FE_RX_DLY_INT BIT(0)
|
||||
|
||||
#define RT5350_RX_DLY_INT BIT(30)
|
||||
#define RT5350_TX_DLY_INT BIT(28)
|
||||
|
||||
/* registers */
|
||||
#define FE_FE_OFFSET 0x0000
|
||||
#define FE_GDMA_OFFSET 0x0020
|
||||
#define FE_PSE_OFFSET 0x0040
|
||||
#define FE_GDMA2_OFFSET 0x0060
|
||||
#define FE_CDMA_OFFSET 0x0080
|
||||
#define FE_DMA_VID0 0x00a8
|
||||
#define FE_PDMA_OFFSET 0x0100
|
||||
#define FE_PPE_OFFSET 0x0200
|
||||
#define FE_CMTABLE_OFFSET 0x0400
|
||||
#define FE_POLICYTABLE_OFFSET 0x1000
|
||||
|
||||
#define RT5350_PDMA_OFFSET 0x0800
|
||||
#define RT5350_SDM_OFFSET 0x0c00
|
||||
|
||||
#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
|
||||
#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
|
||||
#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
|
||||
#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
|
||||
#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
|
||||
#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
|
||||
#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
|
||||
#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
|
||||
|
||||
#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
|
||||
#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
|
||||
#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
|
||||
#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
|
||||
#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
|
||||
|
||||
#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
|
||||
#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
|
||||
#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
|
||||
#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
|
||||
#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
|
||||
|
||||
#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
|
||||
#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
|
||||
#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
|
||||
#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
|
||||
|
||||
#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
|
||||
#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
|
||||
|
||||
#ifdef CONFIG_SOC_MT7621
|
||||
#define MT7620A_GDMA_OFFSET 0x0500
|
||||
#else
|
||||
#define MT7620A_GDMA_OFFSET 0x0600
|
||||
#endif
|
||||
#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
|
||||
#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
|
||||
#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
|
||||
#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
|
||||
#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
|
||||
|
||||
#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
|
||||
#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
|
||||
#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
|
||||
#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
|
||||
#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
|
||||
#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
|
||||
#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
|
||||
#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
|
||||
#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
|
||||
#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
|
||||
#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
|
||||
#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
|
||||
#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
|
||||
#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
|
||||
#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
|
||||
#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
|
||||
#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
|
||||
#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
|
||||
#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
|
||||
#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
|
||||
#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
|
||||
#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
|
||||
#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
|
||||
#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
|
||||
#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
|
||||
#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
|
||||
#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
|
||||
#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
|
||||
#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
|
||||
#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
|
||||
|
||||
#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
|
||||
#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
|
||||
#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
|
||||
#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
|
||||
#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
|
||||
#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
|
||||
#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
|
||||
#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
|
||||
#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
|
||||
#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
|
||||
#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
|
||||
#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
|
||||
#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
|
||||
#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
|
||||
#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
|
||||
#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
|
||||
#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
|
||||
#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
|
||||
#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
|
||||
#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
|
||||
#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
|
||||
#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
|
||||
#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
|
||||
#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
|
||||
#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
|
||||
#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
|
||||
#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
|
||||
#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
|
||||
|
||||
#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
|
||||
#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
|
||||
#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
|
||||
#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
|
||||
#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
|
||||
#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
|
||||
#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
|
||||
#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
|
||||
#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
|
||||
#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
|
||||
|
||||
#define RT5350_SDM_ICS_EN BIT(16)
|
||||
#define RT5350_SDM_TCS_EN BIT(17)
|
||||
#define RT5350_SDM_UCS_EN BIT(18)
|
||||
|
||||
|
||||
/* MDIO_CFG register bits */
|
||||
#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
|
||||
#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
|
||||
#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
|
||||
#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
|
||||
#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
|
||||
#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
|
||||
#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
|
||||
#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
|
||||
#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
|
||||
#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
|
||||
#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
|
||||
#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
|
||||
#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
|
||||
#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
|
||||
#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
|
||||
#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
|
||||
#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
|
||||
#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
|
||||
#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
|
||||
#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
|
||||
#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
|
||||
#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
|
||||
#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
|
||||
#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
|
||||
#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
|
||||
|
||||
/* uni-cast port */
|
||||
#define FE_GDM1_JMB_LEN_MASK 0xf
|
||||
#define FE_GDM1_JMB_LEN_SHIFT 28
|
||||
#define FE_GDM1_ICS_EN BIT(22)
|
||||
#define FE_GDM1_TCS_EN BIT(21)
|
||||
#define FE_GDM1_UCS_EN BIT(20)
|
||||
#define FE_GDM1_JMB_EN BIT(19)
|
||||
#define FE_GDM1_STRPCRC BIT(16)
|
||||
#define FE_GDM1_UFRC_P_CPU (0 << 12)
|
||||
#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
|
||||
#define FE_GDM1_UFRC_P_PPE (6 << 12)
|
||||
|
||||
/* checksums */
|
||||
#define FE_ICS_GEN_EN BIT(2)
|
||||
#define FE_UCS_GEN_EN BIT(1)
|
||||
#define FE_TCS_GEN_EN BIT(0)
|
||||
|
||||
/* dma ring */
|
||||
#define FE_PST_DRX_IDX0 BIT(16)
|
||||
#define FE_PST_DTX_IDX3 BIT(3)
|
||||
#define FE_PST_DTX_IDX2 BIT(2)
|
||||
#define FE_PST_DTX_IDX1 BIT(1)
|
||||
#define FE_PST_DTX_IDX0 BIT(0)
|
||||
|
||||
#define FE_TX_WB_DDONE BIT(6)
|
||||
#define FE_RX_DMA_BUSY BIT(3)
|
||||
#define FE_TX_DMA_BUSY BIT(1)
|
||||
#define FE_RX_DMA_EN BIT(2)
|
||||
#define FE_TX_DMA_EN BIT(0)
|
||||
|
||||
#define FE_PDMA_SIZE_4DWORDS (0 << 4)
|
||||
#define FE_PDMA_SIZE_8DWORDS (1 << 4)
|
||||
#define FE_PDMA_SIZE_16DWORDS (2 << 4)
|
||||
|
||||
#define FE_US_CYC_CNT_MASK 0xff
|
||||
#define FE_US_CYC_CNT_SHIFT 0x8
|
||||
#define FE_US_CYC_CNT_DIVISOR 1000000
|
||||
|
||||
#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
|
||||
#define RX_DMA_LSO BIT(30)
|
||||
#define RX_DMA_DONE BIT(31)
|
||||
#define RX_DMA_L4VALID BIT(30)
|
||||
|
||||
struct fe_rx_dma {
|
||||
unsigned int rxd1;
|
||||
unsigned int rxd2;
|
||||
unsigned int rxd3;
|
||||
unsigned int rxd4;
|
||||
} __packed __aligned(4);
|
||||
|
||||
#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
|
||||
#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
|
||||
#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
|
||||
#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
|
||||
#define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
|
||||
#define TX_DMA_LS1 BIT(14)
|
||||
#define TX_DMA_LS0 BIT(30)
|
||||
#define TX_DMA_DONE BIT(31)
|
||||
|
||||
#define TX_DMA_INS_VLAN_MT7621 BIT(16)
|
||||
#define TX_DMA_INS_VLAN BIT(7)
|
||||
#define TX_DMA_INS_PPPOE BIT(12)
|
||||
#define TX_DMA_QN(_x) ((_x) << 16)
|
||||
#define TX_DMA_PN(_x) ((_x) << 24)
|
||||
#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
|
||||
#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
|
||||
#define TX_DMA_UDF BIT(20)
|
||||
#define TX_DMA_CHKSUM (0x7 << 29)
|
||||
#define TX_DMA_TSO BIT(28)
|
||||
|
||||
/* frame engine counters */
|
||||
#define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
|
||||
#define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
|
||||
#define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
|
||||
|
||||
/* phy device flags */
|
||||
#define FE_PHY_FLAG_PORT BIT(0)
|
||||
#define FE_PHY_FLAG_ATTACH BIT(1)
|
||||
|
||||
struct fe_tx_dma {
|
||||
unsigned int txd1;
|
||||
unsigned int txd2;
|
||||
unsigned int txd3;
|
||||
unsigned int txd4;
|
||||
} __packed __aligned(4);
|
||||
|
||||
struct fe_priv;
|
||||
|
||||
struct fe_phy {
|
||||
struct phy_device *phy[8];
|
||||
struct device_node *phy_node[8];
|
||||
const __be32 *phy_fixed[8];
|
||||
int duplex[8];
|
||||
int speed[8];
|
||||
int tx_fc[8];
|
||||
int rx_fc[8];
|
||||
spinlock_t lock;
|
||||
|
||||
int (*connect)(struct fe_priv *priv);
|
||||
void (*disconnect)(struct fe_priv *priv);
|
||||
void (*start)(struct fe_priv *priv);
|
||||
void (*stop)(struct fe_priv *priv);
|
||||
};
|
||||
|
||||
struct fe_soc_data
|
||||
{
|
||||
unsigned char mac[6];
|
||||
const u32 *reg_table;
|
||||
|
||||
void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
|
||||
void (*reset_fe)(void);
|
||||
void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
|
||||
int (*fwd_config)(struct fe_priv *priv);
|
||||
void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
|
||||
void (*rx_dma)(struct fe_priv *priv, int idx, int len);
|
||||
int (*switch_init)(struct fe_priv *priv);
|
||||
int (*switch_config)(struct fe_priv *priv);
|
||||
void (*port_init)(struct fe_priv *priv, struct device_node *port);
|
||||
int (*has_carrier)(struct fe_priv *priv);
|
||||
int (*mdio_init)(struct fe_priv *priv);
|
||||
void (*mdio_cleanup)(struct fe_priv *priv);
|
||||
int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
|
||||
int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
|
||||
void (*mdio_adjust_link)(struct fe_priv *priv, int port);
|
||||
|
||||
void *swpriv;
|
||||
u32 pdma_glo_cfg;
|
||||
u32 rx_dly_int;
|
||||
u32 tx_dly_int;
|
||||
u32 checksum_bit;
|
||||
u32 tx_udf_bit;
|
||||
};
|
||||
|
||||
#define FE_FLAG_PADDING_64B BIT(0)
|
||||
#define FE_FLAG_PADDING_BUG BIT(1)
|
||||
#define FE_FLAG_JUMBO_FRAME BIT(2)
|
||||
|
||||
#define FE_STAT_REG_DECLARE \
|
||||
_FE(tx_bytes) \
|
||||
_FE(tx_packets) \
|
||||
_FE(tx_skip) \
|
||||
_FE(tx_collisions) \
|
||||
_FE(rx_bytes) \
|
||||
_FE(rx_packets) \
|
||||
_FE(rx_overflow) \
|
||||
_FE(rx_fcs_errors) \
|
||||
_FE(rx_short_errors) \
|
||||
_FE(rx_long_errors) \
|
||||
_FE(rx_checksum_errors) \
|
||||
_FE(rx_flow_control_packets)
|
||||
|
||||
struct fe_hw_stats
|
||||
{
|
||||
spinlock_t stats_lock;
|
||||
struct u64_stats_sync syncp;
|
||||
#define _FE(x) u64 x;
|
||||
FE_STAT_REG_DECLARE
|
||||
#undef _FE
|
||||
};
|
||||
|
||||
struct fe_priv
|
||||
{
|
||||
spinlock_t page_lock;
|
||||
|
||||
struct fe_soc_data *soc;
|
||||
struct net_device *netdev;
|
||||
u32 msg_enable;
|
||||
u32 flags;
|
||||
|
||||
struct device *device;
|
||||
unsigned long sysclk;
|
||||
|
||||
u16 frag_size;
|
||||
u16 rx_buf_size;
|
||||
struct fe_rx_dma *rx_dma;
|
||||
u8 **rx_data;
|
||||
dma_addr_t rx_phys;
|
||||
struct napi_struct rx_napi;
|
||||
|
||||
struct fe_tx_dma *tx_dma;
|
||||
struct sk_buff **tx_skb;
|
||||
dma_addr_t tx_phys;
|
||||
unsigned int tx_free_idx;
|
||||
|
||||
struct fe_phy *phy;
|
||||
struct mii_bus *mii_bus;
|
||||
struct phy_device *phy_dev;
|
||||
u32 phy_flags;
|
||||
|
||||
int link[8];
|
||||
|
||||
struct fe_hw_stats *hw_stats;
|
||||
unsigned long vlan_map;
|
||||
};
|
||||
|
||||
extern const struct of_device_id of_fe_match[];
|
||||
|
||||
void fe_w32(u32 val, unsigned reg);
|
||||
u32 fe_r32(unsigned reg);
|
||||
|
||||
int fe_set_clock_cycle(struct fe_priv *priv);
|
||||
void fe_csum_config(struct fe_priv *priv);
|
||||
void fe_stats_update(struct fe_priv *priv);
|
||||
void fe_fwd_config(struct fe_priv *priv);
|
||||
void fe_reg_w32(u32 val, enum fe_reg reg);
|
||||
u32 fe_reg_r32(enum fe_reg reg);
|
||||
|
||||
static inline void *priv_netdev(struct fe_priv *priv)
|
||||
{
|
||||
return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
|
||||
}
|
||||
|
||||
#endif /* FE_ETH_H */
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/if_vlan.h>
|
||||
|
||||
#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
#include <mt7620.h>
|
||||
#include "ralink_soc_eth.h"
|
||||
#include "gsw_mt7620a.h"
|
||||
|
||||
#define MT7620A_CDMA_CSG_CFG 0x400
|
||||
#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
|
||||
#define MT7621_DMA_VID 0xa8
|
||||
#define MT7620A_DMA_2B_OFFSET BIT(31)
|
||||
#define MT7620A_RESET_FE BIT(21)
|
||||
#define MT7621_RESET_FE BIT(6)
|
||||
#define MT7620A_RESET_ESW BIT(23)
|
||||
#define MT7620_L4_VALID BIT(23)
|
||||
#define MT7621_L4_VALID BIT(24)
|
||||
|
||||
#define MT7620_TX_DMA_UDF BIT(15)
|
||||
#define MT7621_TX_DMA_UDF BIT(19)
|
||||
#define TX_DMA_FP_BMAP ((0xff) << 19)
|
||||
|
||||
#define SYSC_REG_RESET_CTRL 0x34
|
||||
|
||||
#define CDMA_ICS_EN BIT(2)
|
||||
#define CDMA_UCS_EN BIT(1)
|
||||
#define CDMA_TCS_EN BIT(0)
|
||||
|
||||
#define GDMA_ICS_EN BIT(22)
|
||||
#define GDMA_TCS_EN BIT(21)
|
||||
#define GDMA_UCS_EN BIT(20)
|
||||
|
||||
/* frame engine counters */
|
||||
#define MT7620_REG_MIB_OFFSET 0x1000
|
||||
#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
|
||||
#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
|
||||
#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
|
||||
|
||||
#define MT7621_REG_MIB_OFFSET 0x2000
|
||||
#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
|
||||
#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
|
||||
#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
|
||||
|
||||
#define GSW_REG_GDMA1_MAC_ADRL 0x508
|
||||
#define GSW_REG_GDMA1_MAC_ADRH 0x50C
|
||||
|
||||
#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
|
||||
|
||||
static const u32 mt7620_reg_table[FE_REG_COUNT] = {
|
||||
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
|
||||
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
|
||||
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
|
||||
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
|
||||
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
|
||||
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
|
||||
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
|
||||
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
|
||||
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
|
||||
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
|
||||
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
|
||||
[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
|
||||
[FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
|
||||
[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
|
||||
};
|
||||
|
||||
static const u32 mt7621_reg_table[FE_REG_COUNT] = {
|
||||
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
|
||||
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
|
||||
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
|
||||
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
|
||||
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
|
||||
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
|
||||
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
|
||||
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
|
||||
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
|
||||
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
|
||||
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
|
||||
[FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
|
||||
[FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
|
||||
[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
|
||||
};
|
||||
|
||||
static void mt7620_fe_reset(void)
|
||||
{
|
||||
u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
|
||||
rt_sysc_w32(val | MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
|
||||
rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
}
|
||||
|
||||
static void mt7621_fe_reset(void)
|
||||
{
|
||||
u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
|
||||
|
||||
rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL);
|
||||
rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
|
||||
}
|
||||
|
||||
static void mt7620_rxcsum_config(bool enable)
|
||||
{
|
||||
if (enable)
|
||||
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
|
||||
GDMA_TCS_EN | GDMA_UCS_EN),
|
||||
MT7620A_GDMA1_FWD_CFG);
|
||||
else
|
||||
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
|
||||
GDMA_TCS_EN | GDMA_UCS_EN),
|
||||
MT7620A_GDMA1_FWD_CFG);
|
||||
}
|
||||
|
||||
static void mt7620_txcsum_config(bool enable)
|
||||
{
|
||||
if (enable)
|
||||
fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
|
||||
CDMA_UCS_EN | CDMA_TCS_EN),
|
||||
MT7620A_CDMA_CSG_CFG);
|
||||
else
|
||||
fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
|
||||
CDMA_UCS_EN | CDMA_TCS_EN),
|
||||
MT7620A_CDMA_CSG_CFG);
|
||||
}
|
||||
|
||||
static int mt7620_fwd_config(struct fe_priv *priv)
|
||||
{
|
||||
struct net_device *dev = priv_netdev(priv);
|
||||
|
||||
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
|
||||
|
||||
mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
|
||||
mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt7621_fwd_config(struct fe_priv *priv)
|
||||
{
|
||||
struct net_device *dev = priv_netdev(priv);
|
||||
|
||||
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
|
||||
|
||||
mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
|
||||
mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
|
||||
{
|
||||
priv->tx_dma[idx].txd4 = 0;
|
||||
}
|
||||
|
||||
static void mt7621_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
|
||||
{
|
||||
priv->tx_dma[idx].txd4 = BIT(25);
|
||||
}
|
||||
|
||||
static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
|
||||
{
|
||||
priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
|
||||
}
|
||||
|
||||
static void mt7620_init_data(struct fe_soc_data *data,
|
||||
struct net_device *netdev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(netdev);
|
||||
|
||||
priv->flags = FE_FLAG_PADDING_64B;
|
||||
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
|
||||
NETIF_F_HW_VLAN_CTAG_TX;
|
||||
|
||||
if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
|
||||
netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
|
||||
NETIF_F_IPV6_CSUM;
|
||||
}
|
||||
|
||||
static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&priv->page_lock, flags);
|
||||
fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
|
||||
fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
|
||||
GSW_REG_GDMA1_MAC_ADRL);
|
||||
spin_unlock_irqrestore(&priv->page_lock, flags);
|
||||
}
|
||||
|
||||
static struct fe_soc_data mt7620_data = {
|
||||
.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
|
||||
.init_data = mt7620_init_data,
|
||||
.reset_fe = mt7620_fe_reset,
|
||||
.set_mac = mt7620_set_mac,
|
||||
.fwd_config = mt7620_fwd_config,
|
||||
.tx_dma = mt7620_tx_dma,
|
||||
.rx_dma = mt7620_rx_dma,
|
||||
.switch_init = mt7620_gsw_probe,
|
||||
.switch_config = mt7620_gsw_config,
|
||||
.port_init = mt7620_port_init,
|
||||
.reg_table = mt7620_reg_table,
|
||||
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
|
||||
.rx_dly_int = RT5350_RX_DLY_INT,
|
||||
.tx_dly_int = RT5350_TX_DLY_INT,
|
||||
.checksum_bit = MT7620_L4_VALID,
|
||||
.tx_udf_bit = MT7620_TX_DMA_UDF,
|
||||
.has_carrier = mt7620a_has_carrier,
|
||||
.mdio_read = mt7620_mdio_read,
|
||||
.mdio_write = mt7620_mdio_write,
|
||||
.mdio_adjust_link = mt7620_mdio_link_adjust,
|
||||
};
|
||||
|
||||
static struct fe_soc_data mt7621_data = {
|
||||
.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
|
||||
.init_data = mt7620_init_data,
|
||||
.reset_fe = mt7621_fe_reset,
|
||||
.set_mac = mt7621_set_mac,
|
||||
.fwd_config = mt7621_fwd_config,
|
||||
.tx_dma = mt7621_tx_dma,
|
||||
.rx_dma = mt7620_rx_dma,
|
||||
.switch_init = mt7620_gsw_probe,
|
||||
.switch_config = mt7621_gsw_config,
|
||||
.reg_table = mt7621_reg_table,
|
||||
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
|
||||
.rx_dly_int = RT5350_RX_DLY_INT,
|
||||
.tx_dly_int = RT5350_TX_DLY_INT,
|
||||
.checksum_bit = MT7621_L4_VALID,
|
||||
.tx_udf_bit = MT7621_TX_DMA_UDF,
|
||||
.has_carrier = mt7620a_has_carrier,
|
||||
.mdio_read = mt7620_mdio_read,
|
||||
.mdio_write = mt7620_mdio_write,
|
||||
.mdio_adjust_link = mt7620_mdio_link_adjust,
|
||||
};
|
||||
|
||||
const struct of_device_id of_fe_match[] = {
|
||||
{ .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
|
||||
{ .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, of_fe_match);
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
#include "ralink_soc_eth.h"
|
||||
#include "mdio_rt2880.h"
|
||||
|
||||
#define SYSC_REG_RESET_CTRL 0x034
|
||||
#define RT2880_RESET_FE BIT(18)
|
||||
|
||||
static void rt2880_init_data(struct fe_soc_data *data,
|
||||
struct net_device *netdev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(netdev);
|
||||
|
||||
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
|
||||
FE_FLAG_JUMBO_FRAME;
|
||||
netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
|
||||
/* maybe have hardware bug. */
|
||||
//netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
|
||||
}
|
||||
|
||||
void rt2880_fe_reset(void)
|
||||
{
|
||||
rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
|
||||
}
|
||||
|
||||
static int rt2880_fwd_config(struct fe_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = fe_set_clock_cycle(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
fe_fwd_config(priv);
|
||||
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
|
||||
fe_csum_config(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct fe_soc_data rt2880_data = {
|
||||
.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
|
||||
.init_data = rt2880_init_data,
|
||||
.reset_fe = rt2880_fe_reset,
|
||||
.fwd_config = rt2880_fwd_config,
|
||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||
.checksum_bit = RX_DMA_L4VALID,
|
||||
.tx_udf_bit = TX_DMA_UDF,
|
||||
.rx_dly_int = FE_RX_DLY_INT,
|
||||
.tx_dly_int = FE_TX_DLY_INT,
|
||||
.mdio_read = rt2880_mdio_read,
|
||||
.mdio_write = rt2880_mdio_write,
|
||||
.mdio_adjust_link = rt2880_mdio_link_adjust,
|
||||
.port_init = rt2880_port_init,
|
||||
};
|
||||
|
||||
const struct of_device_id of_fe_match[] = {
|
||||
{ .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, of_fe_match);
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
#include "ralink_soc_eth.h"
|
||||
#include "mdio_rt2880.h"
|
||||
|
||||
#define RT305X_RESET_FE BIT(21)
|
||||
#define RT305X_RESET_ESW BIT(23)
|
||||
#define SYSC_REG_RESET_CTRL 0x034
|
||||
|
||||
static const u32 rt5350_reg_table[FE_REG_COUNT] = {
|
||||
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
|
||||
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
|
||||
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
|
||||
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
|
||||
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
|
||||
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
|
||||
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
|
||||
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
|
||||
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
|
||||
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
|
||||
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
|
||||
[FE_REG_FE_RST_GL] = 0,
|
||||
[FE_REG_FE_DMA_VID_BASE] = 0,
|
||||
};
|
||||
|
||||
static void rt305x_init_data(struct fe_soc_data *data,
|
||||
struct net_device *netdev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(netdev);
|
||||
|
||||
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG;
|
||||
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
|
||||
NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
|
||||
}
|
||||
|
||||
static int rt3050_fwd_config(struct fe_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (ralink_soc != RT305X_SOC_RT3052) {
|
||||
ret = fe_set_clock_cycle(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
fe_fwd_config(priv);
|
||||
if (ralink_soc != RT305X_SOC_RT3352)
|
||||
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
|
||||
fe_csum_config(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rt305x_fe_reset(void)
|
||||
{
|
||||
rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
|
||||
rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
|
||||
}
|
||||
|
||||
static void rt5350_init_data(struct fe_soc_data *data,
|
||||
struct net_device *netdev)
|
||||
{
|
||||
netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
|
||||
}
|
||||
|
||||
static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&priv->page_lock, flags);
|
||||
fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
|
||||
fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
|
||||
RT5350_SDM_MAC_ADRL);
|
||||
spin_unlock_irqrestore(&priv->page_lock, flags);
|
||||
}
|
||||
|
||||
static void rt5350_rxcsum_config(bool enable)
|
||||
{
|
||||
if (enable)
|
||||
fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
|
||||
RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
|
||||
RT5350_SDM_CFG);
|
||||
else
|
||||
fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
|
||||
RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
|
||||
RT5350_SDM_CFG);
|
||||
}
|
||||
|
||||
static int rt5350_fwd_config(struct fe_priv *priv)
|
||||
{
|
||||
struct net_device *dev = priv_netdev(priv);
|
||||
|
||||
rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rt5350_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
|
||||
{
|
||||
priv->tx_dma[idx].txd4 = 0;
|
||||
}
|
||||
|
||||
static void rt5350_fe_reset(void)
|
||||
{
|
||||
rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
|
||||
rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
|
||||
}
|
||||
|
||||
static struct fe_soc_data rt3050_data = {
|
||||
.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
|
||||
.init_data = rt305x_init_data,
|
||||
.reset_fe = rt305x_fe_reset,
|
||||
.fwd_config = rt3050_fwd_config,
|
||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||
.checksum_bit = RX_DMA_L4VALID,
|
||||
.tx_udf_bit = TX_DMA_UDF,
|
||||
.rx_dly_int = FE_RX_DLY_INT,
|
||||
.tx_dly_int = FE_TX_DLY_INT,
|
||||
};
|
||||
|
||||
static struct fe_soc_data rt5350_data = {
|
||||
.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
|
||||
.init_data = rt5350_init_data,
|
||||
.reg_table = rt5350_reg_table,
|
||||
.reset_fe = rt5350_fe_reset,
|
||||
.set_mac = rt5350_set_mac,
|
||||
.fwd_config = rt5350_fwd_config,
|
||||
.tx_dma = rt5350_tx_dma,
|
||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||
.checksum_bit = RX_DMA_L4VALID,
|
||||
.tx_udf_bit = TX_DMA_UDF,
|
||||
.rx_dly_int = RT5350_RX_DLY_INT,
|
||||
.tx_dly_int = RT5350_TX_DLY_INT,
|
||||
};
|
||||
|
||||
const struct of_device_id of_fe_match[] = {
|
||||
{ .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
|
||||
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, of_fe_match);
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/mach-ralink/ralink_regs.h>
|
||||
|
||||
#include "ralink_soc_eth.h"
|
||||
#include "mdio_rt2880.h"
|
||||
|
||||
#define RT3883_SYSC_REG_RSTCTRL 0x34
|
||||
#define RT3883_RSTCTRL_FE BIT(21)
|
||||
|
||||
static void rt3883_fe_reset(void)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
|
||||
t |= RT3883_RSTCTRL_FE;
|
||||
rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
|
||||
|
||||
t &= ~RT3883_RSTCTRL_FE;
|
||||
rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
|
||||
}
|
||||
|
||||
static int rt3883_fwd_config(struct fe_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = fe_set_clock_cycle(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
fe_fwd_config(priv);
|
||||
fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
|
||||
fe_csum_config(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void rt3883_init_data(struct fe_soc_data *data,
|
||||
struct net_device *netdev)
|
||||
{
|
||||
struct fe_priv *priv = netdev_priv(netdev);
|
||||
|
||||
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
|
||||
FE_FLAG_JUMBO_FRAME;
|
||||
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
|
||||
NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
|
||||
}
|
||||
|
||||
static struct fe_soc_data rt3883_data = {
|
||||
.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
|
||||
.init_data = rt3883_init_data,
|
||||
.reset_fe = rt3883_fe_reset,
|
||||
.fwd_config = rt3883_fwd_config,
|
||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||
.rx_dly_int = FE_RX_DLY_INT,
|
||||
.tx_dly_int = FE_TX_DLY_INT,
|
||||
.checksum_bit = RX_DMA_L4VALID,
|
||||
.tx_udf_bit = TX_DMA_UDF,
|
||||
.mdio_read = rt2880_mdio_read,
|
||||
.mdio_write = rt2880_mdio_write,
|
||||
.mdio_adjust_link = rt2880_mdio_link_adjust,
|
||||
.port_init = rt2880_port_init,
|
||||
};
|
||||
|
||||
const struct of_device_id of_fe_match[] = {
|
||||
{ .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, of_fe_match);
|
||||
|
||||
|
|
@ -112,6 +112,8 @@ CONFIG_NEED_PER_CPU_KM=y
|
|||
CONFIG_NET_RALINK=y
|
||||
CONFIG_NET_RALINK_GSW_MT7620=y
|
||||
CONFIG_NET_RALINK_MDIO=y
|
||||
CONFIG_NET_RALINK_MT7620=y
|
||||
# CONFIG_NET_RALINK_RT305X is not set
|
||||
CONFIG_NLS=m
|
||||
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
|
||||
CONFIG_OF=y
|
||||
|
|
@ -140,6 +142,7 @@ CONFIG_PINMUX=y
|
|||
CONFIG_RALINK=y
|
||||
CONFIG_RALINK_USBPHY=y
|
||||
CONFIG_RALINK_WDT=y
|
||||
CONFIG_RA_NAT_NONE=y
|
||||
# CONFIG_RCU_STALL_COMMON is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
# CONFIG_SAMSUNG_USB2PHY is not set
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
|
||||
CONFIG_ARCH_DISCARD_MEMBLOCK=y
|
||||
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
|
||||
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
|
||||
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
|
|
@ -83,6 +84,7 @@ CONFIG_IRQCHIP=y
|
|||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_INTC=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_M25PXX_USE_FAST_READ=y
|
||||
CONFIG_MDIO_BOARDINFO=y
|
||||
|
|
@ -107,6 +109,8 @@ CONFIG_NEED_PER_CPU_KM=y
|
|||
CONFIG_NET_RALINK=y
|
||||
CONFIG_NET_RALINK_GSW_MT7620=y
|
||||
CONFIG_NET_RALINK_MDIO=y
|
||||
CONFIG_NET_RALINK_MT7620=y
|
||||
# CONFIG_NET_RALINK_RT305X is not set
|
||||
CONFIG_NLS=m
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
|
|
@ -129,9 +133,9 @@ CONFIG_PINCTRL_RT2880=y
|
|||
CONFIG_PINMUX=y
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
CONFIG_RALINK=y
|
||||
CONFIG_RALINK_GDMA=y
|
||||
CONFIG_RALINK_USBPHY=y
|
||||
CONFIG_RALINK_WDT=y
|
||||
CONFIG_RA_NAT_NONE=y
|
||||
# CONFIG_RCU_STALL_COMMON is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
# CONFIG_SAMSUNG_USB2PHY is not set
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,22 +0,0 @@
|
|||
Index: linux-3.10.34/drivers/net/ethernet/ralink/mdio_rt2880.c
|
||||
===================================================================
|
||||
--- linux-3.10.34.orig/drivers/net/ethernet/ralink/mdio_rt2880.c
|
||||
+++ linux-3.10.34/drivers/net/ethernet/ralink/mdio_rt2880.c
|
||||
@@ -136,7 +136,7 @@ int rt2880_mdio_read(struct mii_bus *bus
|
||||
if (err)
|
||||
return 0xffff;
|
||||
|
||||
- pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
|
||||
+ pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
|
||||
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
|
||||
|
||||
return fe_r32(FE_MDIO_ACCESS) & 0xffff;
|
||||
@@ -148,7 +148,7 @@ int rt2880_mdio_write(struct mii_bus *bu
|
||||
int err;
|
||||
u32 t;
|
||||
|
||||
- pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
|
||||
+ pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
|
||||
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
|
||||
|
||||
err = rt2880_mdio_wait_ready(priv);
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
Index: linux-3.10.49/arch/mips/include/asm/mach-ralink/ralink_regs.h
|
||||
===================================================================
|
||||
--- linux-3.10.49.orig/arch/mips/include/asm/mach-ralink/ralink_regs.h 2014-11-19 00:10:56.662374797 +0100
|
||||
+++ linux-3.10.49/arch/mips/include/asm/mach-ralink/ralink_regs.h 2014-11-19 00:11:31.511729604 +0100
|
||||
@@ -13,6 +13,20 @@
|
||||
#ifndef _RALINK_REGS_H_
|
||||
#define _RALINK_REGS_H_
|
||||
|
||||
+enum ralink_soc_type {
|
||||
+ RALINK_UNKNOWN = 0,
|
||||
+ RT305X_SOC_RT3050,
|
||||
+ RT305X_SOC_RT3052,
|
||||
+ RT305X_SOC_RT3350,
|
||||
+ RT305X_SOC_RT3352,
|
||||
+ RT305X_SOC_RT5350,
|
||||
+ MT762X_SOC_MT7620A,
|
||||
+ MT762X_SOC_MT7620N,
|
||||
+ MT762X_SOC_MT7621AT,
|
||||
+ MT762X_SOC_MT7628AN,
|
||||
+};
|
||||
+extern enum ralink_soc_type ralink_soc;
|
||||
+
|
||||
extern __iomem void *rt_sysc_membase;
|
||||
extern __iomem void *rt_memc_membase;
|
||||
|
||||
Index: linux-3.10.49/arch/mips/include/asm/mach-ralink/rt305x.h
|
||||
===================================================================
|
||||
--- linux-3.10.49.orig/arch/mips/include/asm/mach-ralink/rt305x.h 2014-11-19 00:10:56.662374797 +0100
|
||||
+++ linux-3.10.49/arch/mips/include/asm/mach-ralink/rt305x.h 2014-11-19 00:11:31.511729604 +0100
|
||||
@@ -13,25 +13,16 @@
|
||||
#ifndef _RT305X_REGS_H_
|
||||
#define _RT305X_REGS_H_
|
||||
|
||||
-enum rt305x_soc_type {
|
||||
- RT305X_SOC_UNKNOWN = 0,
|
||||
- RT305X_SOC_RT3050,
|
||||
- RT305X_SOC_RT3052,
|
||||
- RT305X_SOC_RT3350,
|
||||
- RT305X_SOC_RT3352,
|
||||
- RT305X_SOC_RT5350,
|
||||
-};
|
||||
-
|
||||
-extern enum rt305x_soc_type rt305x_soc;
|
||||
+extern enum ralink_soc_type ralink_soc;
|
||||
|
||||
static inline int soc_is_rt3050(void)
|
||||
{
|
||||
- return rt305x_soc == RT305X_SOC_RT3050;
|
||||
+ return ralink_soc == RT305X_SOC_RT3050;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3052(void)
|
||||
{
|
||||
- return rt305x_soc == RT305X_SOC_RT3052;
|
||||
+ return ralink_soc == RT305X_SOC_RT3052;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt305x(void)
|
||||
@@ -41,17 +32,17 @@
|
||||
|
||||
static inline int soc_is_rt3350(void)
|
||||
{
|
||||
- return rt305x_soc == RT305X_SOC_RT3350;
|
||||
+ return ralink_soc == RT305X_SOC_RT3350;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3352(void)
|
||||
{
|
||||
- return rt305x_soc == RT305X_SOC_RT3352;
|
||||
+ return ralink_soc == RT305X_SOC_RT3352;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt5350(void)
|
||||
{
|
||||
- return rt305x_soc == RT305X_SOC_RT5350;
|
||||
+ return ralink_soc == RT305X_SOC_RT5350;
|
||||
}
|
||||
|
||||
#define RT305X_SYSC_BASE 0x10000000
|
||||
Index: linux-3.10.49/arch/mips/ralink/rt305x.c
|
||||
===================================================================
|
||||
--- linux-3.10.49.orig/arch/mips/ralink/rt305x.c 2014-11-19 00:10:07.980482146 +0100
|
||||
+++ linux-3.10.49/arch/mips/ralink/rt305x.c 2014-11-19 00:11:31.511729604 +0100
|
||||
@@ -21,8 +21,6 @@
|
||||
|
||||
#include "common.h"
|
||||
|
||||
-enum rt305x_soc_type rt305x_soc;
|
||||
-
|
||||
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
|
||||
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
|
||||
static struct rt2880_pmx_func uartf_func[] = {
|
||||
@@ -234,24 +232,24 @@
|
||||
|
||||
icache_sets = (read_c0_config1() >> 22) & 7;
|
||||
if (icache_sets == 1) {
|
||||
- rt305x_soc = RT305X_SOC_RT3050;
|
||||
+ ralink_soc = RT305X_SOC_RT3050;
|
||||
name = "RT3050";
|
||||
soc_info->compatible = "ralink,rt3050-soc";
|
||||
} else {
|
||||
- rt305x_soc = RT305X_SOC_RT3052;
|
||||
+ ralink_soc = RT305X_SOC_RT3052;
|
||||
name = "RT3052";
|
||||
soc_info->compatible = "ralink,rt3052-soc";
|
||||
}
|
||||
} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
|
||||
- rt305x_soc = RT305X_SOC_RT3350;
|
||||
+ ralink_soc = RT305X_SOC_RT3350;
|
||||
name = "RT3350";
|
||||
soc_info->compatible = "ralink,rt3350-soc";
|
||||
} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
|
||||
- rt305x_soc = RT305X_SOC_RT3352;
|
||||
+ ralink_soc = RT305X_SOC_RT3352;
|
||||
name = "RT3352";
|
||||
soc_info->compatible = "ralink,rt3352-soc";
|
||||
} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
|
||||
- rt305x_soc = RT305X_SOC_RT5350;
|
||||
+ ralink_soc = RT305X_SOC_RT5350;
|
||||
name = "RT5350";
|
||||
soc_info->compatible = "ralink,rt5350-soc";
|
||||
} else {
|
||||
Index: linux-3.10.49/arch/mips/ralink/prom.c
|
||||
===================================================================
|
||||
--- linux-3.10.49.orig/arch/mips/ralink/prom.c 2014-11-19 00:10:56.662374797 +0100
|
||||
+++ linux-3.10.49/arch/mips/ralink/prom.c 2014-11-19 00:11:31.511729604 +0100
|
||||
@@ -15,9 +15,13 @@
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
+#include <asm/mach-ralink/ralink_regs.h>
|
||||
+
|
||||
#include "common.h"
|
||||
|
||||
struct ralink_soc_info soc_info;
|
||||
+enum ralink_soc_type ralink_soc;
|
||||
+EXPORT_SYMBOL_GPL(ralink_soc);
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
Index: linux-3.10.49/arch/mips/ralink/mt7621.c
|
||||
===================================================================
|
||||
--- linux-3.10.49.orig/arch/mips/ralink/mt7621.c 2014-11-19 00:10:56.662374797 +0100
|
||||
+++ linux-3.10.49/arch/mips/ralink/mt7621.c 2014-11-19 00:11:31.511729604 +0100
|
||||
@@ -175,6 +175,7 @@
|
||||
soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
|
||||
soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
|
||||
soc_info->mem_base = MT7621_DRAM_BASE;
|
||||
+ ralink_soc = MT762X_SOC_MT7621AT;
|
||||
|
||||
rt2880_pinmux_data = mt7621_pinmux_data;
|
||||
|
||||
Loading…
Reference in New Issue