This patch originally failed to combine INTA/B/C/D onto a single ARM CPU
interrupt. Instead, it mapped INTA/B/C and excluded D. This patch
corrects the issue by mapping all four interrupts to the single ARM CPU
interrupt. The original intent of the patch still holds as the newer PCB
take advantage of isolated interrupts. This fix only applies to older
PCB's that do not route INTA/B/C/D to unique external ARM CPU
interrupts.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Backport of r42830
git-svn-id: svn://svn.openwrt.org/openwrt/branches/barrier_breaker@42846 3c298f89-4303-0410-b956-a3cf2f4a3e73
The cns3xxx uses irq61 for pcie0_intr which in the case of a PCIe-to-PCI
bridge ends up combining INTA/B/C/D on a single ARM CPU interrupt. This is
not optimal when you have multiple cores. To overcome this limitation an
enhancement was made on newer Laguna PCB's that support miniPCI cards
to route the INTA/B/C/D signals to unique external ARM CPU interrupts which
can help balance CPU core utilization and in some cases increase overall
system performance or responsiveness.
For more details see:
http://trac.gateworks.com/wiki/multicoreprocessing#PCIInterruptsteering
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Backport of r42400
git-svn-id: svn://svn.openwrt.org/openwrt/branches/barrier_breaker@42402 3c298f89-4303-0410-b956-a3cf2f4a3e73
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Backport of r41917
git-svn-id: svn://svn.openwrt.org/openwrt/branches/barrier_breaker@41921 3c298f89-4303-0410-b956-a3cf2f4a3e73
nbd