From 41fa6dec9df9b4e55ac522c899270a72e51a9b4b Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 9 Jul 2011 12:15:06 -0700 Subject: [PATCH V2 2/2] MIPS: BCM63XX: Enable second core SMP on BCM6328 if available BCM6328 has a OTP which tells us if the second core is available. Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/prom.c | 6 +++++- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 ++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 7 +++++++ 3 files changed, 14 insertions(+), 1 deletion(-) --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -69,7 +69,11 @@ void __init prom_init(void) * for now. */ if (BCMCPU_IS_6328()) { - bmips_smp_enabled = 0; + reg = bcm_readl(BCM_6328_OTP_BASE + + OTP_USER_BITS_6328_REG(3)); + + if (reg & OTP_6328_REG3_TP1_DISABLED) + bmips_smp_enabled = 0; } else if (BCMCPU_IS_6358()) { bmips_smp_enabled = 0; } --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -296,6 +296,8 @@ enum bcm63xx_regs_set { #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) #define BCM_6328_RNG_BASE (0xdeadbeef) #define BCM_6328_MISC_BASE (0xb0001800) +#define BCM_6328_OTP_BASE (0xb0000600) + /* * 6338 register sets base address */ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -1477,4 +1477,11 @@ #define PCIE_DEVICE_OFFSET 0x8000 +/************************************************************************* + * _REG relative to RSET_OTP + *************************************************************************/ + +#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4) +#define OTP_6328_REG3_TP1_DISABLED BIT(9) + #endif /* BCM63XX_REGS_H_ */